1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "tcg/tcg-cpu.h" 25 #include "pmu.h" 26 #include "time_helper.h" 27 #include "exec/exec-all.h" 28 #include "exec/tb-flush.h" 29 #include "sysemu/cpu-timers.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 #if !defined(CONFIG_USER_ONLY) 47 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) 48 { 49 bool virt = env->virt_enabled; 50 51 if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { 52 return RISCV_EXCP_NONE; 53 } 54 55 if (!(env->mstateen[index] & bit)) { 56 return RISCV_EXCP_ILLEGAL_INST; 57 } 58 59 if (virt) { 60 if (!(env->hstateen[index] & bit)) { 61 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 62 } 63 64 if (env->priv == PRV_U && !(env->sstateen[index] & bit)) { 65 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 66 } 67 } 68 69 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { 70 if (!(env->sstateen[index] & bit)) { 71 return RISCV_EXCP_ILLEGAL_INST; 72 } 73 } 74 75 return RISCV_EXCP_NONE; 76 } 77 #endif 78 79 static RISCVException fs(CPURISCVState *env, int csrno) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 83 !riscv_cpu_cfg(env)->ext_zfinx) { 84 return RISCV_EXCP_ILLEGAL_INST; 85 } 86 87 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 88 return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); 89 } 90 #endif 91 return RISCV_EXCP_NONE; 92 } 93 94 static RISCVException vs(CPURISCVState *env, int csrno) 95 { 96 if (riscv_cpu_cfg(env)->ext_zve32f) { 97 #if !defined(CONFIG_USER_ONLY) 98 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 99 return RISCV_EXCP_ILLEGAL_INST; 100 } 101 #endif 102 return RISCV_EXCP_NONE; 103 } 104 return RISCV_EXCP_ILLEGAL_INST; 105 } 106 107 static RISCVException ctr(CPURISCVState *env, int csrno) 108 { 109 #if !defined(CONFIG_USER_ONLY) 110 RISCVCPU *cpu = env_archcpu(env); 111 int ctr_index; 112 target_ulong ctr_mask; 113 int base_csrno = CSR_CYCLE; 114 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; 115 116 if (rv32 && csrno >= CSR_CYCLEH) { 117 /* Offset for RV32 hpmcounternh counters */ 118 base_csrno += 0x80; 119 } 120 ctr_index = csrno - base_csrno; 121 ctr_mask = BIT(ctr_index); 122 123 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || 124 (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { 125 goto skip_ext_pmu_check; 126 } 127 128 if (!(cpu->pmu_avail_ctrs & ctr_mask)) { 129 /* No counter is enabled in PMU or the counter is out of range */ 130 return RISCV_EXCP_ILLEGAL_INST; 131 } 132 133 skip_ext_pmu_check: 134 135 if (env->debugger) { 136 return RISCV_EXCP_NONE; 137 } 138 139 if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) { 140 return RISCV_EXCP_ILLEGAL_INST; 141 } 142 143 if (env->virt_enabled) { 144 if (!get_field(env->hcounteren, ctr_mask) || 145 (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) { 146 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 147 } 148 } 149 150 if (riscv_has_ext(env, RVS) && env->priv == PRV_U && 151 !get_field(env->scounteren, ctr_mask)) { 152 return RISCV_EXCP_ILLEGAL_INST; 153 } 154 155 #endif 156 return RISCV_EXCP_NONE; 157 } 158 159 static RISCVException ctr32(CPURISCVState *env, int csrno) 160 { 161 if (riscv_cpu_mxl(env) != MXL_RV32) { 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 return ctr(env, csrno); 166 } 167 168 static RISCVException zcmt(CPURISCVState *env, int csrno) 169 { 170 if (!riscv_cpu_cfg(env)->ext_zcmt) { 171 return RISCV_EXCP_ILLEGAL_INST; 172 } 173 174 #if !defined(CONFIG_USER_ONLY) 175 RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); 176 if (ret != RISCV_EXCP_NONE) { 177 return ret; 178 } 179 #endif 180 181 return RISCV_EXCP_NONE; 182 } 183 184 #if !defined(CONFIG_USER_ONLY) 185 static RISCVException mctr(CPURISCVState *env, int csrno) 186 { 187 int pmu_num = riscv_cpu_cfg(env)->pmu_num; 188 int ctr_index; 189 int base_csrno = CSR_MHPMCOUNTER3; 190 191 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { 192 /* Offset for RV32 mhpmcounternh counters */ 193 base_csrno += 0x80; 194 } 195 ctr_index = csrno - base_csrno; 196 if (!pmu_num || ctr_index >= pmu_num) { 197 /* The PMU is not enabled or counter is out of range */ 198 return RISCV_EXCP_ILLEGAL_INST; 199 } 200 201 return RISCV_EXCP_NONE; 202 } 203 204 static RISCVException mctr32(CPURISCVState *env, int csrno) 205 { 206 if (riscv_cpu_mxl(env) != MXL_RV32) { 207 return RISCV_EXCP_ILLEGAL_INST; 208 } 209 210 return mctr(env, csrno); 211 } 212 213 static RISCVException sscofpmf(CPURISCVState *env, int csrno) 214 { 215 if (!riscv_cpu_cfg(env)->ext_sscofpmf) { 216 return RISCV_EXCP_ILLEGAL_INST; 217 } 218 219 return RISCV_EXCP_NONE; 220 } 221 222 static RISCVException any(CPURISCVState *env, int csrno) 223 { 224 return RISCV_EXCP_NONE; 225 } 226 227 static RISCVException any32(CPURISCVState *env, int csrno) 228 { 229 if (riscv_cpu_mxl(env) != MXL_RV32) { 230 return RISCV_EXCP_ILLEGAL_INST; 231 } 232 233 return any(env, csrno); 234 235 } 236 237 static int aia_any(CPURISCVState *env, int csrno) 238 { 239 if (!riscv_cpu_cfg(env)->ext_smaia) { 240 return RISCV_EXCP_ILLEGAL_INST; 241 } 242 243 return any(env, csrno); 244 } 245 246 static int aia_any32(CPURISCVState *env, int csrno) 247 { 248 if (!riscv_cpu_cfg(env)->ext_smaia) { 249 return RISCV_EXCP_ILLEGAL_INST; 250 } 251 252 return any32(env, csrno); 253 } 254 255 static RISCVException smode(CPURISCVState *env, int csrno) 256 { 257 if (riscv_has_ext(env, RVS)) { 258 return RISCV_EXCP_NONE; 259 } 260 261 return RISCV_EXCP_ILLEGAL_INST; 262 } 263 264 static int smode32(CPURISCVState *env, int csrno) 265 { 266 if (riscv_cpu_mxl(env) != MXL_RV32) { 267 return RISCV_EXCP_ILLEGAL_INST; 268 } 269 270 return smode(env, csrno); 271 } 272 273 static int aia_smode(CPURISCVState *env, int csrno) 274 { 275 if (!riscv_cpu_cfg(env)->ext_ssaia) { 276 return RISCV_EXCP_ILLEGAL_INST; 277 } 278 279 return smode(env, csrno); 280 } 281 282 static int aia_smode32(CPURISCVState *env, int csrno) 283 { 284 if (!riscv_cpu_cfg(env)->ext_ssaia) { 285 return RISCV_EXCP_ILLEGAL_INST; 286 } 287 288 return smode32(env, csrno); 289 } 290 291 static RISCVException hmode(CPURISCVState *env, int csrno) 292 { 293 if (riscv_has_ext(env, RVH)) { 294 return RISCV_EXCP_NONE; 295 } 296 297 return RISCV_EXCP_ILLEGAL_INST; 298 } 299 300 static RISCVException hmode32(CPURISCVState *env, int csrno) 301 { 302 if (riscv_cpu_mxl(env) != MXL_RV32) { 303 return RISCV_EXCP_ILLEGAL_INST; 304 } 305 306 return hmode(env, csrno); 307 308 } 309 310 static RISCVException umode(CPURISCVState *env, int csrno) 311 { 312 if (riscv_has_ext(env, RVU)) { 313 return RISCV_EXCP_NONE; 314 } 315 316 return RISCV_EXCP_ILLEGAL_INST; 317 } 318 319 static RISCVException umode32(CPURISCVState *env, int csrno) 320 { 321 if (riscv_cpu_mxl(env) != MXL_RV32) { 322 return RISCV_EXCP_ILLEGAL_INST; 323 } 324 325 return umode(env, csrno); 326 } 327 328 static RISCVException mstateen(CPURISCVState *env, int csrno) 329 { 330 if (!riscv_cpu_cfg(env)->ext_smstateen) { 331 return RISCV_EXCP_ILLEGAL_INST; 332 } 333 334 return any(env, csrno); 335 } 336 337 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) 338 { 339 if (!riscv_cpu_cfg(env)->ext_smstateen) { 340 return RISCV_EXCP_ILLEGAL_INST; 341 } 342 343 RISCVException ret = hmode(env, csrno); 344 if (ret != RISCV_EXCP_NONE) { 345 return ret; 346 } 347 348 if (env->debugger) { 349 return RISCV_EXCP_NONE; 350 } 351 352 if (env->priv < PRV_M) { 353 if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { 354 return RISCV_EXCP_ILLEGAL_INST; 355 } 356 } 357 358 return RISCV_EXCP_NONE; 359 } 360 361 static RISCVException hstateen(CPURISCVState *env, int csrno) 362 { 363 return hstateen_pred(env, csrno, CSR_HSTATEEN0); 364 } 365 366 static RISCVException hstateenh(CPURISCVState *env, int csrno) 367 { 368 return hstateen_pred(env, csrno, CSR_HSTATEEN0H); 369 } 370 371 static RISCVException sstateen(CPURISCVState *env, int csrno) 372 { 373 bool virt = env->virt_enabled; 374 int index = csrno - CSR_SSTATEEN0; 375 376 if (!riscv_cpu_cfg(env)->ext_smstateen) { 377 return RISCV_EXCP_ILLEGAL_INST; 378 } 379 380 RISCVException ret = smode(env, csrno); 381 if (ret != RISCV_EXCP_NONE) { 382 return ret; 383 } 384 385 if (env->debugger) { 386 return RISCV_EXCP_NONE; 387 } 388 389 if (env->priv < PRV_M) { 390 if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { 391 return RISCV_EXCP_ILLEGAL_INST; 392 } 393 394 if (virt) { 395 if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { 396 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 397 } 398 } 399 } 400 401 return RISCV_EXCP_NONE; 402 } 403 404 static RISCVException sstc(CPURISCVState *env, int csrno) 405 { 406 bool hmode_check = false; 407 408 if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { 409 return RISCV_EXCP_ILLEGAL_INST; 410 } 411 412 if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { 413 hmode_check = true; 414 } 415 416 RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno); 417 if (ret != RISCV_EXCP_NONE) { 418 return ret; 419 } 420 421 if (env->debugger) { 422 return RISCV_EXCP_NONE; 423 } 424 425 if (env->priv == PRV_M) { 426 return RISCV_EXCP_NONE; 427 } 428 429 /* 430 * No need of separate function for rv32 as menvcfg stores both menvcfg 431 * menvcfgh for RV32. 432 */ 433 if (!(get_field(env->mcounteren, COUNTEREN_TM) && 434 get_field(env->menvcfg, MENVCFG_STCE))) { 435 return RISCV_EXCP_ILLEGAL_INST; 436 } 437 438 if (env->virt_enabled) { 439 if (!(get_field(env->hcounteren, COUNTEREN_TM) && 440 get_field(env->henvcfg, HENVCFG_STCE))) { 441 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 442 } 443 } 444 445 return RISCV_EXCP_NONE; 446 } 447 448 static RISCVException sstc_32(CPURISCVState *env, int csrno) 449 { 450 if (riscv_cpu_mxl(env) != MXL_RV32) { 451 return RISCV_EXCP_ILLEGAL_INST; 452 } 453 454 return sstc(env, csrno); 455 } 456 457 static RISCVException satp(CPURISCVState *env, int csrno) 458 { 459 if (env->priv == PRV_S && !env->virt_enabled && 460 get_field(env->mstatus, MSTATUS_TVM)) { 461 return RISCV_EXCP_ILLEGAL_INST; 462 } 463 if (env->priv == PRV_S && env->virt_enabled && 464 get_field(env->hstatus, HSTATUS_VTVM)) { 465 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 466 } 467 468 return smode(env, csrno); 469 } 470 471 static RISCVException hgatp(CPURISCVState *env, int csrno) 472 { 473 if (env->priv == PRV_S && !env->virt_enabled && 474 get_field(env->mstatus, MSTATUS_TVM)) { 475 return RISCV_EXCP_ILLEGAL_INST; 476 } 477 478 return hmode(env, csrno); 479 } 480 481 /* Checks if PointerMasking registers could be accessed */ 482 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 483 { 484 /* Check if j-ext is present */ 485 if (riscv_has_ext(env, RVJ)) { 486 return RISCV_EXCP_NONE; 487 } 488 return RISCV_EXCP_ILLEGAL_INST; 489 } 490 491 static int aia_hmode(CPURISCVState *env, int csrno) 492 { 493 if (!riscv_cpu_cfg(env)->ext_ssaia) { 494 return RISCV_EXCP_ILLEGAL_INST; 495 } 496 497 return hmode(env, csrno); 498 } 499 500 static int aia_hmode32(CPURISCVState *env, int csrno) 501 { 502 if (!riscv_cpu_cfg(env)->ext_ssaia) { 503 return RISCV_EXCP_ILLEGAL_INST; 504 } 505 506 return hmode32(env, csrno); 507 } 508 509 static RISCVException pmp(CPURISCVState *env, int csrno) 510 { 511 if (riscv_cpu_cfg(env)->pmp) { 512 if (csrno <= CSR_PMPCFG3) { 513 uint32_t reg_index = csrno - CSR_PMPCFG0; 514 515 /* TODO: RV128 restriction check */ 516 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 517 return RISCV_EXCP_ILLEGAL_INST; 518 } 519 } 520 521 return RISCV_EXCP_NONE; 522 } 523 524 return RISCV_EXCP_ILLEGAL_INST; 525 } 526 527 static RISCVException epmp(CPURISCVState *env, int csrno) 528 { 529 if (riscv_cpu_cfg(env)->epmp) { 530 return RISCV_EXCP_NONE; 531 } 532 533 return RISCV_EXCP_ILLEGAL_INST; 534 } 535 536 static RISCVException debug(CPURISCVState *env, int csrno) 537 { 538 if (riscv_cpu_cfg(env)->debug) { 539 return RISCV_EXCP_NONE; 540 } 541 542 return RISCV_EXCP_ILLEGAL_INST; 543 } 544 #endif 545 546 static RISCVException seed(CPURISCVState *env, int csrno) 547 { 548 if (!riscv_cpu_cfg(env)->ext_zkr) { 549 return RISCV_EXCP_ILLEGAL_INST; 550 } 551 552 #if !defined(CONFIG_USER_ONLY) 553 if (env->debugger) { 554 return RISCV_EXCP_NONE; 555 } 556 557 /* 558 * With a CSR read-write instruction: 559 * 1) The seed CSR is always available in machine mode as normal. 560 * 2) Attempted access to seed from virtual modes VS and VU always raises 561 * an exception(virtual instruction exception only if mseccfg.sseed=1). 562 * 3) Without the corresponding access control bit set to 1, any attempted 563 * access to seed from U, S or HS modes will raise an illegal instruction 564 * exception. 565 */ 566 if (env->priv == PRV_M) { 567 return RISCV_EXCP_NONE; 568 } else if (env->virt_enabled) { 569 if (env->mseccfg & MSECCFG_SSEED) { 570 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 571 } else { 572 return RISCV_EXCP_ILLEGAL_INST; 573 } 574 } else { 575 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { 576 return RISCV_EXCP_NONE; 577 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { 578 return RISCV_EXCP_NONE; 579 } else { 580 return RISCV_EXCP_ILLEGAL_INST; 581 } 582 } 583 #else 584 return RISCV_EXCP_NONE; 585 #endif 586 } 587 588 /* User Floating-Point CSRs */ 589 static RISCVException read_fflags(CPURISCVState *env, int csrno, 590 target_ulong *val) 591 { 592 *val = riscv_cpu_get_fflags(env); 593 return RISCV_EXCP_NONE; 594 } 595 596 static RISCVException write_fflags(CPURISCVState *env, int csrno, 597 target_ulong val) 598 { 599 #if !defined(CONFIG_USER_ONLY) 600 if (riscv_has_ext(env, RVF)) { 601 env->mstatus |= MSTATUS_FS; 602 } 603 #endif 604 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 605 return RISCV_EXCP_NONE; 606 } 607 608 static RISCVException read_frm(CPURISCVState *env, int csrno, 609 target_ulong *val) 610 { 611 *val = env->frm; 612 return RISCV_EXCP_NONE; 613 } 614 615 static RISCVException write_frm(CPURISCVState *env, int csrno, 616 target_ulong val) 617 { 618 #if !defined(CONFIG_USER_ONLY) 619 if (riscv_has_ext(env, RVF)) { 620 env->mstatus |= MSTATUS_FS; 621 } 622 #endif 623 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 624 return RISCV_EXCP_NONE; 625 } 626 627 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 628 target_ulong *val) 629 { 630 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 631 | (env->frm << FSR_RD_SHIFT); 632 return RISCV_EXCP_NONE; 633 } 634 635 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 636 target_ulong val) 637 { 638 #if !defined(CONFIG_USER_ONLY) 639 if (riscv_has_ext(env, RVF)) { 640 env->mstatus |= MSTATUS_FS; 641 } 642 #endif 643 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 644 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 645 return RISCV_EXCP_NONE; 646 } 647 648 static RISCVException read_vtype(CPURISCVState *env, int csrno, 649 target_ulong *val) 650 { 651 uint64_t vill; 652 switch (env->xl) { 653 case MXL_RV32: 654 vill = (uint32_t)env->vill << 31; 655 break; 656 case MXL_RV64: 657 vill = (uint64_t)env->vill << 63; 658 break; 659 default: 660 g_assert_not_reached(); 661 } 662 *val = (target_ulong)vill | env->vtype; 663 return RISCV_EXCP_NONE; 664 } 665 666 static RISCVException read_vl(CPURISCVState *env, int csrno, 667 target_ulong *val) 668 { 669 *val = env->vl; 670 return RISCV_EXCP_NONE; 671 } 672 673 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 674 { 675 *val = riscv_cpu_cfg(env)->vlen >> 3; 676 return RISCV_EXCP_NONE; 677 } 678 679 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 680 target_ulong *val) 681 { 682 *val = env->vxrm; 683 return RISCV_EXCP_NONE; 684 } 685 686 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 687 target_ulong val) 688 { 689 #if !defined(CONFIG_USER_ONLY) 690 env->mstatus |= MSTATUS_VS; 691 #endif 692 env->vxrm = val; 693 return RISCV_EXCP_NONE; 694 } 695 696 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 697 target_ulong *val) 698 { 699 *val = env->vxsat; 700 return RISCV_EXCP_NONE; 701 } 702 703 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 704 target_ulong val) 705 { 706 #if !defined(CONFIG_USER_ONLY) 707 env->mstatus |= MSTATUS_VS; 708 #endif 709 env->vxsat = val; 710 return RISCV_EXCP_NONE; 711 } 712 713 static RISCVException read_vstart(CPURISCVState *env, int csrno, 714 target_ulong *val) 715 { 716 *val = env->vstart; 717 return RISCV_EXCP_NONE; 718 } 719 720 static RISCVException write_vstart(CPURISCVState *env, int csrno, 721 target_ulong val) 722 { 723 #if !defined(CONFIG_USER_ONLY) 724 env->mstatus |= MSTATUS_VS; 725 #endif 726 /* 727 * The vstart CSR is defined to have only enough writable bits 728 * to hold the largest element index, i.e. lg2(VLEN) bits. 729 */ 730 env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen)); 731 return RISCV_EXCP_NONE; 732 } 733 734 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 735 { 736 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 737 return RISCV_EXCP_NONE; 738 } 739 740 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 741 { 742 #if !defined(CONFIG_USER_ONLY) 743 env->mstatus |= MSTATUS_VS; 744 #endif 745 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 746 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 747 return RISCV_EXCP_NONE; 748 } 749 750 /* User Timers and Counters */ 751 static target_ulong get_ticks(bool shift) 752 { 753 int64_t val; 754 target_ulong result; 755 756 #if !defined(CONFIG_USER_ONLY) 757 if (icount_enabled()) { 758 val = icount_get(); 759 } else { 760 val = cpu_get_host_ticks(); 761 } 762 #else 763 val = cpu_get_host_ticks(); 764 #endif 765 766 if (shift) { 767 result = val >> 32; 768 } else { 769 result = val; 770 } 771 772 return result; 773 } 774 775 #if defined(CONFIG_USER_ONLY) 776 static RISCVException read_time(CPURISCVState *env, int csrno, 777 target_ulong *val) 778 { 779 *val = cpu_get_host_ticks(); 780 return RISCV_EXCP_NONE; 781 } 782 783 static RISCVException read_timeh(CPURISCVState *env, int csrno, 784 target_ulong *val) 785 { 786 *val = cpu_get_host_ticks() >> 32; 787 return RISCV_EXCP_NONE; 788 } 789 790 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) 791 { 792 *val = get_ticks(false); 793 return RISCV_EXCP_NONE; 794 } 795 796 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) 797 { 798 *val = get_ticks(true); 799 return RISCV_EXCP_NONE; 800 } 801 802 #else /* CONFIG_USER_ONLY */ 803 804 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) 805 { 806 int evt_index = csrno - CSR_MCOUNTINHIBIT; 807 808 *val = env->mhpmevent_val[evt_index]; 809 810 return RISCV_EXCP_NONE; 811 } 812 813 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) 814 { 815 int evt_index = csrno - CSR_MCOUNTINHIBIT; 816 uint64_t mhpmevt_val = val; 817 818 env->mhpmevent_val[evt_index] = val; 819 820 if (riscv_cpu_mxl(env) == MXL_RV32) { 821 mhpmevt_val = mhpmevt_val | 822 ((uint64_t)env->mhpmeventh_val[evt_index] << 32); 823 } 824 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); 825 826 return RISCV_EXCP_NONE; 827 } 828 829 static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val) 830 { 831 int evt_index = csrno - CSR_MHPMEVENT3H + 3; 832 833 *val = env->mhpmeventh_val[evt_index]; 834 835 return RISCV_EXCP_NONE; 836 } 837 838 static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val) 839 { 840 int evt_index = csrno - CSR_MHPMEVENT3H + 3; 841 uint64_t mhpmevth_val = val; 842 uint64_t mhpmevt_val = env->mhpmevent_val[evt_index]; 843 844 mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32); 845 env->mhpmeventh_val[evt_index] = val; 846 847 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); 848 849 return RISCV_EXCP_NONE; 850 } 851 852 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) 853 { 854 int ctr_idx = csrno - CSR_MCYCLE; 855 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 856 uint64_t mhpmctr_val = val; 857 858 counter->mhpmcounter_val = val; 859 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 860 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 861 counter->mhpmcounter_prev = get_ticks(false); 862 if (ctr_idx > 2) { 863 if (riscv_cpu_mxl(env) == MXL_RV32) { 864 mhpmctr_val = mhpmctr_val | 865 ((uint64_t)counter->mhpmcounterh_val << 32); 866 } 867 riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); 868 } 869 } else { 870 /* Other counters can keep incrementing from the given value */ 871 counter->mhpmcounter_prev = val; 872 } 873 874 return RISCV_EXCP_NONE; 875 } 876 877 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val) 878 { 879 int ctr_idx = csrno - CSR_MCYCLEH; 880 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 881 uint64_t mhpmctr_val = counter->mhpmcounter_val; 882 uint64_t mhpmctrh_val = val; 883 884 counter->mhpmcounterh_val = val; 885 mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32); 886 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 887 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 888 counter->mhpmcounterh_prev = get_ticks(true); 889 if (ctr_idx > 2) { 890 riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); 891 } 892 } else { 893 counter->mhpmcounterh_prev = val; 894 } 895 896 return RISCV_EXCP_NONE; 897 } 898 899 static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, 900 bool upper_half, uint32_t ctr_idx) 901 { 902 PMUCTRState counter = env->pmu_ctrs[ctr_idx]; 903 target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev : 904 counter.mhpmcounter_prev; 905 target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val : 906 counter.mhpmcounter_val; 907 908 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { 909 /* 910 * Counter should not increment if inhibit bit is set. We can't really 911 * stop the icount counting. Just return the counter value written by 912 * the supervisor to indicate that counter was not incremented. 913 */ 914 if (!counter.started) { 915 *val = ctr_val; 916 return RISCV_EXCP_NONE; 917 } else { 918 /* Mark that the counter has been stopped */ 919 counter.started = false; 920 } 921 } 922 923 /* 924 * The kernel computes the perf delta by subtracting the current value from 925 * the value it initialized previously (ctr_val). 926 */ 927 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 928 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 929 *val = get_ticks(upper_half) - ctr_prev + ctr_val; 930 } else { 931 *val = ctr_val; 932 } 933 934 return RISCV_EXCP_NONE; 935 } 936 937 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) 938 { 939 uint16_t ctr_index; 940 941 if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) { 942 ctr_index = csrno - CSR_MCYCLE; 943 } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) { 944 ctr_index = csrno - CSR_CYCLE; 945 } else { 946 return RISCV_EXCP_ILLEGAL_INST; 947 } 948 949 return riscv_pmu_read_ctr(env, val, false, ctr_index); 950 } 951 952 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) 953 { 954 uint16_t ctr_index; 955 956 if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) { 957 ctr_index = csrno - CSR_MCYCLEH; 958 } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) { 959 ctr_index = csrno - CSR_CYCLEH; 960 } else { 961 return RISCV_EXCP_ILLEGAL_INST; 962 } 963 964 return riscv_pmu_read_ctr(env, val, true, ctr_index); 965 } 966 967 static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) 968 { 969 int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; 970 int i; 971 *val = 0; 972 target_ulong *mhpm_evt_val; 973 uint64_t of_bit_mask; 974 975 if (riscv_cpu_mxl(env) == MXL_RV32) { 976 mhpm_evt_val = env->mhpmeventh_val; 977 of_bit_mask = MHPMEVENTH_BIT_OF; 978 } else { 979 mhpm_evt_val = env->mhpmevent_val; 980 of_bit_mask = MHPMEVENT_BIT_OF; 981 } 982 983 for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { 984 if ((get_field(env->mcounteren, BIT(i))) && 985 (mhpm_evt_val[i] & of_bit_mask)) { 986 *val |= BIT(i); 987 } 988 } 989 990 return RISCV_EXCP_NONE; 991 } 992 993 static RISCVException read_time(CPURISCVState *env, int csrno, 994 target_ulong *val) 995 { 996 uint64_t delta = env->virt_enabled ? env->htimedelta : 0; 997 998 if (!env->rdtime_fn) { 999 return RISCV_EXCP_ILLEGAL_INST; 1000 } 1001 1002 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 1003 return RISCV_EXCP_NONE; 1004 } 1005 1006 static RISCVException read_timeh(CPURISCVState *env, int csrno, 1007 target_ulong *val) 1008 { 1009 uint64_t delta = env->virt_enabled ? env->htimedelta : 0; 1010 1011 if (!env->rdtime_fn) { 1012 return RISCV_EXCP_ILLEGAL_INST; 1013 } 1014 1015 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 1016 return RISCV_EXCP_NONE; 1017 } 1018 1019 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, 1020 target_ulong *val) 1021 { 1022 *val = env->vstimecmp; 1023 1024 return RISCV_EXCP_NONE; 1025 } 1026 1027 static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, 1028 target_ulong *val) 1029 { 1030 *val = env->vstimecmp >> 32; 1031 1032 return RISCV_EXCP_NONE; 1033 } 1034 1035 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, 1036 target_ulong val) 1037 { 1038 if (riscv_cpu_mxl(env) == MXL_RV32) { 1039 env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val); 1040 } else { 1041 env->vstimecmp = val; 1042 } 1043 1044 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 1045 env->htimedelta, MIP_VSTIP); 1046 1047 return RISCV_EXCP_NONE; 1048 } 1049 1050 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, 1051 target_ulong val) 1052 { 1053 env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val); 1054 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 1055 env->htimedelta, MIP_VSTIP); 1056 1057 return RISCV_EXCP_NONE; 1058 } 1059 1060 static RISCVException read_stimecmp(CPURISCVState *env, int csrno, 1061 target_ulong *val) 1062 { 1063 if (env->virt_enabled) { 1064 *val = env->vstimecmp; 1065 } else { 1066 *val = env->stimecmp; 1067 } 1068 1069 return RISCV_EXCP_NONE; 1070 } 1071 1072 static RISCVException read_stimecmph(CPURISCVState *env, int csrno, 1073 target_ulong *val) 1074 { 1075 if (env->virt_enabled) { 1076 *val = env->vstimecmp >> 32; 1077 } else { 1078 *val = env->stimecmp >> 32; 1079 } 1080 1081 return RISCV_EXCP_NONE; 1082 } 1083 1084 static RISCVException write_stimecmp(CPURISCVState *env, int csrno, 1085 target_ulong val) 1086 { 1087 if (env->virt_enabled) { 1088 if (env->hvictl & HVICTL_VTI) { 1089 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1090 } 1091 return write_vstimecmp(env, csrno, val); 1092 } 1093 1094 if (riscv_cpu_mxl(env) == MXL_RV32) { 1095 env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val); 1096 } else { 1097 env->stimecmp = val; 1098 } 1099 1100 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); 1101 1102 return RISCV_EXCP_NONE; 1103 } 1104 1105 static RISCVException write_stimecmph(CPURISCVState *env, int csrno, 1106 target_ulong val) 1107 { 1108 if (env->virt_enabled) { 1109 if (env->hvictl & HVICTL_VTI) { 1110 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1111 } 1112 return write_vstimecmph(env, csrno, val); 1113 } 1114 1115 env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val); 1116 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); 1117 1118 return RISCV_EXCP_NONE; 1119 } 1120 1121 #define VSTOPI_NUM_SRCS 5 1122 1123 #define LOCAL_INTERRUPTS (~0x1FFF) 1124 1125 static const uint64_t delegable_ints = 1126 S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; 1127 static const uint64_t vs_delegable_ints = 1128 (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; 1129 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 1130 HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; 1131 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 1132 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 1133 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 1134 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 1135 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 1136 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 1137 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 1138 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 1139 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 1140 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 1141 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 1142 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 1143 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 1144 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 1145 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 1146 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 1147 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 1148 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 1149 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 1150 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 1151 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 1152 (1ULL << (RISCV_EXCP_VS_ECALL)) | 1153 (1ULL << (RISCV_EXCP_M_ECALL)) | 1154 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 1155 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 1156 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 1157 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 1158 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 1159 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 1160 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 1161 1162 /* 1163 * Spec allows for bits 13:63 to be either read-only or writable. 1164 * So far we have interrupt LCOFIP in that region which is writable. 1165 * 1166 * Also, spec allows to inject virtual interrupts in this region even 1167 * without any hardware interrupts for that interrupt number. 1168 * 1169 * For now interrupt in 13:63 region are all kept writable. 13 being 1170 * LCOFIP and 14:63 being virtual only. Change this in future if we 1171 * introduce more interrupts that are not writable. 1172 */ 1173 1174 /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */ 1175 static const target_ulong mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | 1176 LOCAL_INTERRUPTS; 1177 static const target_ulong mvien_writable_mask = MIP_SSIP | MIP_SEIP | 1178 LOCAL_INTERRUPTS; 1179 1180 static const target_ulong sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; 1181 static const target_ulong hip_writable_mask = MIP_VSSIP; 1182 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | 1183 MIP_VSEIP | LOCAL_INTERRUPTS; 1184 static const target_ulong hvien_writable_mask = LOCAL_INTERRUPTS; 1185 1186 static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; 1187 1188 const bool valid_vm_1_10_32[16] = { 1189 [VM_1_10_MBARE] = true, 1190 [VM_1_10_SV32] = true 1191 }; 1192 1193 const bool valid_vm_1_10_64[16] = { 1194 [VM_1_10_MBARE] = true, 1195 [VM_1_10_SV39] = true, 1196 [VM_1_10_SV48] = true, 1197 [VM_1_10_SV57] = true 1198 }; 1199 1200 /* Machine Information Registers */ 1201 static RISCVException read_zero(CPURISCVState *env, int csrno, 1202 target_ulong *val) 1203 { 1204 *val = 0; 1205 return RISCV_EXCP_NONE; 1206 } 1207 1208 static RISCVException write_ignore(CPURISCVState *env, int csrno, 1209 target_ulong val) 1210 { 1211 return RISCV_EXCP_NONE; 1212 } 1213 1214 static RISCVException read_mvendorid(CPURISCVState *env, int csrno, 1215 target_ulong *val) 1216 { 1217 *val = riscv_cpu_cfg(env)->mvendorid; 1218 return RISCV_EXCP_NONE; 1219 } 1220 1221 static RISCVException read_marchid(CPURISCVState *env, int csrno, 1222 target_ulong *val) 1223 { 1224 *val = riscv_cpu_cfg(env)->marchid; 1225 return RISCV_EXCP_NONE; 1226 } 1227 1228 static RISCVException read_mimpid(CPURISCVState *env, int csrno, 1229 target_ulong *val) 1230 { 1231 *val = riscv_cpu_cfg(env)->mimpid; 1232 return RISCV_EXCP_NONE; 1233 } 1234 1235 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 1236 target_ulong *val) 1237 { 1238 *val = env->mhartid; 1239 return RISCV_EXCP_NONE; 1240 } 1241 1242 /* Machine Trap Setup */ 1243 1244 /* We do not store SD explicitly, only compute it on demand. */ 1245 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 1246 { 1247 if ((status & MSTATUS_FS) == MSTATUS_FS || 1248 (status & MSTATUS_VS) == MSTATUS_VS || 1249 (status & MSTATUS_XS) == MSTATUS_XS) { 1250 switch (xl) { 1251 case MXL_RV32: 1252 return status | MSTATUS32_SD; 1253 case MXL_RV64: 1254 return status | MSTATUS64_SD; 1255 case MXL_RV128: 1256 return MSTATUSH128_SD; 1257 default: 1258 g_assert_not_reached(); 1259 } 1260 } 1261 return status; 1262 } 1263 1264 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 1265 target_ulong *val) 1266 { 1267 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 1268 return RISCV_EXCP_NONE; 1269 } 1270 1271 static bool validate_vm(CPURISCVState *env, target_ulong vm) 1272 { 1273 return (vm & 0xf) <= 1274 satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map); 1275 } 1276 1277 static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp, 1278 target_ulong val) 1279 { 1280 bool valid = false; 1281 target_ulong new_mpp = get_field(val, MSTATUS_MPP); 1282 1283 switch (new_mpp) { 1284 case PRV_M: 1285 valid = true; 1286 break; 1287 case PRV_S: 1288 valid = riscv_has_ext(env, RVS); 1289 break; 1290 case PRV_U: 1291 valid = riscv_has_ext(env, RVU); 1292 break; 1293 } 1294 1295 /* Remain field unchanged if new_mpp value is invalid */ 1296 if (!valid) { 1297 val = set_field(val, MSTATUS_MPP, old_mpp); 1298 } 1299 1300 return val; 1301 } 1302 1303 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 1304 target_ulong val) 1305 { 1306 uint64_t mstatus = env->mstatus; 1307 uint64_t mask = 0; 1308 RISCVMXL xl = riscv_cpu_mxl(env); 1309 1310 /* 1311 * MPP field have been made WARL since priv version 1.11. However, 1312 * legalization for it will not break any software running on 1.10. 1313 */ 1314 val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); 1315 1316 /* flush tlb on mstatus fields that affect VM */ 1317 if ((val ^ mstatus) & MSTATUS_MXR) { 1318 tlb_flush(env_cpu(env)); 1319 } 1320 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 1321 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 1322 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 1323 MSTATUS_TW | MSTATUS_VS; 1324 1325 if (riscv_has_ext(env, RVF)) { 1326 mask |= MSTATUS_FS; 1327 } 1328 1329 if (xl != MXL_RV32 || env->debugger) { 1330 if (riscv_has_ext(env, RVH)) { 1331 mask |= MSTATUS_MPV | MSTATUS_GVA; 1332 } 1333 if ((val & MSTATUS64_UXL) != 0) { 1334 mask |= MSTATUS64_UXL; 1335 } 1336 } 1337 1338 mstatus = (mstatus & ~mask) | (val & mask); 1339 1340 env->mstatus = mstatus; 1341 1342 /* 1343 * Except in debug mode, UXL/SXL can only be modified by higher 1344 * privilege mode. So xl will not be changed in normal mode. 1345 */ 1346 if (env->debugger) { 1347 env->xl = cpu_recompute_xl(env); 1348 } 1349 1350 riscv_cpu_update_mask(env); 1351 return RISCV_EXCP_NONE; 1352 } 1353 1354 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 1355 target_ulong *val) 1356 { 1357 *val = env->mstatus >> 32; 1358 return RISCV_EXCP_NONE; 1359 } 1360 1361 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 1362 target_ulong val) 1363 { 1364 uint64_t valh = (uint64_t)val << 32; 1365 uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; 1366 1367 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 1368 1369 return RISCV_EXCP_NONE; 1370 } 1371 1372 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 1373 Int128 *val) 1374 { 1375 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, 1376 env->mstatus)); 1377 return RISCV_EXCP_NONE; 1378 } 1379 1380 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 1381 Int128 *val) 1382 { 1383 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 1384 return RISCV_EXCP_NONE; 1385 } 1386 1387 static RISCVException read_misa(CPURISCVState *env, int csrno, 1388 target_ulong *val) 1389 { 1390 target_ulong misa; 1391 1392 switch (env->misa_mxl) { 1393 case MXL_RV32: 1394 misa = (target_ulong)MXL_RV32 << 30; 1395 break; 1396 #ifdef TARGET_RISCV64 1397 case MXL_RV64: 1398 misa = (target_ulong)MXL_RV64 << 62; 1399 break; 1400 #endif 1401 default: 1402 g_assert_not_reached(); 1403 } 1404 1405 *val = misa | env->misa_ext; 1406 return RISCV_EXCP_NONE; 1407 } 1408 1409 static RISCVException write_misa(CPURISCVState *env, int csrno, 1410 target_ulong val) 1411 { 1412 RISCVCPU *cpu = env_archcpu(env); 1413 uint32_t orig_misa_ext = env->misa_ext; 1414 Error *local_err = NULL; 1415 1416 if (!riscv_cpu_cfg(env)->misa_w) { 1417 /* drop write to misa */ 1418 return RISCV_EXCP_NONE; 1419 } 1420 1421 /* Mask extensions that are not supported by this hart */ 1422 val &= env->misa_ext_mask; 1423 1424 /* 1425 * Suppress 'C' if next instruction is not aligned 1426 * TODO: this should check next_pc 1427 */ 1428 if ((val & RVC) && (GETPC() & ~3) != 0) { 1429 val &= ~RVC; 1430 } 1431 1432 /* Disable RVG if any of its dependencies are disabled */ 1433 if (!(val & RVI && val & RVM && val & RVA && 1434 val & RVF && val & RVD)) { 1435 val &= ~RVG; 1436 } 1437 1438 /* If nothing changed, do nothing. */ 1439 if (val == env->misa_ext) { 1440 return RISCV_EXCP_NONE; 1441 } 1442 1443 env->misa_ext = val; 1444 riscv_cpu_validate_set_extensions(cpu, &local_err); 1445 if (local_err != NULL) { 1446 /* Rollback on validation error */ 1447 qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value " 1448 "0x%x, keeping existing MISA ext 0x%x\n", 1449 env->misa_ext, orig_misa_ext); 1450 1451 env->misa_ext = orig_misa_ext; 1452 1453 return RISCV_EXCP_NONE; 1454 } 1455 1456 if (!(env->misa_ext & RVF)) { 1457 env->mstatus &= ~MSTATUS_FS; 1458 } 1459 1460 /* flush translation cache */ 1461 tb_flush(env_cpu(env)); 1462 env->xl = riscv_cpu_mxl(env); 1463 return RISCV_EXCP_NONE; 1464 } 1465 1466 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 1467 target_ulong *val) 1468 { 1469 *val = env->medeleg; 1470 return RISCV_EXCP_NONE; 1471 } 1472 1473 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 1474 target_ulong val) 1475 { 1476 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 1477 return RISCV_EXCP_NONE; 1478 } 1479 1480 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 1481 uint64_t *ret_val, 1482 uint64_t new_val, uint64_t wr_mask) 1483 { 1484 uint64_t mask = wr_mask & delegable_ints; 1485 1486 if (ret_val) { 1487 *ret_val = env->mideleg; 1488 } 1489 1490 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 1491 1492 if (riscv_has_ext(env, RVH)) { 1493 env->mideleg |= HS_MODE_INTERRUPTS; 1494 } 1495 1496 return RISCV_EXCP_NONE; 1497 } 1498 1499 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 1500 target_ulong *ret_val, 1501 target_ulong new_val, target_ulong wr_mask) 1502 { 1503 uint64_t rval; 1504 RISCVException ret; 1505 1506 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 1507 if (ret_val) { 1508 *ret_val = rval; 1509 } 1510 1511 return ret; 1512 } 1513 1514 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 1515 target_ulong *ret_val, 1516 target_ulong new_val, 1517 target_ulong wr_mask) 1518 { 1519 uint64_t rval; 1520 RISCVException ret; 1521 1522 ret = rmw_mideleg64(env, csrno, &rval, 1523 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1524 if (ret_val) { 1525 *ret_val = rval >> 32; 1526 } 1527 1528 return ret; 1529 } 1530 1531 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 1532 uint64_t *ret_val, 1533 uint64_t new_val, uint64_t wr_mask) 1534 { 1535 uint64_t mask = wr_mask & all_ints; 1536 1537 if (ret_val) { 1538 *ret_val = env->mie; 1539 } 1540 1541 env->mie = (env->mie & ~mask) | (new_val & mask); 1542 1543 if (!riscv_has_ext(env, RVH)) { 1544 env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS); 1545 } 1546 1547 return RISCV_EXCP_NONE; 1548 } 1549 1550 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 1551 target_ulong *ret_val, 1552 target_ulong new_val, target_ulong wr_mask) 1553 { 1554 uint64_t rval; 1555 RISCVException ret; 1556 1557 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 1558 if (ret_val) { 1559 *ret_val = rval; 1560 } 1561 1562 return ret; 1563 } 1564 1565 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 1566 target_ulong *ret_val, 1567 target_ulong new_val, target_ulong wr_mask) 1568 { 1569 uint64_t rval; 1570 RISCVException ret; 1571 1572 ret = rmw_mie64(env, csrno, &rval, 1573 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1574 if (ret_val) { 1575 *ret_val = rval >> 32; 1576 } 1577 1578 return ret; 1579 } 1580 1581 static RISCVException rmw_mvien64(CPURISCVState *env, int csrno, 1582 uint64_t *ret_val, 1583 uint64_t new_val, uint64_t wr_mask) 1584 { 1585 uint64_t mask = wr_mask & mvien_writable_mask; 1586 1587 if (ret_val) { 1588 *ret_val = env->mvien; 1589 } 1590 1591 env->mvien = (env->mvien & ~mask) | (new_val & mask); 1592 1593 return RISCV_EXCP_NONE; 1594 } 1595 1596 static RISCVException rmw_mvien(CPURISCVState *env, int csrno, 1597 target_ulong *ret_val, 1598 target_ulong new_val, target_ulong wr_mask) 1599 { 1600 uint64_t rval; 1601 RISCVException ret; 1602 1603 ret = rmw_mvien64(env, csrno, &rval, new_val, wr_mask); 1604 if (ret_val) { 1605 *ret_val = rval; 1606 } 1607 1608 return ret; 1609 } 1610 1611 static RISCVException rmw_mvienh(CPURISCVState *env, int csrno, 1612 target_ulong *ret_val, 1613 target_ulong new_val, target_ulong wr_mask) 1614 { 1615 uint64_t rval; 1616 RISCVException ret; 1617 1618 ret = rmw_mvien64(env, csrno, &rval, 1619 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1620 if (ret_val) { 1621 *ret_val = rval >> 32; 1622 } 1623 1624 return ret; 1625 } 1626 1627 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 1628 { 1629 int irq; 1630 uint8_t iprio; 1631 1632 irq = riscv_cpu_mirq_pending(env); 1633 if (irq <= 0 || irq > 63) { 1634 *val = 0; 1635 } else { 1636 iprio = env->miprio[irq]; 1637 if (!iprio) { 1638 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 1639 iprio = IPRIO_MMAXIPRIO; 1640 } 1641 } 1642 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 1643 *val |= iprio; 1644 } 1645 1646 return RISCV_EXCP_NONE; 1647 } 1648 1649 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 1650 { 1651 if (!env->virt_enabled) { 1652 return csrno; 1653 } 1654 1655 switch (csrno) { 1656 case CSR_SISELECT: 1657 return CSR_VSISELECT; 1658 case CSR_SIREG: 1659 return CSR_VSIREG; 1660 case CSR_STOPEI: 1661 return CSR_VSTOPEI; 1662 default: 1663 return csrno; 1664 }; 1665 } 1666 1667 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 1668 target_ulong new_val, target_ulong wr_mask) 1669 { 1670 target_ulong *iselect; 1671 1672 /* Translate CSR number for VS-mode */ 1673 csrno = aia_xlate_vs_csrno(env, csrno); 1674 1675 /* Find the iselect CSR based on CSR number */ 1676 switch (csrno) { 1677 case CSR_MISELECT: 1678 iselect = &env->miselect; 1679 break; 1680 case CSR_SISELECT: 1681 iselect = &env->siselect; 1682 break; 1683 case CSR_VSISELECT: 1684 iselect = &env->vsiselect; 1685 break; 1686 default: 1687 return RISCV_EXCP_ILLEGAL_INST; 1688 }; 1689 1690 if (val) { 1691 *val = *iselect; 1692 } 1693 1694 wr_mask &= ISELECT_MASK; 1695 if (wr_mask) { 1696 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1697 } 1698 1699 return RISCV_EXCP_NONE; 1700 } 1701 1702 static int rmw_iprio(target_ulong xlen, 1703 target_ulong iselect, uint8_t *iprio, 1704 target_ulong *val, target_ulong new_val, 1705 target_ulong wr_mask, int ext_irq_no) 1706 { 1707 int i, firq, nirqs; 1708 target_ulong old_val; 1709 1710 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1711 return -EINVAL; 1712 } 1713 if (xlen != 32 && iselect & 0x1) { 1714 return -EINVAL; 1715 } 1716 1717 nirqs = 4 * (xlen / 32); 1718 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1719 1720 old_val = 0; 1721 for (i = 0; i < nirqs; i++) { 1722 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1723 } 1724 1725 if (val) { 1726 *val = old_val; 1727 } 1728 1729 if (wr_mask) { 1730 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1731 for (i = 0; i < nirqs; i++) { 1732 /* 1733 * M-level and S-level external IRQ priority always read-only 1734 * zero. This means default priority order is always preferred 1735 * for M-level and S-level external IRQs. 1736 */ 1737 if ((firq + i) == ext_irq_no) { 1738 continue; 1739 } 1740 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1741 } 1742 } 1743 1744 return 0; 1745 } 1746 1747 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1748 target_ulong new_val, target_ulong wr_mask) 1749 { 1750 bool virt, isel_reserved; 1751 uint8_t *iprio; 1752 int ret = -EINVAL; 1753 target_ulong priv, isel, vgein; 1754 1755 /* Translate CSR number for VS-mode */ 1756 csrno = aia_xlate_vs_csrno(env, csrno); 1757 1758 /* Decode register details from CSR number */ 1759 virt = false; 1760 isel_reserved = false; 1761 switch (csrno) { 1762 case CSR_MIREG: 1763 iprio = env->miprio; 1764 isel = env->miselect; 1765 priv = PRV_M; 1766 break; 1767 case CSR_SIREG: 1768 if (env->priv == PRV_S && env->mvien & MIP_SEIP && 1769 env->siselect >= ISELECT_IMSIC_EIDELIVERY && 1770 env->siselect <= ISELECT_IMSIC_EIE63) { 1771 goto done; 1772 } 1773 iprio = env->siprio; 1774 isel = env->siselect; 1775 priv = PRV_S; 1776 break; 1777 case CSR_VSIREG: 1778 iprio = env->hviprio; 1779 isel = env->vsiselect; 1780 priv = PRV_S; 1781 virt = true; 1782 break; 1783 default: 1784 goto done; 1785 }; 1786 1787 /* Find the selected guest interrupt file */ 1788 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1789 1790 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1791 /* Local interrupt priority registers not available for VS-mode */ 1792 if (!virt) { 1793 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1794 isel, iprio, val, new_val, wr_mask, 1795 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1796 } 1797 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1798 /* IMSIC registers only available when machine implements it. */ 1799 if (env->aia_ireg_rmw_fn[priv]) { 1800 /* Selected guest interrupt file should not be zero */ 1801 if (virt && (!vgein || env->geilen < vgein)) { 1802 goto done; 1803 } 1804 /* Call machine specific IMSIC register emulation */ 1805 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1806 AIA_MAKE_IREG(isel, priv, virt, vgein, 1807 riscv_cpu_mxl_bits(env)), 1808 val, new_val, wr_mask); 1809 } 1810 } else { 1811 isel_reserved = true; 1812 } 1813 1814 done: 1815 if (ret) { 1816 return (env->virt_enabled && virt && !isel_reserved) ? 1817 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1818 } 1819 return RISCV_EXCP_NONE; 1820 } 1821 1822 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1823 target_ulong new_val, target_ulong wr_mask) 1824 { 1825 bool virt; 1826 int ret = -EINVAL; 1827 target_ulong priv, vgein; 1828 1829 /* Translate CSR number for VS-mode */ 1830 csrno = aia_xlate_vs_csrno(env, csrno); 1831 1832 /* Decode register details from CSR number */ 1833 virt = false; 1834 switch (csrno) { 1835 case CSR_MTOPEI: 1836 priv = PRV_M; 1837 break; 1838 case CSR_STOPEI: 1839 if (env->mvien & MIP_SEIP && env->priv == PRV_S) { 1840 goto done; 1841 } 1842 priv = PRV_S; 1843 break; 1844 case CSR_VSTOPEI: 1845 priv = PRV_S; 1846 virt = true; 1847 break; 1848 default: 1849 goto done; 1850 }; 1851 1852 /* IMSIC CSRs only available when machine implements IMSIC. */ 1853 if (!env->aia_ireg_rmw_fn[priv]) { 1854 goto done; 1855 } 1856 1857 /* Find the selected guest interrupt file */ 1858 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1859 1860 /* Selected guest interrupt file should be valid */ 1861 if (virt && (!vgein || env->geilen < vgein)) { 1862 goto done; 1863 } 1864 1865 /* Call machine specific IMSIC register emulation for TOPEI */ 1866 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1867 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1868 riscv_cpu_mxl_bits(env)), 1869 val, new_val, wr_mask); 1870 1871 done: 1872 if (ret) { 1873 return (env->virt_enabled && virt) ? 1874 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1875 } 1876 return RISCV_EXCP_NONE; 1877 } 1878 1879 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1880 target_ulong *val) 1881 { 1882 *val = env->mtvec; 1883 return RISCV_EXCP_NONE; 1884 } 1885 1886 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1887 target_ulong val) 1888 { 1889 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1890 if ((val & 3) < 2) { 1891 env->mtvec = val; 1892 } else { 1893 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1894 } 1895 return RISCV_EXCP_NONE; 1896 } 1897 1898 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, 1899 target_ulong *val) 1900 { 1901 *val = env->mcountinhibit; 1902 return RISCV_EXCP_NONE; 1903 } 1904 1905 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, 1906 target_ulong val) 1907 { 1908 int cidx; 1909 PMUCTRState *counter; 1910 RISCVCPU *cpu = env_archcpu(env); 1911 1912 /* WARL register - disable unavailable counters; TM bit is always 0 */ 1913 env->mcountinhibit = 1914 val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); 1915 1916 /* Check if any other counter is also monitoring cycles/instructions */ 1917 for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { 1918 if (!get_field(env->mcountinhibit, BIT(cidx))) { 1919 counter = &env->pmu_ctrs[cidx]; 1920 counter->started = true; 1921 } 1922 } 1923 1924 return RISCV_EXCP_NONE; 1925 } 1926 1927 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1928 target_ulong *val) 1929 { 1930 *val = env->mcounteren; 1931 return RISCV_EXCP_NONE; 1932 } 1933 1934 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1935 target_ulong val) 1936 { 1937 RISCVCPU *cpu = env_archcpu(env); 1938 1939 /* WARL register - disable unavailable counters */ 1940 env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM | 1941 COUNTEREN_IR); 1942 return RISCV_EXCP_NONE; 1943 } 1944 1945 /* Machine Trap Handling */ 1946 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1947 Int128 *val) 1948 { 1949 *val = int128_make128(env->mscratch, env->mscratchh); 1950 return RISCV_EXCP_NONE; 1951 } 1952 1953 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1954 Int128 val) 1955 { 1956 env->mscratch = int128_getlo(val); 1957 env->mscratchh = int128_gethi(val); 1958 return RISCV_EXCP_NONE; 1959 } 1960 1961 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1962 target_ulong *val) 1963 { 1964 *val = env->mscratch; 1965 return RISCV_EXCP_NONE; 1966 } 1967 1968 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1969 target_ulong val) 1970 { 1971 env->mscratch = val; 1972 return RISCV_EXCP_NONE; 1973 } 1974 1975 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1976 target_ulong *val) 1977 { 1978 *val = env->mepc; 1979 return RISCV_EXCP_NONE; 1980 } 1981 1982 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1983 target_ulong val) 1984 { 1985 env->mepc = val; 1986 return RISCV_EXCP_NONE; 1987 } 1988 1989 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1990 target_ulong *val) 1991 { 1992 *val = env->mcause; 1993 return RISCV_EXCP_NONE; 1994 } 1995 1996 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1997 target_ulong val) 1998 { 1999 env->mcause = val; 2000 return RISCV_EXCP_NONE; 2001 } 2002 2003 static RISCVException read_mtval(CPURISCVState *env, int csrno, 2004 target_ulong *val) 2005 { 2006 *val = env->mtval; 2007 return RISCV_EXCP_NONE; 2008 } 2009 2010 static RISCVException write_mtval(CPURISCVState *env, int csrno, 2011 target_ulong val) 2012 { 2013 env->mtval = val; 2014 return RISCV_EXCP_NONE; 2015 } 2016 2017 /* Execution environment configuration setup */ 2018 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 2019 target_ulong *val) 2020 { 2021 *val = env->menvcfg; 2022 return RISCV_EXCP_NONE; 2023 } 2024 2025 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 2026 target_ulong val) 2027 { 2028 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); 2029 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 2030 2031 if (riscv_cpu_mxl(env) == MXL_RV64) { 2032 mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | 2033 (cfg->ext_sstc ? MENVCFG_STCE : 0) | 2034 (cfg->ext_svadu ? MENVCFG_ADUE : 0); 2035 } 2036 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 2037 2038 return RISCV_EXCP_NONE; 2039 } 2040 2041 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 2042 target_ulong *val) 2043 { 2044 *val = env->menvcfg >> 32; 2045 return RISCV_EXCP_NONE; 2046 } 2047 2048 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 2049 target_ulong val) 2050 { 2051 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); 2052 uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | 2053 (cfg->ext_sstc ? MENVCFG_STCE : 0) | 2054 (cfg->ext_svadu ? MENVCFG_ADUE : 0); 2055 uint64_t valh = (uint64_t)val << 32; 2056 2057 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 2058 2059 return RISCV_EXCP_NONE; 2060 } 2061 2062 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 2063 target_ulong *val) 2064 { 2065 RISCVException ret; 2066 2067 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2068 if (ret != RISCV_EXCP_NONE) { 2069 return ret; 2070 } 2071 2072 *val = env->senvcfg; 2073 return RISCV_EXCP_NONE; 2074 } 2075 2076 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 2077 target_ulong val) 2078 { 2079 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 2080 RISCVException ret; 2081 2082 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2083 if (ret != RISCV_EXCP_NONE) { 2084 return ret; 2085 } 2086 2087 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 2088 return RISCV_EXCP_NONE; 2089 } 2090 2091 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 2092 target_ulong *val) 2093 { 2094 RISCVException ret; 2095 2096 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2097 if (ret != RISCV_EXCP_NONE) { 2098 return ret; 2099 } 2100 2101 /* 2102 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 2103 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 2104 * henvcfg.hade is read_only 0 when menvcfg.hade = 0 2105 */ 2106 *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | 2107 env->menvcfg); 2108 return RISCV_EXCP_NONE; 2109 } 2110 2111 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 2112 target_ulong val) 2113 { 2114 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 2115 RISCVException ret; 2116 2117 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2118 if (ret != RISCV_EXCP_NONE) { 2119 return ret; 2120 } 2121 2122 if (riscv_cpu_mxl(env) == MXL_RV64) { 2123 mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); 2124 } 2125 2126 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 2127 2128 return RISCV_EXCP_NONE; 2129 } 2130 2131 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 2132 target_ulong *val) 2133 { 2134 RISCVException ret; 2135 2136 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2137 if (ret != RISCV_EXCP_NONE) { 2138 return ret; 2139 } 2140 2141 *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | 2142 env->menvcfg)) >> 32; 2143 return RISCV_EXCP_NONE; 2144 } 2145 2146 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 2147 target_ulong val) 2148 { 2149 uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | 2150 HENVCFG_ADUE); 2151 uint64_t valh = (uint64_t)val << 32; 2152 RISCVException ret; 2153 2154 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2155 if (ret != RISCV_EXCP_NONE) { 2156 return ret; 2157 } 2158 2159 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 2160 return RISCV_EXCP_NONE; 2161 } 2162 2163 static RISCVException read_mstateen(CPURISCVState *env, int csrno, 2164 target_ulong *val) 2165 { 2166 *val = env->mstateen[csrno - CSR_MSTATEEN0]; 2167 2168 return RISCV_EXCP_NONE; 2169 } 2170 2171 static RISCVException write_mstateen(CPURISCVState *env, int csrno, 2172 uint64_t wr_mask, target_ulong new_val) 2173 { 2174 uint64_t *reg; 2175 2176 reg = &env->mstateen[csrno - CSR_MSTATEEN0]; 2177 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); 2178 2179 return RISCV_EXCP_NONE; 2180 } 2181 2182 static RISCVException write_mstateen0(CPURISCVState *env, int csrno, 2183 target_ulong new_val) 2184 { 2185 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2186 if (!riscv_has_ext(env, RVF)) { 2187 wr_mask |= SMSTATEEN0_FCSR; 2188 } 2189 2190 return write_mstateen(env, csrno, wr_mask, new_val); 2191 } 2192 2193 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, 2194 target_ulong new_val) 2195 { 2196 return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); 2197 } 2198 2199 static RISCVException read_mstateenh(CPURISCVState *env, int csrno, 2200 target_ulong *val) 2201 { 2202 *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; 2203 2204 return RISCV_EXCP_NONE; 2205 } 2206 2207 static RISCVException write_mstateenh(CPURISCVState *env, int csrno, 2208 uint64_t wr_mask, target_ulong new_val) 2209 { 2210 uint64_t *reg, val; 2211 2212 reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; 2213 val = (uint64_t)new_val << 32; 2214 val |= *reg & 0xFFFFFFFF; 2215 *reg = (*reg & ~wr_mask) | (val & wr_mask); 2216 2217 return RISCV_EXCP_NONE; 2218 } 2219 2220 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, 2221 target_ulong new_val) 2222 { 2223 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2224 2225 return write_mstateenh(env, csrno, wr_mask, new_val); 2226 } 2227 2228 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, 2229 target_ulong new_val) 2230 { 2231 return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); 2232 } 2233 2234 static RISCVException read_hstateen(CPURISCVState *env, int csrno, 2235 target_ulong *val) 2236 { 2237 int index = csrno - CSR_HSTATEEN0; 2238 2239 *val = env->hstateen[index] & env->mstateen[index]; 2240 2241 return RISCV_EXCP_NONE; 2242 } 2243 2244 static RISCVException write_hstateen(CPURISCVState *env, int csrno, 2245 uint64_t mask, target_ulong new_val) 2246 { 2247 int index = csrno - CSR_HSTATEEN0; 2248 uint64_t *reg, wr_mask; 2249 2250 reg = &env->hstateen[index]; 2251 wr_mask = env->mstateen[index] & mask; 2252 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); 2253 2254 return RISCV_EXCP_NONE; 2255 } 2256 2257 static RISCVException write_hstateen0(CPURISCVState *env, int csrno, 2258 target_ulong new_val) 2259 { 2260 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2261 2262 if (!riscv_has_ext(env, RVF)) { 2263 wr_mask |= SMSTATEEN0_FCSR; 2264 } 2265 2266 return write_hstateen(env, csrno, wr_mask, new_val); 2267 } 2268 2269 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, 2270 target_ulong new_val) 2271 { 2272 return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); 2273 } 2274 2275 static RISCVException read_hstateenh(CPURISCVState *env, int csrno, 2276 target_ulong *val) 2277 { 2278 int index = csrno - CSR_HSTATEEN0H; 2279 2280 *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); 2281 2282 return RISCV_EXCP_NONE; 2283 } 2284 2285 static RISCVException write_hstateenh(CPURISCVState *env, int csrno, 2286 uint64_t mask, target_ulong new_val) 2287 { 2288 int index = csrno - CSR_HSTATEEN0H; 2289 uint64_t *reg, wr_mask, val; 2290 2291 reg = &env->hstateen[index]; 2292 val = (uint64_t)new_val << 32; 2293 val |= *reg & 0xFFFFFFFF; 2294 wr_mask = env->mstateen[index] & mask; 2295 *reg = (*reg & ~wr_mask) | (val & wr_mask); 2296 2297 return RISCV_EXCP_NONE; 2298 } 2299 2300 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, 2301 target_ulong new_val) 2302 { 2303 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2304 2305 return write_hstateenh(env, csrno, wr_mask, new_val); 2306 } 2307 2308 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, 2309 target_ulong new_val) 2310 { 2311 return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); 2312 } 2313 2314 static RISCVException read_sstateen(CPURISCVState *env, int csrno, 2315 target_ulong *val) 2316 { 2317 bool virt = env->virt_enabled; 2318 int index = csrno - CSR_SSTATEEN0; 2319 2320 *val = env->sstateen[index] & env->mstateen[index]; 2321 if (virt) { 2322 *val &= env->hstateen[index]; 2323 } 2324 2325 return RISCV_EXCP_NONE; 2326 } 2327 2328 static RISCVException write_sstateen(CPURISCVState *env, int csrno, 2329 uint64_t mask, target_ulong new_val) 2330 { 2331 bool virt = env->virt_enabled; 2332 int index = csrno - CSR_SSTATEEN0; 2333 uint64_t wr_mask; 2334 uint64_t *reg; 2335 2336 wr_mask = env->mstateen[index] & mask; 2337 if (virt) { 2338 wr_mask &= env->hstateen[index]; 2339 } 2340 2341 reg = &env->sstateen[index]; 2342 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); 2343 2344 return RISCV_EXCP_NONE; 2345 } 2346 2347 static RISCVException write_sstateen0(CPURISCVState *env, int csrno, 2348 target_ulong new_val) 2349 { 2350 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2351 2352 if (!riscv_has_ext(env, RVF)) { 2353 wr_mask |= SMSTATEEN0_FCSR; 2354 } 2355 2356 return write_sstateen(env, csrno, wr_mask, new_val); 2357 } 2358 2359 static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno, 2360 target_ulong new_val) 2361 { 2362 return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); 2363 } 2364 2365 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 2366 uint64_t *ret_val, 2367 uint64_t new_val, uint64_t wr_mask) 2368 { 2369 uint64_t old_mip, mask = wr_mask & delegable_ints; 2370 uint32_t gin; 2371 2372 if (mask & MIP_SEIP) { 2373 env->software_seip = new_val & MIP_SEIP; 2374 new_val |= env->external_seip * MIP_SEIP; 2375 } 2376 2377 if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) && 2378 get_field(env->menvcfg, MENVCFG_STCE)) { 2379 /* sstc extension forbids STIP & VSTIP to be writeable in mip */ 2380 mask = mask & ~(MIP_STIP | MIP_VSTIP); 2381 } 2382 2383 if (mask) { 2384 old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask)); 2385 } else { 2386 old_mip = env->mip; 2387 } 2388 2389 if (csrno != CSR_HVIP) { 2390 gin = get_field(env->hstatus, HSTATUS_VGEIN); 2391 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 2392 old_mip |= env->vstime_irq ? MIP_VSTIP : 0; 2393 } 2394 2395 if (ret_val) { 2396 *ret_val = old_mip; 2397 } 2398 2399 return RISCV_EXCP_NONE; 2400 } 2401 2402 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 2403 target_ulong *ret_val, 2404 target_ulong new_val, target_ulong wr_mask) 2405 { 2406 uint64_t rval; 2407 RISCVException ret; 2408 2409 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 2410 if (ret_val) { 2411 *ret_val = rval; 2412 } 2413 2414 return ret; 2415 } 2416 2417 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 2418 target_ulong *ret_val, 2419 target_ulong new_val, target_ulong wr_mask) 2420 { 2421 uint64_t rval; 2422 RISCVException ret; 2423 2424 ret = rmw_mip64(env, csrno, &rval, 2425 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2426 if (ret_val) { 2427 *ret_val = rval >> 32; 2428 } 2429 2430 return ret; 2431 } 2432 2433 /* 2434 * The function is written for two use-cases: 2435 * 1- To access mvip csr as is for m-mode access. 2436 * 2- To access sip as a combination of mip and mvip for s-mode. 2437 * 2438 * Both report bits 1, 5, 9 and 13:63 but with the exception of 2439 * STIP being read-only zero in case of mvip when sstc extension 2440 * is present. 2441 * Also, sip needs to be read-only zero when both mideleg[i] and 2442 * mvien[i] are zero but mvip needs to be an alias of mip. 2443 */ 2444 static RISCVException rmw_mvip64(CPURISCVState *env, int csrno, 2445 uint64_t *ret_val, 2446 uint64_t new_val, uint64_t wr_mask) 2447 { 2448 RISCVCPU *cpu = env_archcpu(env); 2449 target_ulong ret_mip = 0; 2450 RISCVException ret; 2451 uint64_t old_mvip; 2452 2453 /* 2454 * mideleg[i] mvien[i] 2455 * 0 0 No delegation. mvip[i] is alias of mip[i]. 2456 * 0 1 mvip[i] becomes source of interrupt, mip bypassed. 2457 * 1 X mip[i] is source of interrupt and mvip[i] aliases 2458 * mip[i]. 2459 * 2460 * So alias condition would be for bits: 2461 * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) | 2462 * (!sstc & MIP_STIP) 2463 * 2464 * Non-alias condition will be for bits: 2465 * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien) 2466 * 2467 * alias_mask denotes the bits that come from mip nalias_mask denotes bits 2468 * that come from hvip. 2469 */ 2470 uint64_t alias_mask = ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & 2471 (env->mideleg | ~env->mvien)) | MIP_STIP; 2472 uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & 2473 (~env->mideleg & env->mvien); 2474 uint64_t wr_mask_mvip; 2475 uint64_t wr_mask_mip; 2476 2477 /* 2478 * mideleg[i] mvien[i] 2479 * 0 0 sip[i] read-only zero. 2480 * 0 1 sip[i] alias of mvip[i]. 2481 * 1 X sip[i] alias of mip[i]. 2482 * 2483 * Both alias and non-alias mask remain same for sip except for bits 2484 * which are zero in both mideleg and mvien. 2485 */ 2486 if (csrno == CSR_SIP) { 2487 /* Remove bits that are zero in both mideleg and mvien. */ 2488 alias_mask &= (env->mideleg | env->mvien); 2489 nalias_mask &= (env->mideleg | env->mvien); 2490 } 2491 2492 /* 2493 * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear 2494 * that our in mip returned value. 2495 */ 2496 if (cpu->cfg.ext_sstc && (env->priv == PRV_M) && 2497 get_field(env->menvcfg, MENVCFG_STCE)) { 2498 alias_mask &= ~MIP_STIP; 2499 } 2500 2501 wr_mask_mip = wr_mask & alias_mask & mvip_writable_mask; 2502 wr_mask_mvip = wr_mask & nalias_mask & mvip_writable_mask; 2503 2504 /* 2505 * For bits set in alias_mask, mvip needs to be alias of mip, so forward 2506 * this to rmw_mip. 2507 */ 2508 ret = rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); 2509 if (ret != RISCV_EXCP_NONE) { 2510 return ret; 2511 } 2512 2513 old_mvip = env->mvip; 2514 2515 /* 2516 * Write to mvip. Update only non-alias bits. Alias bits were updated 2517 * in mip in rmw_mip above. 2518 */ 2519 if (wr_mask_mvip) { 2520 env->mvip = (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvip); 2521 2522 /* 2523 * Given mvip is separate source from mip, we need to trigger interrupt 2524 * from here separately. Normally this happen from riscv_cpu_update_mip. 2525 */ 2526 riscv_cpu_interrupt(env); 2527 } 2528 2529 if (ret_val) { 2530 ret_mip &= alias_mask; 2531 old_mvip &= nalias_mask; 2532 2533 *ret_val = old_mvip | ret_mip; 2534 } 2535 2536 return RISCV_EXCP_NONE; 2537 } 2538 2539 static RISCVException rmw_mvip(CPURISCVState *env, int csrno, 2540 target_ulong *ret_val, 2541 target_ulong new_val, target_ulong wr_mask) 2542 { 2543 uint64_t rval; 2544 RISCVException ret; 2545 2546 ret = rmw_mvip64(env, csrno, &rval, new_val, wr_mask); 2547 if (ret_val) { 2548 *ret_val = rval; 2549 } 2550 2551 return ret; 2552 } 2553 2554 static RISCVException rmw_mviph(CPURISCVState *env, int csrno, 2555 target_ulong *ret_val, 2556 target_ulong new_val, target_ulong wr_mask) 2557 { 2558 uint64_t rval; 2559 RISCVException ret; 2560 2561 ret = rmw_mvip64(env, csrno, &rval, 2562 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2563 if (ret_val) { 2564 *ret_val = rval >> 32; 2565 } 2566 2567 return ret; 2568 } 2569 2570 /* Supervisor Trap Setup */ 2571 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 2572 Int128 *val) 2573 { 2574 uint64_t mask = sstatus_v1_10_mask; 2575 uint64_t sstatus = env->mstatus & mask; 2576 if (env->xl != MXL_RV32 || env->debugger) { 2577 mask |= SSTATUS64_UXL; 2578 } 2579 2580 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 2581 return RISCV_EXCP_NONE; 2582 } 2583 2584 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 2585 target_ulong *val) 2586 { 2587 target_ulong mask = (sstatus_v1_10_mask); 2588 if (env->xl != MXL_RV32 || env->debugger) { 2589 mask |= SSTATUS64_UXL; 2590 } 2591 /* TODO: Use SXL not MXL. */ 2592 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 2593 return RISCV_EXCP_NONE; 2594 } 2595 2596 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 2597 target_ulong val) 2598 { 2599 target_ulong mask = (sstatus_v1_10_mask); 2600 2601 if (env->xl != MXL_RV32 || env->debugger) { 2602 if ((val & SSTATUS64_UXL) != 0) { 2603 mask |= SSTATUS64_UXL; 2604 } 2605 } 2606 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 2607 return write_mstatus(env, CSR_MSTATUS, newval); 2608 } 2609 2610 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 2611 uint64_t *ret_val, 2612 uint64_t new_val, uint64_t wr_mask) 2613 { 2614 uint64_t alias_mask = (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) & 2615 env->hideleg; 2616 uint64_t nalias_mask = LOCAL_INTERRUPTS & (~env->hideleg & env->hvien); 2617 uint64_t rval, rval_vs, vsbits; 2618 uint64_t wr_mask_vsie; 2619 uint64_t wr_mask_mie; 2620 RISCVException ret; 2621 2622 /* Bring VS-level bits to correct position */ 2623 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 2624 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 2625 new_val |= vsbits << 1; 2626 2627 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 2628 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 2629 wr_mask |= vsbits << 1; 2630 2631 wr_mask_mie = wr_mask & alias_mask; 2632 wr_mask_vsie = wr_mask & nalias_mask; 2633 2634 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask_mie); 2635 2636 rval_vs = env->vsie & nalias_mask; 2637 env->vsie = (env->vsie & ~wr_mask_vsie) | (new_val & wr_mask_vsie); 2638 2639 if (ret_val) { 2640 rval &= alias_mask; 2641 vsbits = rval & VS_MODE_INTERRUPTS; 2642 rval &= ~VS_MODE_INTERRUPTS; 2643 *ret_val = rval | (vsbits >> 1) | rval_vs; 2644 } 2645 2646 return ret; 2647 } 2648 2649 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 2650 target_ulong *ret_val, 2651 target_ulong new_val, target_ulong wr_mask) 2652 { 2653 uint64_t rval; 2654 RISCVException ret; 2655 2656 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 2657 if (ret_val) { 2658 *ret_val = rval; 2659 } 2660 2661 return ret; 2662 } 2663 2664 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 2665 target_ulong *ret_val, 2666 target_ulong new_val, target_ulong wr_mask) 2667 { 2668 uint64_t rval; 2669 RISCVException ret; 2670 2671 ret = rmw_vsie64(env, csrno, &rval, 2672 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2673 if (ret_val) { 2674 *ret_val = rval >> 32; 2675 } 2676 2677 return ret; 2678 } 2679 2680 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 2681 uint64_t *ret_val, 2682 uint64_t new_val, uint64_t wr_mask) 2683 { 2684 uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & 2685 (~env->mideleg & env->mvien); 2686 uint64_t alias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->mideleg; 2687 uint64_t sie_mask = wr_mask & nalias_mask; 2688 RISCVException ret; 2689 2690 /* 2691 * mideleg[i] mvien[i] 2692 * 0 0 sie[i] read-only zero. 2693 * 0 1 sie[i] is a separate writable bit. 2694 * 1 X sie[i] alias of mie[i]. 2695 * 2696 * Both alias and non-alias mask remain same for sip except for bits 2697 * which are zero in both mideleg and mvien. 2698 */ 2699 if (env->virt_enabled) { 2700 if (env->hvictl & HVICTL_VTI) { 2701 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2702 } 2703 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 2704 if (ret_val) { 2705 *ret_val &= alias_mask; 2706 } 2707 } else { 2708 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_mask); 2709 if (ret_val) { 2710 *ret_val &= alias_mask; 2711 *ret_val |= env->sie & nalias_mask; 2712 } 2713 2714 env->sie = (env->sie & ~sie_mask) | (new_val & sie_mask); 2715 } 2716 2717 return ret; 2718 } 2719 2720 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 2721 target_ulong *ret_val, 2722 target_ulong new_val, target_ulong wr_mask) 2723 { 2724 uint64_t rval; 2725 RISCVException ret; 2726 2727 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 2728 if (ret == RISCV_EXCP_NONE && ret_val) { 2729 *ret_val = rval; 2730 } 2731 2732 return ret; 2733 } 2734 2735 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 2736 target_ulong *ret_val, 2737 target_ulong new_val, target_ulong wr_mask) 2738 { 2739 uint64_t rval; 2740 RISCVException ret; 2741 2742 ret = rmw_sie64(env, csrno, &rval, 2743 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2744 if (ret_val) { 2745 *ret_val = rval >> 32; 2746 } 2747 2748 return ret; 2749 } 2750 2751 static RISCVException read_stvec(CPURISCVState *env, int csrno, 2752 target_ulong *val) 2753 { 2754 *val = env->stvec; 2755 return RISCV_EXCP_NONE; 2756 } 2757 2758 static RISCVException write_stvec(CPURISCVState *env, int csrno, 2759 target_ulong val) 2760 { 2761 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 2762 if ((val & 3) < 2) { 2763 env->stvec = val; 2764 } else { 2765 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 2766 } 2767 return RISCV_EXCP_NONE; 2768 } 2769 2770 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 2771 target_ulong *val) 2772 { 2773 *val = env->scounteren; 2774 return RISCV_EXCP_NONE; 2775 } 2776 2777 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 2778 target_ulong val) 2779 { 2780 env->scounteren = val; 2781 return RISCV_EXCP_NONE; 2782 } 2783 2784 /* Supervisor Trap Handling */ 2785 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 2786 Int128 *val) 2787 { 2788 *val = int128_make128(env->sscratch, env->sscratchh); 2789 return RISCV_EXCP_NONE; 2790 } 2791 2792 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 2793 Int128 val) 2794 { 2795 env->sscratch = int128_getlo(val); 2796 env->sscratchh = int128_gethi(val); 2797 return RISCV_EXCP_NONE; 2798 } 2799 2800 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 2801 target_ulong *val) 2802 { 2803 *val = env->sscratch; 2804 return RISCV_EXCP_NONE; 2805 } 2806 2807 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 2808 target_ulong val) 2809 { 2810 env->sscratch = val; 2811 return RISCV_EXCP_NONE; 2812 } 2813 2814 static RISCVException read_sepc(CPURISCVState *env, int csrno, 2815 target_ulong *val) 2816 { 2817 *val = env->sepc; 2818 return RISCV_EXCP_NONE; 2819 } 2820 2821 static RISCVException write_sepc(CPURISCVState *env, int csrno, 2822 target_ulong val) 2823 { 2824 env->sepc = val; 2825 return RISCV_EXCP_NONE; 2826 } 2827 2828 static RISCVException read_scause(CPURISCVState *env, int csrno, 2829 target_ulong *val) 2830 { 2831 *val = env->scause; 2832 return RISCV_EXCP_NONE; 2833 } 2834 2835 static RISCVException write_scause(CPURISCVState *env, int csrno, 2836 target_ulong val) 2837 { 2838 env->scause = val; 2839 return RISCV_EXCP_NONE; 2840 } 2841 2842 static RISCVException read_stval(CPURISCVState *env, int csrno, 2843 target_ulong *val) 2844 { 2845 *val = env->stval; 2846 return RISCV_EXCP_NONE; 2847 } 2848 2849 static RISCVException write_stval(CPURISCVState *env, int csrno, 2850 target_ulong val) 2851 { 2852 env->stval = val; 2853 return RISCV_EXCP_NONE; 2854 } 2855 2856 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2857 uint64_t *ret_val, 2858 uint64_t new_val, uint64_t wr_mask); 2859 2860 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 2861 uint64_t *ret_val, 2862 uint64_t new_val, uint64_t wr_mask) 2863 { 2864 RISCVException ret; 2865 uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; 2866 uint64_t vsbits; 2867 2868 /* Add virtualized bits into vsip mask. */ 2869 mask |= env->hvien & ~env->hideleg; 2870 2871 /* Bring VS-level bits to correct position */ 2872 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 2873 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 2874 new_val |= vsbits << 1; 2875 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 2876 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 2877 wr_mask |= vsbits << 1; 2878 2879 ret = rmw_hvip64(env, csrno, &rval, new_val, 2880 wr_mask & mask & vsip_writable_mask); 2881 if (ret_val) { 2882 rval &= mask; 2883 vsbits = rval & VS_MODE_INTERRUPTS; 2884 rval &= ~VS_MODE_INTERRUPTS; 2885 *ret_val = rval | (vsbits >> 1); 2886 } 2887 2888 return ret; 2889 } 2890 2891 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 2892 target_ulong *ret_val, 2893 target_ulong new_val, target_ulong wr_mask) 2894 { 2895 uint64_t rval; 2896 RISCVException ret; 2897 2898 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 2899 if (ret_val) { 2900 *ret_val = rval; 2901 } 2902 2903 return ret; 2904 } 2905 2906 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 2907 target_ulong *ret_val, 2908 target_ulong new_val, target_ulong wr_mask) 2909 { 2910 uint64_t rval; 2911 RISCVException ret; 2912 2913 ret = rmw_vsip64(env, csrno, &rval, 2914 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2915 if (ret_val) { 2916 *ret_val = rval >> 32; 2917 } 2918 2919 return ret; 2920 } 2921 2922 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 2923 uint64_t *ret_val, 2924 uint64_t new_val, uint64_t wr_mask) 2925 { 2926 RISCVException ret; 2927 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; 2928 2929 if (env->virt_enabled) { 2930 if (env->hvictl & HVICTL_VTI) { 2931 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2932 } 2933 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 2934 } else { 2935 ret = rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask); 2936 } 2937 2938 if (ret_val) { 2939 *ret_val &= (env->mideleg | env->mvien) & 2940 (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); 2941 } 2942 2943 return ret; 2944 } 2945 2946 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 2947 target_ulong *ret_val, 2948 target_ulong new_val, target_ulong wr_mask) 2949 { 2950 uint64_t rval; 2951 RISCVException ret; 2952 2953 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 2954 if (ret_val) { 2955 *ret_val = rval; 2956 } 2957 2958 return ret; 2959 } 2960 2961 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 2962 target_ulong *ret_val, 2963 target_ulong new_val, target_ulong wr_mask) 2964 { 2965 uint64_t rval; 2966 RISCVException ret; 2967 2968 ret = rmw_sip64(env, csrno, &rval, 2969 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2970 if (ret_val) { 2971 *ret_val = rval >> 32; 2972 } 2973 2974 return ret; 2975 } 2976 2977 /* Supervisor Protection and Translation */ 2978 static RISCVException read_satp(CPURISCVState *env, int csrno, 2979 target_ulong *val) 2980 { 2981 if (!riscv_cpu_cfg(env)->mmu) { 2982 *val = 0; 2983 return RISCV_EXCP_NONE; 2984 } 2985 *val = env->satp; 2986 return RISCV_EXCP_NONE; 2987 } 2988 2989 static RISCVException write_satp(CPURISCVState *env, int csrno, 2990 target_ulong val) 2991 { 2992 target_ulong mask; 2993 bool vm; 2994 2995 if (!riscv_cpu_cfg(env)->mmu) { 2996 return RISCV_EXCP_NONE; 2997 } 2998 2999 if (riscv_cpu_mxl(env) == MXL_RV32) { 3000 vm = validate_vm(env, get_field(val, SATP32_MODE)); 3001 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 3002 } else { 3003 vm = validate_vm(env, get_field(val, SATP64_MODE)); 3004 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 3005 } 3006 3007 if (vm && mask) { 3008 /* 3009 * The ISA defines SATP.MODE=Bare as "no translation", but we still 3010 * pass these through QEMU's TLB emulation as it improves 3011 * performance. Flushing the TLB on SATP writes with paging 3012 * enabled avoids leaking those invalid cached mappings. 3013 */ 3014 tlb_flush(env_cpu(env)); 3015 env->satp = val; 3016 } 3017 return RISCV_EXCP_NONE; 3018 } 3019 3020 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 3021 { 3022 int irq, ret; 3023 target_ulong topei; 3024 uint64_t vseip, vsgein; 3025 uint32_t iid, iprio, hviid, hviprio, gein; 3026 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 3027 3028 gein = get_field(env->hstatus, HSTATUS_VGEIN); 3029 hviid = get_field(env->hvictl, HVICTL_IID); 3030 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 3031 3032 if (gein) { 3033 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 3034 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 3035 if (gein <= env->geilen && vseip) { 3036 siid[scount] = IRQ_S_EXT; 3037 siprio[scount] = IPRIO_MMAXIPRIO + 1; 3038 if (env->aia_ireg_rmw_fn[PRV_S]) { 3039 /* 3040 * Call machine specific IMSIC register emulation for 3041 * reading TOPEI. 3042 */ 3043 ret = env->aia_ireg_rmw_fn[PRV_S]( 3044 env->aia_ireg_rmw_fn_arg[PRV_S], 3045 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 3046 riscv_cpu_mxl_bits(env)), 3047 &topei, 0, 0); 3048 if (!ret && topei) { 3049 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 3050 } 3051 } 3052 scount++; 3053 } 3054 } else { 3055 if (hviid == IRQ_S_EXT && hviprio) { 3056 siid[scount] = IRQ_S_EXT; 3057 siprio[scount] = hviprio; 3058 scount++; 3059 } 3060 } 3061 3062 if (env->hvictl & HVICTL_VTI) { 3063 if (hviid != IRQ_S_EXT) { 3064 siid[scount] = hviid; 3065 siprio[scount] = hviprio; 3066 scount++; 3067 } 3068 } else { 3069 irq = riscv_cpu_vsirq_pending(env); 3070 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 3071 siid[scount] = irq; 3072 siprio[scount] = env->hviprio[irq]; 3073 scount++; 3074 } 3075 } 3076 3077 iid = 0; 3078 iprio = UINT_MAX; 3079 for (s = 0; s < scount; s++) { 3080 if (siprio[s] < iprio) { 3081 iid = siid[s]; 3082 iprio = siprio[s]; 3083 } 3084 } 3085 3086 if (iid) { 3087 if (env->hvictl & HVICTL_IPRIOM) { 3088 if (iprio > IPRIO_MMAXIPRIO) { 3089 iprio = IPRIO_MMAXIPRIO; 3090 } 3091 if (!iprio) { 3092 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 3093 iprio = IPRIO_MMAXIPRIO; 3094 } 3095 } 3096 } else { 3097 iprio = 1; 3098 } 3099 } else { 3100 iprio = 0; 3101 } 3102 3103 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 3104 *val |= iprio; 3105 3106 return RISCV_EXCP_NONE; 3107 } 3108 3109 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 3110 { 3111 int irq; 3112 uint8_t iprio; 3113 3114 if (env->virt_enabled) { 3115 return read_vstopi(env, CSR_VSTOPI, val); 3116 } 3117 3118 irq = riscv_cpu_sirq_pending(env); 3119 if (irq <= 0 || irq > 63) { 3120 *val = 0; 3121 } else { 3122 iprio = env->siprio[irq]; 3123 if (!iprio) { 3124 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 3125 iprio = IPRIO_MMAXIPRIO; 3126 } 3127 } 3128 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 3129 *val |= iprio; 3130 } 3131 3132 return RISCV_EXCP_NONE; 3133 } 3134 3135 /* Hypervisor Extensions */ 3136 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 3137 target_ulong *val) 3138 { 3139 *val = env->hstatus; 3140 if (riscv_cpu_mxl(env) != MXL_RV32) { 3141 /* We only support 64-bit VSXL */ 3142 *val = set_field(*val, HSTATUS_VSXL, 2); 3143 } 3144 /* We only support little endian */ 3145 *val = set_field(*val, HSTATUS_VSBE, 0); 3146 return RISCV_EXCP_NONE; 3147 } 3148 3149 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 3150 target_ulong val) 3151 { 3152 env->hstatus = val; 3153 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 3154 qemu_log_mask(LOG_UNIMP, 3155 "QEMU does not support mixed HSXLEN options."); 3156 } 3157 if (get_field(val, HSTATUS_VSBE) != 0) { 3158 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 3159 } 3160 return RISCV_EXCP_NONE; 3161 } 3162 3163 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 3164 target_ulong *val) 3165 { 3166 *val = env->hedeleg; 3167 return RISCV_EXCP_NONE; 3168 } 3169 3170 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 3171 target_ulong val) 3172 { 3173 env->hedeleg = val & vs_delegable_excps; 3174 return RISCV_EXCP_NONE; 3175 } 3176 3177 static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, 3178 uint64_t *ret_val, 3179 uint64_t new_val, uint64_t wr_mask) 3180 { 3181 uint64_t mask = wr_mask & hvien_writable_mask; 3182 3183 if (ret_val) { 3184 *ret_val = env->hvien; 3185 } 3186 3187 env->hvien = (env->hvien & ~mask) | (new_val & mask); 3188 3189 return RISCV_EXCP_NONE; 3190 } 3191 3192 static RISCVException rmw_hvien(CPURISCVState *env, int csrno, 3193 target_ulong *ret_val, 3194 target_ulong new_val, target_ulong wr_mask) 3195 { 3196 uint64_t rval; 3197 RISCVException ret; 3198 3199 ret = rmw_hvien64(env, csrno, &rval, new_val, wr_mask); 3200 if (ret_val) { 3201 *ret_val = rval; 3202 } 3203 3204 return ret; 3205 } 3206 3207 static RISCVException rmw_hvienh(CPURISCVState *env, int csrno, 3208 target_ulong *ret_val, 3209 target_ulong new_val, target_ulong wr_mask) 3210 { 3211 uint64_t rval; 3212 RISCVException ret; 3213 3214 ret = rmw_hvien64(env, csrno, &rval, 3215 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3216 if (ret_val) { 3217 *ret_val = rval >> 32; 3218 } 3219 3220 return ret; 3221 } 3222 3223 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 3224 uint64_t *ret_val, 3225 uint64_t new_val, uint64_t wr_mask) 3226 { 3227 uint64_t mask = wr_mask & vs_delegable_ints; 3228 3229 if (ret_val) { 3230 *ret_val = env->hideleg & vs_delegable_ints; 3231 } 3232 3233 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 3234 return RISCV_EXCP_NONE; 3235 } 3236 3237 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 3238 target_ulong *ret_val, 3239 target_ulong new_val, target_ulong wr_mask) 3240 { 3241 uint64_t rval; 3242 RISCVException ret; 3243 3244 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 3245 if (ret_val) { 3246 *ret_val = rval; 3247 } 3248 3249 return ret; 3250 } 3251 3252 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 3253 target_ulong *ret_val, 3254 target_ulong new_val, target_ulong wr_mask) 3255 { 3256 uint64_t rval; 3257 RISCVException ret; 3258 3259 ret = rmw_hideleg64(env, csrno, &rval, 3260 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3261 if (ret_val) { 3262 *ret_val = rval >> 32; 3263 } 3264 3265 return ret; 3266 } 3267 3268 /* 3269 * The function is written for two use-cases: 3270 * 1- To access hvip csr as is for HS-mode access. 3271 * 2- To access vsip as a combination of hvip, and mip for vs-mode. 3272 * 3273 * Both report bits 2, 6, 10 and 13:63. 3274 * vsip needs to be read-only zero when both hideleg[i] and 3275 * hvien[i] are zero. 3276 */ 3277 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 3278 uint64_t *ret_val, 3279 uint64_t new_val, uint64_t wr_mask) 3280 { 3281 RISCVException ret; 3282 uint64_t old_hvip; 3283 uint64_t ret_mip; 3284 3285 /* 3286 * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are 3287 * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and hvip[i] 3288 * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. These 3289 * bits are actually being maintained in mip so we read them from there. 3290 * This way we have a single source of truth and allows for easier 3291 * implementation. 3292 * 3293 * For bits 13:63 we have: 3294 * 3295 * hideleg[i] hvien[i] 3296 * 0 0 No delegation. vsip[i] readonly zero. 3297 * 0 1 vsip[i] is alias of hvip[i], sip bypassed. 3298 * 1 X vsip[i] is alias of sip[i], hvip bypassed. 3299 * 3300 * alias_mask denotes the bits that come from sip (mip here given we 3301 * maintain all bits there). nalias_mask denotes bits that come from 3302 * hvip. 3303 */ 3304 uint64_t alias_mask = (env->hideleg | ~env->hvien) | VS_MODE_INTERRUPTS; 3305 uint64_t nalias_mask = (~env->hideleg & env->hvien); 3306 uint64_t wr_mask_hvip; 3307 uint64_t wr_mask_mip; 3308 3309 /* 3310 * Both alias and non-alias mask remain same for vsip except: 3311 * 1- For VS* bits if they are zero in hideleg. 3312 * 2- For 13:63 bits if they are zero in both hideleg and hvien. 3313 */ 3314 if (csrno == CSR_VSIP) { 3315 /* zero-out VS* bits that are not delegated to VS mode. */ 3316 alias_mask &= (env->hideleg | ~VS_MODE_INTERRUPTS); 3317 3318 /* 3319 * zero-out 13:63 bits that are zero in both hideleg and hvien. 3320 * nalias_mask mask can not contain any VS* bits so only second 3321 * condition applies on it. 3322 */ 3323 nalias_mask &= (env->hideleg | env->hvien); 3324 alias_mask &= (env->hideleg | env->hvien); 3325 } 3326 3327 wr_mask_hvip = wr_mask & nalias_mask & hvip_writable_mask; 3328 wr_mask_mip = wr_mask & alias_mask & hvip_writable_mask; 3329 3330 /* Aliased bits, bits 10, 6, 2 need to come from mip. */ 3331 ret = rmw_mip64(env, csrno, &ret_mip, new_val, wr_mask_mip); 3332 if (ret != RISCV_EXCP_NONE) { 3333 return ret; 3334 } 3335 3336 old_hvip = env->hvip; 3337 3338 if (wr_mask_hvip) { 3339 env->hvip = (env->hvip & ~wr_mask_hvip) | (new_val & wr_mask_hvip); 3340 3341 /* 3342 * Given hvip is separate source from mip, we need to trigger interrupt 3343 * from here separately. Normally this happen from riscv_cpu_update_mip. 3344 */ 3345 riscv_cpu_interrupt(env); 3346 } 3347 3348 if (ret_val) { 3349 /* Only take VS* bits from mip. */ 3350 ret_mip &= alias_mask; 3351 3352 /* Take in non-delegated 13:63 bits from hvip. */ 3353 old_hvip &= nalias_mask; 3354 3355 *ret_val = ret_mip | old_hvip; 3356 } 3357 3358 return ret; 3359 } 3360 3361 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 3362 target_ulong *ret_val, 3363 target_ulong new_val, target_ulong wr_mask) 3364 { 3365 uint64_t rval; 3366 RISCVException ret; 3367 3368 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 3369 if (ret_val) { 3370 *ret_val = rval; 3371 } 3372 3373 return ret; 3374 } 3375 3376 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 3377 target_ulong *ret_val, 3378 target_ulong new_val, target_ulong wr_mask) 3379 { 3380 uint64_t rval; 3381 RISCVException ret; 3382 3383 ret = rmw_hvip64(env, csrno, &rval, 3384 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3385 if (ret_val) { 3386 *ret_val = rval >> 32; 3387 } 3388 3389 return ret; 3390 } 3391 3392 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 3393 target_ulong *ret_value, 3394 target_ulong new_value, target_ulong write_mask) 3395 { 3396 int ret = rmw_mip(env, csrno, ret_value, new_value, 3397 write_mask & hip_writable_mask); 3398 3399 if (ret_value) { 3400 *ret_value &= HS_MODE_INTERRUPTS; 3401 } 3402 return ret; 3403 } 3404 3405 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 3406 target_ulong *ret_val, 3407 target_ulong new_val, target_ulong wr_mask) 3408 { 3409 uint64_t rval; 3410 RISCVException ret; 3411 3412 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 3413 if (ret_val) { 3414 *ret_val = rval & HS_MODE_INTERRUPTS; 3415 } 3416 3417 return ret; 3418 } 3419 3420 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 3421 target_ulong *val) 3422 { 3423 *val = env->hcounteren; 3424 return RISCV_EXCP_NONE; 3425 } 3426 3427 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 3428 target_ulong val) 3429 { 3430 env->hcounteren = val; 3431 return RISCV_EXCP_NONE; 3432 } 3433 3434 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 3435 target_ulong *val) 3436 { 3437 if (val) { 3438 *val = env->hgeie; 3439 } 3440 return RISCV_EXCP_NONE; 3441 } 3442 3443 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 3444 target_ulong val) 3445 { 3446 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 3447 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 3448 env->hgeie = val; 3449 /* Update mip.SGEIP bit */ 3450 riscv_cpu_update_mip(env, MIP_SGEIP, 3451 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 3452 return RISCV_EXCP_NONE; 3453 } 3454 3455 static RISCVException read_htval(CPURISCVState *env, int csrno, 3456 target_ulong *val) 3457 { 3458 *val = env->htval; 3459 return RISCV_EXCP_NONE; 3460 } 3461 3462 static RISCVException write_htval(CPURISCVState *env, int csrno, 3463 target_ulong val) 3464 { 3465 env->htval = val; 3466 return RISCV_EXCP_NONE; 3467 } 3468 3469 static RISCVException read_htinst(CPURISCVState *env, int csrno, 3470 target_ulong *val) 3471 { 3472 *val = env->htinst; 3473 return RISCV_EXCP_NONE; 3474 } 3475 3476 static RISCVException write_htinst(CPURISCVState *env, int csrno, 3477 target_ulong val) 3478 { 3479 return RISCV_EXCP_NONE; 3480 } 3481 3482 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 3483 target_ulong *val) 3484 { 3485 if (val) { 3486 *val = env->hgeip; 3487 } 3488 return RISCV_EXCP_NONE; 3489 } 3490 3491 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 3492 target_ulong *val) 3493 { 3494 *val = env->hgatp; 3495 return RISCV_EXCP_NONE; 3496 } 3497 3498 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 3499 target_ulong val) 3500 { 3501 env->hgatp = val; 3502 return RISCV_EXCP_NONE; 3503 } 3504 3505 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 3506 target_ulong *val) 3507 { 3508 if (!env->rdtime_fn) { 3509 return RISCV_EXCP_ILLEGAL_INST; 3510 } 3511 3512 *val = env->htimedelta; 3513 return RISCV_EXCP_NONE; 3514 } 3515 3516 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 3517 target_ulong val) 3518 { 3519 if (!env->rdtime_fn) { 3520 return RISCV_EXCP_ILLEGAL_INST; 3521 } 3522 3523 if (riscv_cpu_mxl(env) == MXL_RV32) { 3524 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 3525 } else { 3526 env->htimedelta = val; 3527 } 3528 3529 if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { 3530 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 3531 env->htimedelta, MIP_VSTIP); 3532 } 3533 3534 return RISCV_EXCP_NONE; 3535 } 3536 3537 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 3538 target_ulong *val) 3539 { 3540 if (!env->rdtime_fn) { 3541 return RISCV_EXCP_ILLEGAL_INST; 3542 } 3543 3544 *val = env->htimedelta >> 32; 3545 return RISCV_EXCP_NONE; 3546 } 3547 3548 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 3549 target_ulong val) 3550 { 3551 if (!env->rdtime_fn) { 3552 return RISCV_EXCP_ILLEGAL_INST; 3553 } 3554 3555 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 3556 3557 if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { 3558 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 3559 env->htimedelta, MIP_VSTIP); 3560 } 3561 3562 return RISCV_EXCP_NONE; 3563 } 3564 3565 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 3566 { 3567 *val = env->hvictl; 3568 return RISCV_EXCP_NONE; 3569 } 3570 3571 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 3572 { 3573 env->hvictl = val & HVICTL_VALID_MASK; 3574 return RISCV_EXCP_NONE; 3575 } 3576 3577 static int read_hvipriox(CPURISCVState *env, int first_index, 3578 uint8_t *iprio, target_ulong *val) 3579 { 3580 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 3581 3582 /* First index has to be a multiple of number of irqs per register */ 3583 if (first_index % num_irqs) { 3584 return (env->virt_enabled) ? 3585 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 3586 } 3587 3588 /* Fill-up return value */ 3589 *val = 0; 3590 for (i = 0; i < num_irqs; i++) { 3591 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 3592 continue; 3593 } 3594 if (rdzero) { 3595 continue; 3596 } 3597 *val |= ((target_ulong)iprio[irq]) << (i * 8); 3598 } 3599 3600 return RISCV_EXCP_NONE; 3601 } 3602 3603 static int write_hvipriox(CPURISCVState *env, int first_index, 3604 uint8_t *iprio, target_ulong val) 3605 { 3606 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 3607 3608 /* First index has to be a multiple of number of irqs per register */ 3609 if (first_index % num_irqs) { 3610 return (env->virt_enabled) ? 3611 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 3612 } 3613 3614 /* Fill-up priority array */ 3615 for (i = 0; i < num_irqs; i++) { 3616 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 3617 continue; 3618 } 3619 if (rdzero) { 3620 iprio[irq] = 0; 3621 } else { 3622 iprio[irq] = (val >> (i * 8)) & 0xff; 3623 } 3624 } 3625 3626 return RISCV_EXCP_NONE; 3627 } 3628 3629 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 3630 { 3631 return read_hvipriox(env, 0, env->hviprio, val); 3632 } 3633 3634 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 3635 { 3636 return write_hvipriox(env, 0, env->hviprio, val); 3637 } 3638 3639 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 3640 { 3641 return read_hvipriox(env, 4, env->hviprio, val); 3642 } 3643 3644 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 3645 { 3646 return write_hvipriox(env, 4, env->hviprio, val); 3647 } 3648 3649 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 3650 { 3651 return read_hvipriox(env, 8, env->hviprio, val); 3652 } 3653 3654 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 3655 { 3656 return write_hvipriox(env, 8, env->hviprio, val); 3657 } 3658 3659 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 3660 { 3661 return read_hvipriox(env, 12, env->hviprio, val); 3662 } 3663 3664 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 3665 { 3666 return write_hvipriox(env, 12, env->hviprio, val); 3667 } 3668 3669 /* Virtual CSR Registers */ 3670 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 3671 target_ulong *val) 3672 { 3673 *val = env->vsstatus; 3674 return RISCV_EXCP_NONE; 3675 } 3676 3677 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 3678 target_ulong val) 3679 { 3680 uint64_t mask = (target_ulong)-1; 3681 if ((val & VSSTATUS64_UXL) == 0) { 3682 mask &= ~VSSTATUS64_UXL; 3683 } 3684 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 3685 return RISCV_EXCP_NONE; 3686 } 3687 3688 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 3689 { 3690 *val = env->vstvec; 3691 return RISCV_EXCP_NONE; 3692 } 3693 3694 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 3695 target_ulong val) 3696 { 3697 env->vstvec = val; 3698 return RISCV_EXCP_NONE; 3699 } 3700 3701 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 3702 target_ulong *val) 3703 { 3704 *val = env->vsscratch; 3705 return RISCV_EXCP_NONE; 3706 } 3707 3708 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 3709 target_ulong val) 3710 { 3711 env->vsscratch = val; 3712 return RISCV_EXCP_NONE; 3713 } 3714 3715 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 3716 target_ulong *val) 3717 { 3718 *val = env->vsepc; 3719 return RISCV_EXCP_NONE; 3720 } 3721 3722 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 3723 target_ulong val) 3724 { 3725 env->vsepc = val; 3726 return RISCV_EXCP_NONE; 3727 } 3728 3729 static RISCVException read_vscause(CPURISCVState *env, int csrno, 3730 target_ulong *val) 3731 { 3732 *val = env->vscause; 3733 return RISCV_EXCP_NONE; 3734 } 3735 3736 static RISCVException write_vscause(CPURISCVState *env, int csrno, 3737 target_ulong val) 3738 { 3739 env->vscause = val; 3740 return RISCV_EXCP_NONE; 3741 } 3742 3743 static RISCVException read_vstval(CPURISCVState *env, int csrno, 3744 target_ulong *val) 3745 { 3746 *val = env->vstval; 3747 return RISCV_EXCP_NONE; 3748 } 3749 3750 static RISCVException write_vstval(CPURISCVState *env, int csrno, 3751 target_ulong val) 3752 { 3753 env->vstval = val; 3754 return RISCV_EXCP_NONE; 3755 } 3756 3757 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 3758 target_ulong *val) 3759 { 3760 *val = env->vsatp; 3761 return RISCV_EXCP_NONE; 3762 } 3763 3764 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 3765 target_ulong val) 3766 { 3767 env->vsatp = val; 3768 return RISCV_EXCP_NONE; 3769 } 3770 3771 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 3772 target_ulong *val) 3773 { 3774 *val = env->mtval2; 3775 return RISCV_EXCP_NONE; 3776 } 3777 3778 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 3779 target_ulong val) 3780 { 3781 env->mtval2 = val; 3782 return RISCV_EXCP_NONE; 3783 } 3784 3785 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 3786 target_ulong *val) 3787 { 3788 *val = env->mtinst; 3789 return RISCV_EXCP_NONE; 3790 } 3791 3792 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 3793 target_ulong val) 3794 { 3795 env->mtinst = val; 3796 return RISCV_EXCP_NONE; 3797 } 3798 3799 /* Physical Memory Protection */ 3800 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 3801 target_ulong *val) 3802 { 3803 *val = mseccfg_csr_read(env); 3804 return RISCV_EXCP_NONE; 3805 } 3806 3807 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 3808 target_ulong val) 3809 { 3810 mseccfg_csr_write(env, val); 3811 return RISCV_EXCP_NONE; 3812 } 3813 3814 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 3815 target_ulong *val) 3816 { 3817 uint32_t reg_index = csrno - CSR_PMPCFG0; 3818 3819 *val = pmpcfg_csr_read(env, reg_index); 3820 return RISCV_EXCP_NONE; 3821 } 3822 3823 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 3824 target_ulong val) 3825 { 3826 uint32_t reg_index = csrno - CSR_PMPCFG0; 3827 3828 pmpcfg_csr_write(env, reg_index, val); 3829 return RISCV_EXCP_NONE; 3830 } 3831 3832 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 3833 target_ulong *val) 3834 { 3835 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 3836 return RISCV_EXCP_NONE; 3837 } 3838 3839 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 3840 target_ulong val) 3841 { 3842 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 3843 return RISCV_EXCP_NONE; 3844 } 3845 3846 static RISCVException read_tselect(CPURISCVState *env, int csrno, 3847 target_ulong *val) 3848 { 3849 *val = tselect_csr_read(env); 3850 return RISCV_EXCP_NONE; 3851 } 3852 3853 static RISCVException write_tselect(CPURISCVState *env, int csrno, 3854 target_ulong val) 3855 { 3856 tselect_csr_write(env, val); 3857 return RISCV_EXCP_NONE; 3858 } 3859 3860 static RISCVException read_tdata(CPURISCVState *env, int csrno, 3861 target_ulong *val) 3862 { 3863 /* return 0 in tdata1 to end the trigger enumeration */ 3864 if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { 3865 *val = 0; 3866 return RISCV_EXCP_NONE; 3867 } 3868 3869 if (!tdata_available(env, csrno - CSR_TDATA1)) { 3870 return RISCV_EXCP_ILLEGAL_INST; 3871 } 3872 3873 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 3874 return RISCV_EXCP_NONE; 3875 } 3876 3877 static RISCVException write_tdata(CPURISCVState *env, int csrno, 3878 target_ulong val) 3879 { 3880 if (!tdata_available(env, csrno - CSR_TDATA1)) { 3881 return RISCV_EXCP_ILLEGAL_INST; 3882 } 3883 3884 tdata_csr_write(env, csrno - CSR_TDATA1, val); 3885 return RISCV_EXCP_NONE; 3886 } 3887 3888 static RISCVException read_tinfo(CPURISCVState *env, int csrno, 3889 target_ulong *val) 3890 { 3891 *val = tinfo_csr_read(env); 3892 return RISCV_EXCP_NONE; 3893 } 3894 3895 /* 3896 * Functions to access Pointer Masking feature registers 3897 * We have to check if current priv lvl could modify 3898 * csr in given mode 3899 */ 3900 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 3901 { 3902 int csr_priv = get_field(csrno, 0x300); 3903 int pm_current; 3904 3905 if (env->debugger) { 3906 return false; 3907 } 3908 /* 3909 * If priv lvls differ that means we're accessing csr from higher priv lvl, 3910 * so allow the access 3911 */ 3912 if (env->priv != csr_priv) { 3913 return false; 3914 } 3915 switch (env->priv) { 3916 case PRV_M: 3917 pm_current = get_field(env->mmte, M_PM_CURRENT); 3918 break; 3919 case PRV_S: 3920 pm_current = get_field(env->mmte, S_PM_CURRENT); 3921 break; 3922 case PRV_U: 3923 pm_current = get_field(env->mmte, U_PM_CURRENT); 3924 break; 3925 default: 3926 g_assert_not_reached(); 3927 } 3928 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 3929 return !pm_current; 3930 } 3931 3932 static RISCVException read_mmte(CPURISCVState *env, int csrno, 3933 target_ulong *val) 3934 { 3935 *val = env->mmte & MMTE_MASK; 3936 return RISCV_EXCP_NONE; 3937 } 3938 3939 static RISCVException write_mmte(CPURISCVState *env, int csrno, 3940 target_ulong val) 3941 { 3942 uint64_t mstatus; 3943 target_ulong wpri_val = val & MMTE_MASK; 3944 3945 if (val != wpri_val) { 3946 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" 3947 TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x", 3948 val, "vs expected 0x", wpri_val); 3949 } 3950 /* for machine mode pm.current is hardwired to 1 */ 3951 wpri_val |= MMTE_M_PM_CURRENT; 3952 3953 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 3954 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 3955 env->mmte = wpri_val | EXT_STATUS_DIRTY; 3956 riscv_cpu_update_mask(env); 3957 3958 /* Set XS and SD bits, since PM CSRs are dirty */ 3959 mstatus = env->mstatus | MSTATUS_XS; 3960 write_mstatus(env, csrno, mstatus); 3961 return RISCV_EXCP_NONE; 3962 } 3963 3964 static RISCVException read_smte(CPURISCVState *env, int csrno, 3965 target_ulong *val) 3966 { 3967 *val = env->mmte & SMTE_MASK; 3968 return RISCV_EXCP_NONE; 3969 } 3970 3971 static RISCVException write_smte(CPURISCVState *env, int csrno, 3972 target_ulong val) 3973 { 3974 target_ulong wpri_val = val & SMTE_MASK; 3975 3976 if (val != wpri_val) { 3977 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" 3978 TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x", 3979 val, "vs expected 0x", wpri_val); 3980 } 3981 3982 /* if pm.current==0 we can't modify current PM CSRs */ 3983 if (check_pm_current_disabled(env, csrno)) { 3984 return RISCV_EXCP_NONE; 3985 } 3986 3987 wpri_val |= (env->mmte & ~SMTE_MASK); 3988 write_mmte(env, csrno, wpri_val); 3989 return RISCV_EXCP_NONE; 3990 } 3991 3992 static RISCVException read_umte(CPURISCVState *env, int csrno, 3993 target_ulong *val) 3994 { 3995 *val = env->mmte & UMTE_MASK; 3996 return RISCV_EXCP_NONE; 3997 } 3998 3999 static RISCVException write_umte(CPURISCVState *env, int csrno, 4000 target_ulong val) 4001 { 4002 target_ulong wpri_val = val & UMTE_MASK; 4003 4004 if (val != wpri_val) { 4005 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" 4006 TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x", 4007 val, "vs expected 0x", wpri_val); 4008 } 4009 4010 if (check_pm_current_disabled(env, csrno)) { 4011 return RISCV_EXCP_NONE; 4012 } 4013 4014 wpri_val |= (env->mmte & ~UMTE_MASK); 4015 write_mmte(env, csrno, wpri_val); 4016 return RISCV_EXCP_NONE; 4017 } 4018 4019 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 4020 target_ulong *val) 4021 { 4022 *val = env->mpmmask; 4023 return RISCV_EXCP_NONE; 4024 } 4025 4026 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 4027 target_ulong val) 4028 { 4029 uint64_t mstatus; 4030 4031 env->mpmmask = val; 4032 if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { 4033 env->cur_pmmask = val; 4034 } 4035 env->mmte |= EXT_STATUS_DIRTY; 4036 4037 /* Set XS and SD bits, since PM CSRs are dirty */ 4038 mstatus = env->mstatus | MSTATUS_XS; 4039 write_mstatus(env, csrno, mstatus); 4040 return RISCV_EXCP_NONE; 4041 } 4042 4043 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 4044 target_ulong *val) 4045 { 4046 *val = env->spmmask; 4047 return RISCV_EXCP_NONE; 4048 } 4049 4050 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 4051 target_ulong val) 4052 { 4053 uint64_t mstatus; 4054 4055 /* if pm.current==0 we can't modify current PM CSRs */ 4056 if (check_pm_current_disabled(env, csrno)) { 4057 return RISCV_EXCP_NONE; 4058 } 4059 env->spmmask = val; 4060 if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { 4061 env->cur_pmmask = val; 4062 if (cpu_get_xl(env, PRV_S) == MXL_RV32) { 4063 env->cur_pmmask &= UINT32_MAX; 4064 } 4065 } 4066 env->mmte |= EXT_STATUS_DIRTY; 4067 4068 /* Set XS and SD bits, since PM CSRs are dirty */ 4069 mstatus = env->mstatus | MSTATUS_XS; 4070 write_mstatus(env, csrno, mstatus); 4071 return RISCV_EXCP_NONE; 4072 } 4073 4074 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 4075 target_ulong *val) 4076 { 4077 *val = env->upmmask; 4078 return RISCV_EXCP_NONE; 4079 } 4080 4081 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 4082 target_ulong val) 4083 { 4084 uint64_t mstatus; 4085 4086 /* if pm.current==0 we can't modify current PM CSRs */ 4087 if (check_pm_current_disabled(env, csrno)) { 4088 return RISCV_EXCP_NONE; 4089 } 4090 env->upmmask = val; 4091 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { 4092 env->cur_pmmask = val; 4093 if (cpu_get_xl(env, PRV_U) == MXL_RV32) { 4094 env->cur_pmmask &= UINT32_MAX; 4095 } 4096 } 4097 env->mmte |= EXT_STATUS_DIRTY; 4098 4099 /* Set XS and SD bits, since PM CSRs are dirty */ 4100 mstatus = env->mstatus | MSTATUS_XS; 4101 write_mstatus(env, csrno, mstatus); 4102 return RISCV_EXCP_NONE; 4103 } 4104 4105 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 4106 target_ulong *val) 4107 { 4108 *val = env->mpmbase; 4109 return RISCV_EXCP_NONE; 4110 } 4111 4112 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 4113 target_ulong val) 4114 { 4115 uint64_t mstatus; 4116 4117 env->mpmbase = val; 4118 if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { 4119 env->cur_pmbase = val; 4120 } 4121 env->mmte |= EXT_STATUS_DIRTY; 4122 4123 /* Set XS and SD bits, since PM CSRs are dirty */ 4124 mstatus = env->mstatus | MSTATUS_XS; 4125 write_mstatus(env, csrno, mstatus); 4126 return RISCV_EXCP_NONE; 4127 } 4128 4129 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 4130 target_ulong *val) 4131 { 4132 *val = env->spmbase; 4133 return RISCV_EXCP_NONE; 4134 } 4135 4136 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 4137 target_ulong val) 4138 { 4139 uint64_t mstatus; 4140 4141 /* if pm.current==0 we can't modify current PM CSRs */ 4142 if (check_pm_current_disabled(env, csrno)) { 4143 return RISCV_EXCP_NONE; 4144 } 4145 env->spmbase = val; 4146 if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { 4147 env->cur_pmbase = val; 4148 if (cpu_get_xl(env, PRV_S) == MXL_RV32) { 4149 env->cur_pmbase &= UINT32_MAX; 4150 } 4151 } 4152 env->mmte |= EXT_STATUS_DIRTY; 4153 4154 /* Set XS and SD bits, since PM CSRs are dirty */ 4155 mstatus = env->mstatus | MSTATUS_XS; 4156 write_mstatus(env, csrno, mstatus); 4157 return RISCV_EXCP_NONE; 4158 } 4159 4160 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 4161 target_ulong *val) 4162 { 4163 *val = env->upmbase; 4164 return RISCV_EXCP_NONE; 4165 } 4166 4167 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 4168 target_ulong val) 4169 { 4170 uint64_t mstatus; 4171 4172 /* if pm.current==0 we can't modify current PM CSRs */ 4173 if (check_pm_current_disabled(env, csrno)) { 4174 return RISCV_EXCP_NONE; 4175 } 4176 env->upmbase = val; 4177 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { 4178 env->cur_pmbase = val; 4179 if (cpu_get_xl(env, PRV_U) == MXL_RV32) { 4180 env->cur_pmbase &= UINT32_MAX; 4181 } 4182 } 4183 env->mmte |= EXT_STATUS_DIRTY; 4184 4185 /* Set XS and SD bits, since PM CSRs are dirty */ 4186 mstatus = env->mstatus | MSTATUS_XS; 4187 write_mstatus(env, csrno, mstatus); 4188 return RISCV_EXCP_NONE; 4189 } 4190 4191 #endif 4192 4193 /* Crypto Extension */ 4194 static RISCVException rmw_seed(CPURISCVState *env, int csrno, 4195 target_ulong *ret_value, 4196 target_ulong new_value, 4197 target_ulong write_mask) 4198 { 4199 uint16_t random_v; 4200 Error *random_e = NULL; 4201 int random_r; 4202 target_ulong rval; 4203 4204 random_r = qemu_guest_getrandom(&random_v, 2, &random_e); 4205 if (unlikely(random_r < 0)) { 4206 /* 4207 * Failed, for unknown reasons in the crypto subsystem. 4208 * The best we can do is log the reason and return a 4209 * failure indication to the guest. There is no reason 4210 * we know to expect the failure to be transitory, so 4211 * indicate DEAD to avoid having the guest spin on WAIT. 4212 */ 4213 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 4214 __func__, error_get_pretty(random_e)); 4215 error_free(random_e); 4216 rval = SEED_OPST_DEAD; 4217 } else { 4218 rval = random_v | SEED_OPST_ES16; 4219 } 4220 4221 if (ret_value) { 4222 *ret_value = rval; 4223 } 4224 4225 return RISCV_EXCP_NONE; 4226 } 4227 4228 /* 4229 * riscv_csrrw - read and/or update control and status register 4230 * 4231 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 4232 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 4233 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 4234 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 4235 */ 4236 4237 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 4238 int csrno, 4239 bool write_mask) 4240 { 4241 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 4242 bool read_only = get_field(csrno, 0xC00) == 3; 4243 int csr_min_priv = csr_ops[csrno].min_priv_ver; 4244 4245 /* ensure the CSR extension is enabled */ 4246 if (!riscv_cpu_cfg(env)->ext_zicsr) { 4247 return RISCV_EXCP_ILLEGAL_INST; 4248 } 4249 4250 /* ensure CSR is implemented by checking predicate */ 4251 if (!csr_ops[csrno].predicate) { 4252 return RISCV_EXCP_ILLEGAL_INST; 4253 } 4254 4255 /* privileged spec version check */ 4256 if (env->priv_ver < csr_min_priv) { 4257 return RISCV_EXCP_ILLEGAL_INST; 4258 } 4259 4260 /* read / write check */ 4261 if (write_mask && read_only) { 4262 return RISCV_EXCP_ILLEGAL_INST; 4263 } 4264 4265 /* 4266 * The predicate() not only does existence check but also does some 4267 * access control check which triggers for example virtual instruction 4268 * exception in some cases. When writing read-only CSRs in those cases 4269 * illegal instruction exception should be triggered instead of virtual 4270 * instruction exception. Hence this comes after the read / write check. 4271 */ 4272 RISCVException ret = csr_ops[csrno].predicate(env, csrno); 4273 if (ret != RISCV_EXCP_NONE) { 4274 return ret; 4275 } 4276 4277 #if !defined(CONFIG_USER_ONLY) 4278 int csr_priv, effective_priv = env->priv; 4279 4280 if (riscv_has_ext(env, RVH) && env->priv == PRV_S && 4281 !env->virt_enabled) { 4282 /* 4283 * We are in HS mode. Add 1 to the effective privilege level to 4284 * allow us to access the Hypervisor CSRs. 4285 */ 4286 effective_priv++; 4287 } 4288 4289 csr_priv = get_field(csrno, 0x300); 4290 if (!env->debugger && (effective_priv < csr_priv)) { 4291 if (csr_priv == (PRV_S + 1) && env->virt_enabled) { 4292 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 4293 } 4294 return RISCV_EXCP_ILLEGAL_INST; 4295 } 4296 #endif 4297 return RISCV_EXCP_NONE; 4298 } 4299 4300 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 4301 target_ulong *ret_value, 4302 target_ulong new_value, 4303 target_ulong write_mask) 4304 { 4305 RISCVException ret; 4306 target_ulong old_value = 0; 4307 4308 /* execute combined read/write operation if it exists */ 4309 if (csr_ops[csrno].op) { 4310 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 4311 } 4312 4313 /* 4314 * ret_value == NULL means that rd=x0 and we're coming from helper_csrw() 4315 * and we can't throw side effects caused by CSR reads. 4316 */ 4317 if (ret_value) { 4318 /* if no accessor exists then return failure */ 4319 if (!csr_ops[csrno].read) { 4320 return RISCV_EXCP_ILLEGAL_INST; 4321 } 4322 /* read old value */ 4323 ret = csr_ops[csrno].read(env, csrno, &old_value); 4324 if (ret != RISCV_EXCP_NONE) { 4325 return ret; 4326 } 4327 } 4328 4329 /* write value if writable and write mask set, otherwise drop writes */ 4330 if (write_mask) { 4331 new_value = (old_value & ~write_mask) | (new_value & write_mask); 4332 if (csr_ops[csrno].write) { 4333 ret = csr_ops[csrno].write(env, csrno, new_value); 4334 if (ret != RISCV_EXCP_NONE) { 4335 return ret; 4336 } 4337 } 4338 } 4339 4340 /* return old value */ 4341 if (ret_value) { 4342 *ret_value = old_value; 4343 } 4344 4345 return RISCV_EXCP_NONE; 4346 } 4347 4348 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 4349 target_ulong *ret_value, 4350 target_ulong new_value, target_ulong write_mask) 4351 { 4352 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask); 4353 if (ret != RISCV_EXCP_NONE) { 4354 return ret; 4355 } 4356 4357 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 4358 } 4359 4360 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 4361 Int128 *ret_value, 4362 Int128 new_value, 4363 Int128 write_mask) 4364 { 4365 RISCVException ret; 4366 Int128 old_value; 4367 4368 /* read old value */ 4369 ret = csr_ops[csrno].read128(env, csrno, &old_value); 4370 if (ret != RISCV_EXCP_NONE) { 4371 return ret; 4372 } 4373 4374 /* write value if writable and write mask set, otherwise drop writes */ 4375 if (int128_nz(write_mask)) { 4376 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 4377 int128_and(new_value, write_mask)); 4378 if (csr_ops[csrno].write128) { 4379 ret = csr_ops[csrno].write128(env, csrno, new_value); 4380 if (ret != RISCV_EXCP_NONE) { 4381 return ret; 4382 } 4383 } else if (csr_ops[csrno].write) { 4384 /* avoids having to write wrappers for all registers */ 4385 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 4386 if (ret != RISCV_EXCP_NONE) { 4387 return ret; 4388 } 4389 } 4390 } 4391 4392 /* return old value */ 4393 if (ret_value) { 4394 *ret_value = old_value; 4395 } 4396 4397 return RISCV_EXCP_NONE; 4398 } 4399 4400 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 4401 Int128 *ret_value, 4402 Int128 new_value, Int128 write_mask) 4403 { 4404 RISCVException ret; 4405 4406 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask)); 4407 if (ret != RISCV_EXCP_NONE) { 4408 return ret; 4409 } 4410 4411 if (csr_ops[csrno].read128) { 4412 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 4413 } 4414 4415 /* 4416 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 4417 * at all defined. 4418 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 4419 * significant), for those, this fallback is correctly handling the 4420 * accesses 4421 */ 4422 target_ulong old_value; 4423 ret = riscv_csrrw_do64(env, csrno, &old_value, 4424 int128_getlo(new_value), 4425 int128_getlo(write_mask)); 4426 if (ret == RISCV_EXCP_NONE && ret_value) { 4427 *ret_value = int128_make64(old_value); 4428 } 4429 return ret; 4430 } 4431 4432 /* 4433 * Debugger support. If not in user mode, set env->debugger before the 4434 * riscv_csrrw call and clear it after the call. 4435 */ 4436 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 4437 target_ulong *ret_value, 4438 target_ulong new_value, 4439 target_ulong write_mask) 4440 { 4441 RISCVException ret; 4442 #if !defined(CONFIG_USER_ONLY) 4443 env->debugger = true; 4444 #endif 4445 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 4446 #if !defined(CONFIG_USER_ONLY) 4447 env->debugger = false; 4448 #endif 4449 return ret; 4450 } 4451 4452 static RISCVException read_jvt(CPURISCVState *env, int csrno, 4453 target_ulong *val) 4454 { 4455 *val = env->jvt; 4456 return RISCV_EXCP_NONE; 4457 } 4458 4459 static RISCVException write_jvt(CPURISCVState *env, int csrno, 4460 target_ulong val) 4461 { 4462 env->jvt = val; 4463 return RISCV_EXCP_NONE; 4464 } 4465 4466 /* 4467 * Control and Status Register function table 4468 * riscv_csr_operations::predicate() must be provided for an implemented CSR 4469 */ 4470 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 4471 /* User Floating-Point CSRs */ 4472 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 4473 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 4474 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 4475 /* Vector CSRs */ 4476 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 4477 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 4478 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 4479 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, 4480 [CSR_VL] = { "vl", vs, read_vl }, 4481 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 4482 [CSR_VLENB] = { "vlenb", vs, read_vlenb }, 4483 /* User Timers and Counters */ 4484 [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, 4485 [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, 4486 [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh }, 4487 [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh }, 4488 4489 /* 4490 * In privileged mode, the monitor will have to emulate TIME CSRs only if 4491 * rdtime callback is not provided by machine/platform emulation. 4492 */ 4493 [CSR_TIME] = { "time", ctr, read_time }, 4494 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 4495 4496 /* Crypto Extension */ 4497 [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, 4498 4499 /* Zcmt Extension */ 4500 [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt}, 4501 4502 #if !defined(CONFIG_USER_ONLY) 4503 /* Machine Timers and Counters */ 4504 [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, 4505 write_mhpmcounter }, 4506 [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, 4507 write_mhpmcounter }, 4508 [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, 4509 write_mhpmcounterh }, 4510 [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, 4511 write_mhpmcounterh }, 4512 4513 /* Machine Information Registers */ 4514 [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, 4515 [CSR_MARCHID] = { "marchid", any, read_marchid }, 4516 [CSR_MIMPID] = { "mimpid", any, read_mimpid }, 4517 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 4518 4519 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 4520 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4521 /* Machine Trap Setup */ 4522 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, 4523 NULL, read_mstatus_i128 }, 4524 [CSR_MISA] = { "misa", any, read_misa, write_misa, 4525 NULL, read_misa_i128 }, 4526 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 4527 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 4528 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 4529 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 4530 [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, 4531 write_mcounteren }, 4532 4533 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, 4534 write_mstatush }, 4535 4536 /* Machine Trap Handling */ 4537 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, 4538 NULL, read_mscratch_i128, write_mscratch_i128 }, 4539 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 4540 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 4541 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 4542 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 4543 4544 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 4545 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 4546 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 4547 4548 /* Machine-Level Interrupts (AIA) */ 4549 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 4550 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 4551 4552 /* Virtual Interrupts for Supervisor Level (AIA) */ 4553 [CSR_MVIEN] = { "mvien", aia_any, NULL, NULL, rmw_mvien }, 4554 [CSR_MVIP] = { "mvip", aia_any, NULL, NULL, rmw_mvip }, 4555 4556 /* Machine-Level High-Half CSRs (AIA) */ 4557 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 4558 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 4559 [CSR_MVIENH] = { "mvienh", aia_any32, NULL, NULL, rmw_mvienh }, 4560 [CSR_MVIPH] = { "mviph", aia_any32, NULL, NULL, rmw_mviph }, 4561 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 4562 4563 /* Execution environment configuration */ 4564 [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, 4565 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4566 [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, 4567 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4568 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 4569 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4570 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 4571 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4572 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 4573 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4574 4575 /* Smstateen extension CSRs */ 4576 [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, 4577 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4578 [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, 4579 write_mstateen0h, 4580 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4581 [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, 4582 write_mstateen_1_3, 4583 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4584 [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, 4585 write_mstateenh_1_3, 4586 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4587 [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, 4588 write_mstateen_1_3, 4589 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4590 [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, 4591 write_mstateenh_1_3, 4592 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4593 [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, 4594 write_mstateen_1_3, 4595 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4596 [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, 4597 write_mstateenh_1_3, 4598 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4599 [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0, 4600 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4601 [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh, 4602 write_hstateen0h, 4603 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4604 [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, 4605 write_hstateen_1_3, 4606 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4607 [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh, 4608 write_hstateenh_1_3, 4609 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4610 [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, 4611 write_hstateen_1_3, 4612 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4613 [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh, 4614 write_hstateenh_1_3, 4615 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4616 [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, 4617 write_hstateen_1_3, 4618 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4619 [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh, 4620 write_hstateenh_1_3, 4621 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4622 [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0, 4623 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4624 [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, 4625 write_sstateen_1_3, 4626 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4627 [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, 4628 write_sstateen_1_3, 4629 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4630 [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, 4631 write_sstateen_1_3, 4632 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4633 4634 /* Supervisor Trap Setup */ 4635 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, 4636 NULL, read_sstatus_i128 }, 4637 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 4638 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 4639 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, 4640 write_scounteren }, 4641 4642 /* Supervisor Trap Handling */ 4643 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, 4644 NULL, read_sscratch_i128, write_sscratch_i128 }, 4645 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 4646 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 4647 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 4648 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 4649 [CSR_STIMECMP] = { "stimecmp", sstc, read_stimecmp, write_stimecmp, 4650 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4651 [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph, 4652 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4653 [CSR_VSTIMECMP] = { "vstimecmp", sstc, read_vstimecmp, 4654 write_vstimecmp, 4655 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4656 [CSR_VSTIMECMPH] = { "vstimecmph", sstc_32, read_vstimecmph, 4657 write_vstimecmph, 4658 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4659 4660 /* Supervisor Protection and Translation */ 4661 [CSR_SATP] = { "satp", satp, read_satp, write_satp }, 4662 4663 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 4664 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 4665 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 4666 4667 /* Supervisor-Level Interrupts (AIA) */ 4668 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 4669 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 4670 4671 /* Supervisor-Level High-Half CSRs (AIA) */ 4672 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 4673 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 4674 4675 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 4676 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4677 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 4678 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4679 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 4680 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4681 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 4682 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4683 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 4684 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4685 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 4686 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4687 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, 4688 write_hcounteren, 4689 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4690 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 4691 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4692 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 4693 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4694 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 4695 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4696 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 4697 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4698 [CSR_HGATP] = { "hgatp", hgatp, read_hgatp, write_hgatp, 4699 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4700 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, 4701 write_htimedelta, 4702 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4703 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, 4704 write_htimedeltah, 4705 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4706 4707 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, 4708 write_vsstatus, 4709 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4710 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 4711 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4712 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 4713 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4714 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 4715 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4716 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, 4717 write_vsscratch, 4718 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4719 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 4720 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4721 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 4722 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4723 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 4724 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4725 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 4726 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4727 4728 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 4729 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4730 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 4731 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4732 4733 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 4734 [CSR_HVIEN] = { "hvien", aia_hmode, NULL, NULL, rmw_hvien }, 4735 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, 4736 write_hvictl }, 4737 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, 4738 write_hviprio1 }, 4739 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, 4740 write_hviprio2 }, 4741 /* 4742 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 4743 */ 4744 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, 4745 rmw_xiselect }, 4746 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 4747 4748 /* VS-Level Interrupts (H-extension with AIA) */ 4749 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 4750 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 4751 4752 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 4753 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, 4754 rmw_hidelegh }, 4755 [CSR_HVIENH] = { "hvienh", aia_hmode32, NULL, NULL, rmw_hvienh }, 4756 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 4757 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, 4758 write_hviprio1h }, 4759 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, 4760 write_hviprio2h }, 4761 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 4762 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 4763 4764 /* Physical Memory Protection */ 4765 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 4766 .min_priv_ver = PRIV_VERSION_1_11_0 }, 4767 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 4768 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 4769 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 4770 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 4771 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 4772 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 4773 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 4774 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 4775 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 4776 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 4777 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 4778 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 4779 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 4780 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 4781 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 4782 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 4783 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 4784 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 4785 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 4786 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 4787 4788 /* Debug CSRs */ 4789 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 4790 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 4791 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 4792 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 4793 [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, 4794 4795 /* User Pointer Masking */ 4796 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 4797 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, 4798 write_upmmask }, 4799 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, 4800 write_upmbase }, 4801 /* Machine Pointer Masking */ 4802 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 4803 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, 4804 write_mpmmask }, 4805 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, 4806 write_mpmbase }, 4807 /* Supervisor Pointer Masking */ 4808 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 4809 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, 4810 write_spmmask }, 4811 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, 4812 write_spmbase }, 4813 4814 /* Performance Counters */ 4815 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, 4816 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter }, 4817 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter }, 4818 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter }, 4819 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter }, 4820 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter }, 4821 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter }, 4822 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter }, 4823 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter }, 4824 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter }, 4825 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter }, 4826 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter }, 4827 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter }, 4828 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter }, 4829 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter }, 4830 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter }, 4831 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter }, 4832 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter }, 4833 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter }, 4834 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter }, 4835 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter }, 4836 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter }, 4837 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter }, 4838 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter }, 4839 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter }, 4840 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter }, 4841 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter }, 4842 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, 4843 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, 4844 4845 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, 4846 write_mhpmcounter }, 4847 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, 4848 write_mhpmcounter }, 4849 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, 4850 write_mhpmcounter }, 4851 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, 4852 write_mhpmcounter }, 4853 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, 4854 write_mhpmcounter }, 4855 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, 4856 write_mhpmcounter }, 4857 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, 4858 write_mhpmcounter }, 4859 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, 4860 write_mhpmcounter }, 4861 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, 4862 write_mhpmcounter }, 4863 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, 4864 write_mhpmcounter }, 4865 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, 4866 write_mhpmcounter }, 4867 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, 4868 write_mhpmcounter }, 4869 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, 4870 write_mhpmcounter }, 4871 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, 4872 write_mhpmcounter }, 4873 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, 4874 write_mhpmcounter }, 4875 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, 4876 write_mhpmcounter }, 4877 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, 4878 write_mhpmcounter }, 4879 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, 4880 write_mhpmcounter }, 4881 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, 4882 write_mhpmcounter }, 4883 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, 4884 write_mhpmcounter }, 4885 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, 4886 write_mhpmcounter }, 4887 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, 4888 write_mhpmcounter }, 4889 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, 4890 write_mhpmcounter }, 4891 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, 4892 write_mhpmcounter }, 4893 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, 4894 write_mhpmcounter }, 4895 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, 4896 write_mhpmcounter }, 4897 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, 4898 write_mhpmcounter }, 4899 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, 4900 write_mhpmcounter }, 4901 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, 4902 write_mhpmcounter }, 4903 4904 [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, 4905 write_mcountinhibit, 4906 .min_priv_ver = PRIV_VERSION_1_11_0 }, 4907 4908 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, 4909 write_mhpmevent }, 4910 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, 4911 write_mhpmevent }, 4912 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent, 4913 write_mhpmevent }, 4914 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent, 4915 write_mhpmevent }, 4916 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent, 4917 write_mhpmevent }, 4918 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent, 4919 write_mhpmevent }, 4920 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent, 4921 write_mhpmevent }, 4922 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent, 4923 write_mhpmevent }, 4924 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent, 4925 write_mhpmevent }, 4926 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent, 4927 write_mhpmevent }, 4928 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent, 4929 write_mhpmevent }, 4930 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent, 4931 write_mhpmevent }, 4932 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent, 4933 write_mhpmevent }, 4934 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent, 4935 write_mhpmevent }, 4936 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent, 4937 write_mhpmevent }, 4938 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent, 4939 write_mhpmevent }, 4940 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent, 4941 write_mhpmevent }, 4942 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent, 4943 write_mhpmevent }, 4944 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent, 4945 write_mhpmevent }, 4946 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent, 4947 write_mhpmevent }, 4948 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent, 4949 write_mhpmevent }, 4950 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent, 4951 write_mhpmevent }, 4952 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent, 4953 write_mhpmevent }, 4954 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent, 4955 write_mhpmevent }, 4956 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent, 4957 write_mhpmevent }, 4958 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent, 4959 write_mhpmevent }, 4960 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent, 4961 write_mhpmevent }, 4962 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent, 4963 write_mhpmevent }, 4964 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, 4965 write_mhpmevent }, 4966 4967 [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh, 4968 write_mhpmeventh, 4969 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4970 [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscofpmf, read_mhpmeventh, 4971 write_mhpmeventh, 4972 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4973 [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscofpmf, read_mhpmeventh, 4974 write_mhpmeventh, 4975 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4976 [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscofpmf, read_mhpmeventh, 4977 write_mhpmeventh, 4978 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4979 [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscofpmf, read_mhpmeventh, 4980 write_mhpmeventh, 4981 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4982 [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscofpmf, read_mhpmeventh, 4983 write_mhpmeventh, 4984 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4985 [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscofpmf, read_mhpmeventh, 4986 write_mhpmeventh, 4987 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4988 [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscofpmf, read_mhpmeventh, 4989 write_mhpmeventh, 4990 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4991 [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscofpmf, read_mhpmeventh, 4992 write_mhpmeventh, 4993 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4994 [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscofpmf, read_mhpmeventh, 4995 write_mhpmeventh, 4996 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4997 [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscofpmf, read_mhpmeventh, 4998 write_mhpmeventh, 4999 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5000 [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscofpmf, read_mhpmeventh, 5001 write_mhpmeventh, 5002 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5003 [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf, read_mhpmeventh, 5004 write_mhpmeventh, 5005 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5006 [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscofpmf, read_mhpmeventh, 5007 write_mhpmeventh, 5008 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5009 [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscofpmf, read_mhpmeventh, 5010 write_mhpmeventh, 5011 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5012 [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscofpmf, read_mhpmeventh, 5013 write_mhpmeventh, 5014 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5015 [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscofpmf, read_mhpmeventh, 5016 write_mhpmeventh, 5017 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5018 [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscofpmf, read_mhpmeventh, 5019 write_mhpmeventh, 5020 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5021 [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscofpmf, read_mhpmeventh, 5022 write_mhpmeventh, 5023 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5024 [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscofpmf, read_mhpmeventh, 5025 write_mhpmeventh, 5026 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5027 [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscofpmf, read_mhpmeventh, 5028 write_mhpmeventh, 5029 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5030 [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscofpmf, read_mhpmeventh, 5031 write_mhpmeventh, 5032 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5033 [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscofpmf, read_mhpmeventh, 5034 write_mhpmeventh, 5035 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5036 [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscofpmf, read_mhpmeventh, 5037 write_mhpmeventh, 5038 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5039 [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscofpmf, read_mhpmeventh, 5040 write_mhpmeventh, 5041 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5042 [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscofpmf, read_mhpmeventh, 5043 write_mhpmeventh, 5044 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5045 [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscofpmf, read_mhpmeventh, 5046 write_mhpmeventh, 5047 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5048 [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscofpmf, read_mhpmeventh, 5049 write_mhpmeventh, 5050 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5051 [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscofpmf, read_mhpmeventh, 5052 write_mhpmeventh, 5053 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5054 5055 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh }, 5056 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh }, 5057 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh }, 5058 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh }, 5059 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh }, 5060 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh }, 5061 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh }, 5062 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh }, 5063 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh }, 5064 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh }, 5065 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh }, 5066 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh }, 5067 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh }, 5068 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh }, 5069 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh }, 5070 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh }, 5071 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh }, 5072 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh }, 5073 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh }, 5074 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh }, 5075 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh }, 5076 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh }, 5077 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh }, 5078 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh }, 5079 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh }, 5080 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh }, 5081 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh }, 5082 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, 5083 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, 5084 5085 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, 5086 write_mhpmcounterh }, 5087 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, 5088 write_mhpmcounterh }, 5089 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, 5090 write_mhpmcounterh }, 5091 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, 5092 write_mhpmcounterh }, 5093 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, 5094 write_mhpmcounterh }, 5095 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, 5096 write_mhpmcounterh }, 5097 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, 5098 write_mhpmcounterh }, 5099 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, 5100 write_mhpmcounterh }, 5101 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, 5102 write_mhpmcounterh }, 5103 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, 5104 write_mhpmcounterh }, 5105 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, 5106 write_mhpmcounterh }, 5107 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, 5108 write_mhpmcounterh }, 5109 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, 5110 write_mhpmcounterh }, 5111 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, 5112 write_mhpmcounterh }, 5113 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, 5114 write_mhpmcounterh }, 5115 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, 5116 write_mhpmcounterh }, 5117 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, 5118 write_mhpmcounterh }, 5119 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, 5120 write_mhpmcounterh }, 5121 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, 5122 write_mhpmcounterh }, 5123 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, 5124 write_mhpmcounterh }, 5125 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, 5126 write_mhpmcounterh }, 5127 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, 5128 write_mhpmcounterh }, 5129 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, 5130 write_mhpmcounterh }, 5131 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, 5132 write_mhpmcounterh }, 5133 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, 5134 write_mhpmcounterh }, 5135 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, 5136 write_mhpmcounterh }, 5137 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, 5138 write_mhpmcounterh }, 5139 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, 5140 write_mhpmcounterh }, 5141 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, 5142 write_mhpmcounterh }, 5143 [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf, 5144 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5145 5146 #endif /* !CONFIG_USER_ONLY */ 5147 }; 5148