1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static int fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa & RVV)) { 43 return 0; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return -RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return 0; 50 } 51 52 static int vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa & RVV) { 55 return 0; 56 } 57 return -RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static int ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return -RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 75 get_field(env->mcounteren, HCOUNTEREN_CY)) { 76 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 81 get_field(env->mcounteren, HCOUNTEREN_TM)) { 82 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 87 get_field(env->mcounteren, HCOUNTEREN_IR)) { 88 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_is_32bit(env)) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 102 get_field(env->mcounteren, HCOUNTEREN_CY)) { 103 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 108 get_field(env->mcounteren, HCOUNTEREN_TM)) { 109 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 114 get_field(env->mcounteren, HCOUNTEREN_IR)) { 115 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return 0; 129 } 130 131 static int ctr32(CPURISCVState *env, int csrno) 132 { 133 if (!riscv_cpu_is_32bit(env)) { 134 return -RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static int any(CPURISCVState *env, int csrno) 142 { 143 return 0; 144 } 145 146 static int any32(CPURISCVState *env, int csrno) 147 { 148 if (!riscv_cpu_is_32bit(env)) { 149 return -RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static int smode(CPURISCVState *env, int csrno) 157 { 158 return -!riscv_has_ext(env, RVS); 159 } 160 161 static int hmode(CPURISCVState *env, int csrno) 162 { 163 if (riscv_has_ext(env, RVS) && 164 riscv_has_ext(env, RVH)) { 165 /* Hypervisor extension is supported */ 166 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 167 env->priv == PRV_M) { 168 return 0; 169 } else { 170 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 171 } 172 } 173 174 return -RISCV_EXCP_ILLEGAL_INST; 175 } 176 177 static int hmode32(CPURISCVState *env, int csrno) 178 { 179 if (!riscv_cpu_is_32bit(env)) { 180 return 0; 181 } 182 183 return hmode(env, csrno); 184 185 } 186 187 static int pmp(CPURISCVState *env, int csrno) 188 { 189 return -!riscv_feature(env, RISCV_FEATURE_PMP); 190 } 191 #endif 192 193 /* User Floating-Point CSRs */ 194 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 195 { 196 #if !defined(CONFIG_USER_ONLY) 197 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 198 return -RISCV_EXCP_ILLEGAL_INST; 199 } 200 #endif 201 *val = riscv_cpu_get_fflags(env); 202 return 0; 203 } 204 205 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 206 { 207 #if !defined(CONFIG_USER_ONLY) 208 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 209 return -RISCV_EXCP_ILLEGAL_INST; 210 } 211 env->mstatus |= MSTATUS_FS; 212 #endif 213 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 214 return 0; 215 } 216 217 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 218 { 219 #if !defined(CONFIG_USER_ONLY) 220 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 221 return -RISCV_EXCP_ILLEGAL_INST; 222 } 223 #endif 224 *val = env->frm; 225 return 0; 226 } 227 228 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 229 { 230 #if !defined(CONFIG_USER_ONLY) 231 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 232 return -RISCV_EXCP_ILLEGAL_INST; 233 } 234 env->mstatus |= MSTATUS_FS; 235 #endif 236 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 237 return 0; 238 } 239 240 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 244 return -RISCV_EXCP_ILLEGAL_INST; 245 } 246 #endif 247 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 248 | (env->frm << FSR_RD_SHIFT); 249 if (vs(env, csrno) >= 0) { 250 *val |= (env->vxrm << FSR_VXRM_SHIFT) 251 | (env->vxsat << FSR_VXSAT_SHIFT); 252 } 253 return 0; 254 } 255 256 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 257 { 258 #if !defined(CONFIG_USER_ONLY) 259 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 260 return -RISCV_EXCP_ILLEGAL_INST; 261 } 262 env->mstatus |= MSTATUS_FS; 263 #endif 264 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 265 if (vs(env, csrno) >= 0) { 266 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 267 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 268 } 269 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 270 return 0; 271 } 272 273 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) 274 { 275 *val = env->vtype; 276 return 0; 277 } 278 279 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) 280 { 281 *val = env->vl; 282 return 0; 283 } 284 285 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) 286 { 287 *val = env->vxrm; 288 return 0; 289 } 290 291 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) 292 { 293 env->vxrm = val; 294 return 0; 295 } 296 297 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) 298 { 299 *val = env->vxsat; 300 return 0; 301 } 302 303 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) 304 { 305 env->vxsat = val; 306 return 0; 307 } 308 309 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) 310 { 311 *val = env->vstart; 312 return 0; 313 } 314 315 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) 316 { 317 env->vstart = val; 318 return 0; 319 } 320 321 /* User Timers and Counters */ 322 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 323 { 324 #if !defined(CONFIG_USER_ONLY) 325 if (icount_enabled()) { 326 *val = icount_get(); 327 } else { 328 *val = cpu_get_host_ticks(); 329 } 330 #else 331 *val = cpu_get_host_ticks(); 332 #endif 333 return 0; 334 } 335 336 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 337 { 338 #if !defined(CONFIG_USER_ONLY) 339 if (icount_enabled()) { 340 *val = icount_get() >> 32; 341 } else { 342 *val = cpu_get_host_ticks() >> 32; 343 } 344 #else 345 *val = cpu_get_host_ticks() >> 32; 346 #endif 347 return 0; 348 } 349 350 #if defined(CONFIG_USER_ONLY) 351 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 352 { 353 *val = cpu_get_host_ticks(); 354 return 0; 355 } 356 357 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 358 { 359 *val = cpu_get_host_ticks() >> 32; 360 return 0; 361 } 362 363 #else /* CONFIG_USER_ONLY */ 364 365 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 366 { 367 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 368 369 if (!env->rdtime_fn) { 370 return -RISCV_EXCP_ILLEGAL_INST; 371 } 372 373 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 374 return 0; 375 } 376 377 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 378 { 379 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 380 381 if (!env->rdtime_fn) { 382 return -RISCV_EXCP_ILLEGAL_INST; 383 } 384 385 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 386 return 0; 387 } 388 389 /* Machine constants */ 390 391 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 392 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 393 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 394 395 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 396 VS_MODE_INTERRUPTS; 397 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 398 VS_MODE_INTERRUPTS; 399 static const target_ulong delegable_excps = 400 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 401 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 402 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 403 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 404 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 405 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 406 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 407 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 408 (1ULL << (RISCV_EXCP_U_ECALL)) | 409 (1ULL << (RISCV_EXCP_S_ECALL)) | 410 (1ULL << (RISCV_EXCP_VS_ECALL)) | 411 (1ULL << (RISCV_EXCP_M_ECALL)) | 412 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 413 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 414 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 415 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 416 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 417 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 418 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 419 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 420 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 421 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 422 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 423 static const target_ulong hip_writable_mask = MIP_VSSIP; 424 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 425 static const target_ulong vsip_writable_mask = MIP_VSSIP; 426 427 static const char valid_vm_1_10_32[16] = { 428 [VM_1_10_MBARE] = 1, 429 [VM_1_10_SV32] = 1 430 }; 431 432 static const char valid_vm_1_10_64[16] = { 433 [VM_1_10_MBARE] = 1, 434 [VM_1_10_SV39] = 1, 435 [VM_1_10_SV48] = 1, 436 [VM_1_10_SV57] = 1 437 }; 438 439 /* Machine Information Registers */ 440 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 441 { 442 return *val = 0; 443 } 444 445 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 446 { 447 *val = env->mhartid; 448 return 0; 449 } 450 451 /* Machine Trap Setup */ 452 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 453 { 454 *val = env->mstatus; 455 return 0; 456 } 457 458 static int validate_vm(CPURISCVState *env, target_ulong vm) 459 { 460 if (riscv_cpu_is_32bit(env)) { 461 return valid_vm_1_10_32[vm & 0xf]; 462 } else { 463 return valid_vm_1_10_64[vm & 0xf]; 464 } 465 } 466 467 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 468 { 469 uint64_t mstatus = env->mstatus; 470 uint64_t mask = 0; 471 int dirty; 472 473 /* flush tlb on mstatus fields that affect VM */ 474 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 475 MSTATUS_MPRV | MSTATUS_SUM)) { 476 tlb_flush(env_cpu(env)); 477 } 478 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 479 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 480 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 481 MSTATUS_TW; 482 483 if (!riscv_cpu_is_32bit(env)) { 484 /* 485 * RV32: MPV and GVA are not in mstatus. The current plan is to 486 * add them to mstatush. For now, we just don't support it. 487 */ 488 mask |= MSTATUS_MPV | MSTATUS_GVA; 489 } 490 491 mstatus = (mstatus & ~mask) | (val & mask); 492 493 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 494 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 495 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 496 env->mstatus = mstatus; 497 498 return 0; 499 } 500 501 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) 502 { 503 *val = env->mstatus >> 32; 504 return 0; 505 } 506 507 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) 508 { 509 uint64_t valh = (uint64_t)val << 32; 510 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 511 512 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 513 tlb_flush(env_cpu(env)); 514 } 515 516 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 517 518 return 0; 519 } 520 521 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 522 { 523 *val = env->misa; 524 return 0; 525 } 526 527 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 528 { 529 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 530 /* drop write to misa */ 531 return 0; 532 } 533 534 /* 'I' or 'E' must be present */ 535 if (!(val & (RVI | RVE))) { 536 /* It is not, drop write to misa */ 537 return 0; 538 } 539 540 /* 'E' excludes all other extensions */ 541 if (val & RVE) { 542 /* when we support 'E' we can do "val = RVE;" however 543 * for now we just drop writes if 'E' is present. 544 */ 545 return 0; 546 } 547 548 /* Mask extensions that are not supported by this hart */ 549 val &= env->misa_mask; 550 551 /* Mask extensions that are not supported by QEMU */ 552 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 553 554 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 555 if ((val & RVD) && !(val & RVF)) { 556 val &= ~RVD; 557 } 558 559 /* Suppress 'C' if next instruction is not aligned 560 * TODO: this should check next_pc 561 */ 562 if ((val & RVC) && (GETPC() & ~3) != 0) { 563 val &= ~RVC; 564 } 565 566 /* misa.MXL writes are not supported by QEMU */ 567 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 568 569 /* flush translation cache */ 570 if (val != env->misa) { 571 tb_flush(env_cpu(env)); 572 } 573 574 env->misa = val; 575 576 return 0; 577 } 578 579 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 580 { 581 *val = env->medeleg; 582 return 0; 583 } 584 585 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 586 { 587 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 588 return 0; 589 } 590 591 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 592 { 593 *val = env->mideleg; 594 return 0; 595 } 596 597 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 598 { 599 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 600 if (riscv_has_ext(env, RVH)) { 601 env->mideleg |= VS_MODE_INTERRUPTS; 602 } 603 return 0; 604 } 605 606 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 607 { 608 *val = env->mie; 609 return 0; 610 } 611 612 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 613 { 614 env->mie = (env->mie & ~all_ints) | (val & all_ints); 615 return 0; 616 } 617 618 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 619 { 620 *val = env->mtvec; 621 return 0; 622 } 623 624 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 625 { 626 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 627 if ((val & 3) < 2) { 628 env->mtvec = val; 629 } else { 630 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 631 } 632 return 0; 633 } 634 635 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 636 { 637 *val = env->mcounteren; 638 return 0; 639 } 640 641 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 642 { 643 env->mcounteren = val; 644 return 0; 645 } 646 647 /* Machine Trap Handling */ 648 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 649 { 650 *val = env->mscratch; 651 return 0; 652 } 653 654 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 655 { 656 env->mscratch = val; 657 return 0; 658 } 659 660 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 661 { 662 *val = env->mepc; 663 return 0; 664 } 665 666 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 667 { 668 env->mepc = val; 669 return 0; 670 } 671 672 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 673 { 674 *val = env->mcause; 675 return 0; 676 } 677 678 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 679 { 680 env->mcause = val; 681 return 0; 682 } 683 684 static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val) 685 { 686 *val = env->mtval; 687 return 0; 688 } 689 690 static int write_mtval(CPURISCVState *env, int csrno, target_ulong val) 691 { 692 env->mtval = val; 693 return 0; 694 } 695 696 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 697 target_ulong new_value, target_ulong write_mask) 698 { 699 RISCVCPU *cpu = env_archcpu(env); 700 /* Allow software control of delegable interrupts not claimed by hardware */ 701 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 702 uint32_t old_mip; 703 704 if (mask) { 705 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 706 } else { 707 old_mip = env->mip; 708 } 709 710 if (ret_value) { 711 *ret_value = old_mip; 712 } 713 714 return 0; 715 } 716 717 /* Supervisor Trap Setup */ 718 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 719 { 720 target_ulong mask = (sstatus_v1_10_mask); 721 *val = env->mstatus & mask; 722 return 0; 723 } 724 725 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 726 { 727 target_ulong mask = (sstatus_v1_10_mask); 728 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 729 return write_mstatus(env, CSR_MSTATUS, newval); 730 } 731 732 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) 733 { 734 /* Shift the VS bits to their S bit location in vsie */ 735 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 736 return 0; 737 } 738 739 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 740 { 741 if (riscv_cpu_virt_enabled(env)) { 742 read_vsie(env, CSR_VSIE, val); 743 } else { 744 *val = env->mie & env->mideleg; 745 } 746 return 0; 747 } 748 749 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) 750 { 751 /* Shift the S bits to their VS bit location in mie */ 752 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 753 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 754 return write_mie(env, CSR_MIE, newval); 755 } 756 757 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 758 { 759 if (riscv_cpu_virt_enabled(env)) { 760 write_vsie(env, CSR_VSIE, val); 761 } else { 762 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 763 (val & S_MODE_INTERRUPTS); 764 write_mie(env, CSR_MIE, newval); 765 } 766 767 return 0; 768 } 769 770 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 771 { 772 *val = env->stvec; 773 return 0; 774 } 775 776 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 777 { 778 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 779 if ((val & 3) < 2) { 780 env->stvec = val; 781 } else { 782 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 783 } 784 return 0; 785 } 786 787 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 788 { 789 *val = env->scounteren; 790 return 0; 791 } 792 793 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 794 { 795 env->scounteren = val; 796 return 0; 797 } 798 799 /* Supervisor Trap Handling */ 800 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 801 { 802 *val = env->sscratch; 803 return 0; 804 } 805 806 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 807 { 808 env->sscratch = val; 809 return 0; 810 } 811 812 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 813 { 814 *val = env->sepc; 815 return 0; 816 } 817 818 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 819 { 820 env->sepc = val; 821 return 0; 822 } 823 824 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 825 { 826 *val = env->scause; 827 return 0; 828 } 829 830 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 831 { 832 env->scause = val; 833 return 0; 834 } 835 836 static int read_stval(CPURISCVState *env, int csrno, target_ulong *val) 837 { 838 *val = env->stval; 839 return 0; 840 } 841 842 static int write_stval(CPURISCVState *env, int csrno, target_ulong val) 843 { 844 env->stval = val; 845 return 0; 846 } 847 848 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, 849 target_ulong new_value, target_ulong write_mask) 850 { 851 /* Shift the S bits to their VS bit location in mip */ 852 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 853 (write_mask << 1) & vsip_writable_mask & env->hideleg); 854 *ret_value &= VS_MODE_INTERRUPTS; 855 /* Shift the VS bits to their S bit location in vsip */ 856 *ret_value >>= 1; 857 return ret; 858 } 859 860 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 861 target_ulong new_value, target_ulong write_mask) 862 { 863 int ret; 864 865 if (riscv_cpu_virt_enabled(env)) { 866 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 867 } else { 868 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 869 write_mask & env->mideleg & sip_writable_mask); 870 } 871 872 *ret_value &= env->mideleg; 873 return ret; 874 } 875 876 /* Supervisor Protection and Translation */ 877 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 878 { 879 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 880 *val = 0; 881 return 0; 882 } 883 884 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 885 return -RISCV_EXCP_ILLEGAL_INST; 886 } else { 887 *val = env->satp; 888 } 889 890 return 0; 891 } 892 893 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 894 { 895 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 896 return 0; 897 } 898 if (validate_vm(env, get_field(val, SATP_MODE)) && 899 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 900 { 901 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 902 return -RISCV_EXCP_ILLEGAL_INST; 903 } else { 904 if ((val ^ env->satp) & SATP_ASID) { 905 tlb_flush(env_cpu(env)); 906 } 907 env->satp = val; 908 } 909 } 910 return 0; 911 } 912 913 /* Hypervisor Extensions */ 914 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) 915 { 916 *val = env->hstatus; 917 if (!riscv_cpu_is_32bit(env)) { 918 /* We only support 64-bit VSXL */ 919 *val = set_field(*val, HSTATUS_VSXL, 2); 920 } 921 /* We only support little endian */ 922 *val = set_field(*val, HSTATUS_VSBE, 0); 923 return 0; 924 } 925 926 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) 927 { 928 env->hstatus = val; 929 if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { 930 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 931 } 932 if (get_field(val, HSTATUS_VSBE) != 0) { 933 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 934 } 935 return 0; 936 } 937 938 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) 939 { 940 *val = env->hedeleg; 941 return 0; 942 } 943 944 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) 945 { 946 env->hedeleg = val; 947 return 0; 948 } 949 950 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) 951 { 952 *val = env->hideleg; 953 return 0; 954 } 955 956 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) 957 { 958 env->hideleg = val; 959 return 0; 960 } 961 962 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, 963 target_ulong new_value, target_ulong write_mask) 964 { 965 int ret = rmw_mip(env, 0, ret_value, new_value, 966 write_mask & hvip_writable_mask); 967 968 *ret_value &= hvip_writable_mask; 969 970 return ret; 971 } 972 973 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, 974 target_ulong new_value, target_ulong write_mask) 975 { 976 int ret = rmw_mip(env, 0, ret_value, new_value, 977 write_mask & hip_writable_mask); 978 979 *ret_value &= hip_writable_mask; 980 981 return ret; 982 } 983 984 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) 985 { 986 *val = env->mie & VS_MODE_INTERRUPTS; 987 return 0; 988 } 989 990 static int write_hie(CPURISCVState *env, int csrno, target_ulong val) 991 { 992 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 993 return write_mie(env, CSR_MIE, newval); 994 } 995 996 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val) 997 { 998 *val = env->hcounteren; 999 return 0; 1000 } 1001 1002 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) 1003 { 1004 env->hcounteren = val; 1005 return 0; 1006 } 1007 1008 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) 1009 { 1010 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1011 return 0; 1012 } 1013 1014 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) 1015 { 1016 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1017 return 0; 1018 } 1019 1020 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) 1021 { 1022 *val = env->htval; 1023 return 0; 1024 } 1025 1026 static int write_htval(CPURISCVState *env, int csrno, target_ulong val) 1027 { 1028 env->htval = val; 1029 return 0; 1030 } 1031 1032 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) 1033 { 1034 *val = env->htinst; 1035 return 0; 1036 } 1037 1038 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) 1039 { 1040 return 0; 1041 } 1042 1043 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) 1044 { 1045 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1046 return 0; 1047 } 1048 1049 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) 1050 { 1051 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1052 return 0; 1053 } 1054 1055 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) 1056 { 1057 *val = env->hgatp; 1058 return 0; 1059 } 1060 1061 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) 1062 { 1063 env->hgatp = val; 1064 return 0; 1065 } 1066 1067 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val) 1068 { 1069 if (!env->rdtime_fn) { 1070 return -RISCV_EXCP_ILLEGAL_INST; 1071 } 1072 1073 *val = env->htimedelta; 1074 return 0; 1075 } 1076 1077 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) 1078 { 1079 if (!env->rdtime_fn) { 1080 return -RISCV_EXCP_ILLEGAL_INST; 1081 } 1082 1083 if (riscv_cpu_is_32bit(env)) { 1084 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1085 } else { 1086 env->htimedelta = val; 1087 } 1088 return 0; 1089 } 1090 1091 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) 1092 { 1093 if (!env->rdtime_fn) { 1094 return -RISCV_EXCP_ILLEGAL_INST; 1095 } 1096 1097 *val = env->htimedelta >> 32; 1098 return 0; 1099 } 1100 1101 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) 1102 { 1103 if (!env->rdtime_fn) { 1104 return -RISCV_EXCP_ILLEGAL_INST; 1105 } 1106 1107 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1108 return 0; 1109 } 1110 1111 /* Virtual CSR Registers */ 1112 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) 1113 { 1114 *val = env->vsstatus; 1115 return 0; 1116 } 1117 1118 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) 1119 { 1120 uint64_t mask = (target_ulong)-1; 1121 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1122 return 0; 1123 } 1124 1125 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1126 { 1127 *val = env->vstvec; 1128 return 0; 1129 } 1130 1131 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) 1132 { 1133 env->vstvec = val; 1134 return 0; 1135 } 1136 1137 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) 1138 { 1139 *val = env->vsscratch; 1140 return 0; 1141 } 1142 1143 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) 1144 { 1145 env->vsscratch = val; 1146 return 0; 1147 } 1148 1149 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) 1150 { 1151 *val = env->vsepc; 1152 return 0; 1153 } 1154 1155 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) 1156 { 1157 env->vsepc = val; 1158 return 0; 1159 } 1160 1161 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) 1162 { 1163 *val = env->vscause; 1164 return 0; 1165 } 1166 1167 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) 1168 { 1169 env->vscause = val; 1170 return 0; 1171 } 1172 1173 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) 1174 { 1175 *val = env->vstval; 1176 return 0; 1177 } 1178 1179 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) 1180 { 1181 env->vstval = val; 1182 return 0; 1183 } 1184 1185 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) 1186 { 1187 *val = env->vsatp; 1188 return 0; 1189 } 1190 1191 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) 1192 { 1193 env->vsatp = val; 1194 return 0; 1195 } 1196 1197 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) 1198 { 1199 *val = env->mtval2; 1200 return 0; 1201 } 1202 1203 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) 1204 { 1205 env->mtval2 = val; 1206 return 0; 1207 } 1208 1209 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) 1210 { 1211 *val = env->mtinst; 1212 return 0; 1213 } 1214 1215 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) 1216 { 1217 env->mtinst = val; 1218 return 0; 1219 } 1220 1221 /* Physical Memory Protection */ 1222 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 1223 { 1224 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1225 return 0; 1226 } 1227 1228 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 1229 { 1230 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1231 return 0; 1232 } 1233 1234 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 1235 { 1236 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1237 return 0; 1238 } 1239 1240 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 1241 { 1242 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1243 return 0; 1244 } 1245 1246 #endif 1247 1248 /* 1249 * riscv_csrrw - read and/or update control and status register 1250 * 1251 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1252 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1253 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1254 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1255 */ 1256 1257 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 1258 target_ulong new_value, target_ulong write_mask) 1259 { 1260 int ret; 1261 target_ulong old_value; 1262 RISCVCPU *cpu = env_archcpu(env); 1263 1264 /* check privileges and return -1 if check fails */ 1265 #if !defined(CONFIG_USER_ONLY) 1266 int effective_priv = env->priv; 1267 int read_only = get_field(csrno, 0xC00) == 3; 1268 1269 if (riscv_has_ext(env, RVH) && 1270 env->priv == PRV_S && 1271 !riscv_cpu_virt_enabled(env)) { 1272 /* 1273 * We are in S mode without virtualisation, therefore we are in HS Mode. 1274 * Add 1 to the effective privledge level to allow us to access the 1275 * Hypervisor CSRs. 1276 */ 1277 effective_priv++; 1278 } 1279 1280 if ((write_mask && read_only) || 1281 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1282 return -RISCV_EXCP_ILLEGAL_INST; 1283 } 1284 #endif 1285 1286 /* ensure the CSR extension is enabled. */ 1287 if (!cpu->cfg.ext_icsr) { 1288 return -RISCV_EXCP_ILLEGAL_INST; 1289 } 1290 1291 /* check predicate */ 1292 if (!csr_ops[csrno].predicate) { 1293 return -RISCV_EXCP_ILLEGAL_INST; 1294 } 1295 ret = csr_ops[csrno].predicate(env, csrno); 1296 if (ret < 0) { 1297 return ret; 1298 } 1299 1300 /* execute combined read/write operation if it exists */ 1301 if (csr_ops[csrno].op) { 1302 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1303 } 1304 1305 /* if no accessor exists then return failure */ 1306 if (!csr_ops[csrno].read) { 1307 return -RISCV_EXCP_ILLEGAL_INST; 1308 } 1309 1310 /* read old value */ 1311 ret = csr_ops[csrno].read(env, csrno, &old_value); 1312 if (ret < 0) { 1313 return ret; 1314 } 1315 1316 /* write value if writable and write mask set, otherwise drop writes */ 1317 if (write_mask) { 1318 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1319 if (csr_ops[csrno].write) { 1320 ret = csr_ops[csrno].write(env, csrno, new_value); 1321 if (ret < 0) { 1322 return ret; 1323 } 1324 } 1325 } 1326 1327 /* return old value */ 1328 if (ret_value) { 1329 *ret_value = old_value; 1330 } 1331 1332 return 0; 1333 } 1334 1335 /* 1336 * Debugger support. If not in user mode, set env->debugger before the 1337 * riscv_csrrw call and clear it after the call. 1338 */ 1339 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 1340 target_ulong new_value, target_ulong write_mask) 1341 { 1342 int ret; 1343 #if !defined(CONFIG_USER_ONLY) 1344 env->debugger = true; 1345 #endif 1346 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1347 #if !defined(CONFIG_USER_ONLY) 1348 env->debugger = false; 1349 #endif 1350 return ret; 1351 } 1352 1353 /* Control and Status Register function table */ 1354 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1355 /* User Floating-Point CSRs */ 1356 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1357 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1358 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1359 /* Vector CSRs */ 1360 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1361 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1362 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1363 [CSR_VL] = { "vl", vs, read_vl }, 1364 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1365 /* User Timers and Counters */ 1366 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1367 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1368 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1369 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1370 1371 /* 1372 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1373 * rdtime callback is not provided by machine/platform emulation. 1374 */ 1375 [CSR_TIME] = { "time", ctr, read_time }, 1376 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1377 1378 #if !defined(CONFIG_USER_ONLY) 1379 /* Machine Timers and Counters */ 1380 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1381 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1382 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1383 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1384 1385 /* Machine Information Registers */ 1386 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1387 [CSR_MARCHID] = { "marchid", any, read_zero }, 1388 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1389 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1390 1391 /* Machine Trap Setup */ 1392 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1393 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1394 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1395 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1396 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1397 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1398 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1399 1400 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1401 1402 /* Machine Trap Handling */ 1403 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1404 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1405 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1406 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1407 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1408 1409 /* Supervisor Trap Setup */ 1410 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1411 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1412 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1413 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1414 1415 /* Supervisor Trap Handling */ 1416 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1417 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1418 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1419 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1420 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1421 1422 /* Supervisor Protection and Translation */ 1423 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1424 1425 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1426 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1427 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1428 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1429 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1430 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1431 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1432 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, 1433 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1434 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1435 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, 1436 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1437 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1438 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1439 1440 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1441 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1442 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1443 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1444 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1445 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1446 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1447 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1448 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1449 1450 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1451 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1452 1453 /* Physical Memory Protection */ 1454 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1455 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1456 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1457 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1458 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1459 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1460 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1461 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1462 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1463 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1464 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1465 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1466 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1467 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1468 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1469 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1470 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1471 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1472 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1473 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1474 1475 /* Performance Counters */ 1476 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1477 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1478 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1479 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1480 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1481 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1482 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1483 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1484 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1485 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1486 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1487 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1488 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1489 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1490 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1491 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1492 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1493 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1494 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1495 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1496 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1497 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1498 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1499 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1500 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1501 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1502 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1503 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1504 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1505 1506 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1507 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1508 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1509 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1510 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1511 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1512 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1513 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1514 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1515 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1516 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1517 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 1518 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 1519 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 1520 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 1521 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 1522 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 1523 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 1524 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 1525 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 1526 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 1527 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 1528 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 1529 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 1530 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 1531 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 1532 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 1533 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 1534 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 1535 1536 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 1537 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 1538 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 1539 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 1540 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 1541 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 1542 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 1543 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 1544 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 1545 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 1546 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 1547 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 1548 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 1549 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 1550 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 1551 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 1552 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 1553 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 1554 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 1555 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 1556 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 1557 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 1558 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 1559 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 1560 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 1561 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 1562 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 1563 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 1564 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 1565 1566 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 1567 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 1568 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 1569 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 1570 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 1571 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 1572 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 1573 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 1574 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 1575 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 1576 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 1577 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 1578 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 1579 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 1580 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 1581 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 1582 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 1583 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 1584 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 1585 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 1586 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 1587 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 1588 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 1589 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 1590 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 1591 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 1592 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 1593 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 1594 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 1595 1596 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 1597 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 1598 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 1599 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 1600 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 1601 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 1602 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 1603 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 1604 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 1605 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 1606 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 1607 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 1608 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 1609 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 1610 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 1611 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 1612 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 1613 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 1614 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 1615 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 1616 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 1617 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 1618 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 1619 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 1620 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 1621 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 1622 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 1623 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 1624 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 1625 #endif /* !CONFIG_USER_ONLY */ 1626 }; 1627