1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "qemu/main-loop.h" 25 #include "exec/exec-all.h" 26 #include "sysemu/cpu-timers.h" 27 #include "qemu/guest-random.h" 28 #include "qapi/error.h" 29 30 /* CSR function table public API */ 31 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 32 { 33 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 34 } 35 36 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 37 { 38 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 39 } 40 41 /* Predicates */ 42 static RISCVException fs(CPURISCVState *env, int csrno) 43 { 44 #if !defined(CONFIG_USER_ONLY) 45 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 46 !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 47 return RISCV_EXCP_ILLEGAL_INST; 48 } 49 #endif 50 return RISCV_EXCP_NONE; 51 } 52 53 static RISCVException vs(CPURISCVState *env, int csrno) 54 { 55 CPUState *cs = env_cpu(env); 56 RISCVCPU *cpu = RISCV_CPU(cs); 57 58 if (env->misa_ext & RVV || 59 cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 60 #if !defined(CONFIG_USER_ONLY) 61 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 62 return RISCV_EXCP_ILLEGAL_INST; 63 } 64 #endif 65 return RISCV_EXCP_NONE; 66 } 67 return RISCV_EXCP_ILLEGAL_INST; 68 } 69 70 static RISCVException ctr(CPURISCVState *env, int csrno) 71 { 72 #if !defined(CONFIG_USER_ONLY) 73 CPUState *cs = env_cpu(env); 74 RISCVCPU *cpu = RISCV_CPU(cs); 75 int ctr_index; 76 77 if (!cpu->cfg.ext_counters) { 78 /* The Counters extensions is not enabled */ 79 return RISCV_EXCP_ILLEGAL_INST; 80 } 81 82 if (env->priv == PRV_S) { 83 switch (csrno) { 84 case CSR_CYCLE: 85 if (!get_field(env->mcounteren, COUNTEREN_CY)) { 86 return RISCV_EXCP_ILLEGAL_INST; 87 } 88 break; 89 case CSR_TIME: 90 if (!get_field(env->mcounteren, COUNTEREN_TM)) { 91 return RISCV_EXCP_ILLEGAL_INST; 92 } 93 break; 94 case CSR_INSTRET: 95 if (!get_field(env->mcounteren, COUNTEREN_IR)) { 96 return RISCV_EXCP_ILLEGAL_INST; 97 } 98 break; 99 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 100 ctr_index = csrno - CSR_CYCLE; 101 if (!get_field(env->mcounteren, 1 << ctr_index)) { 102 return RISCV_EXCP_ILLEGAL_INST; 103 } 104 break; 105 } 106 if (riscv_cpu_mxl(env) == MXL_RV32) { 107 switch (csrno) { 108 case CSR_CYCLEH: 109 if (!get_field(env->mcounteren, COUNTEREN_CY)) { 110 return RISCV_EXCP_ILLEGAL_INST; 111 } 112 break; 113 case CSR_TIMEH: 114 if (!get_field(env->mcounteren, COUNTEREN_TM)) { 115 return RISCV_EXCP_ILLEGAL_INST; 116 } 117 break; 118 case CSR_INSTRETH: 119 if (!get_field(env->mcounteren, COUNTEREN_IR)) { 120 return RISCV_EXCP_ILLEGAL_INST; 121 } 122 break; 123 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 124 ctr_index = csrno - CSR_CYCLEH; 125 if (!get_field(env->mcounteren, 1 << ctr_index)) { 126 return RISCV_EXCP_ILLEGAL_INST; 127 } 128 break; 129 } 130 } 131 } 132 133 if (riscv_cpu_virt_enabled(env)) { 134 switch (csrno) { 135 case CSR_CYCLE: 136 if (!get_field(env->hcounteren, COUNTEREN_CY) && 137 get_field(env->mcounteren, COUNTEREN_CY)) { 138 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 139 } 140 break; 141 case CSR_TIME: 142 if (!get_field(env->hcounteren, COUNTEREN_TM) && 143 get_field(env->mcounteren, COUNTEREN_TM)) { 144 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 145 } 146 break; 147 case CSR_INSTRET: 148 if (!get_field(env->hcounteren, COUNTEREN_IR) && 149 get_field(env->mcounteren, COUNTEREN_IR)) { 150 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 151 } 152 break; 153 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 154 ctr_index = csrno - CSR_CYCLE; 155 if (!get_field(env->hcounteren, 1 << ctr_index) && 156 get_field(env->mcounteren, 1 << ctr_index)) { 157 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 158 } 159 break; 160 } 161 if (riscv_cpu_mxl(env) == MXL_RV32) { 162 switch (csrno) { 163 case CSR_CYCLEH: 164 if (!get_field(env->hcounteren, COUNTEREN_CY) && 165 get_field(env->mcounteren, COUNTEREN_CY)) { 166 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 167 } 168 break; 169 case CSR_TIMEH: 170 if (!get_field(env->hcounteren, COUNTEREN_TM) && 171 get_field(env->mcounteren, COUNTEREN_TM)) { 172 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 173 } 174 break; 175 case CSR_INSTRETH: 176 if (!get_field(env->hcounteren, COUNTEREN_IR) && 177 get_field(env->mcounteren, COUNTEREN_IR)) { 178 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 179 } 180 break; 181 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 182 ctr_index = csrno - CSR_CYCLEH; 183 if (!get_field(env->hcounteren, 1 << ctr_index) && 184 get_field(env->mcounteren, 1 << ctr_index)) { 185 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 186 } 187 break; 188 } 189 } 190 } 191 #endif 192 return RISCV_EXCP_NONE; 193 } 194 195 static RISCVException ctr32(CPURISCVState *env, int csrno) 196 { 197 if (riscv_cpu_mxl(env) != MXL_RV32) { 198 return RISCV_EXCP_ILLEGAL_INST; 199 } 200 201 return ctr(env, csrno); 202 } 203 204 #if !defined(CONFIG_USER_ONLY) 205 static RISCVException any(CPURISCVState *env, int csrno) 206 { 207 return RISCV_EXCP_NONE; 208 } 209 210 static RISCVException any32(CPURISCVState *env, int csrno) 211 { 212 if (riscv_cpu_mxl(env) != MXL_RV32) { 213 return RISCV_EXCP_ILLEGAL_INST; 214 } 215 216 return any(env, csrno); 217 218 } 219 220 static int aia_any(CPURISCVState *env, int csrno) 221 { 222 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 223 return RISCV_EXCP_ILLEGAL_INST; 224 } 225 226 return any(env, csrno); 227 } 228 229 static int aia_any32(CPURISCVState *env, int csrno) 230 { 231 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 232 return RISCV_EXCP_ILLEGAL_INST; 233 } 234 235 return any32(env, csrno); 236 } 237 238 static RISCVException smode(CPURISCVState *env, int csrno) 239 { 240 if (riscv_has_ext(env, RVS)) { 241 return RISCV_EXCP_NONE; 242 } 243 244 return RISCV_EXCP_ILLEGAL_INST; 245 } 246 247 static int smode32(CPURISCVState *env, int csrno) 248 { 249 if (riscv_cpu_mxl(env) != MXL_RV32) { 250 return RISCV_EXCP_ILLEGAL_INST; 251 } 252 253 return smode(env, csrno); 254 } 255 256 static int aia_smode(CPURISCVState *env, int csrno) 257 { 258 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 259 return RISCV_EXCP_ILLEGAL_INST; 260 } 261 262 return smode(env, csrno); 263 } 264 265 static int aia_smode32(CPURISCVState *env, int csrno) 266 { 267 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 268 return RISCV_EXCP_ILLEGAL_INST; 269 } 270 271 return smode32(env, csrno); 272 } 273 274 static RISCVException hmode(CPURISCVState *env, int csrno) 275 { 276 if (riscv_has_ext(env, RVS) && 277 riscv_has_ext(env, RVH)) { 278 /* Hypervisor extension is supported */ 279 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 280 env->priv == PRV_M) { 281 return RISCV_EXCP_NONE; 282 } else { 283 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 284 } 285 } 286 287 return RISCV_EXCP_ILLEGAL_INST; 288 } 289 290 static RISCVException hmode32(CPURISCVState *env, int csrno) 291 { 292 if (riscv_cpu_mxl(env) != MXL_RV32) { 293 if (!riscv_cpu_virt_enabled(env)) { 294 return RISCV_EXCP_ILLEGAL_INST; 295 } else { 296 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 297 } 298 } 299 300 return hmode(env, csrno); 301 302 } 303 304 /* Checks if PointerMasking registers could be accessed */ 305 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 306 { 307 /* Check if j-ext is present */ 308 if (riscv_has_ext(env, RVJ)) { 309 return RISCV_EXCP_NONE; 310 } 311 return RISCV_EXCP_ILLEGAL_INST; 312 } 313 314 static int aia_hmode(CPURISCVState *env, int csrno) 315 { 316 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 317 return RISCV_EXCP_ILLEGAL_INST; 318 } 319 320 return hmode(env, csrno); 321 } 322 323 static int aia_hmode32(CPURISCVState *env, int csrno) 324 { 325 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 326 return RISCV_EXCP_ILLEGAL_INST; 327 } 328 329 return hmode32(env, csrno); 330 } 331 332 static RISCVException pmp(CPURISCVState *env, int csrno) 333 { 334 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 335 return RISCV_EXCP_NONE; 336 } 337 338 return RISCV_EXCP_ILLEGAL_INST; 339 } 340 341 static RISCVException epmp(CPURISCVState *env, int csrno) 342 { 343 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 344 return RISCV_EXCP_NONE; 345 } 346 347 return RISCV_EXCP_ILLEGAL_INST; 348 } 349 350 static RISCVException debug(CPURISCVState *env, int csrno) 351 { 352 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 353 return RISCV_EXCP_NONE; 354 } 355 356 return RISCV_EXCP_ILLEGAL_INST; 357 } 358 #endif 359 360 static RISCVException seed(CPURISCVState *env, int csrno) 361 { 362 RISCVCPU *cpu = env_archcpu(env); 363 364 if (!cpu->cfg.ext_zkr) { 365 return RISCV_EXCP_ILLEGAL_INST; 366 } 367 368 #if !defined(CONFIG_USER_ONLY) 369 /* 370 * With a CSR read-write instruction: 371 * 1) The seed CSR is always available in machine mode as normal. 372 * 2) Attempted access to seed from virtual modes VS and VU always raises 373 * an exception(virtual instruction exception only if mseccfg.sseed=1). 374 * 3) Without the corresponding access control bit set to 1, any attempted 375 * access to seed from U, S or HS modes will raise an illegal instruction 376 * exception. 377 */ 378 if (env->priv == PRV_M) { 379 return RISCV_EXCP_NONE; 380 } else if (riscv_cpu_virt_enabled(env)) { 381 if (env->mseccfg & MSECCFG_SSEED) { 382 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 383 } else { 384 return RISCV_EXCP_ILLEGAL_INST; 385 } 386 } else { 387 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { 388 return RISCV_EXCP_NONE; 389 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { 390 return RISCV_EXCP_NONE; 391 } else { 392 return RISCV_EXCP_ILLEGAL_INST; 393 } 394 } 395 #else 396 return RISCV_EXCP_NONE; 397 #endif 398 } 399 400 /* User Floating-Point CSRs */ 401 static RISCVException read_fflags(CPURISCVState *env, int csrno, 402 target_ulong *val) 403 { 404 *val = riscv_cpu_get_fflags(env); 405 return RISCV_EXCP_NONE; 406 } 407 408 static RISCVException write_fflags(CPURISCVState *env, int csrno, 409 target_ulong val) 410 { 411 #if !defined(CONFIG_USER_ONLY) 412 if (riscv_has_ext(env, RVF)) { 413 env->mstatus |= MSTATUS_FS; 414 } 415 #endif 416 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 417 return RISCV_EXCP_NONE; 418 } 419 420 static RISCVException read_frm(CPURISCVState *env, int csrno, 421 target_ulong *val) 422 { 423 *val = env->frm; 424 return RISCV_EXCP_NONE; 425 } 426 427 static RISCVException write_frm(CPURISCVState *env, int csrno, 428 target_ulong val) 429 { 430 #if !defined(CONFIG_USER_ONLY) 431 if (riscv_has_ext(env, RVF)) { 432 env->mstatus |= MSTATUS_FS; 433 } 434 #endif 435 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 436 return RISCV_EXCP_NONE; 437 } 438 439 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 440 target_ulong *val) 441 { 442 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 443 | (env->frm << FSR_RD_SHIFT); 444 return RISCV_EXCP_NONE; 445 } 446 447 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 448 target_ulong val) 449 { 450 #if !defined(CONFIG_USER_ONLY) 451 if (riscv_has_ext(env, RVF)) { 452 env->mstatus |= MSTATUS_FS; 453 } 454 #endif 455 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 456 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 457 return RISCV_EXCP_NONE; 458 } 459 460 static RISCVException read_vtype(CPURISCVState *env, int csrno, 461 target_ulong *val) 462 { 463 uint64_t vill; 464 switch (env->xl) { 465 case MXL_RV32: 466 vill = (uint32_t)env->vill << 31; 467 break; 468 case MXL_RV64: 469 vill = (uint64_t)env->vill << 63; 470 break; 471 default: 472 g_assert_not_reached(); 473 } 474 *val = (target_ulong)vill | env->vtype; 475 return RISCV_EXCP_NONE; 476 } 477 478 static RISCVException read_vl(CPURISCVState *env, int csrno, 479 target_ulong *val) 480 { 481 *val = env->vl; 482 return RISCV_EXCP_NONE; 483 } 484 485 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 486 { 487 *val = env_archcpu(env)->cfg.vlen >> 3; 488 return RISCV_EXCP_NONE; 489 } 490 491 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 492 target_ulong *val) 493 { 494 *val = env->vxrm; 495 return RISCV_EXCP_NONE; 496 } 497 498 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 499 target_ulong val) 500 { 501 #if !defined(CONFIG_USER_ONLY) 502 env->mstatus |= MSTATUS_VS; 503 #endif 504 env->vxrm = val; 505 return RISCV_EXCP_NONE; 506 } 507 508 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 509 target_ulong *val) 510 { 511 *val = env->vxsat; 512 return RISCV_EXCP_NONE; 513 } 514 515 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 516 target_ulong val) 517 { 518 #if !defined(CONFIG_USER_ONLY) 519 env->mstatus |= MSTATUS_VS; 520 #endif 521 env->vxsat = val; 522 return RISCV_EXCP_NONE; 523 } 524 525 static RISCVException read_vstart(CPURISCVState *env, int csrno, 526 target_ulong *val) 527 { 528 *val = env->vstart; 529 return RISCV_EXCP_NONE; 530 } 531 532 static RISCVException write_vstart(CPURISCVState *env, int csrno, 533 target_ulong val) 534 { 535 #if !defined(CONFIG_USER_ONLY) 536 env->mstatus |= MSTATUS_VS; 537 #endif 538 /* 539 * The vstart CSR is defined to have only enough writable bits 540 * to hold the largest element index, i.e. lg2(VLEN) bits. 541 */ 542 env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); 543 return RISCV_EXCP_NONE; 544 } 545 546 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 547 { 548 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 549 return RISCV_EXCP_NONE; 550 } 551 552 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 553 { 554 #if !defined(CONFIG_USER_ONLY) 555 env->mstatus |= MSTATUS_VS; 556 #endif 557 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 558 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 559 return RISCV_EXCP_NONE; 560 } 561 562 /* User Timers and Counters */ 563 static RISCVException read_instret(CPURISCVState *env, int csrno, 564 target_ulong *val) 565 { 566 #if !defined(CONFIG_USER_ONLY) 567 if (icount_enabled()) { 568 *val = icount_get(); 569 } else { 570 *val = cpu_get_host_ticks(); 571 } 572 #else 573 *val = cpu_get_host_ticks(); 574 #endif 575 return RISCV_EXCP_NONE; 576 } 577 578 static RISCVException read_instreth(CPURISCVState *env, int csrno, 579 target_ulong *val) 580 { 581 #if !defined(CONFIG_USER_ONLY) 582 if (icount_enabled()) { 583 *val = icount_get() >> 32; 584 } else { 585 *val = cpu_get_host_ticks() >> 32; 586 } 587 #else 588 *val = cpu_get_host_ticks() >> 32; 589 #endif 590 return RISCV_EXCP_NONE; 591 } 592 593 #if defined(CONFIG_USER_ONLY) 594 static RISCVException read_time(CPURISCVState *env, int csrno, 595 target_ulong *val) 596 { 597 *val = cpu_get_host_ticks(); 598 return RISCV_EXCP_NONE; 599 } 600 601 static RISCVException read_timeh(CPURISCVState *env, int csrno, 602 target_ulong *val) 603 { 604 *val = cpu_get_host_ticks() >> 32; 605 return RISCV_EXCP_NONE; 606 } 607 608 #else /* CONFIG_USER_ONLY */ 609 610 static RISCVException read_time(CPURISCVState *env, int csrno, 611 target_ulong *val) 612 { 613 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 614 615 if (!env->rdtime_fn) { 616 return RISCV_EXCP_ILLEGAL_INST; 617 } 618 619 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 620 return RISCV_EXCP_NONE; 621 } 622 623 static RISCVException read_timeh(CPURISCVState *env, int csrno, 624 target_ulong *val) 625 { 626 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 627 628 if (!env->rdtime_fn) { 629 return RISCV_EXCP_ILLEGAL_INST; 630 } 631 632 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 633 return RISCV_EXCP_NONE; 634 } 635 636 /* Machine constants */ 637 638 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 639 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 640 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 641 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 642 643 #define VSTOPI_NUM_SRCS 5 644 645 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | 646 VS_MODE_INTERRUPTS; 647 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; 648 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 649 HS_MODE_INTERRUPTS; 650 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 651 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 652 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 653 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 654 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 655 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 656 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 657 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 658 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 659 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 660 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 661 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 662 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 663 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 664 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 665 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 666 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 667 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 668 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 669 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 670 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 671 (1ULL << (RISCV_EXCP_VS_ECALL)) | 672 (1ULL << (RISCV_EXCP_M_ECALL)) | 673 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 674 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 675 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 676 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 677 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 678 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 679 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 680 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 681 static const target_ulong hip_writable_mask = MIP_VSSIP; 682 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 683 static const target_ulong vsip_writable_mask = MIP_VSSIP; 684 685 static const char valid_vm_1_10_32[16] = { 686 [VM_1_10_MBARE] = 1, 687 [VM_1_10_SV32] = 1 688 }; 689 690 static const char valid_vm_1_10_64[16] = { 691 [VM_1_10_MBARE] = 1, 692 [VM_1_10_SV39] = 1, 693 [VM_1_10_SV48] = 1, 694 [VM_1_10_SV57] = 1 695 }; 696 697 /* Machine Information Registers */ 698 static RISCVException read_zero(CPURISCVState *env, int csrno, 699 target_ulong *val) 700 { 701 *val = 0; 702 return RISCV_EXCP_NONE; 703 } 704 705 static RISCVException write_ignore(CPURISCVState *env, int csrno, 706 target_ulong val) 707 { 708 return RISCV_EXCP_NONE; 709 } 710 711 static RISCVException read_mvendorid(CPURISCVState *env, int csrno, 712 target_ulong *val) 713 { 714 CPUState *cs = env_cpu(env); 715 RISCVCPU *cpu = RISCV_CPU(cs); 716 717 *val = cpu->cfg.mvendorid; 718 return RISCV_EXCP_NONE; 719 } 720 721 static RISCVException read_marchid(CPURISCVState *env, int csrno, 722 target_ulong *val) 723 { 724 CPUState *cs = env_cpu(env); 725 RISCVCPU *cpu = RISCV_CPU(cs); 726 727 *val = cpu->cfg.marchid; 728 return RISCV_EXCP_NONE; 729 } 730 731 static RISCVException read_mimpid(CPURISCVState *env, int csrno, 732 target_ulong *val) 733 { 734 CPUState *cs = env_cpu(env); 735 RISCVCPU *cpu = RISCV_CPU(cs); 736 737 *val = cpu->cfg.mimpid; 738 return RISCV_EXCP_NONE; 739 } 740 741 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 742 target_ulong *val) 743 { 744 *val = env->mhartid; 745 return RISCV_EXCP_NONE; 746 } 747 748 /* Machine Trap Setup */ 749 750 /* We do not store SD explicitly, only compute it on demand. */ 751 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 752 { 753 if ((status & MSTATUS_FS) == MSTATUS_FS || 754 (status & MSTATUS_VS) == MSTATUS_VS || 755 (status & MSTATUS_XS) == MSTATUS_XS) { 756 switch (xl) { 757 case MXL_RV32: 758 return status | MSTATUS32_SD; 759 case MXL_RV64: 760 return status | MSTATUS64_SD; 761 case MXL_RV128: 762 return MSTATUSH128_SD; 763 default: 764 g_assert_not_reached(); 765 } 766 } 767 return status; 768 } 769 770 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 771 target_ulong *val) 772 { 773 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 774 return RISCV_EXCP_NONE; 775 } 776 777 static int validate_vm(CPURISCVState *env, target_ulong vm) 778 { 779 if (riscv_cpu_mxl(env) == MXL_RV32) { 780 return valid_vm_1_10_32[vm & 0xf]; 781 } else { 782 return valid_vm_1_10_64[vm & 0xf]; 783 } 784 } 785 786 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 787 target_ulong val) 788 { 789 uint64_t mstatus = env->mstatus; 790 uint64_t mask = 0; 791 RISCVMXL xl = riscv_cpu_mxl(env); 792 793 /* flush tlb on mstatus fields that affect VM */ 794 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 795 MSTATUS_MPRV | MSTATUS_SUM)) { 796 tlb_flush(env_cpu(env)); 797 } 798 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 799 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 800 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 801 MSTATUS_TW | MSTATUS_VS; 802 803 if (riscv_has_ext(env, RVF)) { 804 mask |= MSTATUS_FS; 805 } 806 807 if (xl != MXL_RV32 || env->debugger) { 808 /* 809 * RV32: MPV and GVA are not in mstatus. The current plan is to 810 * add them to mstatush. For now, we just don't support it. 811 */ 812 mask |= MSTATUS_MPV | MSTATUS_GVA; 813 if ((val & MSTATUS64_UXL) != 0) { 814 mask |= MSTATUS64_UXL; 815 } 816 } 817 818 mstatus = (mstatus & ~mask) | (val & mask); 819 820 if (xl > MXL_RV32) { 821 /* SXL field is for now read only */ 822 mstatus = set_field(mstatus, MSTATUS64_SXL, xl); 823 } 824 env->mstatus = mstatus; 825 env->xl = cpu_recompute_xl(env); 826 827 return RISCV_EXCP_NONE; 828 } 829 830 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 831 target_ulong *val) 832 { 833 *val = env->mstatus >> 32; 834 return RISCV_EXCP_NONE; 835 } 836 837 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 838 target_ulong val) 839 { 840 uint64_t valh = (uint64_t)val << 32; 841 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 842 843 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 844 tlb_flush(env_cpu(env)); 845 } 846 847 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 848 849 return RISCV_EXCP_NONE; 850 } 851 852 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 853 Int128 *val) 854 { 855 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); 856 return RISCV_EXCP_NONE; 857 } 858 859 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 860 Int128 *val) 861 { 862 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 863 return RISCV_EXCP_NONE; 864 } 865 866 static RISCVException read_misa(CPURISCVState *env, int csrno, 867 target_ulong *val) 868 { 869 target_ulong misa; 870 871 switch (env->misa_mxl) { 872 case MXL_RV32: 873 misa = (target_ulong)MXL_RV32 << 30; 874 break; 875 #ifdef TARGET_RISCV64 876 case MXL_RV64: 877 misa = (target_ulong)MXL_RV64 << 62; 878 break; 879 #endif 880 default: 881 g_assert_not_reached(); 882 } 883 884 *val = misa | env->misa_ext; 885 return RISCV_EXCP_NONE; 886 } 887 888 static RISCVException write_misa(CPURISCVState *env, int csrno, 889 target_ulong val) 890 { 891 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 892 /* drop write to misa */ 893 return RISCV_EXCP_NONE; 894 } 895 896 /* 'I' or 'E' must be present */ 897 if (!(val & (RVI | RVE))) { 898 /* It is not, drop write to misa */ 899 return RISCV_EXCP_NONE; 900 } 901 902 /* 'E' excludes all other extensions */ 903 if (val & RVE) { 904 /* when we support 'E' we can do "val = RVE;" however 905 * for now we just drop writes if 'E' is present. 906 */ 907 return RISCV_EXCP_NONE; 908 } 909 910 /* 911 * misa.MXL writes are not supported by QEMU. 912 * Drop writes to those bits. 913 */ 914 915 /* Mask extensions that are not supported by this hart */ 916 val &= env->misa_ext_mask; 917 918 /* Mask extensions that are not supported by QEMU */ 919 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 920 921 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 922 if ((val & RVD) && !(val & RVF)) { 923 val &= ~RVD; 924 } 925 926 /* Suppress 'C' if next instruction is not aligned 927 * TODO: this should check next_pc 928 */ 929 if ((val & RVC) && (GETPC() & ~3) != 0) { 930 val &= ~RVC; 931 } 932 933 /* If nothing changed, do nothing. */ 934 if (val == env->misa_ext) { 935 return RISCV_EXCP_NONE; 936 } 937 938 if (!(val & RVF)) { 939 env->mstatus &= ~MSTATUS_FS; 940 } 941 942 /* flush translation cache */ 943 tb_flush(env_cpu(env)); 944 env->misa_ext = val; 945 env->xl = riscv_cpu_mxl(env); 946 return RISCV_EXCP_NONE; 947 } 948 949 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 950 target_ulong *val) 951 { 952 *val = env->medeleg; 953 return RISCV_EXCP_NONE; 954 } 955 956 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 957 target_ulong val) 958 { 959 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 960 return RISCV_EXCP_NONE; 961 } 962 963 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 964 uint64_t *ret_val, 965 uint64_t new_val, uint64_t wr_mask) 966 { 967 uint64_t mask = wr_mask & delegable_ints; 968 969 if (ret_val) { 970 *ret_val = env->mideleg; 971 } 972 973 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 974 975 if (riscv_has_ext(env, RVH)) { 976 env->mideleg |= HS_MODE_INTERRUPTS; 977 } 978 979 return RISCV_EXCP_NONE; 980 } 981 982 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 983 target_ulong *ret_val, 984 target_ulong new_val, target_ulong wr_mask) 985 { 986 uint64_t rval; 987 RISCVException ret; 988 989 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 990 if (ret_val) { 991 *ret_val = rval; 992 } 993 994 return ret; 995 } 996 997 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 998 target_ulong *ret_val, 999 target_ulong new_val, 1000 target_ulong wr_mask) 1001 { 1002 uint64_t rval; 1003 RISCVException ret; 1004 1005 ret = rmw_mideleg64(env, csrno, &rval, 1006 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1007 if (ret_val) { 1008 *ret_val = rval >> 32; 1009 } 1010 1011 return ret; 1012 } 1013 1014 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 1015 uint64_t *ret_val, 1016 uint64_t new_val, uint64_t wr_mask) 1017 { 1018 uint64_t mask = wr_mask & all_ints; 1019 1020 if (ret_val) { 1021 *ret_val = env->mie; 1022 } 1023 1024 env->mie = (env->mie & ~mask) | (new_val & mask); 1025 1026 if (!riscv_has_ext(env, RVH)) { 1027 env->mie &= ~((uint64_t)MIP_SGEIP); 1028 } 1029 1030 return RISCV_EXCP_NONE; 1031 } 1032 1033 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 1034 target_ulong *ret_val, 1035 target_ulong new_val, target_ulong wr_mask) 1036 { 1037 uint64_t rval; 1038 RISCVException ret; 1039 1040 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 1041 if (ret_val) { 1042 *ret_val = rval; 1043 } 1044 1045 return ret; 1046 } 1047 1048 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 1049 target_ulong *ret_val, 1050 target_ulong new_val, target_ulong wr_mask) 1051 { 1052 uint64_t rval; 1053 RISCVException ret; 1054 1055 ret = rmw_mie64(env, csrno, &rval, 1056 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1057 if (ret_val) { 1058 *ret_val = rval >> 32; 1059 } 1060 1061 return ret; 1062 } 1063 1064 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 1065 { 1066 int irq; 1067 uint8_t iprio; 1068 1069 irq = riscv_cpu_mirq_pending(env); 1070 if (irq <= 0 || irq > 63) { 1071 *val = 0; 1072 } else { 1073 iprio = env->miprio[irq]; 1074 if (!iprio) { 1075 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 1076 iprio = IPRIO_MMAXIPRIO; 1077 } 1078 } 1079 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 1080 *val |= iprio; 1081 } 1082 1083 return RISCV_EXCP_NONE; 1084 } 1085 1086 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 1087 { 1088 if (!riscv_cpu_virt_enabled(env)) { 1089 return csrno; 1090 } 1091 1092 switch (csrno) { 1093 case CSR_SISELECT: 1094 return CSR_VSISELECT; 1095 case CSR_SIREG: 1096 return CSR_VSIREG; 1097 case CSR_SSETEIPNUM: 1098 return CSR_VSSETEIPNUM; 1099 case CSR_SCLREIPNUM: 1100 return CSR_VSCLREIPNUM; 1101 case CSR_SSETEIENUM: 1102 return CSR_VSSETEIENUM; 1103 case CSR_SCLREIENUM: 1104 return CSR_VSCLREIENUM; 1105 case CSR_STOPEI: 1106 return CSR_VSTOPEI; 1107 default: 1108 return csrno; 1109 }; 1110 } 1111 1112 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 1113 target_ulong new_val, target_ulong wr_mask) 1114 { 1115 target_ulong *iselect; 1116 1117 /* Translate CSR number for VS-mode */ 1118 csrno = aia_xlate_vs_csrno(env, csrno); 1119 1120 /* Find the iselect CSR based on CSR number */ 1121 switch (csrno) { 1122 case CSR_MISELECT: 1123 iselect = &env->miselect; 1124 break; 1125 case CSR_SISELECT: 1126 iselect = &env->siselect; 1127 break; 1128 case CSR_VSISELECT: 1129 iselect = &env->vsiselect; 1130 break; 1131 default: 1132 return RISCV_EXCP_ILLEGAL_INST; 1133 }; 1134 1135 if (val) { 1136 *val = *iselect; 1137 } 1138 1139 wr_mask &= ISELECT_MASK; 1140 if (wr_mask) { 1141 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1142 } 1143 1144 return RISCV_EXCP_NONE; 1145 } 1146 1147 static int rmw_iprio(target_ulong xlen, 1148 target_ulong iselect, uint8_t *iprio, 1149 target_ulong *val, target_ulong new_val, 1150 target_ulong wr_mask, int ext_irq_no) 1151 { 1152 int i, firq, nirqs; 1153 target_ulong old_val; 1154 1155 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1156 return -EINVAL; 1157 } 1158 if (xlen != 32 && iselect & 0x1) { 1159 return -EINVAL; 1160 } 1161 1162 nirqs = 4 * (xlen / 32); 1163 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1164 1165 old_val = 0; 1166 for (i = 0; i < nirqs; i++) { 1167 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1168 } 1169 1170 if (val) { 1171 *val = old_val; 1172 } 1173 1174 if (wr_mask) { 1175 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1176 for (i = 0; i < nirqs; i++) { 1177 /* 1178 * M-level and S-level external IRQ priority always read-only 1179 * zero. This means default priority order is always preferred 1180 * for M-level and S-level external IRQs. 1181 */ 1182 if ((firq + i) == ext_irq_no) { 1183 continue; 1184 } 1185 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1186 } 1187 } 1188 1189 return 0; 1190 } 1191 1192 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1193 target_ulong new_val, target_ulong wr_mask) 1194 { 1195 bool virt; 1196 uint8_t *iprio; 1197 int ret = -EINVAL; 1198 target_ulong priv, isel, vgein; 1199 1200 /* Translate CSR number for VS-mode */ 1201 csrno = aia_xlate_vs_csrno(env, csrno); 1202 1203 /* Decode register details from CSR number */ 1204 virt = false; 1205 switch (csrno) { 1206 case CSR_MIREG: 1207 iprio = env->miprio; 1208 isel = env->miselect; 1209 priv = PRV_M; 1210 break; 1211 case CSR_SIREG: 1212 iprio = env->siprio; 1213 isel = env->siselect; 1214 priv = PRV_S; 1215 break; 1216 case CSR_VSIREG: 1217 iprio = env->hviprio; 1218 isel = env->vsiselect; 1219 priv = PRV_S; 1220 virt = true; 1221 break; 1222 default: 1223 goto done; 1224 }; 1225 1226 /* Find the selected guest interrupt file */ 1227 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1228 1229 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1230 /* Local interrupt priority registers not available for VS-mode */ 1231 if (!virt) { 1232 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1233 isel, iprio, val, new_val, wr_mask, 1234 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1235 } 1236 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1237 /* IMSIC registers only available when machine implements it. */ 1238 if (env->aia_ireg_rmw_fn[priv]) { 1239 /* Selected guest interrupt file should not be zero */ 1240 if (virt && (!vgein || env->geilen < vgein)) { 1241 goto done; 1242 } 1243 /* Call machine specific IMSIC register emulation */ 1244 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1245 AIA_MAKE_IREG(isel, priv, virt, vgein, 1246 riscv_cpu_mxl_bits(env)), 1247 val, new_val, wr_mask); 1248 } 1249 } 1250 1251 done: 1252 if (ret) { 1253 return (riscv_cpu_virt_enabled(env) && virt) ? 1254 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1255 } 1256 return RISCV_EXCP_NONE; 1257 } 1258 1259 static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val, 1260 target_ulong new_val, target_ulong wr_mask) 1261 { 1262 int ret = -EINVAL; 1263 bool set, pend, virt; 1264 target_ulong priv, isel, vgein, xlen, nval, wmask; 1265 1266 /* Translate CSR number for VS-mode */ 1267 csrno = aia_xlate_vs_csrno(env, csrno); 1268 1269 /* Decode register details from CSR number */ 1270 virt = set = pend = false; 1271 switch (csrno) { 1272 case CSR_MSETEIPNUM: 1273 priv = PRV_M; 1274 set = true; 1275 pend = true; 1276 break; 1277 case CSR_MCLREIPNUM: 1278 priv = PRV_M; 1279 pend = true; 1280 break; 1281 case CSR_MSETEIENUM: 1282 priv = PRV_M; 1283 set = true; 1284 break; 1285 case CSR_MCLREIENUM: 1286 priv = PRV_M; 1287 break; 1288 case CSR_SSETEIPNUM: 1289 priv = PRV_S; 1290 set = true; 1291 pend = true; 1292 break; 1293 case CSR_SCLREIPNUM: 1294 priv = PRV_S; 1295 pend = true; 1296 break; 1297 case CSR_SSETEIENUM: 1298 priv = PRV_S; 1299 set = true; 1300 break; 1301 case CSR_SCLREIENUM: 1302 priv = PRV_S; 1303 break; 1304 case CSR_VSSETEIPNUM: 1305 priv = PRV_S; 1306 virt = true; 1307 set = true; 1308 pend = true; 1309 break; 1310 case CSR_VSCLREIPNUM: 1311 priv = PRV_S; 1312 virt = true; 1313 pend = true; 1314 break; 1315 case CSR_VSSETEIENUM: 1316 priv = PRV_S; 1317 virt = true; 1318 set = true; 1319 break; 1320 case CSR_VSCLREIENUM: 1321 priv = PRV_S; 1322 virt = true; 1323 break; 1324 default: 1325 goto done; 1326 }; 1327 1328 /* IMSIC CSRs only available when machine implements IMSIC. */ 1329 if (!env->aia_ireg_rmw_fn[priv]) { 1330 goto done; 1331 } 1332 1333 /* Find the selected guest interrupt file */ 1334 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1335 1336 /* Selected guest interrupt file should be valid */ 1337 if (virt && (!vgein || env->geilen < vgein)) { 1338 goto done; 1339 } 1340 1341 /* Set/Clear CSRs always read zero */ 1342 if (val) { 1343 *val = 0; 1344 } 1345 1346 if (wr_mask) { 1347 /* Get interrupt number */ 1348 new_val &= wr_mask; 1349 1350 /* Find target interrupt pending/enable register */ 1351 xlen = riscv_cpu_mxl_bits(env); 1352 isel = (new_val / xlen); 1353 isel *= (xlen / IMSIC_EIPx_BITS); 1354 isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; 1355 1356 /* Find the interrupt bit to be set/clear */ 1357 wmask = ((target_ulong)1) << (new_val % xlen); 1358 nval = (set) ? wmask : 0; 1359 1360 /* Call machine specific IMSIC register emulation */ 1361 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1362 AIA_MAKE_IREG(isel, priv, virt, 1363 vgein, xlen), 1364 NULL, nval, wmask); 1365 } else { 1366 ret = 0; 1367 } 1368 1369 done: 1370 if (ret) { 1371 return (riscv_cpu_virt_enabled(env) && virt) ? 1372 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1373 } 1374 return RISCV_EXCP_NONE; 1375 } 1376 1377 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1378 target_ulong new_val, target_ulong wr_mask) 1379 { 1380 bool virt; 1381 int ret = -EINVAL; 1382 target_ulong priv, vgein; 1383 1384 /* Translate CSR number for VS-mode */ 1385 csrno = aia_xlate_vs_csrno(env, csrno); 1386 1387 /* Decode register details from CSR number */ 1388 virt = false; 1389 switch (csrno) { 1390 case CSR_MTOPEI: 1391 priv = PRV_M; 1392 break; 1393 case CSR_STOPEI: 1394 priv = PRV_S; 1395 break; 1396 case CSR_VSTOPEI: 1397 priv = PRV_S; 1398 virt = true; 1399 break; 1400 default: 1401 goto done; 1402 }; 1403 1404 /* IMSIC CSRs only available when machine implements IMSIC. */ 1405 if (!env->aia_ireg_rmw_fn[priv]) { 1406 goto done; 1407 } 1408 1409 /* Find the selected guest interrupt file */ 1410 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1411 1412 /* Selected guest interrupt file should be valid */ 1413 if (virt && (!vgein || env->geilen < vgein)) { 1414 goto done; 1415 } 1416 1417 /* Call machine specific IMSIC register emulation for TOPEI */ 1418 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1419 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1420 riscv_cpu_mxl_bits(env)), 1421 val, new_val, wr_mask); 1422 1423 done: 1424 if (ret) { 1425 return (riscv_cpu_virt_enabled(env) && virt) ? 1426 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1427 } 1428 return RISCV_EXCP_NONE; 1429 } 1430 1431 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1432 target_ulong *val) 1433 { 1434 *val = env->mtvec; 1435 return RISCV_EXCP_NONE; 1436 } 1437 1438 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1439 target_ulong val) 1440 { 1441 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1442 if ((val & 3) < 2) { 1443 env->mtvec = val; 1444 } else { 1445 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1446 } 1447 return RISCV_EXCP_NONE; 1448 } 1449 1450 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1451 target_ulong *val) 1452 { 1453 *val = env->mcounteren; 1454 return RISCV_EXCP_NONE; 1455 } 1456 1457 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1458 target_ulong val) 1459 { 1460 env->mcounteren = val; 1461 return RISCV_EXCP_NONE; 1462 } 1463 1464 /* Machine Trap Handling */ 1465 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1466 Int128 *val) 1467 { 1468 *val = int128_make128(env->mscratch, env->mscratchh); 1469 return RISCV_EXCP_NONE; 1470 } 1471 1472 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1473 Int128 val) 1474 { 1475 env->mscratch = int128_getlo(val); 1476 env->mscratchh = int128_gethi(val); 1477 return RISCV_EXCP_NONE; 1478 } 1479 1480 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1481 target_ulong *val) 1482 { 1483 *val = env->mscratch; 1484 return RISCV_EXCP_NONE; 1485 } 1486 1487 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1488 target_ulong val) 1489 { 1490 env->mscratch = val; 1491 return RISCV_EXCP_NONE; 1492 } 1493 1494 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1495 target_ulong *val) 1496 { 1497 *val = env->mepc; 1498 return RISCV_EXCP_NONE; 1499 } 1500 1501 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1502 target_ulong val) 1503 { 1504 env->mepc = val; 1505 return RISCV_EXCP_NONE; 1506 } 1507 1508 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1509 target_ulong *val) 1510 { 1511 *val = env->mcause; 1512 return RISCV_EXCP_NONE; 1513 } 1514 1515 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1516 target_ulong val) 1517 { 1518 env->mcause = val; 1519 return RISCV_EXCP_NONE; 1520 } 1521 1522 static RISCVException read_mtval(CPURISCVState *env, int csrno, 1523 target_ulong *val) 1524 { 1525 *val = env->mtval; 1526 return RISCV_EXCP_NONE; 1527 } 1528 1529 static RISCVException write_mtval(CPURISCVState *env, int csrno, 1530 target_ulong val) 1531 { 1532 env->mtval = val; 1533 return RISCV_EXCP_NONE; 1534 } 1535 1536 /* Execution environment configuration setup */ 1537 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 1538 target_ulong *val) 1539 { 1540 *val = env->menvcfg; 1541 return RISCV_EXCP_NONE; 1542 } 1543 1544 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 1545 target_ulong val) 1546 { 1547 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 1548 1549 if (riscv_cpu_mxl(env) == MXL_RV64) { 1550 mask |= MENVCFG_PBMTE | MENVCFG_STCE; 1551 } 1552 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 1553 1554 return RISCV_EXCP_NONE; 1555 } 1556 1557 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 1558 target_ulong *val) 1559 { 1560 *val = env->menvcfg >> 32; 1561 return RISCV_EXCP_NONE; 1562 } 1563 1564 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 1565 target_ulong val) 1566 { 1567 uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; 1568 uint64_t valh = (uint64_t)val << 32; 1569 1570 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 1571 1572 return RISCV_EXCP_NONE; 1573 } 1574 1575 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 1576 target_ulong *val) 1577 { 1578 *val = env->senvcfg; 1579 return RISCV_EXCP_NONE; 1580 } 1581 1582 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 1583 target_ulong val) 1584 { 1585 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 1586 1587 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 1588 1589 return RISCV_EXCP_NONE; 1590 } 1591 1592 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 1593 target_ulong *val) 1594 { 1595 *val = env->henvcfg; 1596 return RISCV_EXCP_NONE; 1597 } 1598 1599 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 1600 target_ulong val) 1601 { 1602 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 1603 1604 if (riscv_cpu_mxl(env) == MXL_RV64) { 1605 mask |= HENVCFG_PBMTE | HENVCFG_STCE; 1606 } 1607 1608 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 1609 1610 return RISCV_EXCP_NONE; 1611 } 1612 1613 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 1614 target_ulong *val) 1615 { 1616 *val = env->henvcfg >> 32; 1617 return RISCV_EXCP_NONE; 1618 } 1619 1620 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 1621 target_ulong val) 1622 { 1623 uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; 1624 uint64_t valh = (uint64_t)val << 32; 1625 1626 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 1627 1628 return RISCV_EXCP_NONE; 1629 } 1630 1631 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 1632 uint64_t *ret_val, 1633 uint64_t new_val, uint64_t wr_mask) 1634 { 1635 RISCVCPU *cpu = env_archcpu(env); 1636 uint64_t old_mip, mask = wr_mask & delegable_ints; 1637 uint32_t gin; 1638 1639 if (mask & MIP_SEIP) { 1640 env->software_seip = new_val & MIP_SEIP; 1641 new_val |= env->external_seip * MIP_SEIP; 1642 } 1643 1644 if (mask) { 1645 old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); 1646 } else { 1647 old_mip = env->mip; 1648 } 1649 1650 if (csrno != CSR_HVIP) { 1651 gin = get_field(env->hstatus, HSTATUS_VGEIN); 1652 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 1653 } 1654 1655 if (ret_val) { 1656 *ret_val = old_mip; 1657 } 1658 1659 return RISCV_EXCP_NONE; 1660 } 1661 1662 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 1663 target_ulong *ret_val, 1664 target_ulong new_val, target_ulong wr_mask) 1665 { 1666 uint64_t rval; 1667 RISCVException ret; 1668 1669 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 1670 if (ret_val) { 1671 *ret_val = rval; 1672 } 1673 1674 return ret; 1675 } 1676 1677 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 1678 target_ulong *ret_val, 1679 target_ulong new_val, target_ulong wr_mask) 1680 { 1681 uint64_t rval; 1682 RISCVException ret; 1683 1684 ret = rmw_mip64(env, csrno, &rval, 1685 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1686 if (ret_val) { 1687 *ret_val = rval >> 32; 1688 } 1689 1690 return ret; 1691 } 1692 1693 /* Supervisor Trap Setup */ 1694 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 1695 Int128 *val) 1696 { 1697 uint64_t mask = sstatus_v1_10_mask; 1698 uint64_t sstatus = env->mstatus & mask; 1699 if (env->xl != MXL_RV32 || env->debugger) { 1700 mask |= SSTATUS64_UXL; 1701 } 1702 1703 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 1704 return RISCV_EXCP_NONE; 1705 } 1706 1707 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 1708 target_ulong *val) 1709 { 1710 target_ulong mask = (sstatus_v1_10_mask); 1711 if (env->xl != MXL_RV32 || env->debugger) { 1712 mask |= SSTATUS64_UXL; 1713 } 1714 /* TODO: Use SXL not MXL. */ 1715 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 1716 return RISCV_EXCP_NONE; 1717 } 1718 1719 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 1720 target_ulong val) 1721 { 1722 target_ulong mask = (sstatus_v1_10_mask); 1723 1724 if (env->xl != MXL_RV32 || env->debugger) { 1725 if ((val & SSTATUS64_UXL) != 0) { 1726 mask |= SSTATUS64_UXL; 1727 } 1728 } 1729 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 1730 return write_mstatus(env, CSR_MSTATUS, newval); 1731 } 1732 1733 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 1734 uint64_t *ret_val, 1735 uint64_t new_val, uint64_t wr_mask) 1736 { 1737 RISCVException ret; 1738 uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; 1739 1740 /* Bring VS-level bits to correct position */ 1741 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1742 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1743 new_val |= vsbits << 1; 1744 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1745 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1746 wr_mask |= vsbits << 1; 1747 1748 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); 1749 if (ret_val) { 1750 rval &= mask; 1751 vsbits = rval & VS_MODE_INTERRUPTS; 1752 rval &= ~VS_MODE_INTERRUPTS; 1753 *ret_val = rval | (vsbits >> 1); 1754 } 1755 1756 return ret; 1757 } 1758 1759 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 1760 target_ulong *ret_val, 1761 target_ulong new_val, target_ulong wr_mask) 1762 { 1763 uint64_t rval; 1764 RISCVException ret; 1765 1766 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 1767 if (ret_val) { 1768 *ret_val = rval; 1769 } 1770 1771 return ret; 1772 } 1773 1774 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 1775 target_ulong *ret_val, 1776 target_ulong new_val, target_ulong wr_mask) 1777 { 1778 uint64_t rval; 1779 RISCVException ret; 1780 1781 ret = rmw_vsie64(env, csrno, &rval, 1782 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1783 if (ret_val) { 1784 *ret_val = rval >> 32; 1785 } 1786 1787 return ret; 1788 } 1789 1790 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 1791 uint64_t *ret_val, 1792 uint64_t new_val, uint64_t wr_mask) 1793 { 1794 RISCVException ret; 1795 uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; 1796 1797 if (riscv_cpu_virt_enabled(env)) { 1798 if (env->hvictl & HVICTL_VTI) { 1799 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1800 } 1801 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 1802 } else { 1803 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); 1804 } 1805 1806 if (ret_val) { 1807 *ret_val &= mask; 1808 } 1809 1810 return ret; 1811 } 1812 1813 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 1814 target_ulong *ret_val, 1815 target_ulong new_val, target_ulong wr_mask) 1816 { 1817 uint64_t rval; 1818 RISCVException ret; 1819 1820 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 1821 if (ret == RISCV_EXCP_NONE && ret_val) { 1822 *ret_val = rval; 1823 } 1824 1825 return ret; 1826 } 1827 1828 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 1829 target_ulong *ret_val, 1830 target_ulong new_val, target_ulong wr_mask) 1831 { 1832 uint64_t rval; 1833 RISCVException ret; 1834 1835 ret = rmw_sie64(env, csrno, &rval, 1836 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1837 if (ret_val) { 1838 *ret_val = rval >> 32; 1839 } 1840 1841 return ret; 1842 } 1843 1844 static RISCVException read_stvec(CPURISCVState *env, int csrno, 1845 target_ulong *val) 1846 { 1847 *val = env->stvec; 1848 return RISCV_EXCP_NONE; 1849 } 1850 1851 static RISCVException write_stvec(CPURISCVState *env, int csrno, 1852 target_ulong val) 1853 { 1854 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1855 if ((val & 3) < 2) { 1856 env->stvec = val; 1857 } else { 1858 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 1859 } 1860 return RISCV_EXCP_NONE; 1861 } 1862 1863 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 1864 target_ulong *val) 1865 { 1866 *val = env->scounteren; 1867 return RISCV_EXCP_NONE; 1868 } 1869 1870 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 1871 target_ulong val) 1872 { 1873 env->scounteren = val; 1874 return RISCV_EXCP_NONE; 1875 } 1876 1877 /* Supervisor Trap Handling */ 1878 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 1879 Int128 *val) 1880 { 1881 *val = int128_make128(env->sscratch, env->sscratchh); 1882 return RISCV_EXCP_NONE; 1883 } 1884 1885 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 1886 Int128 val) 1887 { 1888 env->sscratch = int128_getlo(val); 1889 env->sscratchh = int128_gethi(val); 1890 return RISCV_EXCP_NONE; 1891 } 1892 1893 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 1894 target_ulong *val) 1895 { 1896 *val = env->sscratch; 1897 return RISCV_EXCP_NONE; 1898 } 1899 1900 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 1901 target_ulong val) 1902 { 1903 env->sscratch = val; 1904 return RISCV_EXCP_NONE; 1905 } 1906 1907 static RISCVException read_sepc(CPURISCVState *env, int csrno, 1908 target_ulong *val) 1909 { 1910 *val = env->sepc; 1911 return RISCV_EXCP_NONE; 1912 } 1913 1914 static RISCVException write_sepc(CPURISCVState *env, int csrno, 1915 target_ulong val) 1916 { 1917 env->sepc = val; 1918 return RISCV_EXCP_NONE; 1919 } 1920 1921 static RISCVException read_scause(CPURISCVState *env, int csrno, 1922 target_ulong *val) 1923 { 1924 *val = env->scause; 1925 return RISCV_EXCP_NONE; 1926 } 1927 1928 static RISCVException write_scause(CPURISCVState *env, int csrno, 1929 target_ulong val) 1930 { 1931 env->scause = val; 1932 return RISCV_EXCP_NONE; 1933 } 1934 1935 static RISCVException read_stval(CPURISCVState *env, int csrno, 1936 target_ulong *val) 1937 { 1938 *val = env->stval; 1939 return RISCV_EXCP_NONE; 1940 } 1941 1942 static RISCVException write_stval(CPURISCVState *env, int csrno, 1943 target_ulong val) 1944 { 1945 env->stval = val; 1946 return RISCV_EXCP_NONE; 1947 } 1948 1949 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 1950 uint64_t *ret_val, 1951 uint64_t new_val, uint64_t wr_mask) 1952 { 1953 RISCVException ret; 1954 uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; 1955 1956 /* Bring VS-level bits to correct position */ 1957 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1958 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1959 new_val |= vsbits << 1; 1960 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1961 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1962 wr_mask |= vsbits << 1; 1963 1964 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); 1965 if (ret_val) { 1966 rval &= mask; 1967 vsbits = rval & VS_MODE_INTERRUPTS; 1968 rval &= ~VS_MODE_INTERRUPTS; 1969 *ret_val = rval | (vsbits >> 1); 1970 } 1971 1972 return ret; 1973 } 1974 1975 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 1976 target_ulong *ret_val, 1977 target_ulong new_val, target_ulong wr_mask) 1978 { 1979 uint64_t rval; 1980 RISCVException ret; 1981 1982 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 1983 if (ret_val) { 1984 *ret_val = rval; 1985 } 1986 1987 return ret; 1988 } 1989 1990 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 1991 target_ulong *ret_val, 1992 target_ulong new_val, target_ulong wr_mask) 1993 { 1994 uint64_t rval; 1995 RISCVException ret; 1996 1997 ret = rmw_vsip64(env, csrno, &rval, 1998 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1999 if (ret_val) { 2000 *ret_val = rval >> 32; 2001 } 2002 2003 return ret; 2004 } 2005 2006 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 2007 uint64_t *ret_val, 2008 uint64_t new_val, uint64_t wr_mask) 2009 { 2010 RISCVException ret; 2011 uint64_t mask = env->mideleg & sip_writable_mask; 2012 2013 if (riscv_cpu_virt_enabled(env)) { 2014 if (env->hvictl & HVICTL_VTI) { 2015 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2016 } 2017 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 2018 } else { 2019 ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); 2020 } 2021 2022 if (ret_val) { 2023 *ret_val &= env->mideleg & S_MODE_INTERRUPTS; 2024 } 2025 2026 return ret; 2027 } 2028 2029 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 2030 target_ulong *ret_val, 2031 target_ulong new_val, target_ulong wr_mask) 2032 { 2033 uint64_t rval; 2034 RISCVException ret; 2035 2036 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 2037 if (ret_val) { 2038 *ret_val = rval; 2039 } 2040 2041 return ret; 2042 } 2043 2044 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 2045 target_ulong *ret_val, 2046 target_ulong new_val, target_ulong wr_mask) 2047 { 2048 uint64_t rval; 2049 RISCVException ret; 2050 2051 ret = rmw_sip64(env, csrno, &rval, 2052 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2053 if (ret_val) { 2054 *ret_val = rval >> 32; 2055 } 2056 2057 return ret; 2058 } 2059 2060 /* Supervisor Protection and Translation */ 2061 static RISCVException read_satp(CPURISCVState *env, int csrno, 2062 target_ulong *val) 2063 { 2064 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2065 *val = 0; 2066 return RISCV_EXCP_NONE; 2067 } 2068 2069 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2070 return RISCV_EXCP_ILLEGAL_INST; 2071 } else { 2072 *val = env->satp; 2073 } 2074 2075 return RISCV_EXCP_NONE; 2076 } 2077 2078 static RISCVException write_satp(CPURISCVState *env, int csrno, 2079 target_ulong val) 2080 { 2081 target_ulong vm, mask; 2082 2083 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2084 return RISCV_EXCP_NONE; 2085 } 2086 2087 if (riscv_cpu_mxl(env) == MXL_RV32) { 2088 vm = validate_vm(env, get_field(val, SATP32_MODE)); 2089 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 2090 } else { 2091 vm = validate_vm(env, get_field(val, SATP64_MODE)); 2092 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 2093 } 2094 2095 if (vm && mask) { 2096 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2097 return RISCV_EXCP_ILLEGAL_INST; 2098 } else { 2099 /* 2100 * The ISA defines SATP.MODE=Bare as "no translation", but we still 2101 * pass these through QEMU's TLB emulation as it improves 2102 * performance. Flushing the TLB on SATP writes with paging 2103 * enabled avoids leaking those invalid cached mappings. 2104 */ 2105 tlb_flush(env_cpu(env)); 2106 env->satp = val; 2107 } 2108 } 2109 return RISCV_EXCP_NONE; 2110 } 2111 2112 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 2113 { 2114 int irq, ret; 2115 target_ulong topei; 2116 uint64_t vseip, vsgein; 2117 uint32_t iid, iprio, hviid, hviprio, gein; 2118 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 2119 2120 gein = get_field(env->hstatus, HSTATUS_VGEIN); 2121 hviid = get_field(env->hvictl, HVICTL_IID); 2122 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 2123 2124 if (gein) { 2125 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 2126 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 2127 if (gein <= env->geilen && vseip) { 2128 siid[scount] = IRQ_S_EXT; 2129 siprio[scount] = IPRIO_MMAXIPRIO + 1; 2130 if (env->aia_ireg_rmw_fn[PRV_S]) { 2131 /* 2132 * Call machine specific IMSIC register emulation for 2133 * reading TOPEI. 2134 */ 2135 ret = env->aia_ireg_rmw_fn[PRV_S]( 2136 env->aia_ireg_rmw_fn_arg[PRV_S], 2137 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 2138 riscv_cpu_mxl_bits(env)), 2139 &topei, 0, 0); 2140 if (!ret && topei) { 2141 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 2142 } 2143 } 2144 scount++; 2145 } 2146 } else { 2147 if (hviid == IRQ_S_EXT && hviprio) { 2148 siid[scount] = IRQ_S_EXT; 2149 siprio[scount] = hviprio; 2150 scount++; 2151 } 2152 } 2153 2154 if (env->hvictl & HVICTL_VTI) { 2155 if (hviid != IRQ_S_EXT) { 2156 siid[scount] = hviid; 2157 siprio[scount] = hviprio; 2158 scount++; 2159 } 2160 } else { 2161 irq = riscv_cpu_vsirq_pending(env); 2162 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 2163 siid[scount] = irq; 2164 siprio[scount] = env->hviprio[irq]; 2165 scount++; 2166 } 2167 } 2168 2169 iid = 0; 2170 iprio = UINT_MAX; 2171 for (s = 0; s < scount; s++) { 2172 if (siprio[s] < iprio) { 2173 iid = siid[s]; 2174 iprio = siprio[s]; 2175 } 2176 } 2177 2178 if (iid) { 2179 if (env->hvictl & HVICTL_IPRIOM) { 2180 if (iprio > IPRIO_MMAXIPRIO) { 2181 iprio = IPRIO_MMAXIPRIO; 2182 } 2183 if (!iprio) { 2184 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 2185 iprio = IPRIO_MMAXIPRIO; 2186 } 2187 } 2188 } else { 2189 iprio = 1; 2190 } 2191 } else { 2192 iprio = 0; 2193 } 2194 2195 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2196 *val |= iprio; 2197 return RISCV_EXCP_NONE; 2198 } 2199 2200 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 2201 { 2202 int irq; 2203 uint8_t iprio; 2204 2205 if (riscv_cpu_virt_enabled(env)) { 2206 return read_vstopi(env, CSR_VSTOPI, val); 2207 } 2208 2209 irq = riscv_cpu_sirq_pending(env); 2210 if (irq <= 0 || irq > 63) { 2211 *val = 0; 2212 } else { 2213 iprio = env->siprio[irq]; 2214 if (!iprio) { 2215 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 2216 iprio = IPRIO_MMAXIPRIO; 2217 } 2218 } 2219 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2220 *val |= iprio; 2221 } 2222 2223 return RISCV_EXCP_NONE; 2224 } 2225 2226 /* Hypervisor Extensions */ 2227 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 2228 target_ulong *val) 2229 { 2230 *val = env->hstatus; 2231 if (riscv_cpu_mxl(env) != MXL_RV32) { 2232 /* We only support 64-bit VSXL */ 2233 *val = set_field(*val, HSTATUS_VSXL, 2); 2234 } 2235 /* We only support little endian */ 2236 *val = set_field(*val, HSTATUS_VSBE, 0); 2237 return RISCV_EXCP_NONE; 2238 } 2239 2240 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 2241 target_ulong val) 2242 { 2243 env->hstatus = val; 2244 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 2245 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 2246 } 2247 if (get_field(val, HSTATUS_VSBE) != 0) { 2248 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 2249 } 2250 return RISCV_EXCP_NONE; 2251 } 2252 2253 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 2254 target_ulong *val) 2255 { 2256 *val = env->hedeleg; 2257 return RISCV_EXCP_NONE; 2258 } 2259 2260 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 2261 target_ulong val) 2262 { 2263 env->hedeleg = val & vs_delegable_excps; 2264 return RISCV_EXCP_NONE; 2265 } 2266 2267 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 2268 uint64_t *ret_val, 2269 uint64_t new_val, uint64_t wr_mask) 2270 { 2271 uint64_t mask = wr_mask & vs_delegable_ints; 2272 2273 if (ret_val) { 2274 *ret_val = env->hideleg & vs_delegable_ints; 2275 } 2276 2277 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 2278 return RISCV_EXCP_NONE; 2279 } 2280 2281 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 2282 target_ulong *ret_val, 2283 target_ulong new_val, target_ulong wr_mask) 2284 { 2285 uint64_t rval; 2286 RISCVException ret; 2287 2288 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 2289 if (ret_val) { 2290 *ret_val = rval; 2291 } 2292 2293 return ret; 2294 } 2295 2296 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 2297 target_ulong *ret_val, 2298 target_ulong new_val, target_ulong wr_mask) 2299 { 2300 uint64_t rval; 2301 RISCVException ret; 2302 2303 ret = rmw_hideleg64(env, csrno, &rval, 2304 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2305 if (ret_val) { 2306 *ret_val = rval >> 32; 2307 } 2308 2309 return ret; 2310 } 2311 2312 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2313 uint64_t *ret_val, 2314 uint64_t new_val, uint64_t wr_mask) 2315 { 2316 RISCVException ret; 2317 2318 ret = rmw_mip64(env, csrno, ret_val, new_val, 2319 wr_mask & hvip_writable_mask); 2320 if (ret_val) { 2321 *ret_val &= VS_MODE_INTERRUPTS; 2322 } 2323 2324 return ret; 2325 } 2326 2327 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 2328 target_ulong *ret_val, 2329 target_ulong new_val, target_ulong wr_mask) 2330 { 2331 uint64_t rval; 2332 RISCVException ret; 2333 2334 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 2335 if (ret_val) { 2336 *ret_val = rval; 2337 } 2338 2339 return ret; 2340 } 2341 2342 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 2343 target_ulong *ret_val, 2344 target_ulong new_val, target_ulong wr_mask) 2345 { 2346 uint64_t rval; 2347 RISCVException ret; 2348 2349 ret = rmw_hvip64(env, csrno, &rval, 2350 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2351 if (ret_val) { 2352 *ret_val = rval >> 32; 2353 } 2354 2355 return ret; 2356 } 2357 2358 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 2359 target_ulong *ret_value, 2360 target_ulong new_value, target_ulong write_mask) 2361 { 2362 int ret = rmw_mip(env, csrno, ret_value, new_value, 2363 write_mask & hip_writable_mask); 2364 2365 if (ret_value) { 2366 *ret_value &= HS_MODE_INTERRUPTS; 2367 } 2368 return ret; 2369 } 2370 2371 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 2372 target_ulong *ret_val, 2373 target_ulong new_val, target_ulong wr_mask) 2374 { 2375 uint64_t rval; 2376 RISCVException ret; 2377 2378 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 2379 if (ret_val) { 2380 *ret_val = rval & HS_MODE_INTERRUPTS; 2381 } 2382 2383 return ret; 2384 } 2385 2386 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 2387 target_ulong *val) 2388 { 2389 *val = env->hcounteren; 2390 return RISCV_EXCP_NONE; 2391 } 2392 2393 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 2394 target_ulong val) 2395 { 2396 env->hcounteren = val; 2397 return RISCV_EXCP_NONE; 2398 } 2399 2400 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 2401 target_ulong *val) 2402 { 2403 if (val) { 2404 *val = env->hgeie; 2405 } 2406 return RISCV_EXCP_NONE; 2407 } 2408 2409 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 2410 target_ulong val) 2411 { 2412 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 2413 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 2414 env->hgeie = val; 2415 /* Update mip.SGEIP bit */ 2416 riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, 2417 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 2418 return RISCV_EXCP_NONE; 2419 } 2420 2421 static RISCVException read_htval(CPURISCVState *env, int csrno, 2422 target_ulong *val) 2423 { 2424 *val = env->htval; 2425 return RISCV_EXCP_NONE; 2426 } 2427 2428 static RISCVException write_htval(CPURISCVState *env, int csrno, 2429 target_ulong val) 2430 { 2431 env->htval = val; 2432 return RISCV_EXCP_NONE; 2433 } 2434 2435 static RISCVException read_htinst(CPURISCVState *env, int csrno, 2436 target_ulong *val) 2437 { 2438 *val = env->htinst; 2439 return RISCV_EXCP_NONE; 2440 } 2441 2442 static RISCVException write_htinst(CPURISCVState *env, int csrno, 2443 target_ulong val) 2444 { 2445 return RISCV_EXCP_NONE; 2446 } 2447 2448 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 2449 target_ulong *val) 2450 { 2451 if (val) { 2452 *val = env->hgeip; 2453 } 2454 return RISCV_EXCP_NONE; 2455 } 2456 2457 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 2458 target_ulong *val) 2459 { 2460 *val = env->hgatp; 2461 return RISCV_EXCP_NONE; 2462 } 2463 2464 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 2465 target_ulong val) 2466 { 2467 env->hgatp = val; 2468 return RISCV_EXCP_NONE; 2469 } 2470 2471 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 2472 target_ulong *val) 2473 { 2474 if (!env->rdtime_fn) { 2475 return RISCV_EXCP_ILLEGAL_INST; 2476 } 2477 2478 *val = env->htimedelta; 2479 return RISCV_EXCP_NONE; 2480 } 2481 2482 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 2483 target_ulong val) 2484 { 2485 if (!env->rdtime_fn) { 2486 return RISCV_EXCP_ILLEGAL_INST; 2487 } 2488 2489 if (riscv_cpu_mxl(env) == MXL_RV32) { 2490 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 2491 } else { 2492 env->htimedelta = val; 2493 } 2494 return RISCV_EXCP_NONE; 2495 } 2496 2497 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 2498 target_ulong *val) 2499 { 2500 if (!env->rdtime_fn) { 2501 return RISCV_EXCP_ILLEGAL_INST; 2502 } 2503 2504 *val = env->htimedelta >> 32; 2505 return RISCV_EXCP_NONE; 2506 } 2507 2508 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 2509 target_ulong val) 2510 { 2511 if (!env->rdtime_fn) { 2512 return RISCV_EXCP_ILLEGAL_INST; 2513 } 2514 2515 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 2516 return RISCV_EXCP_NONE; 2517 } 2518 2519 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 2520 { 2521 *val = env->hvictl; 2522 return RISCV_EXCP_NONE; 2523 } 2524 2525 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 2526 { 2527 env->hvictl = val & HVICTL_VALID_MASK; 2528 return RISCV_EXCP_NONE; 2529 } 2530 2531 static int read_hvipriox(CPURISCVState *env, int first_index, 2532 uint8_t *iprio, target_ulong *val) 2533 { 2534 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2535 2536 /* First index has to be a multiple of number of irqs per register */ 2537 if (first_index % num_irqs) { 2538 return (riscv_cpu_virt_enabled(env)) ? 2539 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2540 } 2541 2542 /* Fill-up return value */ 2543 *val = 0; 2544 for (i = 0; i < num_irqs; i++) { 2545 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2546 continue; 2547 } 2548 if (rdzero) { 2549 continue; 2550 } 2551 *val |= ((target_ulong)iprio[irq]) << (i * 8); 2552 } 2553 2554 return RISCV_EXCP_NONE; 2555 } 2556 2557 static int write_hvipriox(CPURISCVState *env, int first_index, 2558 uint8_t *iprio, target_ulong val) 2559 { 2560 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2561 2562 /* First index has to be a multiple of number of irqs per register */ 2563 if (first_index % num_irqs) { 2564 return (riscv_cpu_virt_enabled(env)) ? 2565 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2566 } 2567 2568 /* Fill-up priority arrary */ 2569 for (i = 0; i < num_irqs; i++) { 2570 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2571 continue; 2572 } 2573 if (rdzero) { 2574 iprio[irq] = 0; 2575 } else { 2576 iprio[irq] = (val >> (i * 8)) & 0xff; 2577 } 2578 } 2579 2580 return RISCV_EXCP_NONE; 2581 } 2582 2583 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 2584 { 2585 return read_hvipriox(env, 0, env->hviprio, val); 2586 } 2587 2588 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 2589 { 2590 return write_hvipriox(env, 0, env->hviprio, val); 2591 } 2592 2593 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 2594 { 2595 return read_hvipriox(env, 4, env->hviprio, val); 2596 } 2597 2598 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 2599 { 2600 return write_hvipriox(env, 4, env->hviprio, val); 2601 } 2602 2603 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 2604 { 2605 return read_hvipriox(env, 8, env->hviprio, val); 2606 } 2607 2608 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 2609 { 2610 return write_hvipriox(env, 8, env->hviprio, val); 2611 } 2612 2613 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 2614 { 2615 return read_hvipriox(env, 12, env->hviprio, val); 2616 } 2617 2618 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 2619 { 2620 return write_hvipriox(env, 12, env->hviprio, val); 2621 } 2622 2623 /* Virtual CSR Registers */ 2624 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 2625 target_ulong *val) 2626 { 2627 *val = env->vsstatus; 2628 return RISCV_EXCP_NONE; 2629 } 2630 2631 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 2632 target_ulong val) 2633 { 2634 uint64_t mask = (target_ulong)-1; 2635 if ((val & VSSTATUS64_UXL) == 0) { 2636 mask &= ~VSSTATUS64_UXL; 2637 } 2638 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 2639 return RISCV_EXCP_NONE; 2640 } 2641 2642 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 2643 { 2644 *val = env->vstvec; 2645 return RISCV_EXCP_NONE; 2646 } 2647 2648 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 2649 target_ulong val) 2650 { 2651 env->vstvec = val; 2652 return RISCV_EXCP_NONE; 2653 } 2654 2655 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 2656 target_ulong *val) 2657 { 2658 *val = env->vsscratch; 2659 return RISCV_EXCP_NONE; 2660 } 2661 2662 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 2663 target_ulong val) 2664 { 2665 env->vsscratch = val; 2666 return RISCV_EXCP_NONE; 2667 } 2668 2669 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 2670 target_ulong *val) 2671 { 2672 *val = env->vsepc; 2673 return RISCV_EXCP_NONE; 2674 } 2675 2676 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 2677 target_ulong val) 2678 { 2679 env->vsepc = val; 2680 return RISCV_EXCP_NONE; 2681 } 2682 2683 static RISCVException read_vscause(CPURISCVState *env, int csrno, 2684 target_ulong *val) 2685 { 2686 *val = env->vscause; 2687 return RISCV_EXCP_NONE; 2688 } 2689 2690 static RISCVException write_vscause(CPURISCVState *env, int csrno, 2691 target_ulong val) 2692 { 2693 env->vscause = val; 2694 return RISCV_EXCP_NONE; 2695 } 2696 2697 static RISCVException read_vstval(CPURISCVState *env, int csrno, 2698 target_ulong *val) 2699 { 2700 *val = env->vstval; 2701 return RISCV_EXCP_NONE; 2702 } 2703 2704 static RISCVException write_vstval(CPURISCVState *env, int csrno, 2705 target_ulong val) 2706 { 2707 env->vstval = val; 2708 return RISCV_EXCP_NONE; 2709 } 2710 2711 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 2712 target_ulong *val) 2713 { 2714 *val = env->vsatp; 2715 return RISCV_EXCP_NONE; 2716 } 2717 2718 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 2719 target_ulong val) 2720 { 2721 env->vsatp = val; 2722 return RISCV_EXCP_NONE; 2723 } 2724 2725 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 2726 target_ulong *val) 2727 { 2728 *val = env->mtval2; 2729 return RISCV_EXCP_NONE; 2730 } 2731 2732 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 2733 target_ulong val) 2734 { 2735 env->mtval2 = val; 2736 return RISCV_EXCP_NONE; 2737 } 2738 2739 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 2740 target_ulong *val) 2741 { 2742 *val = env->mtinst; 2743 return RISCV_EXCP_NONE; 2744 } 2745 2746 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 2747 target_ulong val) 2748 { 2749 env->mtinst = val; 2750 return RISCV_EXCP_NONE; 2751 } 2752 2753 /* Physical Memory Protection */ 2754 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 2755 target_ulong *val) 2756 { 2757 *val = mseccfg_csr_read(env); 2758 return RISCV_EXCP_NONE; 2759 } 2760 2761 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 2762 target_ulong val) 2763 { 2764 mseccfg_csr_write(env, val); 2765 return RISCV_EXCP_NONE; 2766 } 2767 2768 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) 2769 { 2770 /* TODO: RV128 restriction check */ 2771 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 2772 return false; 2773 } 2774 return true; 2775 } 2776 2777 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 2778 target_ulong *val) 2779 { 2780 uint32_t reg_index = csrno - CSR_PMPCFG0; 2781 2782 if (!check_pmp_reg_index(env, reg_index)) { 2783 return RISCV_EXCP_ILLEGAL_INST; 2784 } 2785 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 2786 return RISCV_EXCP_NONE; 2787 } 2788 2789 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 2790 target_ulong val) 2791 { 2792 uint32_t reg_index = csrno - CSR_PMPCFG0; 2793 2794 if (!check_pmp_reg_index(env, reg_index)) { 2795 return RISCV_EXCP_ILLEGAL_INST; 2796 } 2797 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 2798 return RISCV_EXCP_NONE; 2799 } 2800 2801 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 2802 target_ulong *val) 2803 { 2804 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 2805 return RISCV_EXCP_NONE; 2806 } 2807 2808 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 2809 target_ulong val) 2810 { 2811 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 2812 return RISCV_EXCP_NONE; 2813 } 2814 2815 static RISCVException read_tselect(CPURISCVState *env, int csrno, 2816 target_ulong *val) 2817 { 2818 *val = tselect_csr_read(env); 2819 return RISCV_EXCP_NONE; 2820 } 2821 2822 static RISCVException write_tselect(CPURISCVState *env, int csrno, 2823 target_ulong val) 2824 { 2825 tselect_csr_write(env, val); 2826 return RISCV_EXCP_NONE; 2827 } 2828 2829 static RISCVException read_tdata(CPURISCVState *env, int csrno, 2830 target_ulong *val) 2831 { 2832 /* return 0 in tdata1 to end the trigger enumeration */ 2833 if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { 2834 *val = 0; 2835 return RISCV_EXCP_NONE; 2836 } 2837 2838 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2839 return RISCV_EXCP_ILLEGAL_INST; 2840 } 2841 2842 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 2843 return RISCV_EXCP_NONE; 2844 } 2845 2846 static RISCVException write_tdata(CPURISCVState *env, int csrno, 2847 target_ulong val) 2848 { 2849 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2850 return RISCV_EXCP_ILLEGAL_INST; 2851 } 2852 2853 tdata_csr_write(env, csrno - CSR_TDATA1, val); 2854 return RISCV_EXCP_NONE; 2855 } 2856 2857 /* 2858 * Functions to access Pointer Masking feature registers 2859 * We have to check if current priv lvl could modify 2860 * csr in given mode 2861 */ 2862 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 2863 { 2864 int csr_priv = get_field(csrno, 0x300); 2865 int pm_current; 2866 2867 if (env->debugger) { 2868 return false; 2869 } 2870 /* 2871 * If priv lvls differ that means we're accessing csr from higher priv lvl, 2872 * so allow the access 2873 */ 2874 if (env->priv != csr_priv) { 2875 return false; 2876 } 2877 switch (env->priv) { 2878 case PRV_M: 2879 pm_current = get_field(env->mmte, M_PM_CURRENT); 2880 break; 2881 case PRV_S: 2882 pm_current = get_field(env->mmte, S_PM_CURRENT); 2883 break; 2884 case PRV_U: 2885 pm_current = get_field(env->mmte, U_PM_CURRENT); 2886 break; 2887 default: 2888 g_assert_not_reached(); 2889 } 2890 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 2891 return !pm_current; 2892 } 2893 2894 static RISCVException read_mmte(CPURISCVState *env, int csrno, 2895 target_ulong *val) 2896 { 2897 *val = env->mmte & MMTE_MASK; 2898 return RISCV_EXCP_NONE; 2899 } 2900 2901 static RISCVException write_mmte(CPURISCVState *env, int csrno, 2902 target_ulong val) 2903 { 2904 uint64_t mstatus; 2905 target_ulong wpri_val = val & MMTE_MASK; 2906 2907 if (val != wpri_val) { 2908 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2909 "MMTE: WPRI violation written 0x", val, 2910 "vs expected 0x", wpri_val); 2911 } 2912 /* for machine mode pm.current is hardwired to 1 */ 2913 wpri_val |= MMTE_M_PM_CURRENT; 2914 2915 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 2916 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 2917 env->mmte = wpri_val | PM_EXT_DIRTY; 2918 riscv_cpu_update_mask(env); 2919 2920 /* Set XS and SD bits, since PM CSRs are dirty */ 2921 mstatus = env->mstatus | MSTATUS_XS; 2922 write_mstatus(env, csrno, mstatus); 2923 return RISCV_EXCP_NONE; 2924 } 2925 2926 static RISCVException read_smte(CPURISCVState *env, int csrno, 2927 target_ulong *val) 2928 { 2929 *val = env->mmte & SMTE_MASK; 2930 return RISCV_EXCP_NONE; 2931 } 2932 2933 static RISCVException write_smte(CPURISCVState *env, int csrno, 2934 target_ulong val) 2935 { 2936 target_ulong wpri_val = val & SMTE_MASK; 2937 2938 if (val != wpri_val) { 2939 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2940 "SMTE: WPRI violation written 0x", val, 2941 "vs expected 0x", wpri_val); 2942 } 2943 2944 /* if pm.current==0 we can't modify current PM CSRs */ 2945 if (check_pm_current_disabled(env, csrno)) { 2946 return RISCV_EXCP_NONE; 2947 } 2948 2949 wpri_val |= (env->mmte & ~SMTE_MASK); 2950 write_mmte(env, csrno, wpri_val); 2951 return RISCV_EXCP_NONE; 2952 } 2953 2954 static RISCVException read_umte(CPURISCVState *env, int csrno, 2955 target_ulong *val) 2956 { 2957 *val = env->mmte & UMTE_MASK; 2958 return RISCV_EXCP_NONE; 2959 } 2960 2961 static RISCVException write_umte(CPURISCVState *env, int csrno, 2962 target_ulong val) 2963 { 2964 target_ulong wpri_val = val & UMTE_MASK; 2965 2966 if (val != wpri_val) { 2967 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2968 "UMTE: WPRI violation written 0x", val, 2969 "vs expected 0x", wpri_val); 2970 } 2971 2972 if (check_pm_current_disabled(env, csrno)) { 2973 return RISCV_EXCP_NONE; 2974 } 2975 2976 wpri_val |= (env->mmte & ~UMTE_MASK); 2977 write_mmte(env, csrno, wpri_val); 2978 return RISCV_EXCP_NONE; 2979 } 2980 2981 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 2982 target_ulong *val) 2983 { 2984 *val = env->mpmmask; 2985 return RISCV_EXCP_NONE; 2986 } 2987 2988 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 2989 target_ulong val) 2990 { 2991 uint64_t mstatus; 2992 2993 env->mpmmask = val; 2994 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 2995 env->cur_pmmask = val; 2996 } 2997 env->mmte |= PM_EXT_DIRTY; 2998 2999 /* Set XS and SD bits, since PM CSRs are dirty */ 3000 mstatus = env->mstatus | MSTATUS_XS; 3001 write_mstatus(env, csrno, mstatus); 3002 return RISCV_EXCP_NONE; 3003 } 3004 3005 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 3006 target_ulong *val) 3007 { 3008 *val = env->spmmask; 3009 return RISCV_EXCP_NONE; 3010 } 3011 3012 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 3013 target_ulong val) 3014 { 3015 uint64_t mstatus; 3016 3017 /* if pm.current==0 we can't modify current PM CSRs */ 3018 if (check_pm_current_disabled(env, csrno)) { 3019 return RISCV_EXCP_NONE; 3020 } 3021 env->spmmask = val; 3022 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3023 env->cur_pmmask = val; 3024 } 3025 env->mmte |= PM_EXT_DIRTY; 3026 3027 /* Set XS and SD bits, since PM CSRs are dirty */ 3028 mstatus = env->mstatus | MSTATUS_XS; 3029 write_mstatus(env, csrno, mstatus); 3030 return RISCV_EXCP_NONE; 3031 } 3032 3033 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 3034 target_ulong *val) 3035 { 3036 *val = env->upmmask; 3037 return RISCV_EXCP_NONE; 3038 } 3039 3040 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 3041 target_ulong val) 3042 { 3043 uint64_t mstatus; 3044 3045 /* if pm.current==0 we can't modify current PM CSRs */ 3046 if (check_pm_current_disabled(env, csrno)) { 3047 return RISCV_EXCP_NONE; 3048 } 3049 env->upmmask = val; 3050 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3051 env->cur_pmmask = val; 3052 } 3053 env->mmte |= PM_EXT_DIRTY; 3054 3055 /* Set XS and SD bits, since PM CSRs are dirty */ 3056 mstatus = env->mstatus | MSTATUS_XS; 3057 write_mstatus(env, csrno, mstatus); 3058 return RISCV_EXCP_NONE; 3059 } 3060 3061 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 3062 target_ulong *val) 3063 { 3064 *val = env->mpmbase; 3065 return RISCV_EXCP_NONE; 3066 } 3067 3068 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 3069 target_ulong val) 3070 { 3071 uint64_t mstatus; 3072 3073 env->mpmbase = val; 3074 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 3075 env->cur_pmbase = val; 3076 } 3077 env->mmte |= PM_EXT_DIRTY; 3078 3079 /* Set XS and SD bits, since PM CSRs are dirty */ 3080 mstatus = env->mstatus | MSTATUS_XS; 3081 write_mstatus(env, csrno, mstatus); 3082 return RISCV_EXCP_NONE; 3083 } 3084 3085 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 3086 target_ulong *val) 3087 { 3088 *val = env->spmbase; 3089 return RISCV_EXCP_NONE; 3090 } 3091 3092 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 3093 target_ulong val) 3094 { 3095 uint64_t mstatus; 3096 3097 /* if pm.current==0 we can't modify current PM CSRs */ 3098 if (check_pm_current_disabled(env, csrno)) { 3099 return RISCV_EXCP_NONE; 3100 } 3101 env->spmbase = val; 3102 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3103 env->cur_pmbase = val; 3104 } 3105 env->mmte |= PM_EXT_DIRTY; 3106 3107 /* Set XS and SD bits, since PM CSRs are dirty */ 3108 mstatus = env->mstatus | MSTATUS_XS; 3109 write_mstatus(env, csrno, mstatus); 3110 return RISCV_EXCP_NONE; 3111 } 3112 3113 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 3114 target_ulong *val) 3115 { 3116 *val = env->upmbase; 3117 return RISCV_EXCP_NONE; 3118 } 3119 3120 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 3121 target_ulong val) 3122 { 3123 uint64_t mstatus; 3124 3125 /* if pm.current==0 we can't modify current PM CSRs */ 3126 if (check_pm_current_disabled(env, csrno)) { 3127 return RISCV_EXCP_NONE; 3128 } 3129 env->upmbase = val; 3130 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3131 env->cur_pmbase = val; 3132 } 3133 env->mmte |= PM_EXT_DIRTY; 3134 3135 /* Set XS and SD bits, since PM CSRs are dirty */ 3136 mstatus = env->mstatus | MSTATUS_XS; 3137 write_mstatus(env, csrno, mstatus); 3138 return RISCV_EXCP_NONE; 3139 } 3140 3141 #endif 3142 3143 /* Crypto Extension */ 3144 static RISCVException rmw_seed(CPURISCVState *env, int csrno, 3145 target_ulong *ret_value, 3146 target_ulong new_value, 3147 target_ulong write_mask) 3148 { 3149 uint16_t random_v; 3150 Error *random_e = NULL; 3151 int random_r; 3152 target_ulong rval; 3153 3154 random_r = qemu_guest_getrandom(&random_v, 2, &random_e); 3155 if (unlikely(random_r < 0)) { 3156 /* 3157 * Failed, for unknown reasons in the crypto subsystem. 3158 * The best we can do is log the reason and return a 3159 * failure indication to the guest. There is no reason 3160 * we know to expect the failure to be transitory, so 3161 * indicate DEAD to avoid having the guest spin on WAIT. 3162 */ 3163 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 3164 __func__, error_get_pretty(random_e)); 3165 error_free(random_e); 3166 rval = SEED_OPST_DEAD; 3167 } else { 3168 rval = random_v | SEED_OPST_ES16; 3169 } 3170 3171 if (ret_value) { 3172 *ret_value = rval; 3173 } 3174 3175 return RISCV_EXCP_NONE; 3176 } 3177 3178 /* 3179 * riscv_csrrw - read and/or update control and status register 3180 * 3181 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 3182 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 3183 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 3184 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 3185 */ 3186 3187 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 3188 int csrno, 3189 bool write_mask, 3190 RISCVCPU *cpu) 3191 { 3192 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 3193 int read_only = get_field(csrno, 0xC00) == 3; 3194 int csr_min_priv = csr_ops[csrno].min_priv_ver; 3195 #if !defined(CONFIG_USER_ONLY) 3196 int csr_priv, effective_priv = env->priv; 3197 3198 if (riscv_has_ext(env, RVH) && env->priv == PRV_S) { 3199 /* 3200 * We are in either HS or VS mode. 3201 * Add 1 to the effective privledge level to allow us to access the 3202 * Hypervisor CSRs. The `hmode` predicate will determine if access 3203 * should be allowed(HS) or if a virtual instruction exception should be 3204 * raised(VS). 3205 */ 3206 effective_priv++; 3207 } 3208 3209 csr_priv = get_field(csrno, 0x300); 3210 if (!env->debugger && (effective_priv < csr_priv)) { 3211 if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { 3212 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 3213 } 3214 return RISCV_EXCP_ILLEGAL_INST; 3215 } 3216 #endif 3217 if (write_mask && read_only) { 3218 return RISCV_EXCP_ILLEGAL_INST; 3219 } 3220 3221 /* ensure the CSR extension is enabled. */ 3222 if (!cpu->cfg.ext_icsr) { 3223 return RISCV_EXCP_ILLEGAL_INST; 3224 } 3225 3226 /* check predicate */ 3227 if (!csr_ops[csrno].predicate) { 3228 return RISCV_EXCP_ILLEGAL_INST; 3229 } 3230 3231 if (env->priv_ver < csr_min_priv) { 3232 return RISCV_EXCP_ILLEGAL_INST; 3233 } 3234 3235 return csr_ops[csrno].predicate(env, csrno); 3236 } 3237 3238 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 3239 target_ulong *ret_value, 3240 target_ulong new_value, 3241 target_ulong write_mask) 3242 { 3243 RISCVException ret; 3244 target_ulong old_value; 3245 3246 /* execute combined read/write operation if it exists */ 3247 if (csr_ops[csrno].op) { 3248 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 3249 } 3250 3251 /* if no accessor exists then return failure */ 3252 if (!csr_ops[csrno].read) { 3253 return RISCV_EXCP_ILLEGAL_INST; 3254 } 3255 /* read old value */ 3256 ret = csr_ops[csrno].read(env, csrno, &old_value); 3257 if (ret != RISCV_EXCP_NONE) { 3258 return ret; 3259 } 3260 3261 /* write value if writable and write mask set, otherwise drop writes */ 3262 if (write_mask) { 3263 new_value = (old_value & ~write_mask) | (new_value & write_mask); 3264 if (csr_ops[csrno].write) { 3265 ret = csr_ops[csrno].write(env, csrno, new_value); 3266 if (ret != RISCV_EXCP_NONE) { 3267 return ret; 3268 } 3269 } 3270 } 3271 3272 /* return old value */ 3273 if (ret_value) { 3274 *ret_value = old_value; 3275 } 3276 3277 return RISCV_EXCP_NONE; 3278 } 3279 3280 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 3281 target_ulong *ret_value, 3282 target_ulong new_value, target_ulong write_mask) 3283 { 3284 RISCVCPU *cpu = env_archcpu(env); 3285 3286 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); 3287 if (ret != RISCV_EXCP_NONE) { 3288 return ret; 3289 } 3290 3291 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 3292 } 3293 3294 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 3295 Int128 *ret_value, 3296 Int128 new_value, 3297 Int128 write_mask) 3298 { 3299 RISCVException ret; 3300 Int128 old_value; 3301 3302 /* read old value */ 3303 ret = csr_ops[csrno].read128(env, csrno, &old_value); 3304 if (ret != RISCV_EXCP_NONE) { 3305 return ret; 3306 } 3307 3308 /* write value if writable and write mask set, otherwise drop writes */ 3309 if (int128_nz(write_mask)) { 3310 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 3311 int128_and(new_value, write_mask)); 3312 if (csr_ops[csrno].write128) { 3313 ret = csr_ops[csrno].write128(env, csrno, new_value); 3314 if (ret != RISCV_EXCP_NONE) { 3315 return ret; 3316 } 3317 } else if (csr_ops[csrno].write) { 3318 /* avoids having to write wrappers for all registers */ 3319 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 3320 if (ret != RISCV_EXCP_NONE) { 3321 return ret; 3322 } 3323 } 3324 } 3325 3326 /* return old value */ 3327 if (ret_value) { 3328 *ret_value = old_value; 3329 } 3330 3331 return RISCV_EXCP_NONE; 3332 } 3333 3334 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 3335 Int128 *ret_value, 3336 Int128 new_value, Int128 write_mask) 3337 { 3338 RISCVException ret; 3339 RISCVCPU *cpu = env_archcpu(env); 3340 3341 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); 3342 if (ret != RISCV_EXCP_NONE) { 3343 return ret; 3344 } 3345 3346 if (csr_ops[csrno].read128) { 3347 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 3348 } 3349 3350 /* 3351 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 3352 * at all defined. 3353 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 3354 * significant), for those, this fallback is correctly handling the accesses 3355 */ 3356 target_ulong old_value; 3357 ret = riscv_csrrw_do64(env, csrno, &old_value, 3358 int128_getlo(new_value), 3359 int128_getlo(write_mask)); 3360 if (ret == RISCV_EXCP_NONE && ret_value) { 3361 *ret_value = int128_make64(old_value); 3362 } 3363 return ret; 3364 } 3365 3366 /* 3367 * Debugger support. If not in user mode, set env->debugger before the 3368 * riscv_csrrw call and clear it after the call. 3369 */ 3370 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 3371 target_ulong *ret_value, 3372 target_ulong new_value, 3373 target_ulong write_mask) 3374 { 3375 RISCVException ret; 3376 #if !defined(CONFIG_USER_ONLY) 3377 env->debugger = true; 3378 #endif 3379 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 3380 #if !defined(CONFIG_USER_ONLY) 3381 env->debugger = false; 3382 #endif 3383 return ret; 3384 } 3385 3386 /* Control and Status Register function table */ 3387 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 3388 /* User Floating-Point CSRs */ 3389 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 3390 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 3391 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 3392 /* Vector CSRs */ 3393 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, 3394 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3395 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, 3396 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3397 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, 3398 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3399 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, 3400 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3401 [CSR_VL] = { "vl", vs, read_vl, 3402 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3403 [CSR_VTYPE] = { "vtype", vs, read_vtype, 3404 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3405 [CSR_VLENB] = { "vlenb", vs, read_vlenb, 3406 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3407 /* User Timers and Counters */ 3408 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 3409 [CSR_INSTRET] = { "instret", ctr, read_instret }, 3410 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 3411 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 3412 3413 /* 3414 * In privileged mode, the monitor will have to emulate TIME CSRs only if 3415 * rdtime callback is not provided by machine/platform emulation. 3416 */ 3417 [CSR_TIME] = { "time", ctr, read_time }, 3418 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 3419 3420 /* Crypto Extension */ 3421 [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, 3422 3423 #if !defined(CONFIG_USER_ONLY) 3424 /* Machine Timers and Counters */ 3425 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 3426 [CSR_MINSTRET] = { "minstret", any, read_instret }, 3427 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 3428 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 3429 3430 /* Machine Information Registers */ 3431 [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, 3432 [CSR_MARCHID] = { "marchid", any, read_marchid }, 3433 [CSR_MIMPID] = { "mimpid", any, read_mimpid }, 3434 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 3435 3436 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 3437 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3438 /* Machine Trap Setup */ 3439 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, 3440 read_mstatus_i128 }, 3441 [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, 3442 read_misa_i128 }, 3443 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 3444 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 3445 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 3446 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 3447 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 3448 3449 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 3450 3451 /* Machine Trap Handling */ 3452 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, 3453 read_mscratch_i128, write_mscratch_i128 }, 3454 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 3455 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 3456 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 3457 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 3458 3459 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 3460 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 3461 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 3462 3463 /* Machine-Level Interrupts (AIA) */ 3464 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 3465 3466 /* Machine-Level IMSIC Interface (AIA) */ 3467 [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3468 [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3469 [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3470 [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3471 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 3472 3473 /* Virtual Interrupts for Supervisor Level (AIA) */ 3474 [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, 3475 [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, 3476 3477 /* Machine-Level High-Half CSRs (AIA) */ 3478 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 3479 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 3480 [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, 3481 [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, 3482 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 3483 3484 /* Execution environment configuration */ 3485 [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, 3486 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3487 [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, 3488 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3489 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 3490 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3491 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 3492 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3493 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 3494 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3495 3496 /* Supervisor Trap Setup */ 3497 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, 3498 read_sstatus_i128 }, 3499 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 3500 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 3501 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 3502 3503 /* Supervisor Trap Handling */ 3504 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, 3505 read_sscratch_i128, write_sscratch_i128 }, 3506 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 3507 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 3508 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 3509 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 3510 3511 /* Supervisor Protection and Translation */ 3512 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 3513 3514 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 3515 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 3516 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 3517 3518 /* Supervisor-Level Interrupts (AIA) */ 3519 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 3520 3521 /* Supervisor-Level IMSIC Interface (AIA) */ 3522 [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3523 [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3524 [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3525 [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3526 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 3527 3528 /* Supervisor-Level High-Half CSRs (AIA) */ 3529 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 3530 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 3531 3532 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 3533 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3534 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 3535 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3536 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 3537 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3538 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 3539 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3540 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 3541 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3542 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 3543 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3544 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, 3545 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3546 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 3547 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3548 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 3549 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3550 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 3551 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3552 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 3553 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3554 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, 3555 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3556 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, 3557 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3558 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, 3559 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3560 3561 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, 3562 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3563 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 3564 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3565 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 3566 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3567 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 3568 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3569 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, 3570 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3571 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 3572 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3573 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 3574 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3575 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 3576 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3577 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 3578 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3579 3580 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 3581 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3582 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 3583 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3584 3585 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 3586 [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, 3587 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, 3588 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, 3589 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, 3590 3591 /* 3592 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 3593 */ 3594 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, 3595 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 3596 3597 /* VS-Level Interrupts (H-extension with AIA) */ 3598 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 3599 3600 /* VS-Level IMSIC Interface (H-extension with AIA) */ 3601 [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3602 [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3603 [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3604 [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3605 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 3606 3607 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 3608 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, 3609 [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, 3610 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 3611 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, 3612 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, 3613 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 3614 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 3615 3616 /* Physical Memory Protection */ 3617 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 3618 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3619 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 3620 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 3621 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 3622 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 3623 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 3624 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 3625 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 3626 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 3627 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 3628 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 3629 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 3630 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 3631 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 3632 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 3633 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 3634 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 3635 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 3636 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 3637 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 3638 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 3639 3640 /* Debug CSRs */ 3641 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 3642 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 3643 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 3644 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 3645 3646 /* User Pointer Masking */ 3647 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 3648 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 3649 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 3650 /* Machine Pointer Masking */ 3651 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 3652 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 3653 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 3654 /* Supervisor Pointer Masking */ 3655 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 3656 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 3657 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 3658 3659 /* Performance Counters */ 3660 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 3661 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 3662 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 3663 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 3664 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 3665 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 3666 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 3667 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 3668 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 3669 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 3670 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 3671 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 3672 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 3673 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 3674 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 3675 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 3676 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 3677 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 3678 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 3679 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 3680 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 3681 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 3682 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 3683 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 3684 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 3685 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 3686 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 3687 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 3688 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 3689 3690 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 3691 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 3692 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 3693 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 3694 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 3695 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 3696 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 3697 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 3698 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 3699 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 3700 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 3701 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 3702 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 3703 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 3704 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 3705 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 3706 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 3707 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 3708 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 3709 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 3710 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 3711 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 3712 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 3713 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 3714 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 3715 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 3716 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 3717 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 3718 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 3719 3720 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 3721 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 3722 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 3723 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 3724 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 3725 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 3726 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 3727 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 3728 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 3729 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 3730 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 3731 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 3732 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 3733 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 3734 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 3735 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 3736 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 3737 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 3738 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 3739 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 3740 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 3741 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 3742 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 3743 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 3744 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 3745 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 3746 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 3747 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 3748 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 3749 3750 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 3751 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 3752 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 3753 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 3754 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 3755 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 3756 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 3757 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 3758 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 3759 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 3760 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 3761 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 3762 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 3763 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 3764 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 3765 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 3766 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 3767 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 3768 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 3769 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 3770 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 3771 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 3772 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 3773 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 3774 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 3775 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 3776 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 3777 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 3778 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 3779 3780 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 3781 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 3782 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 3783 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 3784 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 3785 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 3786 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 3787 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 3788 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 3789 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 3790 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 3791 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 3792 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 3793 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 3794 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 3795 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 3796 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 3797 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 3798 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 3799 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 3800 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 3801 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 3802 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 3803 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 3804 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 3805 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 3806 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 3807 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 3808 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 3809 #endif /* !CONFIG_USER_ONLY */ 3810 }; 3811