1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 42 return RISCV_EXCP_ILLEGAL_INST; 43 } 44 #endif 45 return RISCV_EXCP_NONE; 46 } 47 48 static RISCVException vs(CPURISCVState *env, int csrno) 49 { 50 if (env->misa_ext & RVV) { 51 return RISCV_EXCP_NONE; 52 } 53 return RISCV_EXCP_ILLEGAL_INST; 54 } 55 56 static RISCVException ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 CPUState *cs = env_cpu(env); 60 RISCVCPU *cpu = RISCV_CPU(cs); 61 62 if (!cpu->cfg.ext_counters) { 63 /* The Counters extensions is not enabled */ 64 return RISCV_EXCP_ILLEGAL_INST; 65 } 66 67 if (riscv_cpu_virt_enabled(env)) { 68 switch (csrno) { 69 case CSR_CYCLE: 70 if (!get_field(env->hcounteren, COUNTEREN_CY) && 71 get_field(env->mcounteren, COUNTEREN_CY)) { 72 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 73 } 74 break; 75 case CSR_TIME: 76 if (!get_field(env->hcounteren, COUNTEREN_TM) && 77 get_field(env->mcounteren, COUNTEREN_TM)) { 78 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 79 } 80 break; 81 case CSR_INSTRET: 82 if (!get_field(env->hcounteren, COUNTEREN_IR) && 83 get_field(env->mcounteren, COUNTEREN_IR)) { 84 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 85 } 86 break; 87 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 88 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 89 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 90 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 91 } 92 break; 93 } 94 if (riscv_cpu_mxl(env) == MXL_RV32) { 95 switch (csrno) { 96 case CSR_CYCLEH: 97 if (!get_field(env->hcounteren, COUNTEREN_CY) && 98 get_field(env->mcounteren, COUNTEREN_CY)) { 99 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 100 } 101 break; 102 case CSR_TIMEH: 103 if (!get_field(env->hcounteren, COUNTEREN_TM) && 104 get_field(env->mcounteren, COUNTEREN_TM)) { 105 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 106 } 107 break; 108 case CSR_INSTRETH: 109 if (!get_field(env->hcounteren, COUNTEREN_IR) && 110 get_field(env->mcounteren, COUNTEREN_IR)) { 111 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 112 } 113 break; 114 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 115 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 116 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 117 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 118 } 119 break; 120 } 121 } 122 } 123 #endif 124 return RISCV_EXCP_NONE; 125 } 126 127 static RISCVException ctr32(CPURISCVState *env, int csrno) 128 { 129 if (riscv_cpu_mxl(env) != MXL_RV32) { 130 return RISCV_EXCP_ILLEGAL_INST; 131 } 132 133 return ctr(env, csrno); 134 } 135 136 #if !defined(CONFIG_USER_ONLY) 137 static RISCVException any(CPURISCVState *env, int csrno) 138 { 139 return RISCV_EXCP_NONE; 140 } 141 142 static RISCVException any32(CPURISCVState *env, int csrno) 143 { 144 if (riscv_cpu_mxl(env) != MXL_RV32) { 145 return RISCV_EXCP_ILLEGAL_INST; 146 } 147 148 return any(env, csrno); 149 150 } 151 152 static RISCVException smode(CPURISCVState *env, int csrno) 153 { 154 if (riscv_has_ext(env, RVS)) { 155 return RISCV_EXCP_NONE; 156 } 157 158 return RISCV_EXCP_ILLEGAL_INST; 159 } 160 161 static RISCVException hmode(CPURISCVState *env, int csrno) 162 { 163 if (riscv_has_ext(env, RVS) && 164 riscv_has_ext(env, RVH)) { 165 /* Hypervisor extension is supported */ 166 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 167 env->priv == PRV_M) { 168 return RISCV_EXCP_NONE; 169 } else { 170 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 171 } 172 } 173 174 return RISCV_EXCP_ILLEGAL_INST; 175 } 176 177 static RISCVException hmode32(CPURISCVState *env, int csrno) 178 { 179 if (riscv_cpu_mxl(env) != MXL_RV32) { 180 if (riscv_cpu_virt_enabled(env)) { 181 return RISCV_EXCP_ILLEGAL_INST; 182 } else { 183 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 184 } 185 } 186 187 return hmode(env, csrno); 188 189 } 190 191 /* Checks if PointerMasking registers could be accessed */ 192 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 193 { 194 /* Check if j-ext is present */ 195 if (riscv_has_ext(env, RVJ)) { 196 return RISCV_EXCP_NONE; 197 } 198 return RISCV_EXCP_ILLEGAL_INST; 199 } 200 201 static RISCVException pmp(CPURISCVState *env, int csrno) 202 { 203 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 204 return RISCV_EXCP_NONE; 205 } 206 207 return RISCV_EXCP_ILLEGAL_INST; 208 } 209 210 static RISCVException epmp(CPURISCVState *env, int csrno) 211 { 212 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 213 return RISCV_EXCP_NONE; 214 } 215 216 return RISCV_EXCP_ILLEGAL_INST; 217 } 218 #endif 219 220 /* User Floating-Point CSRs */ 221 static RISCVException read_fflags(CPURISCVState *env, int csrno, 222 target_ulong *val) 223 { 224 *val = riscv_cpu_get_fflags(env); 225 return RISCV_EXCP_NONE; 226 } 227 228 static RISCVException write_fflags(CPURISCVState *env, int csrno, 229 target_ulong val) 230 { 231 #if !defined(CONFIG_USER_ONLY) 232 env->mstatus |= MSTATUS_FS; 233 #endif 234 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 235 return RISCV_EXCP_NONE; 236 } 237 238 static RISCVException read_frm(CPURISCVState *env, int csrno, 239 target_ulong *val) 240 { 241 *val = env->frm; 242 return RISCV_EXCP_NONE; 243 } 244 245 static RISCVException write_frm(CPURISCVState *env, int csrno, 246 target_ulong val) 247 { 248 #if !defined(CONFIG_USER_ONLY) 249 env->mstatus |= MSTATUS_FS; 250 #endif 251 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 252 return RISCV_EXCP_NONE; 253 } 254 255 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 256 target_ulong *val) 257 { 258 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 259 | (env->frm << FSR_RD_SHIFT); 260 return RISCV_EXCP_NONE; 261 } 262 263 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 264 target_ulong val) 265 { 266 #if !defined(CONFIG_USER_ONLY) 267 env->mstatus |= MSTATUS_FS; 268 #endif 269 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 270 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 271 return RISCV_EXCP_NONE; 272 } 273 274 static RISCVException read_vtype(CPURISCVState *env, int csrno, 275 target_ulong *val) 276 { 277 *val = env->vtype; 278 return RISCV_EXCP_NONE; 279 } 280 281 static RISCVException read_vl(CPURISCVState *env, int csrno, 282 target_ulong *val) 283 { 284 *val = env->vl; 285 return RISCV_EXCP_NONE; 286 } 287 288 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 289 target_ulong *val) 290 { 291 *val = env->vxrm; 292 return RISCV_EXCP_NONE; 293 } 294 295 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 296 target_ulong val) 297 { 298 #if !defined(CONFIG_USER_ONLY) 299 env->mstatus |= MSTATUS_VS; 300 #endif 301 env->vxrm = val; 302 return RISCV_EXCP_NONE; 303 } 304 305 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 306 target_ulong *val) 307 { 308 *val = env->vxsat; 309 return RISCV_EXCP_NONE; 310 } 311 312 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 313 target_ulong val) 314 { 315 #if !defined(CONFIG_USER_ONLY) 316 env->mstatus |= MSTATUS_VS; 317 #endif 318 env->vxsat = val; 319 return RISCV_EXCP_NONE; 320 } 321 322 static RISCVException read_vstart(CPURISCVState *env, int csrno, 323 target_ulong *val) 324 { 325 *val = env->vstart; 326 return RISCV_EXCP_NONE; 327 } 328 329 static RISCVException write_vstart(CPURISCVState *env, int csrno, 330 target_ulong val) 331 { 332 #if !defined(CONFIG_USER_ONLY) 333 env->mstatus |= MSTATUS_VS; 334 #endif 335 env->vstart = val; 336 return RISCV_EXCP_NONE; 337 } 338 339 /* User Timers and Counters */ 340 static RISCVException read_instret(CPURISCVState *env, int csrno, 341 target_ulong *val) 342 { 343 #if !defined(CONFIG_USER_ONLY) 344 if (icount_enabled()) { 345 *val = icount_get(); 346 } else { 347 *val = cpu_get_host_ticks(); 348 } 349 #else 350 *val = cpu_get_host_ticks(); 351 #endif 352 return RISCV_EXCP_NONE; 353 } 354 355 static RISCVException read_instreth(CPURISCVState *env, int csrno, 356 target_ulong *val) 357 { 358 #if !defined(CONFIG_USER_ONLY) 359 if (icount_enabled()) { 360 *val = icount_get() >> 32; 361 } else { 362 *val = cpu_get_host_ticks() >> 32; 363 } 364 #else 365 *val = cpu_get_host_ticks() >> 32; 366 #endif 367 return RISCV_EXCP_NONE; 368 } 369 370 #if defined(CONFIG_USER_ONLY) 371 static RISCVException read_time(CPURISCVState *env, int csrno, 372 target_ulong *val) 373 { 374 *val = cpu_get_host_ticks(); 375 return RISCV_EXCP_NONE; 376 } 377 378 static RISCVException read_timeh(CPURISCVState *env, int csrno, 379 target_ulong *val) 380 { 381 *val = cpu_get_host_ticks() >> 32; 382 return RISCV_EXCP_NONE; 383 } 384 385 #else /* CONFIG_USER_ONLY */ 386 387 static RISCVException read_time(CPURISCVState *env, int csrno, 388 target_ulong *val) 389 { 390 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 391 392 if (!env->rdtime_fn) { 393 return RISCV_EXCP_ILLEGAL_INST; 394 } 395 396 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 397 return RISCV_EXCP_NONE; 398 } 399 400 static RISCVException read_timeh(CPURISCVState *env, int csrno, 401 target_ulong *val) 402 { 403 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 404 405 if (!env->rdtime_fn) { 406 return RISCV_EXCP_ILLEGAL_INST; 407 } 408 409 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 410 return RISCV_EXCP_NONE; 411 } 412 413 /* Machine constants */ 414 415 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 416 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 417 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 418 419 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 420 VS_MODE_INTERRUPTS; 421 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; 422 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 423 VS_MODE_INTERRUPTS; 424 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 425 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 426 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 427 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 428 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 429 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 430 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 431 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 432 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 433 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 434 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 435 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 436 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 437 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 438 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 439 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 440 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 441 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 442 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 443 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 444 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 445 (1ULL << (RISCV_EXCP_VS_ECALL)) | 446 (1ULL << (RISCV_EXCP_M_ECALL)) | 447 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 448 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 449 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 450 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 451 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 452 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 453 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 454 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 455 static const target_ulong hip_writable_mask = MIP_VSSIP; 456 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 457 static const target_ulong vsip_writable_mask = MIP_VSSIP; 458 459 static const char valid_vm_1_10_32[16] = { 460 [VM_1_10_MBARE] = 1, 461 [VM_1_10_SV32] = 1 462 }; 463 464 static const char valid_vm_1_10_64[16] = { 465 [VM_1_10_MBARE] = 1, 466 [VM_1_10_SV39] = 1, 467 [VM_1_10_SV48] = 1, 468 [VM_1_10_SV57] = 1 469 }; 470 471 /* Machine Information Registers */ 472 static RISCVException read_zero(CPURISCVState *env, int csrno, 473 target_ulong *val) 474 { 475 *val = 0; 476 return RISCV_EXCP_NONE; 477 } 478 479 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 480 target_ulong *val) 481 { 482 *val = env->mhartid; 483 return RISCV_EXCP_NONE; 484 } 485 486 /* Machine Trap Setup */ 487 488 /* We do not store SD explicitly, only compute it on demand. */ 489 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 490 { 491 if ((status & MSTATUS_FS) == MSTATUS_FS || 492 (status & MSTATUS_VS) == MSTATUS_VS || 493 (status & MSTATUS_XS) == MSTATUS_XS) { 494 switch (xl) { 495 case MXL_RV32: 496 return status | MSTATUS32_SD; 497 case MXL_RV64: 498 return status | MSTATUS64_SD; 499 default: 500 g_assert_not_reached(); 501 } 502 } 503 return status; 504 } 505 506 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 507 target_ulong *val) 508 { 509 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 510 return RISCV_EXCP_NONE; 511 } 512 513 static int validate_vm(CPURISCVState *env, target_ulong vm) 514 { 515 if (riscv_cpu_mxl(env) == MXL_RV32) { 516 return valid_vm_1_10_32[vm & 0xf]; 517 } else { 518 return valid_vm_1_10_64[vm & 0xf]; 519 } 520 } 521 522 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 523 target_ulong val) 524 { 525 uint64_t mstatus = env->mstatus; 526 uint64_t mask = 0; 527 528 /* flush tlb on mstatus fields that affect VM */ 529 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 530 MSTATUS_MPRV | MSTATUS_SUM)) { 531 tlb_flush(env_cpu(env)); 532 } 533 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 534 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 535 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 536 MSTATUS_TW | MSTATUS_VS; 537 538 if (riscv_cpu_mxl(env) != MXL_RV32) { 539 /* 540 * RV32: MPV and GVA are not in mstatus. The current plan is to 541 * add them to mstatush. For now, we just don't support it. 542 */ 543 mask |= MSTATUS_MPV | MSTATUS_GVA; 544 } 545 546 mstatus = (mstatus & ~mask) | (val & mask); 547 548 if (riscv_cpu_mxl(env) == MXL_RV64) { 549 /* SXL and UXL fields are for now read only */ 550 mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); 551 mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); 552 } 553 env->mstatus = mstatus; 554 555 return RISCV_EXCP_NONE; 556 } 557 558 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 559 target_ulong *val) 560 { 561 *val = env->mstatus >> 32; 562 return RISCV_EXCP_NONE; 563 } 564 565 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 566 target_ulong val) 567 { 568 uint64_t valh = (uint64_t)val << 32; 569 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 570 571 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 572 tlb_flush(env_cpu(env)); 573 } 574 575 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 576 577 return RISCV_EXCP_NONE; 578 } 579 580 static RISCVException read_misa(CPURISCVState *env, int csrno, 581 target_ulong *val) 582 { 583 target_ulong misa; 584 585 switch (env->misa_mxl) { 586 case MXL_RV32: 587 misa = (target_ulong)MXL_RV32 << 30; 588 break; 589 #ifdef TARGET_RISCV64 590 case MXL_RV64: 591 misa = (target_ulong)MXL_RV64 << 62; 592 break; 593 #endif 594 default: 595 g_assert_not_reached(); 596 } 597 598 *val = misa | env->misa_ext; 599 return RISCV_EXCP_NONE; 600 } 601 602 static RISCVException write_misa(CPURISCVState *env, int csrno, 603 target_ulong val) 604 { 605 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 606 /* drop write to misa */ 607 return RISCV_EXCP_NONE; 608 } 609 610 /* 'I' or 'E' must be present */ 611 if (!(val & (RVI | RVE))) { 612 /* It is not, drop write to misa */ 613 return RISCV_EXCP_NONE; 614 } 615 616 /* 'E' excludes all other extensions */ 617 if (val & RVE) { 618 /* when we support 'E' we can do "val = RVE;" however 619 * for now we just drop writes if 'E' is present. 620 */ 621 return RISCV_EXCP_NONE; 622 } 623 624 /* 625 * misa.MXL writes are not supported by QEMU. 626 * Drop writes to those bits. 627 */ 628 629 /* Mask extensions that are not supported by this hart */ 630 val &= env->misa_ext_mask; 631 632 /* Mask extensions that are not supported by QEMU */ 633 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 634 635 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 636 if ((val & RVD) && !(val & RVF)) { 637 val &= ~RVD; 638 } 639 640 /* Suppress 'C' if next instruction is not aligned 641 * TODO: this should check next_pc 642 */ 643 if ((val & RVC) && (GETPC() & ~3) != 0) { 644 val &= ~RVC; 645 } 646 647 /* If nothing changed, do nothing. */ 648 if (val == env->misa_ext) { 649 return RISCV_EXCP_NONE; 650 } 651 652 /* flush translation cache */ 653 tb_flush(env_cpu(env)); 654 env->misa_ext = val; 655 return RISCV_EXCP_NONE; 656 } 657 658 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 659 target_ulong *val) 660 { 661 *val = env->medeleg; 662 return RISCV_EXCP_NONE; 663 } 664 665 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 666 target_ulong val) 667 { 668 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 669 return RISCV_EXCP_NONE; 670 } 671 672 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 673 target_ulong *val) 674 { 675 *val = env->mideleg; 676 return RISCV_EXCP_NONE; 677 } 678 679 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 680 target_ulong val) 681 { 682 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 683 if (riscv_has_ext(env, RVH)) { 684 env->mideleg |= VS_MODE_INTERRUPTS; 685 } 686 return RISCV_EXCP_NONE; 687 } 688 689 static RISCVException read_mie(CPURISCVState *env, int csrno, 690 target_ulong *val) 691 { 692 *val = env->mie; 693 return RISCV_EXCP_NONE; 694 } 695 696 static RISCVException write_mie(CPURISCVState *env, int csrno, 697 target_ulong val) 698 { 699 env->mie = (env->mie & ~all_ints) | (val & all_ints); 700 return RISCV_EXCP_NONE; 701 } 702 703 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 704 target_ulong *val) 705 { 706 *val = env->mtvec; 707 return RISCV_EXCP_NONE; 708 } 709 710 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 711 target_ulong val) 712 { 713 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 714 if ((val & 3) < 2) { 715 env->mtvec = val; 716 } else { 717 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 718 } 719 return RISCV_EXCP_NONE; 720 } 721 722 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 723 target_ulong *val) 724 { 725 *val = env->mcounteren; 726 return RISCV_EXCP_NONE; 727 } 728 729 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 730 target_ulong val) 731 { 732 env->mcounteren = val; 733 return RISCV_EXCP_NONE; 734 } 735 736 /* Machine Trap Handling */ 737 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 738 target_ulong *val) 739 { 740 *val = env->mscratch; 741 return RISCV_EXCP_NONE; 742 } 743 744 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 745 target_ulong val) 746 { 747 env->mscratch = val; 748 return RISCV_EXCP_NONE; 749 } 750 751 static RISCVException read_mepc(CPURISCVState *env, int csrno, 752 target_ulong *val) 753 { 754 *val = env->mepc; 755 return RISCV_EXCP_NONE; 756 } 757 758 static RISCVException write_mepc(CPURISCVState *env, int csrno, 759 target_ulong val) 760 { 761 env->mepc = val; 762 return RISCV_EXCP_NONE; 763 } 764 765 static RISCVException read_mcause(CPURISCVState *env, int csrno, 766 target_ulong *val) 767 { 768 *val = env->mcause; 769 return RISCV_EXCP_NONE; 770 } 771 772 static RISCVException write_mcause(CPURISCVState *env, int csrno, 773 target_ulong val) 774 { 775 env->mcause = val; 776 return RISCV_EXCP_NONE; 777 } 778 779 static RISCVException read_mtval(CPURISCVState *env, int csrno, 780 target_ulong *val) 781 { 782 *val = env->mtval; 783 return RISCV_EXCP_NONE; 784 } 785 786 static RISCVException write_mtval(CPURISCVState *env, int csrno, 787 target_ulong val) 788 { 789 env->mtval = val; 790 return RISCV_EXCP_NONE; 791 } 792 793 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 794 target_ulong *ret_value, 795 target_ulong new_value, target_ulong write_mask) 796 { 797 RISCVCPU *cpu = env_archcpu(env); 798 /* Allow software control of delegable interrupts not claimed by hardware */ 799 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 800 uint32_t old_mip; 801 802 if (mask) { 803 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 804 } else { 805 old_mip = env->mip; 806 } 807 808 if (ret_value) { 809 *ret_value = old_mip; 810 } 811 812 return RISCV_EXCP_NONE; 813 } 814 815 /* Supervisor Trap Setup */ 816 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 817 target_ulong *val) 818 { 819 target_ulong mask = (sstatus_v1_10_mask); 820 821 /* TODO: Use SXL not MXL. */ 822 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 823 return RISCV_EXCP_NONE; 824 } 825 826 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 827 target_ulong val) 828 { 829 target_ulong mask = (sstatus_v1_10_mask); 830 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 831 return write_mstatus(env, CSR_MSTATUS, newval); 832 } 833 834 static RISCVException read_vsie(CPURISCVState *env, int csrno, 835 target_ulong *val) 836 { 837 /* Shift the VS bits to their S bit location in vsie */ 838 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 839 return RISCV_EXCP_NONE; 840 } 841 842 static RISCVException read_sie(CPURISCVState *env, int csrno, 843 target_ulong *val) 844 { 845 if (riscv_cpu_virt_enabled(env)) { 846 read_vsie(env, CSR_VSIE, val); 847 } else { 848 *val = env->mie & env->mideleg; 849 } 850 return RISCV_EXCP_NONE; 851 } 852 853 static RISCVException write_vsie(CPURISCVState *env, int csrno, 854 target_ulong val) 855 { 856 /* Shift the S bits to their VS bit location in mie */ 857 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 858 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 859 return write_mie(env, CSR_MIE, newval); 860 } 861 862 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 863 { 864 if (riscv_cpu_virt_enabled(env)) { 865 write_vsie(env, CSR_VSIE, val); 866 } else { 867 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 868 (val & S_MODE_INTERRUPTS); 869 write_mie(env, CSR_MIE, newval); 870 } 871 872 return RISCV_EXCP_NONE; 873 } 874 875 static RISCVException read_stvec(CPURISCVState *env, int csrno, 876 target_ulong *val) 877 { 878 *val = env->stvec; 879 return RISCV_EXCP_NONE; 880 } 881 882 static RISCVException write_stvec(CPURISCVState *env, int csrno, 883 target_ulong val) 884 { 885 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 886 if ((val & 3) < 2) { 887 env->stvec = val; 888 } else { 889 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 890 } 891 return RISCV_EXCP_NONE; 892 } 893 894 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 895 target_ulong *val) 896 { 897 *val = env->scounteren; 898 return RISCV_EXCP_NONE; 899 } 900 901 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 902 target_ulong val) 903 { 904 env->scounteren = val; 905 return RISCV_EXCP_NONE; 906 } 907 908 /* Supervisor Trap Handling */ 909 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 910 target_ulong *val) 911 { 912 *val = env->sscratch; 913 return RISCV_EXCP_NONE; 914 } 915 916 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 917 target_ulong val) 918 { 919 env->sscratch = val; 920 return RISCV_EXCP_NONE; 921 } 922 923 static RISCVException read_sepc(CPURISCVState *env, int csrno, 924 target_ulong *val) 925 { 926 *val = env->sepc; 927 return RISCV_EXCP_NONE; 928 } 929 930 static RISCVException write_sepc(CPURISCVState *env, int csrno, 931 target_ulong val) 932 { 933 env->sepc = val; 934 return RISCV_EXCP_NONE; 935 } 936 937 static RISCVException read_scause(CPURISCVState *env, int csrno, 938 target_ulong *val) 939 { 940 *val = env->scause; 941 return RISCV_EXCP_NONE; 942 } 943 944 static RISCVException write_scause(CPURISCVState *env, int csrno, 945 target_ulong val) 946 { 947 env->scause = val; 948 return RISCV_EXCP_NONE; 949 } 950 951 static RISCVException read_stval(CPURISCVState *env, int csrno, 952 target_ulong *val) 953 { 954 *val = env->stval; 955 return RISCV_EXCP_NONE; 956 } 957 958 static RISCVException write_stval(CPURISCVState *env, int csrno, 959 target_ulong val) 960 { 961 env->stval = val; 962 return RISCV_EXCP_NONE; 963 } 964 965 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 966 target_ulong *ret_value, 967 target_ulong new_value, target_ulong write_mask) 968 { 969 /* Shift the S bits to their VS bit location in mip */ 970 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 971 (write_mask << 1) & vsip_writable_mask & env->hideleg); 972 973 if (ret_value) { 974 *ret_value &= VS_MODE_INTERRUPTS; 975 /* Shift the VS bits to their S bit location in vsip */ 976 *ret_value >>= 1; 977 } 978 return ret; 979 } 980 981 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 982 target_ulong *ret_value, 983 target_ulong new_value, target_ulong write_mask) 984 { 985 int ret; 986 987 if (riscv_cpu_virt_enabled(env)) { 988 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 989 } else { 990 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 991 write_mask & env->mideleg & sip_writable_mask); 992 } 993 994 if (ret_value) { 995 *ret_value &= env->mideleg; 996 } 997 return ret; 998 } 999 1000 /* Supervisor Protection and Translation */ 1001 static RISCVException read_satp(CPURISCVState *env, int csrno, 1002 target_ulong *val) 1003 { 1004 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1005 *val = 0; 1006 return RISCV_EXCP_NONE; 1007 } 1008 1009 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1010 return RISCV_EXCP_ILLEGAL_INST; 1011 } else { 1012 *val = env->satp; 1013 } 1014 1015 return RISCV_EXCP_NONE; 1016 } 1017 1018 static RISCVException write_satp(CPURISCVState *env, int csrno, 1019 target_ulong val) 1020 { 1021 target_ulong vm, mask, asid; 1022 1023 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1024 return RISCV_EXCP_NONE; 1025 } 1026 1027 if (riscv_cpu_mxl(env) == MXL_RV32) { 1028 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1029 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1030 asid = (val ^ env->satp) & SATP32_ASID; 1031 } else { 1032 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1033 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1034 asid = (val ^ env->satp) & SATP64_ASID; 1035 } 1036 1037 if (vm && mask) { 1038 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1039 return RISCV_EXCP_ILLEGAL_INST; 1040 } else { 1041 if (asid) { 1042 tlb_flush(env_cpu(env)); 1043 } 1044 env->satp = val; 1045 } 1046 } 1047 return RISCV_EXCP_NONE; 1048 } 1049 1050 /* Hypervisor Extensions */ 1051 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1052 target_ulong *val) 1053 { 1054 *val = env->hstatus; 1055 if (riscv_cpu_mxl(env) != MXL_RV32) { 1056 /* We only support 64-bit VSXL */ 1057 *val = set_field(*val, HSTATUS_VSXL, 2); 1058 } 1059 /* We only support little endian */ 1060 *val = set_field(*val, HSTATUS_VSBE, 0); 1061 return RISCV_EXCP_NONE; 1062 } 1063 1064 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1065 target_ulong val) 1066 { 1067 env->hstatus = val; 1068 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 1069 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1070 } 1071 if (get_field(val, HSTATUS_VSBE) != 0) { 1072 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1073 } 1074 return RISCV_EXCP_NONE; 1075 } 1076 1077 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1078 target_ulong *val) 1079 { 1080 *val = env->hedeleg; 1081 return RISCV_EXCP_NONE; 1082 } 1083 1084 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1085 target_ulong val) 1086 { 1087 env->hedeleg = val & vs_delegable_excps; 1088 return RISCV_EXCP_NONE; 1089 } 1090 1091 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1092 target_ulong *val) 1093 { 1094 *val = env->hideleg; 1095 return RISCV_EXCP_NONE; 1096 } 1097 1098 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1099 target_ulong val) 1100 { 1101 env->hideleg = val & vs_delegable_ints; 1102 return RISCV_EXCP_NONE; 1103 } 1104 1105 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1106 target_ulong *ret_value, 1107 target_ulong new_value, target_ulong write_mask) 1108 { 1109 int ret = rmw_mip(env, 0, ret_value, new_value, 1110 write_mask & hvip_writable_mask); 1111 1112 if (ret_value) { 1113 *ret_value &= hvip_writable_mask; 1114 } 1115 return ret; 1116 } 1117 1118 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1119 target_ulong *ret_value, 1120 target_ulong new_value, target_ulong write_mask) 1121 { 1122 int ret = rmw_mip(env, 0, ret_value, new_value, 1123 write_mask & hip_writable_mask); 1124 1125 if (ret_value) { 1126 *ret_value &= hip_writable_mask; 1127 } 1128 return ret; 1129 } 1130 1131 static RISCVException read_hie(CPURISCVState *env, int csrno, 1132 target_ulong *val) 1133 { 1134 *val = env->mie & VS_MODE_INTERRUPTS; 1135 return RISCV_EXCP_NONE; 1136 } 1137 1138 static RISCVException write_hie(CPURISCVState *env, int csrno, 1139 target_ulong val) 1140 { 1141 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1142 return write_mie(env, CSR_MIE, newval); 1143 } 1144 1145 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1146 target_ulong *val) 1147 { 1148 *val = env->hcounteren; 1149 return RISCV_EXCP_NONE; 1150 } 1151 1152 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1153 target_ulong val) 1154 { 1155 env->hcounteren = val; 1156 return RISCV_EXCP_NONE; 1157 } 1158 1159 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1160 target_ulong val) 1161 { 1162 if (val) { 1163 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1164 } 1165 return RISCV_EXCP_NONE; 1166 } 1167 1168 static RISCVException read_htval(CPURISCVState *env, int csrno, 1169 target_ulong *val) 1170 { 1171 *val = env->htval; 1172 return RISCV_EXCP_NONE; 1173 } 1174 1175 static RISCVException write_htval(CPURISCVState *env, int csrno, 1176 target_ulong val) 1177 { 1178 env->htval = val; 1179 return RISCV_EXCP_NONE; 1180 } 1181 1182 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1183 target_ulong *val) 1184 { 1185 *val = env->htinst; 1186 return RISCV_EXCP_NONE; 1187 } 1188 1189 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1190 target_ulong val) 1191 { 1192 return RISCV_EXCP_NONE; 1193 } 1194 1195 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1196 target_ulong val) 1197 { 1198 if (val) { 1199 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1200 } 1201 return RISCV_EXCP_NONE; 1202 } 1203 1204 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1205 target_ulong *val) 1206 { 1207 *val = env->hgatp; 1208 return RISCV_EXCP_NONE; 1209 } 1210 1211 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1212 target_ulong val) 1213 { 1214 env->hgatp = val; 1215 return RISCV_EXCP_NONE; 1216 } 1217 1218 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1219 target_ulong *val) 1220 { 1221 if (!env->rdtime_fn) { 1222 return RISCV_EXCP_ILLEGAL_INST; 1223 } 1224 1225 *val = env->htimedelta; 1226 return RISCV_EXCP_NONE; 1227 } 1228 1229 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1230 target_ulong val) 1231 { 1232 if (!env->rdtime_fn) { 1233 return RISCV_EXCP_ILLEGAL_INST; 1234 } 1235 1236 if (riscv_cpu_mxl(env) == MXL_RV32) { 1237 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1238 } else { 1239 env->htimedelta = val; 1240 } 1241 return RISCV_EXCP_NONE; 1242 } 1243 1244 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1245 target_ulong *val) 1246 { 1247 if (!env->rdtime_fn) { 1248 return RISCV_EXCP_ILLEGAL_INST; 1249 } 1250 1251 *val = env->htimedelta >> 32; 1252 return RISCV_EXCP_NONE; 1253 } 1254 1255 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1256 target_ulong val) 1257 { 1258 if (!env->rdtime_fn) { 1259 return RISCV_EXCP_ILLEGAL_INST; 1260 } 1261 1262 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1263 return RISCV_EXCP_NONE; 1264 } 1265 1266 /* Virtual CSR Registers */ 1267 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1268 target_ulong *val) 1269 { 1270 *val = env->vsstatus; 1271 return RISCV_EXCP_NONE; 1272 } 1273 1274 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1275 target_ulong val) 1276 { 1277 uint64_t mask = (target_ulong)-1; 1278 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1279 return RISCV_EXCP_NONE; 1280 } 1281 1282 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1283 { 1284 *val = env->vstvec; 1285 return RISCV_EXCP_NONE; 1286 } 1287 1288 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1289 target_ulong val) 1290 { 1291 env->vstvec = val; 1292 return RISCV_EXCP_NONE; 1293 } 1294 1295 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1296 target_ulong *val) 1297 { 1298 *val = env->vsscratch; 1299 return RISCV_EXCP_NONE; 1300 } 1301 1302 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1303 target_ulong val) 1304 { 1305 env->vsscratch = val; 1306 return RISCV_EXCP_NONE; 1307 } 1308 1309 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1310 target_ulong *val) 1311 { 1312 *val = env->vsepc; 1313 return RISCV_EXCP_NONE; 1314 } 1315 1316 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1317 target_ulong val) 1318 { 1319 env->vsepc = val; 1320 return RISCV_EXCP_NONE; 1321 } 1322 1323 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1324 target_ulong *val) 1325 { 1326 *val = env->vscause; 1327 return RISCV_EXCP_NONE; 1328 } 1329 1330 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1331 target_ulong val) 1332 { 1333 env->vscause = val; 1334 return RISCV_EXCP_NONE; 1335 } 1336 1337 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1338 target_ulong *val) 1339 { 1340 *val = env->vstval; 1341 return RISCV_EXCP_NONE; 1342 } 1343 1344 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1345 target_ulong val) 1346 { 1347 env->vstval = val; 1348 return RISCV_EXCP_NONE; 1349 } 1350 1351 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1352 target_ulong *val) 1353 { 1354 *val = env->vsatp; 1355 return RISCV_EXCP_NONE; 1356 } 1357 1358 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1359 target_ulong val) 1360 { 1361 env->vsatp = val; 1362 return RISCV_EXCP_NONE; 1363 } 1364 1365 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1366 target_ulong *val) 1367 { 1368 *val = env->mtval2; 1369 return RISCV_EXCP_NONE; 1370 } 1371 1372 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1373 target_ulong val) 1374 { 1375 env->mtval2 = val; 1376 return RISCV_EXCP_NONE; 1377 } 1378 1379 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1380 target_ulong *val) 1381 { 1382 *val = env->mtinst; 1383 return RISCV_EXCP_NONE; 1384 } 1385 1386 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1387 target_ulong val) 1388 { 1389 env->mtinst = val; 1390 return RISCV_EXCP_NONE; 1391 } 1392 1393 /* Physical Memory Protection */ 1394 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1395 target_ulong *val) 1396 { 1397 *val = mseccfg_csr_read(env); 1398 return RISCV_EXCP_NONE; 1399 } 1400 1401 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1402 target_ulong val) 1403 { 1404 mseccfg_csr_write(env, val); 1405 return RISCV_EXCP_NONE; 1406 } 1407 1408 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1409 target_ulong *val) 1410 { 1411 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1412 return RISCV_EXCP_NONE; 1413 } 1414 1415 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1416 target_ulong val) 1417 { 1418 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1419 return RISCV_EXCP_NONE; 1420 } 1421 1422 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1423 target_ulong *val) 1424 { 1425 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1426 return RISCV_EXCP_NONE; 1427 } 1428 1429 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1430 target_ulong val) 1431 { 1432 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1433 return RISCV_EXCP_NONE; 1434 } 1435 1436 /* 1437 * Functions to access Pointer Masking feature registers 1438 * We have to check if current priv lvl could modify 1439 * csr in given mode 1440 */ 1441 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 1442 { 1443 int csr_priv = get_field(csrno, 0x300); 1444 int pm_current; 1445 1446 /* 1447 * If priv lvls differ that means we're accessing csr from higher priv lvl, 1448 * so allow the access 1449 */ 1450 if (env->priv != csr_priv) { 1451 return false; 1452 } 1453 switch (env->priv) { 1454 case PRV_M: 1455 pm_current = get_field(env->mmte, M_PM_CURRENT); 1456 break; 1457 case PRV_S: 1458 pm_current = get_field(env->mmte, S_PM_CURRENT); 1459 break; 1460 case PRV_U: 1461 pm_current = get_field(env->mmte, U_PM_CURRENT); 1462 break; 1463 default: 1464 g_assert_not_reached(); 1465 } 1466 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 1467 return !pm_current; 1468 } 1469 1470 static RISCVException read_mmte(CPURISCVState *env, int csrno, 1471 target_ulong *val) 1472 { 1473 *val = env->mmte & MMTE_MASK; 1474 return RISCV_EXCP_NONE; 1475 } 1476 1477 static RISCVException write_mmte(CPURISCVState *env, int csrno, 1478 target_ulong val) 1479 { 1480 uint64_t mstatus; 1481 target_ulong wpri_val = val & MMTE_MASK; 1482 1483 if (val != wpri_val) { 1484 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1485 "MMTE: WPRI violation written 0x", val, 1486 "vs expected 0x", wpri_val); 1487 } 1488 /* for machine mode pm.current is hardwired to 1 */ 1489 wpri_val |= MMTE_M_PM_CURRENT; 1490 1491 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 1492 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 1493 env->mmte = wpri_val | PM_EXT_DIRTY; 1494 1495 /* Set XS and SD bits, since PM CSRs are dirty */ 1496 mstatus = env->mstatus | MSTATUS_XS; 1497 write_mstatus(env, csrno, mstatus); 1498 return RISCV_EXCP_NONE; 1499 } 1500 1501 static RISCVException read_smte(CPURISCVState *env, int csrno, 1502 target_ulong *val) 1503 { 1504 *val = env->mmte & SMTE_MASK; 1505 return RISCV_EXCP_NONE; 1506 } 1507 1508 static RISCVException write_smte(CPURISCVState *env, int csrno, 1509 target_ulong val) 1510 { 1511 target_ulong wpri_val = val & SMTE_MASK; 1512 1513 if (val != wpri_val) { 1514 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1515 "SMTE: WPRI violation written 0x", val, 1516 "vs expected 0x", wpri_val); 1517 } 1518 1519 /* if pm.current==0 we can't modify current PM CSRs */ 1520 if (check_pm_current_disabled(env, csrno)) { 1521 return RISCV_EXCP_NONE; 1522 } 1523 1524 wpri_val |= (env->mmte & ~SMTE_MASK); 1525 write_mmte(env, csrno, wpri_val); 1526 return RISCV_EXCP_NONE; 1527 } 1528 1529 static RISCVException read_umte(CPURISCVState *env, int csrno, 1530 target_ulong *val) 1531 { 1532 *val = env->mmte & UMTE_MASK; 1533 return RISCV_EXCP_NONE; 1534 } 1535 1536 static RISCVException write_umte(CPURISCVState *env, int csrno, 1537 target_ulong val) 1538 { 1539 target_ulong wpri_val = val & UMTE_MASK; 1540 1541 if (val != wpri_val) { 1542 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1543 "UMTE: WPRI violation written 0x", val, 1544 "vs expected 0x", wpri_val); 1545 } 1546 1547 if (check_pm_current_disabled(env, csrno)) { 1548 return RISCV_EXCP_NONE; 1549 } 1550 1551 wpri_val |= (env->mmte & ~UMTE_MASK); 1552 write_mmte(env, csrno, wpri_val); 1553 return RISCV_EXCP_NONE; 1554 } 1555 1556 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 1557 target_ulong *val) 1558 { 1559 *val = env->mpmmask; 1560 return RISCV_EXCP_NONE; 1561 } 1562 1563 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 1564 target_ulong val) 1565 { 1566 uint64_t mstatus; 1567 1568 env->mpmmask = val; 1569 env->mmte |= PM_EXT_DIRTY; 1570 1571 /* Set XS and SD bits, since PM CSRs are dirty */ 1572 mstatus = env->mstatus | MSTATUS_XS; 1573 write_mstatus(env, csrno, mstatus); 1574 return RISCV_EXCP_NONE; 1575 } 1576 1577 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 1578 target_ulong *val) 1579 { 1580 *val = env->spmmask; 1581 return RISCV_EXCP_NONE; 1582 } 1583 1584 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 1585 target_ulong val) 1586 { 1587 uint64_t mstatus; 1588 1589 /* if pm.current==0 we can't modify current PM CSRs */ 1590 if (check_pm_current_disabled(env, csrno)) { 1591 return RISCV_EXCP_NONE; 1592 } 1593 env->spmmask = val; 1594 env->mmte |= PM_EXT_DIRTY; 1595 1596 /* Set XS and SD bits, since PM CSRs are dirty */ 1597 mstatus = env->mstatus | MSTATUS_XS; 1598 write_mstatus(env, csrno, mstatus); 1599 return RISCV_EXCP_NONE; 1600 } 1601 1602 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 1603 target_ulong *val) 1604 { 1605 *val = env->upmmask; 1606 return RISCV_EXCP_NONE; 1607 } 1608 1609 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 1610 target_ulong val) 1611 { 1612 uint64_t mstatus; 1613 1614 /* if pm.current==0 we can't modify current PM CSRs */ 1615 if (check_pm_current_disabled(env, csrno)) { 1616 return RISCV_EXCP_NONE; 1617 } 1618 env->upmmask = val; 1619 env->mmte |= PM_EXT_DIRTY; 1620 1621 /* Set XS and SD bits, since PM CSRs are dirty */ 1622 mstatus = env->mstatus | MSTATUS_XS; 1623 write_mstatus(env, csrno, mstatus); 1624 return RISCV_EXCP_NONE; 1625 } 1626 1627 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 1628 target_ulong *val) 1629 { 1630 *val = env->mpmbase; 1631 return RISCV_EXCP_NONE; 1632 } 1633 1634 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 1635 target_ulong val) 1636 { 1637 uint64_t mstatus; 1638 1639 env->mpmbase = val; 1640 env->mmte |= PM_EXT_DIRTY; 1641 1642 /* Set XS and SD bits, since PM CSRs are dirty */ 1643 mstatus = env->mstatus | MSTATUS_XS; 1644 write_mstatus(env, csrno, mstatus); 1645 return RISCV_EXCP_NONE; 1646 } 1647 1648 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 1649 target_ulong *val) 1650 { 1651 *val = env->spmbase; 1652 return RISCV_EXCP_NONE; 1653 } 1654 1655 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 1656 target_ulong val) 1657 { 1658 uint64_t mstatus; 1659 1660 /* if pm.current==0 we can't modify current PM CSRs */ 1661 if (check_pm_current_disabled(env, csrno)) { 1662 return RISCV_EXCP_NONE; 1663 } 1664 env->spmbase = val; 1665 env->mmte |= PM_EXT_DIRTY; 1666 1667 /* Set XS and SD bits, since PM CSRs are dirty */ 1668 mstatus = env->mstatus | MSTATUS_XS; 1669 write_mstatus(env, csrno, mstatus); 1670 return RISCV_EXCP_NONE; 1671 } 1672 1673 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 1674 target_ulong *val) 1675 { 1676 *val = env->upmbase; 1677 return RISCV_EXCP_NONE; 1678 } 1679 1680 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 1681 target_ulong val) 1682 { 1683 uint64_t mstatus; 1684 1685 /* if pm.current==0 we can't modify current PM CSRs */ 1686 if (check_pm_current_disabled(env, csrno)) { 1687 return RISCV_EXCP_NONE; 1688 } 1689 env->upmbase = val; 1690 env->mmte |= PM_EXT_DIRTY; 1691 1692 /* Set XS and SD bits, since PM CSRs are dirty */ 1693 mstatus = env->mstatus | MSTATUS_XS; 1694 write_mstatus(env, csrno, mstatus); 1695 return RISCV_EXCP_NONE; 1696 } 1697 1698 #endif 1699 1700 /* 1701 * riscv_csrrw - read and/or update control and status register 1702 * 1703 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1704 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1705 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1706 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1707 */ 1708 1709 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1710 target_ulong *ret_value, 1711 target_ulong new_value, target_ulong write_mask) 1712 { 1713 RISCVException ret; 1714 target_ulong old_value; 1715 RISCVCPU *cpu = env_archcpu(env); 1716 int read_only = get_field(csrno, 0xC00) == 3; 1717 1718 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 1719 #if !defined(CONFIG_USER_ONLY) 1720 int effective_priv = env->priv; 1721 1722 if (riscv_has_ext(env, RVH) && 1723 env->priv == PRV_S && 1724 !riscv_cpu_virt_enabled(env)) { 1725 /* 1726 * We are in S mode without virtualisation, therefore we are in HS Mode. 1727 * Add 1 to the effective privledge level to allow us to access the 1728 * Hypervisor CSRs. 1729 */ 1730 effective_priv++; 1731 } 1732 1733 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 1734 return RISCV_EXCP_ILLEGAL_INST; 1735 } 1736 #endif 1737 if (write_mask && read_only) { 1738 return RISCV_EXCP_ILLEGAL_INST; 1739 } 1740 1741 /* ensure the CSR extension is enabled. */ 1742 if (!cpu->cfg.ext_icsr) { 1743 return RISCV_EXCP_ILLEGAL_INST; 1744 } 1745 1746 /* check predicate */ 1747 if (!csr_ops[csrno].predicate) { 1748 return RISCV_EXCP_ILLEGAL_INST; 1749 } 1750 ret = csr_ops[csrno].predicate(env, csrno); 1751 if (ret != RISCV_EXCP_NONE) { 1752 return ret; 1753 } 1754 1755 /* execute combined read/write operation if it exists */ 1756 if (csr_ops[csrno].op) { 1757 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1758 } 1759 1760 /* if no accessor exists then return failure */ 1761 if (!csr_ops[csrno].read) { 1762 return RISCV_EXCP_ILLEGAL_INST; 1763 } 1764 /* read old value */ 1765 ret = csr_ops[csrno].read(env, csrno, &old_value); 1766 if (ret != RISCV_EXCP_NONE) { 1767 return ret; 1768 } 1769 1770 /* write value if writable and write mask set, otherwise drop writes */ 1771 if (write_mask) { 1772 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1773 if (csr_ops[csrno].write) { 1774 ret = csr_ops[csrno].write(env, csrno, new_value); 1775 if (ret != RISCV_EXCP_NONE) { 1776 return ret; 1777 } 1778 } 1779 } 1780 1781 /* return old value */ 1782 if (ret_value) { 1783 *ret_value = old_value; 1784 } 1785 1786 return RISCV_EXCP_NONE; 1787 } 1788 1789 /* 1790 * Debugger support. If not in user mode, set env->debugger before the 1791 * riscv_csrrw call and clear it after the call. 1792 */ 1793 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1794 target_ulong *ret_value, 1795 target_ulong new_value, 1796 target_ulong write_mask) 1797 { 1798 RISCVException ret; 1799 #if !defined(CONFIG_USER_ONLY) 1800 env->debugger = true; 1801 #endif 1802 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1803 #if !defined(CONFIG_USER_ONLY) 1804 env->debugger = false; 1805 #endif 1806 return ret; 1807 } 1808 1809 /* Control and Status Register function table */ 1810 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1811 /* User Floating-Point CSRs */ 1812 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1813 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1814 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1815 /* Vector CSRs */ 1816 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1817 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1818 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1819 [CSR_VL] = { "vl", vs, read_vl }, 1820 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1821 /* User Timers and Counters */ 1822 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1823 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1824 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1825 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1826 1827 /* 1828 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1829 * rdtime callback is not provided by machine/platform emulation. 1830 */ 1831 [CSR_TIME] = { "time", ctr, read_time }, 1832 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1833 1834 #if !defined(CONFIG_USER_ONLY) 1835 /* Machine Timers and Counters */ 1836 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1837 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1838 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1839 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1840 1841 /* Machine Information Registers */ 1842 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1843 [CSR_MARCHID] = { "marchid", any, read_zero }, 1844 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1845 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1846 1847 /* Machine Trap Setup */ 1848 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1849 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1850 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1851 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1852 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1853 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1854 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1855 1856 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1857 1858 /* Machine Trap Handling */ 1859 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1860 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1861 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1862 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1863 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1864 1865 /* Supervisor Trap Setup */ 1866 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1867 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1868 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1869 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1870 1871 /* Supervisor Trap Handling */ 1872 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1873 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1874 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1875 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1876 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1877 1878 /* Supervisor Protection and Translation */ 1879 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1880 1881 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1882 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1883 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1884 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1885 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1886 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1887 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1888 [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, 1889 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1890 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1891 [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, 1892 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1893 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1894 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1895 1896 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1897 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1898 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1899 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1900 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1901 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1902 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1903 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1904 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1905 1906 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1907 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1908 1909 /* Physical Memory Protection */ 1910 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1911 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1912 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1913 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1914 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1915 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1916 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1917 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1918 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1919 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1920 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1921 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1922 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1923 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1924 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1925 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1926 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1927 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1928 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1929 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1930 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1931 1932 /* User Pointer Masking */ 1933 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 1934 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 1935 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 1936 /* Machine Pointer Masking */ 1937 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 1938 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 1939 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 1940 /* Supervisor Pointer Masking */ 1941 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 1942 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 1943 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 1944 1945 /* Performance Counters */ 1946 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1947 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1948 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1949 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1950 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1951 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1952 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1953 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1954 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1955 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1956 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1957 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1958 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1959 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1960 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1961 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1962 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1963 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1964 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1965 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1966 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1967 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1968 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1969 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1970 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1971 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1972 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1973 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1974 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1975 1976 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1977 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1978 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1979 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1980 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1981 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1982 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1983 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1984 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1985 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1986 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1987 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 1988 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 1989 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 1990 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 1991 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 1992 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 1993 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 1994 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 1995 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 1996 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 1997 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 1998 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 1999 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 2000 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 2001 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 2002 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 2003 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 2004 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 2005 2006 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 2007 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 2008 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 2009 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 2010 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 2011 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 2012 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 2013 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 2014 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 2015 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 2016 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 2017 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 2018 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 2019 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 2020 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 2021 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 2022 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 2023 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 2024 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 2025 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 2026 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 2027 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 2028 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 2029 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 2030 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 2031 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 2032 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 2033 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 2034 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 2035 2036 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 2037 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 2038 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 2039 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 2040 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 2041 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 2042 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 2043 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 2044 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 2045 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 2046 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 2047 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 2048 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 2049 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 2050 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 2051 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 2052 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 2053 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 2054 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 2055 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 2056 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 2057 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 2058 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 2059 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 2060 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 2061 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 2062 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 2063 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 2064 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 2065 2066 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 2067 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 2068 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 2069 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 2070 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 2071 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 2072 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 2073 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 2074 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 2075 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 2076 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 2077 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 2078 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 2079 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 2080 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 2081 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 2082 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 2083 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 2084 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 2085 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 2086 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 2087 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 2088 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 2089 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 2090 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 2091 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 2092 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 2093 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 2094 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 2095 #endif /* !CONFIG_USER_ONLY */ 2096 }; 2097