xref: /openbmc/qemu/target/riscv/csr.c (revision 961738ff) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     if (env->misa_ext & RVV) {
51 #if !defined(CONFIG_USER_ONLY)
52         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
53             return RISCV_EXCP_ILLEGAL_INST;
54         }
55 #endif
56         return RISCV_EXCP_NONE;
57     }
58     return RISCV_EXCP_ILLEGAL_INST;
59 }
60 
61 static RISCVException ctr(CPURISCVState *env, int csrno)
62 {
63 #if !defined(CONFIG_USER_ONLY)
64     CPUState *cs = env_cpu(env);
65     RISCVCPU *cpu = RISCV_CPU(cs);
66 
67     if (!cpu->cfg.ext_counters) {
68         /* The Counters extensions is not enabled */
69         return RISCV_EXCP_ILLEGAL_INST;
70     }
71 
72     if (riscv_cpu_virt_enabled(env)) {
73         switch (csrno) {
74         case CSR_CYCLE:
75             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
76                 get_field(env->mcounteren, COUNTEREN_CY)) {
77                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
78             }
79             break;
80         case CSR_TIME:
81             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
82                 get_field(env->mcounteren, COUNTEREN_TM)) {
83                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
84             }
85             break;
86         case CSR_INSTRET:
87             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
88                 get_field(env->mcounteren, COUNTEREN_IR)) {
89                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
90             }
91             break;
92         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
93             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
94                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
95                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
96             }
97             break;
98         }
99         if (riscv_cpu_mxl(env) == MXL_RV32) {
100             switch (csrno) {
101             case CSR_CYCLEH:
102                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
103                     get_field(env->mcounteren, COUNTEREN_CY)) {
104                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
105                 }
106                 break;
107             case CSR_TIMEH:
108                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
109                     get_field(env->mcounteren, COUNTEREN_TM)) {
110                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
111                 }
112                 break;
113             case CSR_INSTRETH:
114                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
115                     get_field(env->mcounteren, COUNTEREN_IR)) {
116                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
117                 }
118                 break;
119             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
120                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
121                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
122                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
123                 }
124                 break;
125             }
126         }
127     }
128 #endif
129     return RISCV_EXCP_NONE;
130 }
131 
132 static RISCVException ctr32(CPURISCVState *env, int csrno)
133 {
134     if (riscv_cpu_mxl(env) != MXL_RV32) {
135         return RISCV_EXCP_ILLEGAL_INST;
136     }
137 
138     return ctr(env, csrno);
139 }
140 
141 #if !defined(CONFIG_USER_ONLY)
142 static RISCVException any(CPURISCVState *env, int csrno)
143 {
144     return RISCV_EXCP_NONE;
145 }
146 
147 static RISCVException any32(CPURISCVState *env, int csrno)
148 {
149     if (riscv_cpu_mxl(env) != MXL_RV32) {
150         return RISCV_EXCP_ILLEGAL_INST;
151     }
152 
153     return any(env, csrno);
154 
155 }
156 
157 static RISCVException smode(CPURISCVState *env, int csrno)
158 {
159     if (riscv_has_ext(env, RVS)) {
160         return RISCV_EXCP_NONE;
161     }
162 
163     return RISCV_EXCP_ILLEGAL_INST;
164 }
165 
166 static RISCVException hmode(CPURISCVState *env, int csrno)
167 {
168     if (riscv_has_ext(env, RVS) &&
169         riscv_has_ext(env, RVH)) {
170         /* Hypervisor extension is supported */
171         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
172             env->priv == PRV_M) {
173             return RISCV_EXCP_NONE;
174         } else {
175             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
176         }
177     }
178 
179     return RISCV_EXCP_ILLEGAL_INST;
180 }
181 
182 static RISCVException hmode32(CPURISCVState *env, int csrno)
183 {
184     if (riscv_cpu_mxl(env) != MXL_RV32) {
185         if (riscv_cpu_virt_enabled(env)) {
186             return RISCV_EXCP_ILLEGAL_INST;
187         } else {
188             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
189         }
190     }
191 
192     return hmode(env, csrno);
193 
194 }
195 
196 /* Checks if PointerMasking registers could be accessed */
197 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
198 {
199     /* Check if j-ext is present */
200     if (riscv_has_ext(env, RVJ)) {
201         return RISCV_EXCP_NONE;
202     }
203     return RISCV_EXCP_ILLEGAL_INST;
204 }
205 
206 static RISCVException pmp(CPURISCVState *env, int csrno)
207 {
208     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
209         return RISCV_EXCP_NONE;
210     }
211 
212     return RISCV_EXCP_ILLEGAL_INST;
213 }
214 
215 static RISCVException epmp(CPURISCVState *env, int csrno)
216 {
217     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
218         return RISCV_EXCP_NONE;
219     }
220 
221     return RISCV_EXCP_ILLEGAL_INST;
222 }
223 #endif
224 
225 /* User Floating-Point CSRs */
226 static RISCVException read_fflags(CPURISCVState *env, int csrno,
227                                   target_ulong *val)
228 {
229     *val = riscv_cpu_get_fflags(env);
230     return RISCV_EXCP_NONE;
231 }
232 
233 static RISCVException write_fflags(CPURISCVState *env, int csrno,
234                                    target_ulong val)
235 {
236 #if !defined(CONFIG_USER_ONLY)
237     env->mstatus |= MSTATUS_FS;
238 #endif
239     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
240     return RISCV_EXCP_NONE;
241 }
242 
243 static RISCVException read_frm(CPURISCVState *env, int csrno,
244                                target_ulong *val)
245 {
246     *val = env->frm;
247     return RISCV_EXCP_NONE;
248 }
249 
250 static RISCVException write_frm(CPURISCVState *env, int csrno,
251                                 target_ulong val)
252 {
253 #if !defined(CONFIG_USER_ONLY)
254     env->mstatus |= MSTATUS_FS;
255 #endif
256     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
257     return RISCV_EXCP_NONE;
258 }
259 
260 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
261                                 target_ulong *val)
262 {
263     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
264         | (env->frm << FSR_RD_SHIFT);
265     return RISCV_EXCP_NONE;
266 }
267 
268 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
269                                  target_ulong val)
270 {
271 #if !defined(CONFIG_USER_ONLY)
272     env->mstatus |= MSTATUS_FS;
273 #endif
274     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
275     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
276     return RISCV_EXCP_NONE;
277 }
278 
279 static RISCVException read_vtype(CPURISCVState *env, int csrno,
280                                  target_ulong *val)
281 {
282     *val = env->vtype;
283     return RISCV_EXCP_NONE;
284 }
285 
286 static RISCVException read_vl(CPURISCVState *env, int csrno,
287                               target_ulong *val)
288 {
289     *val = env->vl;
290     return RISCV_EXCP_NONE;
291 }
292 
293 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
294 {
295     *val = env_archcpu(env)->cfg.vlen >> 3;
296     return RISCV_EXCP_NONE;
297 }
298 
299 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
300                                 target_ulong *val)
301 {
302     *val = env->vxrm;
303     return RISCV_EXCP_NONE;
304 }
305 
306 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
307                                  target_ulong val)
308 {
309 #if !defined(CONFIG_USER_ONLY)
310     env->mstatus |= MSTATUS_VS;
311 #endif
312     env->vxrm = val;
313     return RISCV_EXCP_NONE;
314 }
315 
316 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
317                                  target_ulong *val)
318 {
319     *val = env->vxsat;
320     return RISCV_EXCP_NONE;
321 }
322 
323 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
324                                   target_ulong val)
325 {
326 #if !defined(CONFIG_USER_ONLY)
327     env->mstatus |= MSTATUS_VS;
328 #endif
329     env->vxsat = val;
330     return RISCV_EXCP_NONE;
331 }
332 
333 static RISCVException read_vstart(CPURISCVState *env, int csrno,
334                                   target_ulong *val)
335 {
336     *val = env->vstart;
337     return RISCV_EXCP_NONE;
338 }
339 
340 static RISCVException write_vstart(CPURISCVState *env, int csrno,
341                                    target_ulong val)
342 {
343 #if !defined(CONFIG_USER_ONLY)
344     env->mstatus |= MSTATUS_VS;
345 #endif
346     /*
347      * The vstart CSR is defined to have only enough writable bits
348      * to hold the largest element index, i.e. lg2(VLEN) bits.
349      */
350     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
351     return RISCV_EXCP_NONE;
352 }
353 
354 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
355 {
356     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
357     return RISCV_EXCP_NONE;
358 }
359 
360 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
361 {
362 #if !defined(CONFIG_USER_ONLY)
363     env->mstatus |= MSTATUS_VS;
364 #endif
365     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
366     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
367     return RISCV_EXCP_NONE;
368 }
369 
370 /* User Timers and Counters */
371 static RISCVException read_instret(CPURISCVState *env, int csrno,
372                                    target_ulong *val)
373 {
374 #if !defined(CONFIG_USER_ONLY)
375     if (icount_enabled()) {
376         *val = icount_get();
377     } else {
378         *val = cpu_get_host_ticks();
379     }
380 #else
381     *val = cpu_get_host_ticks();
382 #endif
383     return RISCV_EXCP_NONE;
384 }
385 
386 static RISCVException read_instreth(CPURISCVState *env, int csrno,
387                                     target_ulong *val)
388 {
389 #if !defined(CONFIG_USER_ONLY)
390     if (icount_enabled()) {
391         *val = icount_get() >> 32;
392     } else {
393         *val = cpu_get_host_ticks() >> 32;
394     }
395 #else
396     *val = cpu_get_host_ticks() >> 32;
397 #endif
398     return RISCV_EXCP_NONE;
399 }
400 
401 #if defined(CONFIG_USER_ONLY)
402 static RISCVException read_time(CPURISCVState *env, int csrno,
403                                 target_ulong *val)
404 {
405     *val = cpu_get_host_ticks();
406     return RISCV_EXCP_NONE;
407 }
408 
409 static RISCVException read_timeh(CPURISCVState *env, int csrno,
410                                  target_ulong *val)
411 {
412     *val = cpu_get_host_ticks() >> 32;
413     return RISCV_EXCP_NONE;
414 }
415 
416 #else /* CONFIG_USER_ONLY */
417 
418 static RISCVException read_time(CPURISCVState *env, int csrno,
419                                 target_ulong *val)
420 {
421     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
422 
423     if (!env->rdtime_fn) {
424         return RISCV_EXCP_ILLEGAL_INST;
425     }
426 
427     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
428     return RISCV_EXCP_NONE;
429 }
430 
431 static RISCVException read_timeh(CPURISCVState *env, int csrno,
432                                  target_ulong *val)
433 {
434     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
435 
436     if (!env->rdtime_fn) {
437         return RISCV_EXCP_ILLEGAL_INST;
438     }
439 
440     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
441     return RISCV_EXCP_NONE;
442 }
443 
444 /* Machine constants */
445 
446 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
447 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
448 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
449 
450 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
451                                            VS_MODE_INTERRUPTS;
452 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
453 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
454                                      VS_MODE_INTERRUPTS;
455 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
456                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
457                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
458                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
459                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
460                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
461                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
462                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
463                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
464                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
465                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
466                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
467                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
468                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
469                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
470                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
471                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
472                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
473                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
474 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
475     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
476       (1ULL << (RISCV_EXCP_VS_ECALL)) |
477       (1ULL << (RISCV_EXCP_M_ECALL)) |
478       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
479       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
480       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
481       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
482 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
483     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
484     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
485 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
486 static const target_ulong hip_writable_mask = MIP_VSSIP;
487 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
488 static const target_ulong vsip_writable_mask = MIP_VSSIP;
489 
490 static const char valid_vm_1_10_32[16] = {
491     [VM_1_10_MBARE] = 1,
492     [VM_1_10_SV32] = 1
493 };
494 
495 static const char valid_vm_1_10_64[16] = {
496     [VM_1_10_MBARE] = 1,
497     [VM_1_10_SV39] = 1,
498     [VM_1_10_SV48] = 1,
499     [VM_1_10_SV57] = 1
500 };
501 
502 /* Machine Information Registers */
503 static RISCVException read_zero(CPURISCVState *env, int csrno,
504                                 target_ulong *val)
505 {
506     *val = 0;
507     return RISCV_EXCP_NONE;
508 }
509 
510 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
511                                    target_ulong *val)
512 {
513     *val = env->mhartid;
514     return RISCV_EXCP_NONE;
515 }
516 
517 /* Machine Trap Setup */
518 
519 /* We do not store SD explicitly, only compute it on demand. */
520 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
521 {
522     if ((status & MSTATUS_FS) == MSTATUS_FS ||
523         (status & MSTATUS_VS) == MSTATUS_VS ||
524         (status & MSTATUS_XS) == MSTATUS_XS) {
525         switch (xl) {
526         case MXL_RV32:
527             return status | MSTATUS32_SD;
528         case MXL_RV64:
529             return status | MSTATUS64_SD;
530         default:
531             g_assert_not_reached();
532         }
533     }
534     return status;
535 }
536 
537 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
538                                    target_ulong *val)
539 {
540     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
541     return RISCV_EXCP_NONE;
542 }
543 
544 static int validate_vm(CPURISCVState *env, target_ulong vm)
545 {
546     if (riscv_cpu_mxl(env) == MXL_RV32) {
547         return valid_vm_1_10_32[vm & 0xf];
548     } else {
549         return valid_vm_1_10_64[vm & 0xf];
550     }
551 }
552 
553 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
554                                     target_ulong val)
555 {
556     uint64_t mstatus = env->mstatus;
557     uint64_t mask = 0;
558 
559     /* flush tlb on mstatus fields that affect VM */
560     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
561             MSTATUS_MPRV | MSTATUS_SUM)) {
562         tlb_flush(env_cpu(env));
563     }
564     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
565         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
566         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
567         MSTATUS_TW | MSTATUS_VS;
568 
569     if (riscv_cpu_mxl(env) != MXL_RV32) {
570         /*
571          * RV32: MPV and GVA are not in mstatus. The current plan is to
572          * add them to mstatush. For now, we just don't support it.
573          */
574         mask |= MSTATUS_MPV | MSTATUS_GVA;
575     }
576 
577     mstatus = (mstatus & ~mask) | (val & mask);
578 
579     if (riscv_cpu_mxl(env) == MXL_RV64) {
580         /* SXL and UXL fields are for now read only */
581         mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
582         mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
583     }
584     env->mstatus = mstatus;
585 
586     return RISCV_EXCP_NONE;
587 }
588 
589 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
590                                     target_ulong *val)
591 {
592     *val = env->mstatus >> 32;
593     return RISCV_EXCP_NONE;
594 }
595 
596 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
597                                      target_ulong val)
598 {
599     uint64_t valh = (uint64_t)val << 32;
600     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
601 
602     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
603         tlb_flush(env_cpu(env));
604     }
605 
606     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
607 
608     return RISCV_EXCP_NONE;
609 }
610 
611 static RISCVException read_misa(CPURISCVState *env, int csrno,
612                                 target_ulong *val)
613 {
614     target_ulong misa;
615 
616     switch (env->misa_mxl) {
617     case MXL_RV32:
618         misa = (target_ulong)MXL_RV32 << 30;
619         break;
620 #ifdef TARGET_RISCV64
621     case MXL_RV64:
622         misa = (target_ulong)MXL_RV64 << 62;
623         break;
624 #endif
625     default:
626         g_assert_not_reached();
627     }
628 
629     *val = misa | env->misa_ext;
630     return RISCV_EXCP_NONE;
631 }
632 
633 static RISCVException write_misa(CPURISCVState *env, int csrno,
634                                  target_ulong val)
635 {
636     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
637         /* drop write to misa */
638         return RISCV_EXCP_NONE;
639     }
640 
641     /* 'I' or 'E' must be present */
642     if (!(val & (RVI | RVE))) {
643         /* It is not, drop write to misa */
644         return RISCV_EXCP_NONE;
645     }
646 
647     /* 'E' excludes all other extensions */
648     if (val & RVE) {
649         /* when we support 'E' we can do "val = RVE;" however
650          * for now we just drop writes if 'E' is present.
651          */
652         return RISCV_EXCP_NONE;
653     }
654 
655     /*
656      * misa.MXL writes are not supported by QEMU.
657      * Drop writes to those bits.
658      */
659 
660     /* Mask extensions that are not supported by this hart */
661     val &= env->misa_ext_mask;
662 
663     /* Mask extensions that are not supported by QEMU */
664     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
665 
666     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
667     if ((val & RVD) && !(val & RVF)) {
668         val &= ~RVD;
669     }
670 
671     /* Suppress 'C' if next instruction is not aligned
672      * TODO: this should check next_pc
673      */
674     if ((val & RVC) && (GETPC() & ~3) != 0) {
675         val &= ~RVC;
676     }
677 
678     /* If nothing changed, do nothing. */
679     if (val == env->misa_ext) {
680         return RISCV_EXCP_NONE;
681     }
682 
683     /* flush translation cache */
684     tb_flush(env_cpu(env));
685     env->misa_ext = val;
686     return RISCV_EXCP_NONE;
687 }
688 
689 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
690                                    target_ulong *val)
691 {
692     *val = env->medeleg;
693     return RISCV_EXCP_NONE;
694 }
695 
696 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
697                                     target_ulong val)
698 {
699     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
700     return RISCV_EXCP_NONE;
701 }
702 
703 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
704                                    target_ulong *val)
705 {
706     *val = env->mideleg;
707     return RISCV_EXCP_NONE;
708 }
709 
710 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
711                                     target_ulong val)
712 {
713     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
714     if (riscv_has_ext(env, RVH)) {
715         env->mideleg |= VS_MODE_INTERRUPTS;
716     }
717     return RISCV_EXCP_NONE;
718 }
719 
720 static RISCVException read_mie(CPURISCVState *env, int csrno,
721                                target_ulong *val)
722 {
723     *val = env->mie;
724     return RISCV_EXCP_NONE;
725 }
726 
727 static RISCVException write_mie(CPURISCVState *env, int csrno,
728                                 target_ulong val)
729 {
730     env->mie = (env->mie & ~all_ints) | (val & all_ints);
731     return RISCV_EXCP_NONE;
732 }
733 
734 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
735                                  target_ulong *val)
736 {
737     *val = env->mtvec;
738     return RISCV_EXCP_NONE;
739 }
740 
741 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
742                                   target_ulong val)
743 {
744     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
745     if ((val & 3) < 2) {
746         env->mtvec = val;
747     } else {
748         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
749     }
750     return RISCV_EXCP_NONE;
751 }
752 
753 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
754                                       target_ulong *val)
755 {
756     *val = env->mcounteren;
757     return RISCV_EXCP_NONE;
758 }
759 
760 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
761                                        target_ulong val)
762 {
763     env->mcounteren = val;
764     return RISCV_EXCP_NONE;
765 }
766 
767 /* Machine Trap Handling */
768 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
769                                     target_ulong *val)
770 {
771     *val = env->mscratch;
772     return RISCV_EXCP_NONE;
773 }
774 
775 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
776                                      target_ulong val)
777 {
778     env->mscratch = val;
779     return RISCV_EXCP_NONE;
780 }
781 
782 static RISCVException read_mepc(CPURISCVState *env, int csrno,
783                                      target_ulong *val)
784 {
785     *val = env->mepc;
786     return RISCV_EXCP_NONE;
787 }
788 
789 static RISCVException write_mepc(CPURISCVState *env, int csrno,
790                                      target_ulong val)
791 {
792     env->mepc = val;
793     return RISCV_EXCP_NONE;
794 }
795 
796 static RISCVException read_mcause(CPURISCVState *env, int csrno,
797                                      target_ulong *val)
798 {
799     *val = env->mcause;
800     return RISCV_EXCP_NONE;
801 }
802 
803 static RISCVException write_mcause(CPURISCVState *env, int csrno,
804                                      target_ulong val)
805 {
806     env->mcause = val;
807     return RISCV_EXCP_NONE;
808 }
809 
810 static RISCVException read_mtval(CPURISCVState *env, int csrno,
811                                  target_ulong *val)
812 {
813     *val = env->mtval;
814     return RISCV_EXCP_NONE;
815 }
816 
817 static RISCVException write_mtval(CPURISCVState *env, int csrno,
818                                   target_ulong val)
819 {
820     env->mtval = val;
821     return RISCV_EXCP_NONE;
822 }
823 
824 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
825                               target_ulong *ret_value,
826                               target_ulong new_value, target_ulong write_mask)
827 {
828     RISCVCPU *cpu = env_archcpu(env);
829     /* Allow software control of delegable interrupts not claimed by hardware */
830     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
831     uint32_t old_mip;
832 
833     if (mask) {
834         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
835     } else {
836         old_mip = env->mip;
837     }
838 
839     if (ret_value) {
840         *ret_value = old_mip;
841     }
842 
843     return RISCV_EXCP_NONE;
844 }
845 
846 /* Supervisor Trap Setup */
847 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
848                                    target_ulong *val)
849 {
850     target_ulong mask = (sstatus_v1_10_mask);
851 
852     /* TODO: Use SXL not MXL. */
853     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
854     return RISCV_EXCP_NONE;
855 }
856 
857 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
858                                     target_ulong val)
859 {
860     target_ulong mask = (sstatus_v1_10_mask);
861     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
862     return write_mstatus(env, CSR_MSTATUS, newval);
863 }
864 
865 static RISCVException read_vsie(CPURISCVState *env, int csrno,
866                                 target_ulong *val)
867 {
868     /* Shift the VS bits to their S bit location in vsie */
869     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
870     return RISCV_EXCP_NONE;
871 }
872 
873 static RISCVException read_sie(CPURISCVState *env, int csrno,
874                                target_ulong *val)
875 {
876     if (riscv_cpu_virt_enabled(env)) {
877         read_vsie(env, CSR_VSIE, val);
878     } else {
879         *val = env->mie & env->mideleg;
880     }
881     return RISCV_EXCP_NONE;
882 }
883 
884 static RISCVException write_vsie(CPURISCVState *env, int csrno,
885                                  target_ulong val)
886 {
887     /* Shift the S bits to their VS bit location in mie */
888     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
889                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
890     return write_mie(env, CSR_MIE, newval);
891 }
892 
893 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
894 {
895     if (riscv_cpu_virt_enabled(env)) {
896         write_vsie(env, CSR_VSIE, val);
897     } else {
898         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
899                               (val & S_MODE_INTERRUPTS);
900         write_mie(env, CSR_MIE, newval);
901     }
902 
903     return RISCV_EXCP_NONE;
904 }
905 
906 static RISCVException read_stvec(CPURISCVState *env, int csrno,
907                                  target_ulong *val)
908 {
909     *val = env->stvec;
910     return RISCV_EXCP_NONE;
911 }
912 
913 static RISCVException write_stvec(CPURISCVState *env, int csrno,
914                                   target_ulong val)
915 {
916     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
917     if ((val & 3) < 2) {
918         env->stvec = val;
919     } else {
920         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
921     }
922     return RISCV_EXCP_NONE;
923 }
924 
925 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
926                                       target_ulong *val)
927 {
928     *val = env->scounteren;
929     return RISCV_EXCP_NONE;
930 }
931 
932 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
933                                        target_ulong val)
934 {
935     env->scounteren = val;
936     return RISCV_EXCP_NONE;
937 }
938 
939 /* Supervisor Trap Handling */
940 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
941                                     target_ulong *val)
942 {
943     *val = env->sscratch;
944     return RISCV_EXCP_NONE;
945 }
946 
947 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
948                                      target_ulong val)
949 {
950     env->sscratch = val;
951     return RISCV_EXCP_NONE;
952 }
953 
954 static RISCVException read_sepc(CPURISCVState *env, int csrno,
955                                 target_ulong *val)
956 {
957     *val = env->sepc;
958     return RISCV_EXCP_NONE;
959 }
960 
961 static RISCVException write_sepc(CPURISCVState *env, int csrno,
962                                  target_ulong val)
963 {
964     env->sepc = val;
965     return RISCV_EXCP_NONE;
966 }
967 
968 static RISCVException read_scause(CPURISCVState *env, int csrno,
969                                   target_ulong *val)
970 {
971     *val = env->scause;
972     return RISCV_EXCP_NONE;
973 }
974 
975 static RISCVException write_scause(CPURISCVState *env, int csrno,
976                                    target_ulong val)
977 {
978     env->scause = val;
979     return RISCV_EXCP_NONE;
980 }
981 
982 static RISCVException read_stval(CPURISCVState *env, int csrno,
983                                  target_ulong *val)
984 {
985     *val = env->stval;
986     return RISCV_EXCP_NONE;
987 }
988 
989 static RISCVException write_stval(CPURISCVState *env, int csrno,
990                                   target_ulong val)
991 {
992     env->stval = val;
993     return RISCV_EXCP_NONE;
994 }
995 
996 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
997                                target_ulong *ret_value,
998                                target_ulong new_value, target_ulong write_mask)
999 {
1000     /* Shift the S bits to their VS bit location in mip */
1001     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
1002                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1003 
1004     if (ret_value) {
1005         *ret_value &= VS_MODE_INTERRUPTS;
1006         /* Shift the VS bits to their S bit location in vsip */
1007         *ret_value >>= 1;
1008     }
1009     return ret;
1010 }
1011 
1012 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1013                               target_ulong *ret_value,
1014                               target_ulong new_value, target_ulong write_mask)
1015 {
1016     int ret;
1017 
1018     if (riscv_cpu_virt_enabled(env)) {
1019         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1020     } else {
1021         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
1022                       write_mask & env->mideleg & sip_writable_mask);
1023     }
1024 
1025     if (ret_value) {
1026         *ret_value &= env->mideleg;
1027     }
1028     return ret;
1029 }
1030 
1031 /* Supervisor Protection and Translation */
1032 static RISCVException read_satp(CPURISCVState *env, int csrno,
1033                                 target_ulong *val)
1034 {
1035     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1036         *val = 0;
1037         return RISCV_EXCP_NONE;
1038     }
1039 
1040     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1041         return RISCV_EXCP_ILLEGAL_INST;
1042     } else {
1043         *val = env->satp;
1044     }
1045 
1046     return RISCV_EXCP_NONE;
1047 }
1048 
1049 static RISCVException write_satp(CPURISCVState *env, int csrno,
1050                                  target_ulong val)
1051 {
1052     target_ulong vm, mask, asid;
1053 
1054     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1055         return RISCV_EXCP_NONE;
1056     }
1057 
1058     if (riscv_cpu_mxl(env) == MXL_RV32) {
1059         vm = validate_vm(env, get_field(val, SATP32_MODE));
1060         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1061         asid = (val ^ env->satp) & SATP32_ASID;
1062     } else {
1063         vm = validate_vm(env, get_field(val, SATP64_MODE));
1064         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1065         asid = (val ^ env->satp) & SATP64_ASID;
1066     }
1067 
1068     if (vm && mask) {
1069         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1070             return RISCV_EXCP_ILLEGAL_INST;
1071         } else {
1072             if (asid) {
1073                 tlb_flush(env_cpu(env));
1074             }
1075             env->satp = val;
1076         }
1077     }
1078     return RISCV_EXCP_NONE;
1079 }
1080 
1081 /* Hypervisor Extensions */
1082 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1083                                    target_ulong *val)
1084 {
1085     *val = env->hstatus;
1086     if (riscv_cpu_mxl(env) != MXL_RV32) {
1087         /* We only support 64-bit VSXL */
1088         *val = set_field(*val, HSTATUS_VSXL, 2);
1089     }
1090     /* We only support little endian */
1091     *val = set_field(*val, HSTATUS_VSBE, 0);
1092     return RISCV_EXCP_NONE;
1093 }
1094 
1095 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1096                                     target_ulong val)
1097 {
1098     env->hstatus = val;
1099     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1100         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1101     }
1102     if (get_field(val, HSTATUS_VSBE) != 0) {
1103         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1104     }
1105     return RISCV_EXCP_NONE;
1106 }
1107 
1108 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1109                                    target_ulong *val)
1110 {
1111     *val = env->hedeleg;
1112     return RISCV_EXCP_NONE;
1113 }
1114 
1115 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1116                                     target_ulong val)
1117 {
1118     env->hedeleg = val & vs_delegable_excps;
1119     return RISCV_EXCP_NONE;
1120 }
1121 
1122 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1123                                    target_ulong *val)
1124 {
1125     *val = env->hideleg;
1126     return RISCV_EXCP_NONE;
1127 }
1128 
1129 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1130                                     target_ulong val)
1131 {
1132     env->hideleg = val & vs_delegable_ints;
1133     return RISCV_EXCP_NONE;
1134 }
1135 
1136 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1137                                target_ulong *ret_value,
1138                                target_ulong new_value, target_ulong write_mask)
1139 {
1140     int ret = rmw_mip(env, 0, ret_value, new_value,
1141                       write_mask & hvip_writable_mask);
1142 
1143     if (ret_value) {
1144         *ret_value &= hvip_writable_mask;
1145     }
1146     return ret;
1147 }
1148 
1149 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1150                               target_ulong *ret_value,
1151                               target_ulong new_value, target_ulong write_mask)
1152 {
1153     int ret = rmw_mip(env, 0, ret_value, new_value,
1154                       write_mask & hip_writable_mask);
1155 
1156     if (ret_value) {
1157         *ret_value &= hip_writable_mask;
1158     }
1159     return ret;
1160 }
1161 
1162 static RISCVException read_hie(CPURISCVState *env, int csrno,
1163                                target_ulong *val)
1164 {
1165     *val = env->mie & VS_MODE_INTERRUPTS;
1166     return RISCV_EXCP_NONE;
1167 }
1168 
1169 static RISCVException write_hie(CPURISCVState *env, int csrno,
1170                                 target_ulong val)
1171 {
1172     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1173     return write_mie(env, CSR_MIE, newval);
1174 }
1175 
1176 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1177                                       target_ulong *val)
1178 {
1179     *val = env->hcounteren;
1180     return RISCV_EXCP_NONE;
1181 }
1182 
1183 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1184                                        target_ulong val)
1185 {
1186     env->hcounteren = val;
1187     return RISCV_EXCP_NONE;
1188 }
1189 
1190 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1191                                   target_ulong val)
1192 {
1193     if (val) {
1194         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1195     }
1196     return RISCV_EXCP_NONE;
1197 }
1198 
1199 static RISCVException read_htval(CPURISCVState *env, int csrno,
1200                                  target_ulong *val)
1201 {
1202     *val = env->htval;
1203     return RISCV_EXCP_NONE;
1204 }
1205 
1206 static RISCVException write_htval(CPURISCVState *env, int csrno,
1207                                   target_ulong val)
1208 {
1209     env->htval = val;
1210     return RISCV_EXCP_NONE;
1211 }
1212 
1213 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1214                                   target_ulong *val)
1215 {
1216     *val = env->htinst;
1217     return RISCV_EXCP_NONE;
1218 }
1219 
1220 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1221                                    target_ulong val)
1222 {
1223     return RISCV_EXCP_NONE;
1224 }
1225 
1226 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1227                                   target_ulong val)
1228 {
1229     if (val) {
1230         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1231     }
1232     return RISCV_EXCP_NONE;
1233 }
1234 
1235 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1236                                  target_ulong *val)
1237 {
1238     *val = env->hgatp;
1239     return RISCV_EXCP_NONE;
1240 }
1241 
1242 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1243                                   target_ulong val)
1244 {
1245     env->hgatp = val;
1246     return RISCV_EXCP_NONE;
1247 }
1248 
1249 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1250                                       target_ulong *val)
1251 {
1252     if (!env->rdtime_fn) {
1253         return RISCV_EXCP_ILLEGAL_INST;
1254     }
1255 
1256     *val = env->htimedelta;
1257     return RISCV_EXCP_NONE;
1258 }
1259 
1260 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1261                                        target_ulong val)
1262 {
1263     if (!env->rdtime_fn) {
1264         return RISCV_EXCP_ILLEGAL_INST;
1265     }
1266 
1267     if (riscv_cpu_mxl(env) == MXL_RV32) {
1268         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1269     } else {
1270         env->htimedelta = val;
1271     }
1272     return RISCV_EXCP_NONE;
1273 }
1274 
1275 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1276                                        target_ulong *val)
1277 {
1278     if (!env->rdtime_fn) {
1279         return RISCV_EXCP_ILLEGAL_INST;
1280     }
1281 
1282     *val = env->htimedelta >> 32;
1283     return RISCV_EXCP_NONE;
1284 }
1285 
1286 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1287                                         target_ulong val)
1288 {
1289     if (!env->rdtime_fn) {
1290         return RISCV_EXCP_ILLEGAL_INST;
1291     }
1292 
1293     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1294     return RISCV_EXCP_NONE;
1295 }
1296 
1297 /* Virtual CSR Registers */
1298 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1299                                     target_ulong *val)
1300 {
1301     *val = env->vsstatus;
1302     return RISCV_EXCP_NONE;
1303 }
1304 
1305 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1306                                      target_ulong val)
1307 {
1308     uint64_t mask = (target_ulong)-1;
1309     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1310     return RISCV_EXCP_NONE;
1311 }
1312 
1313 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1314 {
1315     *val = env->vstvec;
1316     return RISCV_EXCP_NONE;
1317 }
1318 
1319 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1320                                    target_ulong val)
1321 {
1322     env->vstvec = val;
1323     return RISCV_EXCP_NONE;
1324 }
1325 
1326 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1327                                      target_ulong *val)
1328 {
1329     *val = env->vsscratch;
1330     return RISCV_EXCP_NONE;
1331 }
1332 
1333 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1334                                       target_ulong val)
1335 {
1336     env->vsscratch = val;
1337     return RISCV_EXCP_NONE;
1338 }
1339 
1340 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1341                                  target_ulong *val)
1342 {
1343     *val = env->vsepc;
1344     return RISCV_EXCP_NONE;
1345 }
1346 
1347 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1348                                   target_ulong val)
1349 {
1350     env->vsepc = val;
1351     return RISCV_EXCP_NONE;
1352 }
1353 
1354 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1355                                    target_ulong *val)
1356 {
1357     *val = env->vscause;
1358     return RISCV_EXCP_NONE;
1359 }
1360 
1361 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1362                                     target_ulong val)
1363 {
1364     env->vscause = val;
1365     return RISCV_EXCP_NONE;
1366 }
1367 
1368 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1369                                   target_ulong *val)
1370 {
1371     *val = env->vstval;
1372     return RISCV_EXCP_NONE;
1373 }
1374 
1375 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1376                                    target_ulong val)
1377 {
1378     env->vstval = val;
1379     return RISCV_EXCP_NONE;
1380 }
1381 
1382 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1383                                  target_ulong *val)
1384 {
1385     *val = env->vsatp;
1386     return RISCV_EXCP_NONE;
1387 }
1388 
1389 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1390                                   target_ulong val)
1391 {
1392     env->vsatp = val;
1393     return RISCV_EXCP_NONE;
1394 }
1395 
1396 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1397                                   target_ulong *val)
1398 {
1399     *val = env->mtval2;
1400     return RISCV_EXCP_NONE;
1401 }
1402 
1403 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1404                                    target_ulong val)
1405 {
1406     env->mtval2 = val;
1407     return RISCV_EXCP_NONE;
1408 }
1409 
1410 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1411                                   target_ulong *val)
1412 {
1413     *val = env->mtinst;
1414     return RISCV_EXCP_NONE;
1415 }
1416 
1417 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1418                                    target_ulong val)
1419 {
1420     env->mtinst = val;
1421     return RISCV_EXCP_NONE;
1422 }
1423 
1424 /* Physical Memory Protection */
1425 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1426                                    target_ulong *val)
1427 {
1428     *val = mseccfg_csr_read(env);
1429     return RISCV_EXCP_NONE;
1430 }
1431 
1432 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1433                          target_ulong val)
1434 {
1435     mseccfg_csr_write(env, val);
1436     return RISCV_EXCP_NONE;
1437 }
1438 
1439 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1440                                   target_ulong *val)
1441 {
1442     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1443     return RISCV_EXCP_NONE;
1444 }
1445 
1446 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1447                                    target_ulong val)
1448 {
1449     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1450     return RISCV_EXCP_NONE;
1451 }
1452 
1453 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1454                                    target_ulong *val)
1455 {
1456     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1457     return RISCV_EXCP_NONE;
1458 }
1459 
1460 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1461                                     target_ulong val)
1462 {
1463     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1464     return RISCV_EXCP_NONE;
1465 }
1466 
1467 /*
1468  * Functions to access Pointer Masking feature registers
1469  * We have to check if current priv lvl could modify
1470  * csr in given mode
1471  */
1472 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1473 {
1474     int csr_priv = get_field(csrno, 0x300);
1475     int pm_current;
1476 
1477     /*
1478      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1479      * so allow the access
1480      */
1481     if (env->priv != csr_priv) {
1482         return false;
1483     }
1484     switch (env->priv) {
1485     case PRV_M:
1486         pm_current = get_field(env->mmte, M_PM_CURRENT);
1487         break;
1488     case PRV_S:
1489         pm_current = get_field(env->mmte, S_PM_CURRENT);
1490         break;
1491     case PRV_U:
1492         pm_current = get_field(env->mmte, U_PM_CURRENT);
1493         break;
1494     default:
1495         g_assert_not_reached();
1496     }
1497     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1498     return !pm_current;
1499 }
1500 
1501 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1502                                 target_ulong *val)
1503 {
1504     *val = env->mmte & MMTE_MASK;
1505     return RISCV_EXCP_NONE;
1506 }
1507 
1508 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1509                                  target_ulong val)
1510 {
1511     uint64_t mstatus;
1512     target_ulong wpri_val = val & MMTE_MASK;
1513 
1514     if (val != wpri_val) {
1515         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1516                       "MMTE: WPRI violation written 0x", val,
1517                       "vs expected 0x", wpri_val);
1518     }
1519     /* for machine mode pm.current is hardwired to 1 */
1520     wpri_val |= MMTE_M_PM_CURRENT;
1521 
1522     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1523     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1524     env->mmte = wpri_val | PM_EXT_DIRTY;
1525 
1526     /* Set XS and SD bits, since PM CSRs are dirty */
1527     mstatus = env->mstatus | MSTATUS_XS;
1528     write_mstatus(env, csrno, mstatus);
1529     return RISCV_EXCP_NONE;
1530 }
1531 
1532 static RISCVException read_smte(CPURISCVState *env, int csrno,
1533                                 target_ulong *val)
1534 {
1535     *val = env->mmte & SMTE_MASK;
1536     return RISCV_EXCP_NONE;
1537 }
1538 
1539 static RISCVException write_smte(CPURISCVState *env, int csrno,
1540                                  target_ulong val)
1541 {
1542     target_ulong wpri_val = val & SMTE_MASK;
1543 
1544     if (val != wpri_val) {
1545         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1546                       "SMTE: WPRI violation written 0x", val,
1547                       "vs expected 0x", wpri_val);
1548     }
1549 
1550     /* if pm.current==0 we can't modify current PM CSRs */
1551     if (check_pm_current_disabled(env, csrno)) {
1552         return RISCV_EXCP_NONE;
1553     }
1554 
1555     wpri_val |= (env->mmte & ~SMTE_MASK);
1556     write_mmte(env, csrno, wpri_val);
1557     return RISCV_EXCP_NONE;
1558 }
1559 
1560 static RISCVException read_umte(CPURISCVState *env, int csrno,
1561                                 target_ulong *val)
1562 {
1563     *val = env->mmte & UMTE_MASK;
1564     return RISCV_EXCP_NONE;
1565 }
1566 
1567 static RISCVException write_umte(CPURISCVState *env, int csrno,
1568                                  target_ulong val)
1569 {
1570     target_ulong wpri_val = val & UMTE_MASK;
1571 
1572     if (val != wpri_val) {
1573         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1574                       "UMTE: WPRI violation written 0x", val,
1575                       "vs expected 0x", wpri_val);
1576     }
1577 
1578     if (check_pm_current_disabled(env, csrno)) {
1579         return RISCV_EXCP_NONE;
1580     }
1581 
1582     wpri_val |= (env->mmte & ~UMTE_MASK);
1583     write_mmte(env, csrno, wpri_val);
1584     return RISCV_EXCP_NONE;
1585 }
1586 
1587 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1588                                    target_ulong *val)
1589 {
1590     *val = env->mpmmask;
1591     return RISCV_EXCP_NONE;
1592 }
1593 
1594 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1595                                     target_ulong val)
1596 {
1597     uint64_t mstatus;
1598 
1599     env->mpmmask = val;
1600     env->mmte |= PM_EXT_DIRTY;
1601 
1602     /* Set XS and SD bits, since PM CSRs are dirty */
1603     mstatus = env->mstatus | MSTATUS_XS;
1604     write_mstatus(env, csrno, mstatus);
1605     return RISCV_EXCP_NONE;
1606 }
1607 
1608 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1609                                    target_ulong *val)
1610 {
1611     *val = env->spmmask;
1612     return RISCV_EXCP_NONE;
1613 }
1614 
1615 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1616                                     target_ulong val)
1617 {
1618     uint64_t mstatus;
1619 
1620     /* if pm.current==0 we can't modify current PM CSRs */
1621     if (check_pm_current_disabled(env, csrno)) {
1622         return RISCV_EXCP_NONE;
1623     }
1624     env->spmmask = val;
1625     env->mmte |= PM_EXT_DIRTY;
1626 
1627     /* Set XS and SD bits, since PM CSRs are dirty */
1628     mstatus = env->mstatus | MSTATUS_XS;
1629     write_mstatus(env, csrno, mstatus);
1630     return RISCV_EXCP_NONE;
1631 }
1632 
1633 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1634                                    target_ulong *val)
1635 {
1636     *val = env->upmmask;
1637     return RISCV_EXCP_NONE;
1638 }
1639 
1640 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1641                                     target_ulong val)
1642 {
1643     uint64_t mstatus;
1644 
1645     /* if pm.current==0 we can't modify current PM CSRs */
1646     if (check_pm_current_disabled(env, csrno)) {
1647         return RISCV_EXCP_NONE;
1648     }
1649     env->upmmask = val;
1650     env->mmte |= PM_EXT_DIRTY;
1651 
1652     /* Set XS and SD bits, since PM CSRs are dirty */
1653     mstatus = env->mstatus | MSTATUS_XS;
1654     write_mstatus(env, csrno, mstatus);
1655     return RISCV_EXCP_NONE;
1656 }
1657 
1658 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1659                                    target_ulong *val)
1660 {
1661     *val = env->mpmbase;
1662     return RISCV_EXCP_NONE;
1663 }
1664 
1665 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1666                                     target_ulong val)
1667 {
1668     uint64_t mstatus;
1669 
1670     env->mpmbase = val;
1671     env->mmte |= PM_EXT_DIRTY;
1672 
1673     /* Set XS and SD bits, since PM CSRs are dirty */
1674     mstatus = env->mstatus | MSTATUS_XS;
1675     write_mstatus(env, csrno, mstatus);
1676     return RISCV_EXCP_NONE;
1677 }
1678 
1679 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1680                                    target_ulong *val)
1681 {
1682     *val = env->spmbase;
1683     return RISCV_EXCP_NONE;
1684 }
1685 
1686 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1687                                     target_ulong val)
1688 {
1689     uint64_t mstatus;
1690 
1691     /* if pm.current==0 we can't modify current PM CSRs */
1692     if (check_pm_current_disabled(env, csrno)) {
1693         return RISCV_EXCP_NONE;
1694     }
1695     env->spmbase = val;
1696     env->mmte |= PM_EXT_DIRTY;
1697 
1698     /* Set XS and SD bits, since PM CSRs are dirty */
1699     mstatus = env->mstatus | MSTATUS_XS;
1700     write_mstatus(env, csrno, mstatus);
1701     return RISCV_EXCP_NONE;
1702 }
1703 
1704 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1705                                    target_ulong *val)
1706 {
1707     *val = env->upmbase;
1708     return RISCV_EXCP_NONE;
1709 }
1710 
1711 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1712                                     target_ulong val)
1713 {
1714     uint64_t mstatus;
1715 
1716     /* if pm.current==0 we can't modify current PM CSRs */
1717     if (check_pm_current_disabled(env, csrno)) {
1718         return RISCV_EXCP_NONE;
1719     }
1720     env->upmbase = val;
1721     env->mmte |= PM_EXT_DIRTY;
1722 
1723     /* Set XS and SD bits, since PM CSRs are dirty */
1724     mstatus = env->mstatus | MSTATUS_XS;
1725     write_mstatus(env, csrno, mstatus);
1726     return RISCV_EXCP_NONE;
1727 }
1728 
1729 #endif
1730 
1731 /*
1732  * riscv_csrrw - read and/or update control and status register
1733  *
1734  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1735  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1736  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1737  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1738  */
1739 
1740 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1741                            target_ulong *ret_value,
1742                            target_ulong new_value, target_ulong write_mask)
1743 {
1744     RISCVException ret;
1745     target_ulong old_value;
1746     RISCVCPU *cpu = env_archcpu(env);
1747     int read_only = get_field(csrno, 0xC00) == 3;
1748 
1749     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1750 #if !defined(CONFIG_USER_ONLY)
1751     int effective_priv = env->priv;
1752 
1753     if (riscv_has_ext(env, RVH) &&
1754         env->priv == PRV_S &&
1755         !riscv_cpu_virt_enabled(env)) {
1756         /*
1757          * We are in S mode without virtualisation, therefore we are in HS Mode.
1758          * Add 1 to the effective privledge level to allow us to access the
1759          * Hypervisor CSRs.
1760          */
1761         effective_priv++;
1762     }
1763 
1764     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1765         return RISCV_EXCP_ILLEGAL_INST;
1766     }
1767 #endif
1768     if (write_mask && read_only) {
1769         return RISCV_EXCP_ILLEGAL_INST;
1770     }
1771 
1772     /* ensure the CSR extension is enabled. */
1773     if (!cpu->cfg.ext_icsr) {
1774         return RISCV_EXCP_ILLEGAL_INST;
1775     }
1776 
1777     /* check predicate */
1778     if (!csr_ops[csrno].predicate) {
1779         return RISCV_EXCP_ILLEGAL_INST;
1780     }
1781     ret = csr_ops[csrno].predicate(env, csrno);
1782     if (ret != RISCV_EXCP_NONE) {
1783         return ret;
1784     }
1785 
1786     /* execute combined read/write operation if it exists */
1787     if (csr_ops[csrno].op) {
1788         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1789     }
1790 
1791     /* if no accessor exists then return failure */
1792     if (!csr_ops[csrno].read) {
1793         return RISCV_EXCP_ILLEGAL_INST;
1794     }
1795     /* read old value */
1796     ret = csr_ops[csrno].read(env, csrno, &old_value);
1797     if (ret != RISCV_EXCP_NONE) {
1798         return ret;
1799     }
1800 
1801     /* write value if writable and write mask set, otherwise drop writes */
1802     if (write_mask) {
1803         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1804         if (csr_ops[csrno].write) {
1805             ret = csr_ops[csrno].write(env, csrno, new_value);
1806             if (ret != RISCV_EXCP_NONE) {
1807                 return ret;
1808             }
1809         }
1810     }
1811 
1812     /* return old value */
1813     if (ret_value) {
1814         *ret_value = old_value;
1815     }
1816 
1817     return RISCV_EXCP_NONE;
1818 }
1819 
1820 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
1821                                Int128 *ret_value,
1822                                Int128 new_value, Int128 write_mask)
1823 {
1824     /* fall back to 64-bit version for now */
1825     target_ulong ret_64;
1826     RISCVException ret = riscv_csrrw(env, csrno, &ret_64,
1827                                      int128_getlo(new_value),
1828                                      int128_getlo(write_mask));
1829 
1830     if (ret_value) {
1831         *ret_value = int128_make64(ret_64);
1832     }
1833 
1834     return ret;
1835 }
1836 
1837 /*
1838  * Debugger support.  If not in user mode, set env->debugger before the
1839  * riscv_csrrw call and clear it after the call.
1840  */
1841 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
1842                                  target_ulong *ret_value,
1843                                  target_ulong new_value,
1844                                  target_ulong write_mask)
1845 {
1846     RISCVException ret;
1847 #if !defined(CONFIG_USER_ONLY)
1848     env->debugger = true;
1849 #endif
1850     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1851 #if !defined(CONFIG_USER_ONLY)
1852     env->debugger = false;
1853 #endif
1854     return ret;
1855 }
1856 
1857 /* Control and Status Register function table */
1858 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1859     /* User Floating-Point CSRs */
1860     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
1861     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
1862     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
1863     /* Vector CSRs */
1864     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
1865     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
1866     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
1867     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
1868     [CSR_VL]       = { "vl",       vs,     read_vl                    },
1869     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
1870     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
1871     /* User Timers and Counters */
1872     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
1873     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
1874     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
1875     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
1876 
1877     /*
1878      * In privileged mode, the monitor will have to emulate TIME CSRs only if
1879      * rdtime callback is not provided by machine/platform emulation.
1880      */
1881     [CSR_TIME]  = { "time",  ctr,   read_time  },
1882     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
1883 
1884 #if !defined(CONFIG_USER_ONLY)
1885     /* Machine Timers and Counters */
1886     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
1887     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
1888     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
1889     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
1890 
1891     /* Machine Information Registers */
1892     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
1893     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
1894     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
1895     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
1896 
1897     /* Machine Trap Setup */
1898     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
1899     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa        },
1900     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
1901     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
1902     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
1903     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
1904     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
1905 
1906     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
1907 
1908     /* Machine Trap Handling */
1909     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
1910     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
1911     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
1912     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
1913     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
1914 
1915     /* Supervisor Trap Setup */
1916     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus    },
1917     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
1918     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
1919     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
1920 
1921     /* Supervisor Trap Handling */
1922     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
1923     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
1924     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
1925     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
1926     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
1927 
1928     /* Supervisor Protection and Translation */
1929     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
1930 
1931     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
1932     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
1933     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
1934     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
1935     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
1936     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
1937     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
1938     [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
1939     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
1940     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
1941     [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
1942     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
1943     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
1944     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
1945 
1946     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
1947     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
1948     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
1949     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
1950     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
1951     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
1952     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
1953     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
1954     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
1955 
1956     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
1957     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
1958 
1959     /* Physical Memory Protection */
1960     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
1961     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
1962     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
1963     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
1964     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
1965     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
1966     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
1967     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
1968     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
1969     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
1970     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
1971     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
1972     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
1973     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
1974     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
1975     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
1976     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
1977     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
1978     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
1979     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
1980     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
1981 
1982     /* User Pointer Masking */
1983     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
1984     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
1985     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
1986     /* Machine Pointer Masking */
1987     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
1988     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
1989     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
1990     /* Supervisor Pointer Masking */
1991     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
1992     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
1993     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
1994 
1995     /* Performance Counters */
1996     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
1997     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
1998     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
1999     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2000     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2001     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2002     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2003     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2004     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2005     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2006     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2007     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2008     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2009     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2010     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2011     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2012     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2013     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2014     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2015     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2016     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2017     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2018     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2019     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2020     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2021     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2022     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2023     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2024     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2025 
2026     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2027     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2028     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2029     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2030     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2031     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2032     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2033     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2034     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2035     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2036     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2037     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2038     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2039     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2040     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2041     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2042     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2043     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2044     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2045     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2046     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2047     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2048     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2049     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2050     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2051     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2052     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2053     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2054     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2055 
2056     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2057     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2058     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2059     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2060     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2061     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2062     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2063     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2064     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2065     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2066     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2067     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2068     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2069     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2070     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2071     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2072     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2073     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2074     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2075     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2076     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2077     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2078     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2079     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2080     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2081     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2082     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2083     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2084     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2085 
2086     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2087     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2088     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2089     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2090     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2091     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2092     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2093     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2094     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2095     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2096     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2097     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2098     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2099     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2100     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2101     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2102     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2103     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2104     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2105     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2106     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2107     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2108     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2109     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2110     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2111     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2112     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2113     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2114     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2115 
2116     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2117     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2118     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2119     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2120     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2121     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2122     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2123     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2124     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2125     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2126     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2127     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2128     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2129     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2130     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2131     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2132     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2133     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2134     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2135     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2136     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2137     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2138     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2139     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2140     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2141     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2142     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2143     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2144     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2145 #endif /* !CONFIG_USER_ONLY */
2146 };
2147