1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { 43 return RISCV_EXCP_NONE; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return RISCV_EXCP_NONE; 50 } 51 52 static RISCVException vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa_ext & RVV) { 55 return RISCV_EXCP_NONE; 56 } 57 return RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static RISCVException ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, COUNTEREN_CY) && 75 get_field(env->mcounteren, COUNTEREN_CY)) { 76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, COUNTEREN_TM) && 81 get_field(env->mcounteren, COUNTEREN_TM)) { 82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, COUNTEREN_IR) && 87 get_field(env->mcounteren, COUNTEREN_IR)) { 88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_mxl(env) == MXL_RV32) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, COUNTEREN_CY) && 102 get_field(env->mcounteren, COUNTEREN_CY)) { 103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, COUNTEREN_TM) && 108 get_field(env->mcounteren, COUNTEREN_TM)) { 109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, COUNTEREN_IR) && 114 get_field(env->mcounteren, COUNTEREN_IR)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return RISCV_EXCP_NONE; 129 } 130 131 static RISCVException ctr32(CPURISCVState *env, int csrno) 132 { 133 if (riscv_cpu_mxl(env) != MXL_RV32) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static RISCVException any(CPURISCVState *env, int csrno) 142 { 143 return RISCV_EXCP_NONE; 144 } 145 146 static RISCVException any32(CPURISCVState *env, int csrno) 147 { 148 if (riscv_cpu_mxl(env) != MXL_RV32) { 149 return RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static RISCVException smode(CPURISCVState *env, int csrno) 157 { 158 if (riscv_has_ext(env, RVS)) { 159 return RISCV_EXCP_NONE; 160 } 161 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 static RISCVException hmode(CPURISCVState *env, int csrno) 166 { 167 if (riscv_has_ext(env, RVS) && 168 riscv_has_ext(env, RVH)) { 169 /* Hypervisor extension is supported */ 170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 171 env->priv == PRV_M) { 172 return RISCV_EXCP_NONE; 173 } else { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 } 177 178 return RISCV_EXCP_ILLEGAL_INST; 179 } 180 181 static RISCVException hmode32(CPURISCVState *env, int csrno) 182 { 183 if (riscv_cpu_mxl(env) != MXL_RV32) { 184 if (riscv_cpu_virt_enabled(env)) { 185 return RISCV_EXCP_ILLEGAL_INST; 186 } else { 187 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 188 } 189 } 190 191 return hmode(env, csrno); 192 193 } 194 195 /* Checks if PointerMasking registers could be accessed */ 196 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 197 { 198 /* Check if j-ext is present */ 199 if (riscv_has_ext(env, RVJ)) { 200 return RISCV_EXCP_NONE; 201 } 202 return RISCV_EXCP_ILLEGAL_INST; 203 } 204 205 static RISCVException pmp(CPURISCVState *env, int csrno) 206 { 207 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 208 return RISCV_EXCP_NONE; 209 } 210 211 return RISCV_EXCP_ILLEGAL_INST; 212 } 213 214 static RISCVException epmp(CPURISCVState *env, int csrno) 215 { 216 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 217 return RISCV_EXCP_NONE; 218 } 219 220 return RISCV_EXCP_ILLEGAL_INST; 221 } 222 #endif 223 224 /* User Floating-Point CSRs */ 225 static RISCVException read_fflags(CPURISCVState *env, int csrno, 226 target_ulong *val) 227 { 228 *val = riscv_cpu_get_fflags(env); 229 return RISCV_EXCP_NONE; 230 } 231 232 static RISCVException write_fflags(CPURISCVState *env, int csrno, 233 target_ulong val) 234 { 235 #if !defined(CONFIG_USER_ONLY) 236 env->mstatus |= MSTATUS_FS; 237 #endif 238 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 239 return RISCV_EXCP_NONE; 240 } 241 242 static RISCVException read_frm(CPURISCVState *env, int csrno, 243 target_ulong *val) 244 { 245 *val = env->frm; 246 return RISCV_EXCP_NONE; 247 } 248 249 static RISCVException write_frm(CPURISCVState *env, int csrno, 250 target_ulong val) 251 { 252 #if !defined(CONFIG_USER_ONLY) 253 env->mstatus |= MSTATUS_FS; 254 #endif 255 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 256 return RISCV_EXCP_NONE; 257 } 258 259 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 260 target_ulong *val) 261 { 262 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 263 | (env->frm << FSR_RD_SHIFT); 264 if (vs(env, csrno) >= 0) { 265 *val |= (env->vxrm << FSR_VXRM_SHIFT) 266 | (env->vxsat << FSR_VXSAT_SHIFT); 267 } 268 return RISCV_EXCP_NONE; 269 } 270 271 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 272 target_ulong val) 273 { 274 #if !defined(CONFIG_USER_ONLY) 275 env->mstatus |= MSTATUS_FS; 276 env->mstatus |= MSTATUS_VS; 277 #endif 278 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 279 if (vs(env, csrno) >= 0) { 280 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 281 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 282 } 283 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 284 return RISCV_EXCP_NONE; 285 } 286 287 static RISCVException read_vtype(CPURISCVState *env, int csrno, 288 target_ulong *val) 289 { 290 *val = env->vtype; 291 return RISCV_EXCP_NONE; 292 } 293 294 static RISCVException read_vl(CPURISCVState *env, int csrno, 295 target_ulong *val) 296 { 297 *val = env->vl; 298 return RISCV_EXCP_NONE; 299 } 300 301 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 302 target_ulong *val) 303 { 304 *val = env->vxrm; 305 return RISCV_EXCP_NONE; 306 } 307 308 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 309 target_ulong val) 310 { 311 #if !defined(CONFIG_USER_ONLY) 312 env->mstatus |= MSTATUS_VS; 313 #endif 314 env->vxrm = val; 315 return RISCV_EXCP_NONE; 316 } 317 318 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 319 target_ulong *val) 320 { 321 *val = env->vxsat; 322 return RISCV_EXCP_NONE; 323 } 324 325 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 326 target_ulong val) 327 { 328 #if !defined(CONFIG_USER_ONLY) 329 env->mstatus |= MSTATUS_VS; 330 #endif 331 env->vxsat = val; 332 return RISCV_EXCP_NONE; 333 } 334 335 static RISCVException read_vstart(CPURISCVState *env, int csrno, 336 target_ulong *val) 337 { 338 *val = env->vstart; 339 return RISCV_EXCP_NONE; 340 } 341 342 static RISCVException write_vstart(CPURISCVState *env, int csrno, 343 target_ulong val) 344 { 345 #if !defined(CONFIG_USER_ONLY) 346 env->mstatus |= MSTATUS_VS; 347 #endif 348 env->vstart = val; 349 return RISCV_EXCP_NONE; 350 } 351 352 /* User Timers and Counters */ 353 static RISCVException read_instret(CPURISCVState *env, int csrno, 354 target_ulong *val) 355 { 356 #if !defined(CONFIG_USER_ONLY) 357 if (icount_enabled()) { 358 *val = icount_get(); 359 } else { 360 *val = cpu_get_host_ticks(); 361 } 362 #else 363 *val = cpu_get_host_ticks(); 364 #endif 365 return RISCV_EXCP_NONE; 366 } 367 368 static RISCVException read_instreth(CPURISCVState *env, int csrno, 369 target_ulong *val) 370 { 371 #if !defined(CONFIG_USER_ONLY) 372 if (icount_enabled()) { 373 *val = icount_get() >> 32; 374 } else { 375 *val = cpu_get_host_ticks() >> 32; 376 } 377 #else 378 *val = cpu_get_host_ticks() >> 32; 379 #endif 380 return RISCV_EXCP_NONE; 381 } 382 383 #if defined(CONFIG_USER_ONLY) 384 static RISCVException read_time(CPURISCVState *env, int csrno, 385 target_ulong *val) 386 { 387 *val = cpu_get_host_ticks(); 388 return RISCV_EXCP_NONE; 389 } 390 391 static RISCVException read_timeh(CPURISCVState *env, int csrno, 392 target_ulong *val) 393 { 394 *val = cpu_get_host_ticks() >> 32; 395 return RISCV_EXCP_NONE; 396 } 397 398 #else /* CONFIG_USER_ONLY */ 399 400 static RISCVException read_time(CPURISCVState *env, int csrno, 401 target_ulong *val) 402 { 403 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 404 405 if (!env->rdtime_fn) { 406 return RISCV_EXCP_ILLEGAL_INST; 407 } 408 409 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 410 return RISCV_EXCP_NONE; 411 } 412 413 static RISCVException read_timeh(CPURISCVState *env, int csrno, 414 target_ulong *val) 415 { 416 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 417 418 if (!env->rdtime_fn) { 419 return RISCV_EXCP_ILLEGAL_INST; 420 } 421 422 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 423 return RISCV_EXCP_NONE; 424 } 425 426 /* Machine constants */ 427 428 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 429 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 430 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 431 432 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 433 VS_MODE_INTERRUPTS; 434 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; 435 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 436 VS_MODE_INTERRUPTS; 437 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 438 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 439 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 440 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 441 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 442 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 443 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 444 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 445 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 446 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 447 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 448 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 449 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 450 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 451 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 452 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 453 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 454 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 455 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 456 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 457 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 458 (1ULL << (RISCV_EXCP_VS_ECALL)) | 459 (1ULL << (RISCV_EXCP_M_ECALL)) | 460 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 461 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 462 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 463 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 464 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 465 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 466 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 467 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 468 static const target_ulong hip_writable_mask = MIP_VSSIP; 469 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 470 static const target_ulong vsip_writable_mask = MIP_VSSIP; 471 472 static const char valid_vm_1_10_32[16] = { 473 [VM_1_10_MBARE] = 1, 474 [VM_1_10_SV32] = 1 475 }; 476 477 static const char valid_vm_1_10_64[16] = { 478 [VM_1_10_MBARE] = 1, 479 [VM_1_10_SV39] = 1, 480 [VM_1_10_SV48] = 1, 481 [VM_1_10_SV57] = 1 482 }; 483 484 /* Machine Information Registers */ 485 static RISCVException read_zero(CPURISCVState *env, int csrno, 486 target_ulong *val) 487 { 488 *val = 0; 489 return RISCV_EXCP_NONE; 490 } 491 492 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 493 target_ulong *val) 494 { 495 *val = env->mhartid; 496 return RISCV_EXCP_NONE; 497 } 498 499 /* Machine Trap Setup */ 500 501 /* We do not store SD explicitly, only compute it on demand. */ 502 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 503 { 504 if ((status & MSTATUS_FS) == MSTATUS_FS || 505 (status & MSTATUS_VS) == MSTATUS_VS || 506 (status & MSTATUS_XS) == MSTATUS_XS) { 507 switch (xl) { 508 case MXL_RV32: 509 return status | MSTATUS32_SD; 510 case MXL_RV64: 511 return status | MSTATUS64_SD; 512 default: 513 g_assert_not_reached(); 514 } 515 } 516 return status; 517 } 518 519 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 520 target_ulong *val) 521 { 522 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 523 return RISCV_EXCP_NONE; 524 } 525 526 static int validate_vm(CPURISCVState *env, target_ulong vm) 527 { 528 if (riscv_cpu_mxl(env) == MXL_RV32) { 529 return valid_vm_1_10_32[vm & 0xf]; 530 } else { 531 return valid_vm_1_10_64[vm & 0xf]; 532 } 533 } 534 535 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 536 target_ulong val) 537 { 538 uint64_t mstatus = env->mstatus; 539 uint64_t mask = 0; 540 541 /* flush tlb on mstatus fields that affect VM */ 542 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 543 MSTATUS_MPRV | MSTATUS_SUM)) { 544 tlb_flush(env_cpu(env)); 545 } 546 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 547 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 548 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 549 MSTATUS_TW | MSTATUS_VS; 550 551 if (riscv_cpu_mxl(env) != MXL_RV32) { 552 /* 553 * RV32: MPV and GVA are not in mstatus. The current plan is to 554 * add them to mstatush. For now, we just don't support it. 555 */ 556 mask |= MSTATUS_MPV | MSTATUS_GVA; 557 } 558 559 mstatus = (mstatus & ~mask) | (val & mask); 560 561 if (riscv_cpu_mxl(env) == MXL_RV64) { 562 /* SXL and UXL fields are for now read only */ 563 mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); 564 mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); 565 } 566 env->mstatus = mstatus; 567 568 return RISCV_EXCP_NONE; 569 } 570 571 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 572 target_ulong *val) 573 { 574 *val = env->mstatus >> 32; 575 return RISCV_EXCP_NONE; 576 } 577 578 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 579 target_ulong val) 580 { 581 uint64_t valh = (uint64_t)val << 32; 582 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 583 584 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 585 tlb_flush(env_cpu(env)); 586 } 587 588 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 589 590 return RISCV_EXCP_NONE; 591 } 592 593 static RISCVException read_misa(CPURISCVState *env, int csrno, 594 target_ulong *val) 595 { 596 target_ulong misa; 597 598 switch (env->misa_mxl) { 599 case MXL_RV32: 600 misa = (target_ulong)MXL_RV32 << 30; 601 break; 602 #ifdef TARGET_RISCV64 603 case MXL_RV64: 604 misa = (target_ulong)MXL_RV64 << 62; 605 break; 606 #endif 607 default: 608 g_assert_not_reached(); 609 } 610 611 *val = misa | env->misa_ext; 612 return RISCV_EXCP_NONE; 613 } 614 615 static RISCVException write_misa(CPURISCVState *env, int csrno, 616 target_ulong val) 617 { 618 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 619 /* drop write to misa */ 620 return RISCV_EXCP_NONE; 621 } 622 623 /* 'I' or 'E' must be present */ 624 if (!(val & (RVI | RVE))) { 625 /* It is not, drop write to misa */ 626 return RISCV_EXCP_NONE; 627 } 628 629 /* 'E' excludes all other extensions */ 630 if (val & RVE) { 631 /* when we support 'E' we can do "val = RVE;" however 632 * for now we just drop writes if 'E' is present. 633 */ 634 return RISCV_EXCP_NONE; 635 } 636 637 /* 638 * misa.MXL writes are not supported by QEMU. 639 * Drop writes to those bits. 640 */ 641 642 /* Mask extensions that are not supported by this hart */ 643 val &= env->misa_ext_mask; 644 645 /* Mask extensions that are not supported by QEMU */ 646 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 647 648 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 649 if ((val & RVD) && !(val & RVF)) { 650 val &= ~RVD; 651 } 652 653 /* Suppress 'C' if next instruction is not aligned 654 * TODO: this should check next_pc 655 */ 656 if ((val & RVC) && (GETPC() & ~3) != 0) { 657 val &= ~RVC; 658 } 659 660 /* If nothing changed, do nothing. */ 661 if (val == env->misa_ext) { 662 return RISCV_EXCP_NONE; 663 } 664 665 /* flush translation cache */ 666 tb_flush(env_cpu(env)); 667 env->misa_ext = val; 668 return RISCV_EXCP_NONE; 669 } 670 671 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 672 target_ulong *val) 673 { 674 *val = env->medeleg; 675 return RISCV_EXCP_NONE; 676 } 677 678 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 679 target_ulong val) 680 { 681 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 682 return RISCV_EXCP_NONE; 683 } 684 685 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 686 target_ulong *val) 687 { 688 *val = env->mideleg; 689 return RISCV_EXCP_NONE; 690 } 691 692 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 693 target_ulong val) 694 { 695 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 696 if (riscv_has_ext(env, RVH)) { 697 env->mideleg |= VS_MODE_INTERRUPTS; 698 } 699 return RISCV_EXCP_NONE; 700 } 701 702 static RISCVException read_mie(CPURISCVState *env, int csrno, 703 target_ulong *val) 704 { 705 *val = env->mie; 706 return RISCV_EXCP_NONE; 707 } 708 709 static RISCVException write_mie(CPURISCVState *env, int csrno, 710 target_ulong val) 711 { 712 env->mie = (env->mie & ~all_ints) | (val & all_ints); 713 return RISCV_EXCP_NONE; 714 } 715 716 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 717 target_ulong *val) 718 { 719 *val = env->mtvec; 720 return RISCV_EXCP_NONE; 721 } 722 723 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 724 target_ulong val) 725 { 726 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 727 if ((val & 3) < 2) { 728 env->mtvec = val; 729 } else { 730 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 731 } 732 return RISCV_EXCP_NONE; 733 } 734 735 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 736 target_ulong *val) 737 { 738 *val = env->mcounteren; 739 return RISCV_EXCP_NONE; 740 } 741 742 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 743 target_ulong val) 744 { 745 env->mcounteren = val; 746 return RISCV_EXCP_NONE; 747 } 748 749 /* Machine Trap Handling */ 750 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 751 target_ulong *val) 752 { 753 *val = env->mscratch; 754 return RISCV_EXCP_NONE; 755 } 756 757 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 758 target_ulong val) 759 { 760 env->mscratch = val; 761 return RISCV_EXCP_NONE; 762 } 763 764 static RISCVException read_mepc(CPURISCVState *env, int csrno, 765 target_ulong *val) 766 { 767 *val = env->mepc; 768 return RISCV_EXCP_NONE; 769 } 770 771 static RISCVException write_mepc(CPURISCVState *env, int csrno, 772 target_ulong val) 773 { 774 env->mepc = val; 775 return RISCV_EXCP_NONE; 776 } 777 778 static RISCVException read_mcause(CPURISCVState *env, int csrno, 779 target_ulong *val) 780 { 781 *val = env->mcause; 782 return RISCV_EXCP_NONE; 783 } 784 785 static RISCVException write_mcause(CPURISCVState *env, int csrno, 786 target_ulong val) 787 { 788 env->mcause = val; 789 return RISCV_EXCP_NONE; 790 } 791 792 static RISCVException read_mtval(CPURISCVState *env, int csrno, 793 target_ulong *val) 794 { 795 *val = env->mtval; 796 return RISCV_EXCP_NONE; 797 } 798 799 static RISCVException write_mtval(CPURISCVState *env, int csrno, 800 target_ulong val) 801 { 802 env->mtval = val; 803 return RISCV_EXCP_NONE; 804 } 805 806 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 807 target_ulong *ret_value, 808 target_ulong new_value, target_ulong write_mask) 809 { 810 RISCVCPU *cpu = env_archcpu(env); 811 /* Allow software control of delegable interrupts not claimed by hardware */ 812 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 813 uint32_t old_mip; 814 815 if (mask) { 816 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 817 } else { 818 old_mip = env->mip; 819 } 820 821 if (ret_value) { 822 *ret_value = old_mip; 823 } 824 825 return RISCV_EXCP_NONE; 826 } 827 828 /* Supervisor Trap Setup */ 829 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 830 target_ulong *val) 831 { 832 target_ulong mask = (sstatus_v1_10_mask); 833 834 /* TODO: Use SXL not MXL. */ 835 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 836 return RISCV_EXCP_NONE; 837 } 838 839 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 840 target_ulong val) 841 { 842 target_ulong mask = (sstatus_v1_10_mask); 843 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 844 return write_mstatus(env, CSR_MSTATUS, newval); 845 } 846 847 static RISCVException read_vsie(CPURISCVState *env, int csrno, 848 target_ulong *val) 849 { 850 /* Shift the VS bits to their S bit location in vsie */ 851 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 852 return RISCV_EXCP_NONE; 853 } 854 855 static RISCVException read_sie(CPURISCVState *env, int csrno, 856 target_ulong *val) 857 { 858 if (riscv_cpu_virt_enabled(env)) { 859 read_vsie(env, CSR_VSIE, val); 860 } else { 861 *val = env->mie & env->mideleg; 862 } 863 return RISCV_EXCP_NONE; 864 } 865 866 static RISCVException write_vsie(CPURISCVState *env, int csrno, 867 target_ulong val) 868 { 869 /* Shift the S bits to their VS bit location in mie */ 870 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 871 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 872 return write_mie(env, CSR_MIE, newval); 873 } 874 875 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 876 { 877 if (riscv_cpu_virt_enabled(env)) { 878 write_vsie(env, CSR_VSIE, val); 879 } else { 880 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 881 (val & S_MODE_INTERRUPTS); 882 write_mie(env, CSR_MIE, newval); 883 } 884 885 return RISCV_EXCP_NONE; 886 } 887 888 static RISCVException read_stvec(CPURISCVState *env, int csrno, 889 target_ulong *val) 890 { 891 *val = env->stvec; 892 return RISCV_EXCP_NONE; 893 } 894 895 static RISCVException write_stvec(CPURISCVState *env, int csrno, 896 target_ulong val) 897 { 898 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 899 if ((val & 3) < 2) { 900 env->stvec = val; 901 } else { 902 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 903 } 904 return RISCV_EXCP_NONE; 905 } 906 907 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 908 target_ulong *val) 909 { 910 *val = env->scounteren; 911 return RISCV_EXCP_NONE; 912 } 913 914 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 915 target_ulong val) 916 { 917 env->scounteren = val; 918 return RISCV_EXCP_NONE; 919 } 920 921 /* Supervisor Trap Handling */ 922 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 923 target_ulong *val) 924 { 925 *val = env->sscratch; 926 return RISCV_EXCP_NONE; 927 } 928 929 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 930 target_ulong val) 931 { 932 env->sscratch = val; 933 return RISCV_EXCP_NONE; 934 } 935 936 static RISCVException read_sepc(CPURISCVState *env, int csrno, 937 target_ulong *val) 938 { 939 *val = env->sepc; 940 return RISCV_EXCP_NONE; 941 } 942 943 static RISCVException write_sepc(CPURISCVState *env, int csrno, 944 target_ulong val) 945 { 946 env->sepc = val; 947 return RISCV_EXCP_NONE; 948 } 949 950 static RISCVException read_scause(CPURISCVState *env, int csrno, 951 target_ulong *val) 952 { 953 *val = env->scause; 954 return RISCV_EXCP_NONE; 955 } 956 957 static RISCVException write_scause(CPURISCVState *env, int csrno, 958 target_ulong val) 959 { 960 env->scause = val; 961 return RISCV_EXCP_NONE; 962 } 963 964 static RISCVException read_stval(CPURISCVState *env, int csrno, 965 target_ulong *val) 966 { 967 *val = env->stval; 968 return RISCV_EXCP_NONE; 969 } 970 971 static RISCVException write_stval(CPURISCVState *env, int csrno, 972 target_ulong val) 973 { 974 env->stval = val; 975 return RISCV_EXCP_NONE; 976 } 977 978 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 979 target_ulong *ret_value, 980 target_ulong new_value, target_ulong write_mask) 981 { 982 /* Shift the S bits to their VS bit location in mip */ 983 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 984 (write_mask << 1) & vsip_writable_mask & env->hideleg); 985 986 if (ret_value) { 987 *ret_value &= VS_MODE_INTERRUPTS; 988 /* Shift the VS bits to their S bit location in vsip */ 989 *ret_value >>= 1; 990 } 991 return ret; 992 } 993 994 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 995 target_ulong *ret_value, 996 target_ulong new_value, target_ulong write_mask) 997 { 998 int ret; 999 1000 if (riscv_cpu_virt_enabled(env)) { 1001 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 1002 } else { 1003 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 1004 write_mask & env->mideleg & sip_writable_mask); 1005 } 1006 1007 if (ret_value) { 1008 *ret_value &= env->mideleg; 1009 } 1010 return ret; 1011 } 1012 1013 /* Supervisor Protection and Translation */ 1014 static RISCVException read_satp(CPURISCVState *env, int csrno, 1015 target_ulong *val) 1016 { 1017 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1018 *val = 0; 1019 return RISCV_EXCP_NONE; 1020 } 1021 1022 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1023 return RISCV_EXCP_ILLEGAL_INST; 1024 } else { 1025 *val = env->satp; 1026 } 1027 1028 return RISCV_EXCP_NONE; 1029 } 1030 1031 static RISCVException write_satp(CPURISCVState *env, int csrno, 1032 target_ulong val) 1033 { 1034 target_ulong vm, mask, asid; 1035 1036 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1037 return RISCV_EXCP_NONE; 1038 } 1039 1040 if (riscv_cpu_mxl(env) == MXL_RV32) { 1041 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1042 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1043 asid = (val ^ env->satp) & SATP32_ASID; 1044 } else { 1045 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1046 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1047 asid = (val ^ env->satp) & SATP64_ASID; 1048 } 1049 1050 if (vm && mask) { 1051 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1052 return RISCV_EXCP_ILLEGAL_INST; 1053 } else { 1054 if (asid) { 1055 tlb_flush(env_cpu(env)); 1056 } 1057 env->satp = val; 1058 } 1059 } 1060 return RISCV_EXCP_NONE; 1061 } 1062 1063 /* Hypervisor Extensions */ 1064 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1065 target_ulong *val) 1066 { 1067 *val = env->hstatus; 1068 if (riscv_cpu_mxl(env) != MXL_RV32) { 1069 /* We only support 64-bit VSXL */ 1070 *val = set_field(*val, HSTATUS_VSXL, 2); 1071 } 1072 /* We only support little endian */ 1073 *val = set_field(*val, HSTATUS_VSBE, 0); 1074 return RISCV_EXCP_NONE; 1075 } 1076 1077 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1078 target_ulong val) 1079 { 1080 env->hstatus = val; 1081 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 1082 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1083 } 1084 if (get_field(val, HSTATUS_VSBE) != 0) { 1085 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1086 } 1087 return RISCV_EXCP_NONE; 1088 } 1089 1090 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1091 target_ulong *val) 1092 { 1093 *val = env->hedeleg; 1094 return RISCV_EXCP_NONE; 1095 } 1096 1097 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1098 target_ulong val) 1099 { 1100 env->hedeleg = val & vs_delegable_excps; 1101 return RISCV_EXCP_NONE; 1102 } 1103 1104 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1105 target_ulong *val) 1106 { 1107 *val = env->hideleg; 1108 return RISCV_EXCP_NONE; 1109 } 1110 1111 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1112 target_ulong val) 1113 { 1114 env->hideleg = val & vs_delegable_ints; 1115 return RISCV_EXCP_NONE; 1116 } 1117 1118 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1119 target_ulong *ret_value, 1120 target_ulong new_value, target_ulong write_mask) 1121 { 1122 int ret = rmw_mip(env, 0, ret_value, new_value, 1123 write_mask & hvip_writable_mask); 1124 1125 if (ret_value) { 1126 *ret_value &= hvip_writable_mask; 1127 } 1128 return ret; 1129 } 1130 1131 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1132 target_ulong *ret_value, 1133 target_ulong new_value, target_ulong write_mask) 1134 { 1135 int ret = rmw_mip(env, 0, ret_value, new_value, 1136 write_mask & hip_writable_mask); 1137 1138 if (ret_value) { 1139 *ret_value &= hip_writable_mask; 1140 } 1141 return ret; 1142 } 1143 1144 static RISCVException read_hie(CPURISCVState *env, int csrno, 1145 target_ulong *val) 1146 { 1147 *val = env->mie & VS_MODE_INTERRUPTS; 1148 return RISCV_EXCP_NONE; 1149 } 1150 1151 static RISCVException write_hie(CPURISCVState *env, int csrno, 1152 target_ulong val) 1153 { 1154 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1155 return write_mie(env, CSR_MIE, newval); 1156 } 1157 1158 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1159 target_ulong *val) 1160 { 1161 *val = env->hcounteren; 1162 return RISCV_EXCP_NONE; 1163 } 1164 1165 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1166 target_ulong val) 1167 { 1168 env->hcounteren = val; 1169 return RISCV_EXCP_NONE; 1170 } 1171 1172 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1173 target_ulong val) 1174 { 1175 if (val) { 1176 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1177 } 1178 return RISCV_EXCP_NONE; 1179 } 1180 1181 static RISCVException read_htval(CPURISCVState *env, int csrno, 1182 target_ulong *val) 1183 { 1184 *val = env->htval; 1185 return RISCV_EXCP_NONE; 1186 } 1187 1188 static RISCVException write_htval(CPURISCVState *env, int csrno, 1189 target_ulong val) 1190 { 1191 env->htval = val; 1192 return RISCV_EXCP_NONE; 1193 } 1194 1195 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1196 target_ulong *val) 1197 { 1198 *val = env->htinst; 1199 return RISCV_EXCP_NONE; 1200 } 1201 1202 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1203 target_ulong val) 1204 { 1205 return RISCV_EXCP_NONE; 1206 } 1207 1208 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1209 target_ulong val) 1210 { 1211 if (val) { 1212 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1213 } 1214 return RISCV_EXCP_NONE; 1215 } 1216 1217 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1218 target_ulong *val) 1219 { 1220 *val = env->hgatp; 1221 return RISCV_EXCP_NONE; 1222 } 1223 1224 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1225 target_ulong val) 1226 { 1227 env->hgatp = val; 1228 return RISCV_EXCP_NONE; 1229 } 1230 1231 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1232 target_ulong *val) 1233 { 1234 if (!env->rdtime_fn) { 1235 return RISCV_EXCP_ILLEGAL_INST; 1236 } 1237 1238 *val = env->htimedelta; 1239 return RISCV_EXCP_NONE; 1240 } 1241 1242 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1243 target_ulong val) 1244 { 1245 if (!env->rdtime_fn) { 1246 return RISCV_EXCP_ILLEGAL_INST; 1247 } 1248 1249 if (riscv_cpu_mxl(env) == MXL_RV32) { 1250 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1251 } else { 1252 env->htimedelta = val; 1253 } 1254 return RISCV_EXCP_NONE; 1255 } 1256 1257 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1258 target_ulong *val) 1259 { 1260 if (!env->rdtime_fn) { 1261 return RISCV_EXCP_ILLEGAL_INST; 1262 } 1263 1264 *val = env->htimedelta >> 32; 1265 return RISCV_EXCP_NONE; 1266 } 1267 1268 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1269 target_ulong val) 1270 { 1271 if (!env->rdtime_fn) { 1272 return RISCV_EXCP_ILLEGAL_INST; 1273 } 1274 1275 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1276 return RISCV_EXCP_NONE; 1277 } 1278 1279 /* Virtual CSR Registers */ 1280 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1281 target_ulong *val) 1282 { 1283 *val = env->vsstatus; 1284 return RISCV_EXCP_NONE; 1285 } 1286 1287 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1288 target_ulong val) 1289 { 1290 uint64_t mask = (target_ulong)-1; 1291 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1292 return RISCV_EXCP_NONE; 1293 } 1294 1295 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1296 { 1297 *val = env->vstvec; 1298 return RISCV_EXCP_NONE; 1299 } 1300 1301 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1302 target_ulong val) 1303 { 1304 env->vstvec = val; 1305 return RISCV_EXCP_NONE; 1306 } 1307 1308 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1309 target_ulong *val) 1310 { 1311 *val = env->vsscratch; 1312 return RISCV_EXCP_NONE; 1313 } 1314 1315 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1316 target_ulong val) 1317 { 1318 env->vsscratch = val; 1319 return RISCV_EXCP_NONE; 1320 } 1321 1322 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1323 target_ulong *val) 1324 { 1325 *val = env->vsepc; 1326 return RISCV_EXCP_NONE; 1327 } 1328 1329 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1330 target_ulong val) 1331 { 1332 env->vsepc = val; 1333 return RISCV_EXCP_NONE; 1334 } 1335 1336 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1337 target_ulong *val) 1338 { 1339 *val = env->vscause; 1340 return RISCV_EXCP_NONE; 1341 } 1342 1343 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1344 target_ulong val) 1345 { 1346 env->vscause = val; 1347 return RISCV_EXCP_NONE; 1348 } 1349 1350 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1351 target_ulong *val) 1352 { 1353 *val = env->vstval; 1354 return RISCV_EXCP_NONE; 1355 } 1356 1357 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1358 target_ulong val) 1359 { 1360 env->vstval = val; 1361 return RISCV_EXCP_NONE; 1362 } 1363 1364 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1365 target_ulong *val) 1366 { 1367 *val = env->vsatp; 1368 return RISCV_EXCP_NONE; 1369 } 1370 1371 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1372 target_ulong val) 1373 { 1374 env->vsatp = val; 1375 return RISCV_EXCP_NONE; 1376 } 1377 1378 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1379 target_ulong *val) 1380 { 1381 *val = env->mtval2; 1382 return RISCV_EXCP_NONE; 1383 } 1384 1385 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1386 target_ulong val) 1387 { 1388 env->mtval2 = val; 1389 return RISCV_EXCP_NONE; 1390 } 1391 1392 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1393 target_ulong *val) 1394 { 1395 *val = env->mtinst; 1396 return RISCV_EXCP_NONE; 1397 } 1398 1399 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1400 target_ulong val) 1401 { 1402 env->mtinst = val; 1403 return RISCV_EXCP_NONE; 1404 } 1405 1406 /* Physical Memory Protection */ 1407 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1408 target_ulong *val) 1409 { 1410 *val = mseccfg_csr_read(env); 1411 return RISCV_EXCP_NONE; 1412 } 1413 1414 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1415 target_ulong val) 1416 { 1417 mseccfg_csr_write(env, val); 1418 return RISCV_EXCP_NONE; 1419 } 1420 1421 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1422 target_ulong *val) 1423 { 1424 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1425 return RISCV_EXCP_NONE; 1426 } 1427 1428 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1429 target_ulong val) 1430 { 1431 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1432 return RISCV_EXCP_NONE; 1433 } 1434 1435 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1436 target_ulong *val) 1437 { 1438 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1439 return RISCV_EXCP_NONE; 1440 } 1441 1442 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1443 target_ulong val) 1444 { 1445 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1446 return RISCV_EXCP_NONE; 1447 } 1448 1449 /* 1450 * Functions to access Pointer Masking feature registers 1451 * We have to check if current priv lvl could modify 1452 * csr in given mode 1453 */ 1454 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 1455 { 1456 int csr_priv = get_field(csrno, 0x300); 1457 int pm_current; 1458 1459 /* 1460 * If priv lvls differ that means we're accessing csr from higher priv lvl, 1461 * so allow the access 1462 */ 1463 if (env->priv != csr_priv) { 1464 return false; 1465 } 1466 switch (env->priv) { 1467 case PRV_M: 1468 pm_current = get_field(env->mmte, M_PM_CURRENT); 1469 break; 1470 case PRV_S: 1471 pm_current = get_field(env->mmte, S_PM_CURRENT); 1472 break; 1473 case PRV_U: 1474 pm_current = get_field(env->mmte, U_PM_CURRENT); 1475 break; 1476 default: 1477 g_assert_not_reached(); 1478 } 1479 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 1480 return !pm_current; 1481 } 1482 1483 static RISCVException read_mmte(CPURISCVState *env, int csrno, 1484 target_ulong *val) 1485 { 1486 *val = env->mmte & MMTE_MASK; 1487 return RISCV_EXCP_NONE; 1488 } 1489 1490 static RISCVException write_mmte(CPURISCVState *env, int csrno, 1491 target_ulong val) 1492 { 1493 uint64_t mstatus; 1494 target_ulong wpri_val = val & MMTE_MASK; 1495 1496 if (val != wpri_val) { 1497 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1498 "MMTE: WPRI violation written 0x", val, 1499 "vs expected 0x", wpri_val); 1500 } 1501 /* for machine mode pm.current is hardwired to 1 */ 1502 wpri_val |= MMTE_M_PM_CURRENT; 1503 1504 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 1505 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 1506 env->mmte = wpri_val | PM_EXT_DIRTY; 1507 1508 /* Set XS and SD bits, since PM CSRs are dirty */ 1509 mstatus = env->mstatus | MSTATUS_XS; 1510 write_mstatus(env, csrno, mstatus); 1511 return RISCV_EXCP_NONE; 1512 } 1513 1514 static RISCVException read_smte(CPURISCVState *env, int csrno, 1515 target_ulong *val) 1516 { 1517 *val = env->mmte & SMTE_MASK; 1518 return RISCV_EXCP_NONE; 1519 } 1520 1521 static RISCVException write_smte(CPURISCVState *env, int csrno, 1522 target_ulong val) 1523 { 1524 target_ulong wpri_val = val & SMTE_MASK; 1525 1526 if (val != wpri_val) { 1527 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1528 "SMTE: WPRI violation written 0x", val, 1529 "vs expected 0x", wpri_val); 1530 } 1531 1532 /* if pm.current==0 we can't modify current PM CSRs */ 1533 if (check_pm_current_disabled(env, csrno)) { 1534 return RISCV_EXCP_NONE; 1535 } 1536 1537 wpri_val |= (env->mmte & ~SMTE_MASK); 1538 write_mmte(env, csrno, wpri_val); 1539 return RISCV_EXCP_NONE; 1540 } 1541 1542 static RISCVException read_umte(CPURISCVState *env, int csrno, 1543 target_ulong *val) 1544 { 1545 *val = env->mmte & UMTE_MASK; 1546 return RISCV_EXCP_NONE; 1547 } 1548 1549 static RISCVException write_umte(CPURISCVState *env, int csrno, 1550 target_ulong val) 1551 { 1552 target_ulong wpri_val = val & UMTE_MASK; 1553 1554 if (val != wpri_val) { 1555 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1556 "UMTE: WPRI violation written 0x", val, 1557 "vs expected 0x", wpri_val); 1558 } 1559 1560 if (check_pm_current_disabled(env, csrno)) { 1561 return RISCV_EXCP_NONE; 1562 } 1563 1564 wpri_val |= (env->mmte & ~UMTE_MASK); 1565 write_mmte(env, csrno, wpri_val); 1566 return RISCV_EXCP_NONE; 1567 } 1568 1569 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 1570 target_ulong *val) 1571 { 1572 *val = env->mpmmask; 1573 return RISCV_EXCP_NONE; 1574 } 1575 1576 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 1577 target_ulong val) 1578 { 1579 uint64_t mstatus; 1580 1581 env->mpmmask = val; 1582 env->mmte |= PM_EXT_DIRTY; 1583 1584 /* Set XS and SD bits, since PM CSRs are dirty */ 1585 mstatus = env->mstatus | MSTATUS_XS; 1586 write_mstatus(env, csrno, mstatus); 1587 return RISCV_EXCP_NONE; 1588 } 1589 1590 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 1591 target_ulong *val) 1592 { 1593 *val = env->spmmask; 1594 return RISCV_EXCP_NONE; 1595 } 1596 1597 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 1598 target_ulong val) 1599 { 1600 uint64_t mstatus; 1601 1602 /* if pm.current==0 we can't modify current PM CSRs */ 1603 if (check_pm_current_disabled(env, csrno)) { 1604 return RISCV_EXCP_NONE; 1605 } 1606 env->spmmask = val; 1607 env->mmte |= PM_EXT_DIRTY; 1608 1609 /* Set XS and SD bits, since PM CSRs are dirty */ 1610 mstatus = env->mstatus | MSTATUS_XS; 1611 write_mstatus(env, csrno, mstatus); 1612 return RISCV_EXCP_NONE; 1613 } 1614 1615 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 1616 target_ulong *val) 1617 { 1618 *val = env->upmmask; 1619 return RISCV_EXCP_NONE; 1620 } 1621 1622 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 1623 target_ulong val) 1624 { 1625 uint64_t mstatus; 1626 1627 /* if pm.current==0 we can't modify current PM CSRs */ 1628 if (check_pm_current_disabled(env, csrno)) { 1629 return RISCV_EXCP_NONE; 1630 } 1631 env->upmmask = val; 1632 env->mmte |= PM_EXT_DIRTY; 1633 1634 /* Set XS and SD bits, since PM CSRs are dirty */ 1635 mstatus = env->mstatus | MSTATUS_XS; 1636 write_mstatus(env, csrno, mstatus); 1637 return RISCV_EXCP_NONE; 1638 } 1639 1640 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 1641 target_ulong *val) 1642 { 1643 *val = env->mpmbase; 1644 return RISCV_EXCP_NONE; 1645 } 1646 1647 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 1648 target_ulong val) 1649 { 1650 uint64_t mstatus; 1651 1652 env->mpmbase = val; 1653 env->mmte |= PM_EXT_DIRTY; 1654 1655 /* Set XS and SD bits, since PM CSRs are dirty */ 1656 mstatus = env->mstatus | MSTATUS_XS; 1657 write_mstatus(env, csrno, mstatus); 1658 return RISCV_EXCP_NONE; 1659 } 1660 1661 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 1662 target_ulong *val) 1663 { 1664 *val = env->spmbase; 1665 return RISCV_EXCP_NONE; 1666 } 1667 1668 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 1669 target_ulong val) 1670 { 1671 uint64_t mstatus; 1672 1673 /* if pm.current==0 we can't modify current PM CSRs */ 1674 if (check_pm_current_disabled(env, csrno)) { 1675 return RISCV_EXCP_NONE; 1676 } 1677 env->spmbase = val; 1678 env->mmte |= PM_EXT_DIRTY; 1679 1680 /* Set XS and SD bits, since PM CSRs are dirty */ 1681 mstatus = env->mstatus | MSTATUS_XS; 1682 write_mstatus(env, csrno, mstatus); 1683 return RISCV_EXCP_NONE; 1684 } 1685 1686 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 1687 target_ulong *val) 1688 { 1689 *val = env->upmbase; 1690 return RISCV_EXCP_NONE; 1691 } 1692 1693 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 1694 target_ulong val) 1695 { 1696 uint64_t mstatus; 1697 1698 /* if pm.current==0 we can't modify current PM CSRs */ 1699 if (check_pm_current_disabled(env, csrno)) { 1700 return RISCV_EXCP_NONE; 1701 } 1702 env->upmbase = val; 1703 env->mmte |= PM_EXT_DIRTY; 1704 1705 /* Set XS and SD bits, since PM CSRs are dirty */ 1706 mstatus = env->mstatus | MSTATUS_XS; 1707 write_mstatus(env, csrno, mstatus); 1708 return RISCV_EXCP_NONE; 1709 } 1710 1711 #endif 1712 1713 /* 1714 * riscv_csrrw - read and/or update control and status register 1715 * 1716 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1717 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1718 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1719 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1720 */ 1721 1722 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1723 target_ulong *ret_value, 1724 target_ulong new_value, target_ulong write_mask) 1725 { 1726 RISCVException ret; 1727 target_ulong old_value; 1728 RISCVCPU *cpu = env_archcpu(env); 1729 int read_only = get_field(csrno, 0xC00) == 3; 1730 1731 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 1732 #if !defined(CONFIG_USER_ONLY) 1733 int effective_priv = env->priv; 1734 1735 if (riscv_has_ext(env, RVH) && 1736 env->priv == PRV_S && 1737 !riscv_cpu_virt_enabled(env)) { 1738 /* 1739 * We are in S mode without virtualisation, therefore we are in HS Mode. 1740 * Add 1 to the effective privledge level to allow us to access the 1741 * Hypervisor CSRs. 1742 */ 1743 effective_priv++; 1744 } 1745 1746 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 1747 return RISCV_EXCP_ILLEGAL_INST; 1748 } 1749 #endif 1750 if (write_mask && read_only) { 1751 return RISCV_EXCP_ILLEGAL_INST; 1752 } 1753 1754 /* ensure the CSR extension is enabled. */ 1755 if (!cpu->cfg.ext_icsr) { 1756 return RISCV_EXCP_ILLEGAL_INST; 1757 } 1758 1759 /* check predicate */ 1760 if (!csr_ops[csrno].predicate) { 1761 return RISCV_EXCP_ILLEGAL_INST; 1762 } 1763 ret = csr_ops[csrno].predicate(env, csrno); 1764 if (ret != RISCV_EXCP_NONE) { 1765 return ret; 1766 } 1767 1768 /* execute combined read/write operation if it exists */ 1769 if (csr_ops[csrno].op) { 1770 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1771 } 1772 1773 /* if no accessor exists then return failure */ 1774 if (!csr_ops[csrno].read) { 1775 return RISCV_EXCP_ILLEGAL_INST; 1776 } 1777 /* read old value */ 1778 ret = csr_ops[csrno].read(env, csrno, &old_value); 1779 if (ret != RISCV_EXCP_NONE) { 1780 return ret; 1781 } 1782 1783 /* write value if writable and write mask set, otherwise drop writes */ 1784 if (write_mask) { 1785 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1786 if (csr_ops[csrno].write) { 1787 ret = csr_ops[csrno].write(env, csrno, new_value); 1788 if (ret != RISCV_EXCP_NONE) { 1789 return ret; 1790 } 1791 } 1792 } 1793 1794 /* return old value */ 1795 if (ret_value) { 1796 *ret_value = old_value; 1797 } 1798 1799 return RISCV_EXCP_NONE; 1800 } 1801 1802 /* 1803 * Debugger support. If not in user mode, set env->debugger before the 1804 * riscv_csrrw call and clear it after the call. 1805 */ 1806 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1807 target_ulong *ret_value, 1808 target_ulong new_value, 1809 target_ulong write_mask) 1810 { 1811 RISCVException ret; 1812 #if !defined(CONFIG_USER_ONLY) 1813 env->debugger = true; 1814 #endif 1815 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1816 #if !defined(CONFIG_USER_ONLY) 1817 env->debugger = false; 1818 #endif 1819 return ret; 1820 } 1821 1822 /* Control and Status Register function table */ 1823 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1824 /* User Floating-Point CSRs */ 1825 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1826 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1827 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1828 /* Vector CSRs */ 1829 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1830 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1831 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1832 [CSR_VL] = { "vl", vs, read_vl }, 1833 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1834 /* User Timers and Counters */ 1835 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1836 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1837 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1838 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1839 1840 /* 1841 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1842 * rdtime callback is not provided by machine/platform emulation. 1843 */ 1844 [CSR_TIME] = { "time", ctr, read_time }, 1845 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1846 1847 #if !defined(CONFIG_USER_ONLY) 1848 /* Machine Timers and Counters */ 1849 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1850 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1851 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1852 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1853 1854 /* Machine Information Registers */ 1855 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1856 [CSR_MARCHID] = { "marchid", any, read_zero }, 1857 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1858 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1859 1860 /* Machine Trap Setup */ 1861 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1862 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1863 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1864 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1865 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1866 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1867 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1868 1869 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1870 1871 /* Machine Trap Handling */ 1872 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1873 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1874 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1875 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1876 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1877 1878 /* Supervisor Trap Setup */ 1879 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1880 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1881 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1882 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1883 1884 /* Supervisor Trap Handling */ 1885 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1886 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1887 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1888 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1889 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1890 1891 /* Supervisor Protection and Translation */ 1892 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1893 1894 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1895 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1896 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1897 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1898 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1899 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1900 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1901 [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, 1902 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1903 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1904 [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, 1905 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1906 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1907 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1908 1909 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1910 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1911 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1912 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1913 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1914 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1915 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1916 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1917 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1918 1919 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1920 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1921 1922 /* Physical Memory Protection */ 1923 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1924 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1925 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1926 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1927 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1928 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1929 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1930 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1931 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1932 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1933 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1934 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1935 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1936 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1937 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1938 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1939 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1940 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1941 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1942 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1943 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1944 1945 /* User Pointer Masking */ 1946 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 1947 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 1948 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 1949 /* Machine Pointer Masking */ 1950 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 1951 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 1952 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 1953 /* Supervisor Pointer Masking */ 1954 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 1955 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 1956 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 1957 1958 /* Performance Counters */ 1959 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1960 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1961 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1962 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1963 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1964 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1965 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1966 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1967 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1968 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1969 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1970 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1971 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1972 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1973 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1974 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1975 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1976 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1977 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1978 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1979 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1980 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1981 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1982 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1983 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1984 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1985 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1986 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1987 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1988 1989 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1990 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1991 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1992 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1993 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1994 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1995 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1996 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1997 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1998 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1999 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 2000 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 2001 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 2002 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 2003 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 2004 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 2005 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 2006 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 2007 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 2008 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 2009 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 2010 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 2011 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 2012 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 2013 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 2014 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 2015 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 2016 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 2017 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 2018 2019 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 2020 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 2021 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 2022 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 2023 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 2024 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 2025 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 2026 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 2027 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 2028 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 2029 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 2030 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 2031 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 2032 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 2033 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 2034 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 2035 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 2036 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 2037 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 2038 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 2039 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 2040 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 2041 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 2042 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 2043 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 2044 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 2045 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 2046 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 2047 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 2048 2049 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 2050 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 2051 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 2052 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 2053 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 2054 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 2055 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 2056 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 2057 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 2058 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 2059 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 2060 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 2061 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 2062 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 2063 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 2064 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 2065 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 2066 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 2067 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 2068 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 2069 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 2070 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 2071 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 2072 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 2073 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 2074 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 2075 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 2076 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 2077 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 2078 2079 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 2080 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 2081 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 2082 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 2083 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 2084 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 2085 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 2086 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 2087 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 2088 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 2089 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 2090 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 2091 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 2092 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 2093 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 2094 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 2095 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 2096 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 2097 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 2098 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 2099 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 2100 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 2101 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 2102 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 2103 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 2104 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 2105 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 2106 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 2107 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 2108 #endif /* !CONFIG_USER_ONLY */ 2109 }; 2110