1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 42 return RISCV_EXCP_ILLEGAL_INST; 43 } 44 #endif 45 return RISCV_EXCP_NONE; 46 } 47 48 static RISCVException vs(CPURISCVState *env, int csrno) 49 { 50 if (env->misa_ext & RVV) { 51 #if !defined(CONFIG_USER_ONLY) 52 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 53 return RISCV_EXCP_ILLEGAL_INST; 54 } 55 #endif 56 return RISCV_EXCP_NONE; 57 } 58 return RISCV_EXCP_ILLEGAL_INST; 59 } 60 61 static RISCVException ctr(CPURISCVState *env, int csrno) 62 { 63 #if !defined(CONFIG_USER_ONLY) 64 CPUState *cs = env_cpu(env); 65 RISCVCPU *cpu = RISCV_CPU(cs); 66 67 if (!cpu->cfg.ext_counters) { 68 /* The Counters extensions is not enabled */ 69 return RISCV_EXCP_ILLEGAL_INST; 70 } 71 72 if (riscv_cpu_virt_enabled(env)) { 73 switch (csrno) { 74 case CSR_CYCLE: 75 if (!get_field(env->hcounteren, COUNTEREN_CY) && 76 get_field(env->mcounteren, COUNTEREN_CY)) { 77 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 78 } 79 break; 80 case CSR_TIME: 81 if (!get_field(env->hcounteren, COUNTEREN_TM) && 82 get_field(env->mcounteren, COUNTEREN_TM)) { 83 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 84 } 85 break; 86 case CSR_INSTRET: 87 if (!get_field(env->hcounteren, COUNTEREN_IR) && 88 get_field(env->mcounteren, COUNTEREN_IR)) { 89 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 90 } 91 break; 92 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 93 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 94 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 95 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 96 } 97 break; 98 } 99 if (riscv_cpu_mxl(env) == MXL_RV32) { 100 switch (csrno) { 101 case CSR_CYCLEH: 102 if (!get_field(env->hcounteren, COUNTEREN_CY) && 103 get_field(env->mcounteren, COUNTEREN_CY)) { 104 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 105 } 106 break; 107 case CSR_TIMEH: 108 if (!get_field(env->hcounteren, COUNTEREN_TM) && 109 get_field(env->mcounteren, COUNTEREN_TM)) { 110 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 111 } 112 break; 113 case CSR_INSTRETH: 114 if (!get_field(env->hcounteren, COUNTEREN_IR) && 115 get_field(env->mcounteren, COUNTEREN_IR)) { 116 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 117 } 118 break; 119 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 120 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 121 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 122 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 123 } 124 break; 125 } 126 } 127 } 128 #endif 129 return RISCV_EXCP_NONE; 130 } 131 132 static RISCVException ctr32(CPURISCVState *env, int csrno) 133 { 134 if (riscv_cpu_mxl(env) != MXL_RV32) { 135 return RISCV_EXCP_ILLEGAL_INST; 136 } 137 138 return ctr(env, csrno); 139 } 140 141 #if !defined(CONFIG_USER_ONLY) 142 static RISCVException any(CPURISCVState *env, int csrno) 143 { 144 return RISCV_EXCP_NONE; 145 } 146 147 static RISCVException any32(CPURISCVState *env, int csrno) 148 { 149 if (riscv_cpu_mxl(env) != MXL_RV32) { 150 return RISCV_EXCP_ILLEGAL_INST; 151 } 152 153 return any(env, csrno); 154 155 } 156 157 static RISCVException smode(CPURISCVState *env, int csrno) 158 { 159 if (riscv_has_ext(env, RVS)) { 160 return RISCV_EXCP_NONE; 161 } 162 163 return RISCV_EXCP_ILLEGAL_INST; 164 } 165 166 static RISCVException hmode(CPURISCVState *env, int csrno) 167 { 168 if (riscv_has_ext(env, RVS) && 169 riscv_has_ext(env, RVH)) { 170 /* Hypervisor extension is supported */ 171 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 172 env->priv == PRV_M) { 173 return RISCV_EXCP_NONE; 174 } else { 175 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 176 } 177 } 178 179 return RISCV_EXCP_ILLEGAL_INST; 180 } 181 182 static RISCVException hmode32(CPURISCVState *env, int csrno) 183 { 184 if (riscv_cpu_mxl(env) != MXL_RV32) { 185 if (riscv_cpu_virt_enabled(env)) { 186 return RISCV_EXCP_ILLEGAL_INST; 187 } else { 188 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 189 } 190 } 191 192 return hmode(env, csrno); 193 194 } 195 196 /* Checks if PointerMasking registers could be accessed */ 197 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 198 { 199 /* Check if j-ext is present */ 200 if (riscv_has_ext(env, RVJ)) { 201 return RISCV_EXCP_NONE; 202 } 203 return RISCV_EXCP_ILLEGAL_INST; 204 } 205 206 static RISCVException pmp(CPURISCVState *env, int csrno) 207 { 208 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 209 return RISCV_EXCP_NONE; 210 } 211 212 return RISCV_EXCP_ILLEGAL_INST; 213 } 214 215 static RISCVException epmp(CPURISCVState *env, int csrno) 216 { 217 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 218 return RISCV_EXCP_NONE; 219 } 220 221 return RISCV_EXCP_ILLEGAL_INST; 222 } 223 #endif 224 225 /* User Floating-Point CSRs */ 226 static RISCVException read_fflags(CPURISCVState *env, int csrno, 227 target_ulong *val) 228 { 229 *val = riscv_cpu_get_fflags(env); 230 return RISCV_EXCP_NONE; 231 } 232 233 static RISCVException write_fflags(CPURISCVState *env, int csrno, 234 target_ulong val) 235 { 236 #if !defined(CONFIG_USER_ONLY) 237 env->mstatus |= MSTATUS_FS; 238 #endif 239 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 240 return RISCV_EXCP_NONE; 241 } 242 243 static RISCVException read_frm(CPURISCVState *env, int csrno, 244 target_ulong *val) 245 { 246 *val = env->frm; 247 return RISCV_EXCP_NONE; 248 } 249 250 static RISCVException write_frm(CPURISCVState *env, int csrno, 251 target_ulong val) 252 { 253 #if !defined(CONFIG_USER_ONLY) 254 env->mstatus |= MSTATUS_FS; 255 #endif 256 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 257 return RISCV_EXCP_NONE; 258 } 259 260 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 261 target_ulong *val) 262 { 263 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 264 | (env->frm << FSR_RD_SHIFT); 265 return RISCV_EXCP_NONE; 266 } 267 268 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 269 target_ulong val) 270 { 271 #if !defined(CONFIG_USER_ONLY) 272 env->mstatus |= MSTATUS_FS; 273 #endif 274 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 275 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 276 return RISCV_EXCP_NONE; 277 } 278 279 static RISCVException read_vtype(CPURISCVState *env, int csrno, 280 target_ulong *val) 281 { 282 *val = env->vtype; 283 return RISCV_EXCP_NONE; 284 } 285 286 static RISCVException read_vl(CPURISCVState *env, int csrno, 287 target_ulong *val) 288 { 289 *val = env->vl; 290 return RISCV_EXCP_NONE; 291 } 292 293 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 294 { 295 *val = env_archcpu(env)->cfg.vlen >> 3; 296 return RISCV_EXCP_NONE; 297 } 298 299 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 300 target_ulong *val) 301 { 302 *val = env->vxrm; 303 return RISCV_EXCP_NONE; 304 } 305 306 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 307 target_ulong val) 308 { 309 #if !defined(CONFIG_USER_ONLY) 310 env->mstatus |= MSTATUS_VS; 311 #endif 312 env->vxrm = val; 313 return RISCV_EXCP_NONE; 314 } 315 316 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 317 target_ulong *val) 318 { 319 *val = env->vxsat; 320 return RISCV_EXCP_NONE; 321 } 322 323 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 324 target_ulong val) 325 { 326 #if !defined(CONFIG_USER_ONLY) 327 env->mstatus |= MSTATUS_VS; 328 #endif 329 env->vxsat = val; 330 return RISCV_EXCP_NONE; 331 } 332 333 static RISCVException read_vstart(CPURISCVState *env, int csrno, 334 target_ulong *val) 335 { 336 *val = env->vstart; 337 return RISCV_EXCP_NONE; 338 } 339 340 static RISCVException write_vstart(CPURISCVState *env, int csrno, 341 target_ulong val) 342 { 343 #if !defined(CONFIG_USER_ONLY) 344 env->mstatus |= MSTATUS_VS; 345 #endif 346 env->vstart = val; 347 return RISCV_EXCP_NONE; 348 } 349 350 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 351 { 352 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 353 return RISCV_EXCP_NONE; 354 } 355 356 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 357 { 358 #if !defined(CONFIG_USER_ONLY) 359 env->mstatus |= MSTATUS_VS; 360 #endif 361 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 362 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 363 return RISCV_EXCP_NONE; 364 } 365 366 /* User Timers and Counters */ 367 static RISCVException read_instret(CPURISCVState *env, int csrno, 368 target_ulong *val) 369 { 370 #if !defined(CONFIG_USER_ONLY) 371 if (icount_enabled()) { 372 *val = icount_get(); 373 } else { 374 *val = cpu_get_host_ticks(); 375 } 376 #else 377 *val = cpu_get_host_ticks(); 378 #endif 379 return RISCV_EXCP_NONE; 380 } 381 382 static RISCVException read_instreth(CPURISCVState *env, int csrno, 383 target_ulong *val) 384 { 385 #if !defined(CONFIG_USER_ONLY) 386 if (icount_enabled()) { 387 *val = icount_get() >> 32; 388 } else { 389 *val = cpu_get_host_ticks() >> 32; 390 } 391 #else 392 *val = cpu_get_host_ticks() >> 32; 393 #endif 394 return RISCV_EXCP_NONE; 395 } 396 397 #if defined(CONFIG_USER_ONLY) 398 static RISCVException read_time(CPURISCVState *env, int csrno, 399 target_ulong *val) 400 { 401 *val = cpu_get_host_ticks(); 402 return RISCV_EXCP_NONE; 403 } 404 405 static RISCVException read_timeh(CPURISCVState *env, int csrno, 406 target_ulong *val) 407 { 408 *val = cpu_get_host_ticks() >> 32; 409 return RISCV_EXCP_NONE; 410 } 411 412 #else /* CONFIG_USER_ONLY */ 413 414 static RISCVException read_time(CPURISCVState *env, int csrno, 415 target_ulong *val) 416 { 417 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 418 419 if (!env->rdtime_fn) { 420 return RISCV_EXCP_ILLEGAL_INST; 421 } 422 423 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 424 return RISCV_EXCP_NONE; 425 } 426 427 static RISCVException read_timeh(CPURISCVState *env, int csrno, 428 target_ulong *val) 429 { 430 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 431 432 if (!env->rdtime_fn) { 433 return RISCV_EXCP_ILLEGAL_INST; 434 } 435 436 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 437 return RISCV_EXCP_NONE; 438 } 439 440 /* Machine constants */ 441 442 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 443 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 444 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 445 446 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 447 VS_MODE_INTERRUPTS; 448 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; 449 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 450 VS_MODE_INTERRUPTS; 451 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 452 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 453 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 454 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 455 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 456 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 457 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 458 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 459 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 460 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 461 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 462 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 463 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 464 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 465 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 466 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 467 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 468 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 469 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 470 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 471 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 472 (1ULL << (RISCV_EXCP_VS_ECALL)) | 473 (1ULL << (RISCV_EXCP_M_ECALL)) | 474 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 475 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 476 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 477 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 478 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 479 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 480 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 481 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 482 static const target_ulong hip_writable_mask = MIP_VSSIP; 483 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 484 static const target_ulong vsip_writable_mask = MIP_VSSIP; 485 486 static const char valid_vm_1_10_32[16] = { 487 [VM_1_10_MBARE] = 1, 488 [VM_1_10_SV32] = 1 489 }; 490 491 static const char valid_vm_1_10_64[16] = { 492 [VM_1_10_MBARE] = 1, 493 [VM_1_10_SV39] = 1, 494 [VM_1_10_SV48] = 1, 495 [VM_1_10_SV57] = 1 496 }; 497 498 /* Machine Information Registers */ 499 static RISCVException read_zero(CPURISCVState *env, int csrno, 500 target_ulong *val) 501 { 502 *val = 0; 503 return RISCV_EXCP_NONE; 504 } 505 506 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 507 target_ulong *val) 508 { 509 *val = env->mhartid; 510 return RISCV_EXCP_NONE; 511 } 512 513 /* Machine Trap Setup */ 514 515 /* We do not store SD explicitly, only compute it on demand. */ 516 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 517 { 518 if ((status & MSTATUS_FS) == MSTATUS_FS || 519 (status & MSTATUS_VS) == MSTATUS_VS || 520 (status & MSTATUS_XS) == MSTATUS_XS) { 521 switch (xl) { 522 case MXL_RV32: 523 return status | MSTATUS32_SD; 524 case MXL_RV64: 525 return status | MSTATUS64_SD; 526 default: 527 g_assert_not_reached(); 528 } 529 } 530 return status; 531 } 532 533 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 534 target_ulong *val) 535 { 536 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 537 return RISCV_EXCP_NONE; 538 } 539 540 static int validate_vm(CPURISCVState *env, target_ulong vm) 541 { 542 if (riscv_cpu_mxl(env) == MXL_RV32) { 543 return valid_vm_1_10_32[vm & 0xf]; 544 } else { 545 return valid_vm_1_10_64[vm & 0xf]; 546 } 547 } 548 549 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 550 target_ulong val) 551 { 552 uint64_t mstatus = env->mstatus; 553 uint64_t mask = 0; 554 555 /* flush tlb on mstatus fields that affect VM */ 556 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 557 MSTATUS_MPRV | MSTATUS_SUM)) { 558 tlb_flush(env_cpu(env)); 559 } 560 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 561 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 562 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 563 MSTATUS_TW | MSTATUS_VS; 564 565 if (riscv_cpu_mxl(env) != MXL_RV32) { 566 /* 567 * RV32: MPV and GVA are not in mstatus. The current plan is to 568 * add them to mstatush. For now, we just don't support it. 569 */ 570 mask |= MSTATUS_MPV | MSTATUS_GVA; 571 } 572 573 mstatus = (mstatus & ~mask) | (val & mask); 574 575 if (riscv_cpu_mxl(env) == MXL_RV64) { 576 /* SXL and UXL fields are for now read only */ 577 mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); 578 mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); 579 } 580 env->mstatus = mstatus; 581 582 return RISCV_EXCP_NONE; 583 } 584 585 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 586 target_ulong *val) 587 { 588 *val = env->mstatus >> 32; 589 return RISCV_EXCP_NONE; 590 } 591 592 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 593 target_ulong val) 594 { 595 uint64_t valh = (uint64_t)val << 32; 596 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 597 598 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 599 tlb_flush(env_cpu(env)); 600 } 601 602 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 603 604 return RISCV_EXCP_NONE; 605 } 606 607 static RISCVException read_misa(CPURISCVState *env, int csrno, 608 target_ulong *val) 609 { 610 target_ulong misa; 611 612 switch (env->misa_mxl) { 613 case MXL_RV32: 614 misa = (target_ulong)MXL_RV32 << 30; 615 break; 616 #ifdef TARGET_RISCV64 617 case MXL_RV64: 618 misa = (target_ulong)MXL_RV64 << 62; 619 break; 620 #endif 621 default: 622 g_assert_not_reached(); 623 } 624 625 *val = misa | env->misa_ext; 626 return RISCV_EXCP_NONE; 627 } 628 629 static RISCVException write_misa(CPURISCVState *env, int csrno, 630 target_ulong val) 631 { 632 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 633 /* drop write to misa */ 634 return RISCV_EXCP_NONE; 635 } 636 637 /* 'I' or 'E' must be present */ 638 if (!(val & (RVI | RVE))) { 639 /* It is not, drop write to misa */ 640 return RISCV_EXCP_NONE; 641 } 642 643 /* 'E' excludes all other extensions */ 644 if (val & RVE) { 645 /* when we support 'E' we can do "val = RVE;" however 646 * for now we just drop writes if 'E' is present. 647 */ 648 return RISCV_EXCP_NONE; 649 } 650 651 /* 652 * misa.MXL writes are not supported by QEMU. 653 * Drop writes to those bits. 654 */ 655 656 /* Mask extensions that are not supported by this hart */ 657 val &= env->misa_ext_mask; 658 659 /* Mask extensions that are not supported by QEMU */ 660 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 661 662 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 663 if ((val & RVD) && !(val & RVF)) { 664 val &= ~RVD; 665 } 666 667 /* Suppress 'C' if next instruction is not aligned 668 * TODO: this should check next_pc 669 */ 670 if ((val & RVC) && (GETPC() & ~3) != 0) { 671 val &= ~RVC; 672 } 673 674 /* If nothing changed, do nothing. */ 675 if (val == env->misa_ext) { 676 return RISCV_EXCP_NONE; 677 } 678 679 /* flush translation cache */ 680 tb_flush(env_cpu(env)); 681 env->misa_ext = val; 682 return RISCV_EXCP_NONE; 683 } 684 685 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 686 target_ulong *val) 687 { 688 *val = env->medeleg; 689 return RISCV_EXCP_NONE; 690 } 691 692 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 693 target_ulong val) 694 { 695 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 696 return RISCV_EXCP_NONE; 697 } 698 699 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 700 target_ulong *val) 701 { 702 *val = env->mideleg; 703 return RISCV_EXCP_NONE; 704 } 705 706 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 707 target_ulong val) 708 { 709 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 710 if (riscv_has_ext(env, RVH)) { 711 env->mideleg |= VS_MODE_INTERRUPTS; 712 } 713 return RISCV_EXCP_NONE; 714 } 715 716 static RISCVException read_mie(CPURISCVState *env, int csrno, 717 target_ulong *val) 718 { 719 *val = env->mie; 720 return RISCV_EXCP_NONE; 721 } 722 723 static RISCVException write_mie(CPURISCVState *env, int csrno, 724 target_ulong val) 725 { 726 env->mie = (env->mie & ~all_ints) | (val & all_ints); 727 return RISCV_EXCP_NONE; 728 } 729 730 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 731 target_ulong *val) 732 { 733 *val = env->mtvec; 734 return RISCV_EXCP_NONE; 735 } 736 737 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 738 target_ulong val) 739 { 740 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 741 if ((val & 3) < 2) { 742 env->mtvec = val; 743 } else { 744 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 745 } 746 return RISCV_EXCP_NONE; 747 } 748 749 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 750 target_ulong *val) 751 { 752 *val = env->mcounteren; 753 return RISCV_EXCP_NONE; 754 } 755 756 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 757 target_ulong val) 758 { 759 env->mcounteren = val; 760 return RISCV_EXCP_NONE; 761 } 762 763 /* Machine Trap Handling */ 764 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 765 target_ulong *val) 766 { 767 *val = env->mscratch; 768 return RISCV_EXCP_NONE; 769 } 770 771 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 772 target_ulong val) 773 { 774 env->mscratch = val; 775 return RISCV_EXCP_NONE; 776 } 777 778 static RISCVException read_mepc(CPURISCVState *env, int csrno, 779 target_ulong *val) 780 { 781 *val = env->mepc; 782 return RISCV_EXCP_NONE; 783 } 784 785 static RISCVException write_mepc(CPURISCVState *env, int csrno, 786 target_ulong val) 787 { 788 env->mepc = val; 789 return RISCV_EXCP_NONE; 790 } 791 792 static RISCVException read_mcause(CPURISCVState *env, int csrno, 793 target_ulong *val) 794 { 795 *val = env->mcause; 796 return RISCV_EXCP_NONE; 797 } 798 799 static RISCVException write_mcause(CPURISCVState *env, int csrno, 800 target_ulong val) 801 { 802 env->mcause = val; 803 return RISCV_EXCP_NONE; 804 } 805 806 static RISCVException read_mtval(CPURISCVState *env, int csrno, 807 target_ulong *val) 808 { 809 *val = env->mtval; 810 return RISCV_EXCP_NONE; 811 } 812 813 static RISCVException write_mtval(CPURISCVState *env, int csrno, 814 target_ulong val) 815 { 816 env->mtval = val; 817 return RISCV_EXCP_NONE; 818 } 819 820 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 821 target_ulong *ret_value, 822 target_ulong new_value, target_ulong write_mask) 823 { 824 RISCVCPU *cpu = env_archcpu(env); 825 /* Allow software control of delegable interrupts not claimed by hardware */ 826 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 827 uint32_t old_mip; 828 829 if (mask) { 830 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 831 } else { 832 old_mip = env->mip; 833 } 834 835 if (ret_value) { 836 *ret_value = old_mip; 837 } 838 839 return RISCV_EXCP_NONE; 840 } 841 842 /* Supervisor Trap Setup */ 843 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 844 target_ulong *val) 845 { 846 target_ulong mask = (sstatus_v1_10_mask); 847 848 /* TODO: Use SXL not MXL. */ 849 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 850 return RISCV_EXCP_NONE; 851 } 852 853 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 854 target_ulong val) 855 { 856 target_ulong mask = (sstatus_v1_10_mask); 857 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 858 return write_mstatus(env, CSR_MSTATUS, newval); 859 } 860 861 static RISCVException read_vsie(CPURISCVState *env, int csrno, 862 target_ulong *val) 863 { 864 /* Shift the VS bits to their S bit location in vsie */ 865 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 866 return RISCV_EXCP_NONE; 867 } 868 869 static RISCVException read_sie(CPURISCVState *env, int csrno, 870 target_ulong *val) 871 { 872 if (riscv_cpu_virt_enabled(env)) { 873 read_vsie(env, CSR_VSIE, val); 874 } else { 875 *val = env->mie & env->mideleg; 876 } 877 return RISCV_EXCP_NONE; 878 } 879 880 static RISCVException write_vsie(CPURISCVState *env, int csrno, 881 target_ulong val) 882 { 883 /* Shift the S bits to their VS bit location in mie */ 884 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 885 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 886 return write_mie(env, CSR_MIE, newval); 887 } 888 889 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 890 { 891 if (riscv_cpu_virt_enabled(env)) { 892 write_vsie(env, CSR_VSIE, val); 893 } else { 894 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 895 (val & S_MODE_INTERRUPTS); 896 write_mie(env, CSR_MIE, newval); 897 } 898 899 return RISCV_EXCP_NONE; 900 } 901 902 static RISCVException read_stvec(CPURISCVState *env, int csrno, 903 target_ulong *val) 904 { 905 *val = env->stvec; 906 return RISCV_EXCP_NONE; 907 } 908 909 static RISCVException write_stvec(CPURISCVState *env, int csrno, 910 target_ulong val) 911 { 912 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 913 if ((val & 3) < 2) { 914 env->stvec = val; 915 } else { 916 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 917 } 918 return RISCV_EXCP_NONE; 919 } 920 921 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 922 target_ulong *val) 923 { 924 *val = env->scounteren; 925 return RISCV_EXCP_NONE; 926 } 927 928 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 929 target_ulong val) 930 { 931 env->scounteren = val; 932 return RISCV_EXCP_NONE; 933 } 934 935 /* Supervisor Trap Handling */ 936 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 937 target_ulong *val) 938 { 939 *val = env->sscratch; 940 return RISCV_EXCP_NONE; 941 } 942 943 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 944 target_ulong val) 945 { 946 env->sscratch = val; 947 return RISCV_EXCP_NONE; 948 } 949 950 static RISCVException read_sepc(CPURISCVState *env, int csrno, 951 target_ulong *val) 952 { 953 *val = env->sepc; 954 return RISCV_EXCP_NONE; 955 } 956 957 static RISCVException write_sepc(CPURISCVState *env, int csrno, 958 target_ulong val) 959 { 960 env->sepc = val; 961 return RISCV_EXCP_NONE; 962 } 963 964 static RISCVException read_scause(CPURISCVState *env, int csrno, 965 target_ulong *val) 966 { 967 *val = env->scause; 968 return RISCV_EXCP_NONE; 969 } 970 971 static RISCVException write_scause(CPURISCVState *env, int csrno, 972 target_ulong val) 973 { 974 env->scause = val; 975 return RISCV_EXCP_NONE; 976 } 977 978 static RISCVException read_stval(CPURISCVState *env, int csrno, 979 target_ulong *val) 980 { 981 *val = env->stval; 982 return RISCV_EXCP_NONE; 983 } 984 985 static RISCVException write_stval(CPURISCVState *env, int csrno, 986 target_ulong val) 987 { 988 env->stval = val; 989 return RISCV_EXCP_NONE; 990 } 991 992 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 993 target_ulong *ret_value, 994 target_ulong new_value, target_ulong write_mask) 995 { 996 /* Shift the S bits to their VS bit location in mip */ 997 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 998 (write_mask << 1) & vsip_writable_mask & env->hideleg); 999 1000 if (ret_value) { 1001 *ret_value &= VS_MODE_INTERRUPTS; 1002 /* Shift the VS bits to their S bit location in vsip */ 1003 *ret_value >>= 1; 1004 } 1005 return ret; 1006 } 1007 1008 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 1009 target_ulong *ret_value, 1010 target_ulong new_value, target_ulong write_mask) 1011 { 1012 int ret; 1013 1014 if (riscv_cpu_virt_enabled(env)) { 1015 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 1016 } else { 1017 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 1018 write_mask & env->mideleg & sip_writable_mask); 1019 } 1020 1021 if (ret_value) { 1022 *ret_value &= env->mideleg; 1023 } 1024 return ret; 1025 } 1026 1027 /* Supervisor Protection and Translation */ 1028 static RISCVException read_satp(CPURISCVState *env, int csrno, 1029 target_ulong *val) 1030 { 1031 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1032 *val = 0; 1033 return RISCV_EXCP_NONE; 1034 } 1035 1036 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1037 return RISCV_EXCP_ILLEGAL_INST; 1038 } else { 1039 *val = env->satp; 1040 } 1041 1042 return RISCV_EXCP_NONE; 1043 } 1044 1045 static RISCVException write_satp(CPURISCVState *env, int csrno, 1046 target_ulong val) 1047 { 1048 target_ulong vm, mask, asid; 1049 1050 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1051 return RISCV_EXCP_NONE; 1052 } 1053 1054 if (riscv_cpu_mxl(env) == MXL_RV32) { 1055 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1056 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1057 asid = (val ^ env->satp) & SATP32_ASID; 1058 } else { 1059 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1060 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1061 asid = (val ^ env->satp) & SATP64_ASID; 1062 } 1063 1064 if (vm && mask) { 1065 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1066 return RISCV_EXCP_ILLEGAL_INST; 1067 } else { 1068 if (asid) { 1069 tlb_flush(env_cpu(env)); 1070 } 1071 env->satp = val; 1072 } 1073 } 1074 return RISCV_EXCP_NONE; 1075 } 1076 1077 /* Hypervisor Extensions */ 1078 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1079 target_ulong *val) 1080 { 1081 *val = env->hstatus; 1082 if (riscv_cpu_mxl(env) != MXL_RV32) { 1083 /* We only support 64-bit VSXL */ 1084 *val = set_field(*val, HSTATUS_VSXL, 2); 1085 } 1086 /* We only support little endian */ 1087 *val = set_field(*val, HSTATUS_VSBE, 0); 1088 return RISCV_EXCP_NONE; 1089 } 1090 1091 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1092 target_ulong val) 1093 { 1094 env->hstatus = val; 1095 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 1096 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1097 } 1098 if (get_field(val, HSTATUS_VSBE) != 0) { 1099 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1100 } 1101 return RISCV_EXCP_NONE; 1102 } 1103 1104 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1105 target_ulong *val) 1106 { 1107 *val = env->hedeleg; 1108 return RISCV_EXCP_NONE; 1109 } 1110 1111 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1112 target_ulong val) 1113 { 1114 env->hedeleg = val & vs_delegable_excps; 1115 return RISCV_EXCP_NONE; 1116 } 1117 1118 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1119 target_ulong *val) 1120 { 1121 *val = env->hideleg; 1122 return RISCV_EXCP_NONE; 1123 } 1124 1125 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1126 target_ulong val) 1127 { 1128 env->hideleg = val & vs_delegable_ints; 1129 return RISCV_EXCP_NONE; 1130 } 1131 1132 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1133 target_ulong *ret_value, 1134 target_ulong new_value, target_ulong write_mask) 1135 { 1136 int ret = rmw_mip(env, 0, ret_value, new_value, 1137 write_mask & hvip_writable_mask); 1138 1139 if (ret_value) { 1140 *ret_value &= hvip_writable_mask; 1141 } 1142 return ret; 1143 } 1144 1145 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1146 target_ulong *ret_value, 1147 target_ulong new_value, target_ulong write_mask) 1148 { 1149 int ret = rmw_mip(env, 0, ret_value, new_value, 1150 write_mask & hip_writable_mask); 1151 1152 if (ret_value) { 1153 *ret_value &= hip_writable_mask; 1154 } 1155 return ret; 1156 } 1157 1158 static RISCVException read_hie(CPURISCVState *env, int csrno, 1159 target_ulong *val) 1160 { 1161 *val = env->mie & VS_MODE_INTERRUPTS; 1162 return RISCV_EXCP_NONE; 1163 } 1164 1165 static RISCVException write_hie(CPURISCVState *env, int csrno, 1166 target_ulong val) 1167 { 1168 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1169 return write_mie(env, CSR_MIE, newval); 1170 } 1171 1172 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1173 target_ulong *val) 1174 { 1175 *val = env->hcounteren; 1176 return RISCV_EXCP_NONE; 1177 } 1178 1179 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1180 target_ulong val) 1181 { 1182 env->hcounteren = val; 1183 return RISCV_EXCP_NONE; 1184 } 1185 1186 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1187 target_ulong val) 1188 { 1189 if (val) { 1190 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1191 } 1192 return RISCV_EXCP_NONE; 1193 } 1194 1195 static RISCVException read_htval(CPURISCVState *env, int csrno, 1196 target_ulong *val) 1197 { 1198 *val = env->htval; 1199 return RISCV_EXCP_NONE; 1200 } 1201 1202 static RISCVException write_htval(CPURISCVState *env, int csrno, 1203 target_ulong val) 1204 { 1205 env->htval = val; 1206 return RISCV_EXCP_NONE; 1207 } 1208 1209 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1210 target_ulong *val) 1211 { 1212 *val = env->htinst; 1213 return RISCV_EXCP_NONE; 1214 } 1215 1216 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1217 target_ulong val) 1218 { 1219 return RISCV_EXCP_NONE; 1220 } 1221 1222 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1223 target_ulong val) 1224 { 1225 if (val) { 1226 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1227 } 1228 return RISCV_EXCP_NONE; 1229 } 1230 1231 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1232 target_ulong *val) 1233 { 1234 *val = env->hgatp; 1235 return RISCV_EXCP_NONE; 1236 } 1237 1238 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1239 target_ulong val) 1240 { 1241 env->hgatp = val; 1242 return RISCV_EXCP_NONE; 1243 } 1244 1245 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1246 target_ulong *val) 1247 { 1248 if (!env->rdtime_fn) { 1249 return RISCV_EXCP_ILLEGAL_INST; 1250 } 1251 1252 *val = env->htimedelta; 1253 return RISCV_EXCP_NONE; 1254 } 1255 1256 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1257 target_ulong val) 1258 { 1259 if (!env->rdtime_fn) { 1260 return RISCV_EXCP_ILLEGAL_INST; 1261 } 1262 1263 if (riscv_cpu_mxl(env) == MXL_RV32) { 1264 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1265 } else { 1266 env->htimedelta = val; 1267 } 1268 return RISCV_EXCP_NONE; 1269 } 1270 1271 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1272 target_ulong *val) 1273 { 1274 if (!env->rdtime_fn) { 1275 return RISCV_EXCP_ILLEGAL_INST; 1276 } 1277 1278 *val = env->htimedelta >> 32; 1279 return RISCV_EXCP_NONE; 1280 } 1281 1282 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1283 target_ulong val) 1284 { 1285 if (!env->rdtime_fn) { 1286 return RISCV_EXCP_ILLEGAL_INST; 1287 } 1288 1289 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1290 return RISCV_EXCP_NONE; 1291 } 1292 1293 /* Virtual CSR Registers */ 1294 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1295 target_ulong *val) 1296 { 1297 *val = env->vsstatus; 1298 return RISCV_EXCP_NONE; 1299 } 1300 1301 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1302 target_ulong val) 1303 { 1304 uint64_t mask = (target_ulong)-1; 1305 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1306 return RISCV_EXCP_NONE; 1307 } 1308 1309 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1310 { 1311 *val = env->vstvec; 1312 return RISCV_EXCP_NONE; 1313 } 1314 1315 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1316 target_ulong val) 1317 { 1318 env->vstvec = val; 1319 return RISCV_EXCP_NONE; 1320 } 1321 1322 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1323 target_ulong *val) 1324 { 1325 *val = env->vsscratch; 1326 return RISCV_EXCP_NONE; 1327 } 1328 1329 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1330 target_ulong val) 1331 { 1332 env->vsscratch = val; 1333 return RISCV_EXCP_NONE; 1334 } 1335 1336 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1337 target_ulong *val) 1338 { 1339 *val = env->vsepc; 1340 return RISCV_EXCP_NONE; 1341 } 1342 1343 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1344 target_ulong val) 1345 { 1346 env->vsepc = val; 1347 return RISCV_EXCP_NONE; 1348 } 1349 1350 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1351 target_ulong *val) 1352 { 1353 *val = env->vscause; 1354 return RISCV_EXCP_NONE; 1355 } 1356 1357 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1358 target_ulong val) 1359 { 1360 env->vscause = val; 1361 return RISCV_EXCP_NONE; 1362 } 1363 1364 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1365 target_ulong *val) 1366 { 1367 *val = env->vstval; 1368 return RISCV_EXCP_NONE; 1369 } 1370 1371 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1372 target_ulong val) 1373 { 1374 env->vstval = val; 1375 return RISCV_EXCP_NONE; 1376 } 1377 1378 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1379 target_ulong *val) 1380 { 1381 *val = env->vsatp; 1382 return RISCV_EXCP_NONE; 1383 } 1384 1385 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1386 target_ulong val) 1387 { 1388 env->vsatp = val; 1389 return RISCV_EXCP_NONE; 1390 } 1391 1392 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1393 target_ulong *val) 1394 { 1395 *val = env->mtval2; 1396 return RISCV_EXCP_NONE; 1397 } 1398 1399 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1400 target_ulong val) 1401 { 1402 env->mtval2 = val; 1403 return RISCV_EXCP_NONE; 1404 } 1405 1406 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1407 target_ulong *val) 1408 { 1409 *val = env->mtinst; 1410 return RISCV_EXCP_NONE; 1411 } 1412 1413 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1414 target_ulong val) 1415 { 1416 env->mtinst = val; 1417 return RISCV_EXCP_NONE; 1418 } 1419 1420 /* Physical Memory Protection */ 1421 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1422 target_ulong *val) 1423 { 1424 *val = mseccfg_csr_read(env); 1425 return RISCV_EXCP_NONE; 1426 } 1427 1428 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1429 target_ulong val) 1430 { 1431 mseccfg_csr_write(env, val); 1432 return RISCV_EXCP_NONE; 1433 } 1434 1435 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1436 target_ulong *val) 1437 { 1438 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1439 return RISCV_EXCP_NONE; 1440 } 1441 1442 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1443 target_ulong val) 1444 { 1445 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1446 return RISCV_EXCP_NONE; 1447 } 1448 1449 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1450 target_ulong *val) 1451 { 1452 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1453 return RISCV_EXCP_NONE; 1454 } 1455 1456 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1457 target_ulong val) 1458 { 1459 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1460 return RISCV_EXCP_NONE; 1461 } 1462 1463 /* 1464 * Functions to access Pointer Masking feature registers 1465 * We have to check if current priv lvl could modify 1466 * csr in given mode 1467 */ 1468 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 1469 { 1470 int csr_priv = get_field(csrno, 0x300); 1471 int pm_current; 1472 1473 /* 1474 * If priv lvls differ that means we're accessing csr from higher priv lvl, 1475 * so allow the access 1476 */ 1477 if (env->priv != csr_priv) { 1478 return false; 1479 } 1480 switch (env->priv) { 1481 case PRV_M: 1482 pm_current = get_field(env->mmte, M_PM_CURRENT); 1483 break; 1484 case PRV_S: 1485 pm_current = get_field(env->mmte, S_PM_CURRENT); 1486 break; 1487 case PRV_U: 1488 pm_current = get_field(env->mmte, U_PM_CURRENT); 1489 break; 1490 default: 1491 g_assert_not_reached(); 1492 } 1493 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 1494 return !pm_current; 1495 } 1496 1497 static RISCVException read_mmte(CPURISCVState *env, int csrno, 1498 target_ulong *val) 1499 { 1500 *val = env->mmte & MMTE_MASK; 1501 return RISCV_EXCP_NONE; 1502 } 1503 1504 static RISCVException write_mmte(CPURISCVState *env, int csrno, 1505 target_ulong val) 1506 { 1507 uint64_t mstatus; 1508 target_ulong wpri_val = val & MMTE_MASK; 1509 1510 if (val != wpri_val) { 1511 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1512 "MMTE: WPRI violation written 0x", val, 1513 "vs expected 0x", wpri_val); 1514 } 1515 /* for machine mode pm.current is hardwired to 1 */ 1516 wpri_val |= MMTE_M_PM_CURRENT; 1517 1518 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 1519 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 1520 env->mmte = wpri_val | PM_EXT_DIRTY; 1521 1522 /* Set XS and SD bits, since PM CSRs are dirty */ 1523 mstatus = env->mstatus | MSTATUS_XS; 1524 write_mstatus(env, csrno, mstatus); 1525 return RISCV_EXCP_NONE; 1526 } 1527 1528 static RISCVException read_smte(CPURISCVState *env, int csrno, 1529 target_ulong *val) 1530 { 1531 *val = env->mmte & SMTE_MASK; 1532 return RISCV_EXCP_NONE; 1533 } 1534 1535 static RISCVException write_smte(CPURISCVState *env, int csrno, 1536 target_ulong val) 1537 { 1538 target_ulong wpri_val = val & SMTE_MASK; 1539 1540 if (val != wpri_val) { 1541 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1542 "SMTE: WPRI violation written 0x", val, 1543 "vs expected 0x", wpri_val); 1544 } 1545 1546 /* if pm.current==0 we can't modify current PM CSRs */ 1547 if (check_pm_current_disabled(env, csrno)) { 1548 return RISCV_EXCP_NONE; 1549 } 1550 1551 wpri_val |= (env->mmte & ~SMTE_MASK); 1552 write_mmte(env, csrno, wpri_val); 1553 return RISCV_EXCP_NONE; 1554 } 1555 1556 static RISCVException read_umte(CPURISCVState *env, int csrno, 1557 target_ulong *val) 1558 { 1559 *val = env->mmte & UMTE_MASK; 1560 return RISCV_EXCP_NONE; 1561 } 1562 1563 static RISCVException write_umte(CPURISCVState *env, int csrno, 1564 target_ulong val) 1565 { 1566 target_ulong wpri_val = val & UMTE_MASK; 1567 1568 if (val != wpri_val) { 1569 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1570 "UMTE: WPRI violation written 0x", val, 1571 "vs expected 0x", wpri_val); 1572 } 1573 1574 if (check_pm_current_disabled(env, csrno)) { 1575 return RISCV_EXCP_NONE; 1576 } 1577 1578 wpri_val |= (env->mmte & ~UMTE_MASK); 1579 write_mmte(env, csrno, wpri_val); 1580 return RISCV_EXCP_NONE; 1581 } 1582 1583 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 1584 target_ulong *val) 1585 { 1586 *val = env->mpmmask; 1587 return RISCV_EXCP_NONE; 1588 } 1589 1590 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 1591 target_ulong val) 1592 { 1593 uint64_t mstatus; 1594 1595 env->mpmmask = val; 1596 env->mmte |= PM_EXT_DIRTY; 1597 1598 /* Set XS and SD bits, since PM CSRs are dirty */ 1599 mstatus = env->mstatus | MSTATUS_XS; 1600 write_mstatus(env, csrno, mstatus); 1601 return RISCV_EXCP_NONE; 1602 } 1603 1604 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 1605 target_ulong *val) 1606 { 1607 *val = env->spmmask; 1608 return RISCV_EXCP_NONE; 1609 } 1610 1611 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 1612 target_ulong val) 1613 { 1614 uint64_t mstatus; 1615 1616 /* if pm.current==0 we can't modify current PM CSRs */ 1617 if (check_pm_current_disabled(env, csrno)) { 1618 return RISCV_EXCP_NONE; 1619 } 1620 env->spmmask = val; 1621 env->mmte |= PM_EXT_DIRTY; 1622 1623 /* Set XS and SD bits, since PM CSRs are dirty */ 1624 mstatus = env->mstatus | MSTATUS_XS; 1625 write_mstatus(env, csrno, mstatus); 1626 return RISCV_EXCP_NONE; 1627 } 1628 1629 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 1630 target_ulong *val) 1631 { 1632 *val = env->upmmask; 1633 return RISCV_EXCP_NONE; 1634 } 1635 1636 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 1637 target_ulong val) 1638 { 1639 uint64_t mstatus; 1640 1641 /* if pm.current==0 we can't modify current PM CSRs */ 1642 if (check_pm_current_disabled(env, csrno)) { 1643 return RISCV_EXCP_NONE; 1644 } 1645 env->upmmask = val; 1646 env->mmte |= PM_EXT_DIRTY; 1647 1648 /* Set XS and SD bits, since PM CSRs are dirty */ 1649 mstatus = env->mstatus | MSTATUS_XS; 1650 write_mstatus(env, csrno, mstatus); 1651 return RISCV_EXCP_NONE; 1652 } 1653 1654 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 1655 target_ulong *val) 1656 { 1657 *val = env->mpmbase; 1658 return RISCV_EXCP_NONE; 1659 } 1660 1661 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 1662 target_ulong val) 1663 { 1664 uint64_t mstatus; 1665 1666 env->mpmbase = val; 1667 env->mmte |= PM_EXT_DIRTY; 1668 1669 /* Set XS and SD bits, since PM CSRs are dirty */ 1670 mstatus = env->mstatus | MSTATUS_XS; 1671 write_mstatus(env, csrno, mstatus); 1672 return RISCV_EXCP_NONE; 1673 } 1674 1675 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 1676 target_ulong *val) 1677 { 1678 *val = env->spmbase; 1679 return RISCV_EXCP_NONE; 1680 } 1681 1682 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 1683 target_ulong val) 1684 { 1685 uint64_t mstatus; 1686 1687 /* if pm.current==0 we can't modify current PM CSRs */ 1688 if (check_pm_current_disabled(env, csrno)) { 1689 return RISCV_EXCP_NONE; 1690 } 1691 env->spmbase = val; 1692 env->mmte |= PM_EXT_DIRTY; 1693 1694 /* Set XS and SD bits, since PM CSRs are dirty */ 1695 mstatus = env->mstatus | MSTATUS_XS; 1696 write_mstatus(env, csrno, mstatus); 1697 return RISCV_EXCP_NONE; 1698 } 1699 1700 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 1701 target_ulong *val) 1702 { 1703 *val = env->upmbase; 1704 return RISCV_EXCP_NONE; 1705 } 1706 1707 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 1708 target_ulong val) 1709 { 1710 uint64_t mstatus; 1711 1712 /* if pm.current==0 we can't modify current PM CSRs */ 1713 if (check_pm_current_disabled(env, csrno)) { 1714 return RISCV_EXCP_NONE; 1715 } 1716 env->upmbase = val; 1717 env->mmte |= PM_EXT_DIRTY; 1718 1719 /* Set XS and SD bits, since PM CSRs are dirty */ 1720 mstatus = env->mstatus | MSTATUS_XS; 1721 write_mstatus(env, csrno, mstatus); 1722 return RISCV_EXCP_NONE; 1723 } 1724 1725 #endif 1726 1727 /* 1728 * riscv_csrrw - read and/or update control and status register 1729 * 1730 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1731 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1732 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1733 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1734 */ 1735 1736 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1737 target_ulong *ret_value, 1738 target_ulong new_value, target_ulong write_mask) 1739 { 1740 RISCVException ret; 1741 target_ulong old_value; 1742 RISCVCPU *cpu = env_archcpu(env); 1743 int read_only = get_field(csrno, 0xC00) == 3; 1744 1745 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 1746 #if !defined(CONFIG_USER_ONLY) 1747 int effective_priv = env->priv; 1748 1749 if (riscv_has_ext(env, RVH) && 1750 env->priv == PRV_S && 1751 !riscv_cpu_virt_enabled(env)) { 1752 /* 1753 * We are in S mode without virtualisation, therefore we are in HS Mode. 1754 * Add 1 to the effective privledge level to allow us to access the 1755 * Hypervisor CSRs. 1756 */ 1757 effective_priv++; 1758 } 1759 1760 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 1761 return RISCV_EXCP_ILLEGAL_INST; 1762 } 1763 #endif 1764 if (write_mask && read_only) { 1765 return RISCV_EXCP_ILLEGAL_INST; 1766 } 1767 1768 /* ensure the CSR extension is enabled. */ 1769 if (!cpu->cfg.ext_icsr) { 1770 return RISCV_EXCP_ILLEGAL_INST; 1771 } 1772 1773 /* check predicate */ 1774 if (!csr_ops[csrno].predicate) { 1775 return RISCV_EXCP_ILLEGAL_INST; 1776 } 1777 ret = csr_ops[csrno].predicate(env, csrno); 1778 if (ret != RISCV_EXCP_NONE) { 1779 return ret; 1780 } 1781 1782 /* execute combined read/write operation if it exists */ 1783 if (csr_ops[csrno].op) { 1784 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1785 } 1786 1787 /* if no accessor exists then return failure */ 1788 if (!csr_ops[csrno].read) { 1789 return RISCV_EXCP_ILLEGAL_INST; 1790 } 1791 /* read old value */ 1792 ret = csr_ops[csrno].read(env, csrno, &old_value); 1793 if (ret != RISCV_EXCP_NONE) { 1794 return ret; 1795 } 1796 1797 /* write value if writable and write mask set, otherwise drop writes */ 1798 if (write_mask) { 1799 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1800 if (csr_ops[csrno].write) { 1801 ret = csr_ops[csrno].write(env, csrno, new_value); 1802 if (ret != RISCV_EXCP_NONE) { 1803 return ret; 1804 } 1805 } 1806 } 1807 1808 /* return old value */ 1809 if (ret_value) { 1810 *ret_value = old_value; 1811 } 1812 1813 return RISCV_EXCP_NONE; 1814 } 1815 1816 /* 1817 * Debugger support. If not in user mode, set env->debugger before the 1818 * riscv_csrrw call and clear it after the call. 1819 */ 1820 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1821 target_ulong *ret_value, 1822 target_ulong new_value, 1823 target_ulong write_mask) 1824 { 1825 RISCVException ret; 1826 #if !defined(CONFIG_USER_ONLY) 1827 env->debugger = true; 1828 #endif 1829 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1830 #if !defined(CONFIG_USER_ONLY) 1831 env->debugger = false; 1832 #endif 1833 return ret; 1834 } 1835 1836 /* Control and Status Register function table */ 1837 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1838 /* User Floating-Point CSRs */ 1839 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1840 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1841 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1842 /* Vector CSRs */ 1843 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1844 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1845 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1846 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, 1847 [CSR_VL] = { "vl", vs, read_vl }, 1848 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1849 [CSR_VLENB] = { "vlenb", vs, read_vlenb }, 1850 /* User Timers and Counters */ 1851 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1852 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1853 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1854 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1855 1856 /* 1857 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1858 * rdtime callback is not provided by machine/platform emulation. 1859 */ 1860 [CSR_TIME] = { "time", ctr, read_time }, 1861 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1862 1863 #if !defined(CONFIG_USER_ONLY) 1864 /* Machine Timers and Counters */ 1865 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1866 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1867 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1868 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1869 1870 /* Machine Information Registers */ 1871 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1872 [CSR_MARCHID] = { "marchid", any, read_zero }, 1873 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1874 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1875 1876 /* Machine Trap Setup */ 1877 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1878 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1879 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1880 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1881 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1882 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1883 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1884 1885 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1886 1887 /* Machine Trap Handling */ 1888 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1889 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1890 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1891 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1892 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1893 1894 /* Supervisor Trap Setup */ 1895 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1896 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1897 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1898 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1899 1900 /* Supervisor Trap Handling */ 1901 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1902 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1903 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1904 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1905 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1906 1907 /* Supervisor Protection and Translation */ 1908 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1909 1910 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1911 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1912 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1913 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1914 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1915 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1916 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1917 [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, 1918 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1919 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1920 [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, 1921 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1922 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1923 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1924 1925 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1926 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1927 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1928 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1929 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1930 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1931 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1932 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1933 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1934 1935 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1936 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1937 1938 /* Physical Memory Protection */ 1939 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1940 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1941 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1942 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1943 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1944 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1945 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1946 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1947 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1948 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1949 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1950 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1951 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1952 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1953 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1954 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1955 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1956 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1957 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1958 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1959 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1960 1961 /* User Pointer Masking */ 1962 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 1963 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 1964 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 1965 /* Machine Pointer Masking */ 1966 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 1967 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 1968 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 1969 /* Supervisor Pointer Masking */ 1970 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 1971 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 1972 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 1973 1974 /* Performance Counters */ 1975 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1976 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1977 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1978 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1979 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1980 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1981 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1982 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1983 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1984 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1985 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1986 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1987 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1988 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1989 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1990 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1991 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1992 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1993 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1994 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1995 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1996 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1997 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1998 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1999 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 2000 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 2001 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 2002 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 2003 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 2004 2005 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 2006 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 2007 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 2008 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 2009 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 2010 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 2011 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 2012 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 2013 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 2014 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 2015 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 2016 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 2017 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 2018 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 2019 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 2020 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 2021 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 2022 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 2023 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 2024 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 2025 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 2026 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 2027 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 2028 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 2029 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 2030 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 2031 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 2032 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 2033 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 2034 2035 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 2036 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 2037 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 2038 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 2039 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 2040 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 2041 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 2042 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 2043 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 2044 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 2045 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 2046 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 2047 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 2048 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 2049 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 2050 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 2051 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 2052 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 2053 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 2054 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 2055 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 2056 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 2057 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 2058 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 2059 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 2060 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 2061 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 2062 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 2063 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 2064 2065 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 2066 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 2067 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 2068 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 2069 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 2070 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 2071 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 2072 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 2073 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 2074 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 2075 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 2076 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 2077 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 2078 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 2079 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 2080 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 2081 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 2082 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 2083 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 2084 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 2085 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 2086 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 2087 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 2088 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 2089 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 2090 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 2091 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 2092 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 2093 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 2094 2095 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 2096 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 2097 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 2098 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 2099 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 2100 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 2101 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 2102 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 2103 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 2104 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 2105 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 2106 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 2107 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 2108 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 2109 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 2110 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 2111 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 2112 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 2113 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 2114 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 2115 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 2116 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 2117 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 2118 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 2119 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 2120 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 2121 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 2122 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 2123 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 2124 #endif /* !CONFIG_USER_ONLY */ 2125 }; 2126