1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa & RVV)) { 43 return RISCV_EXCP_NONE; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return RISCV_EXCP_NONE; 50 } 51 52 static RISCVException vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa & RVV) { 55 return RISCV_EXCP_NONE; 56 } 57 return RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static RISCVException ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 75 get_field(env->mcounteren, HCOUNTEREN_CY)) { 76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 81 get_field(env->mcounteren, HCOUNTEREN_TM)) { 82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 87 get_field(env->mcounteren, HCOUNTEREN_IR)) { 88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_is_32bit(env)) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 102 get_field(env->mcounteren, HCOUNTEREN_CY)) { 103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 108 get_field(env->mcounteren, HCOUNTEREN_TM)) { 109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 114 get_field(env->mcounteren, HCOUNTEREN_IR)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return RISCV_EXCP_NONE; 129 } 130 131 static RISCVException ctr32(CPURISCVState *env, int csrno) 132 { 133 if (!riscv_cpu_is_32bit(env)) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static RISCVException any(CPURISCVState *env, int csrno) 142 { 143 return RISCV_EXCP_NONE; 144 } 145 146 static RISCVException any32(CPURISCVState *env, int csrno) 147 { 148 if (!riscv_cpu_is_32bit(env)) { 149 return RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static RISCVException smode(CPURISCVState *env, int csrno) 157 { 158 if (riscv_has_ext(env, RVS)) { 159 return RISCV_EXCP_NONE; 160 } 161 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 static RISCVException hmode(CPURISCVState *env, int csrno) 166 { 167 if (riscv_has_ext(env, RVS) && 168 riscv_has_ext(env, RVH)) { 169 /* Hypervisor extension is supported */ 170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 171 env->priv == PRV_M) { 172 return RISCV_EXCP_NONE; 173 } else { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 } 177 178 return RISCV_EXCP_ILLEGAL_INST; 179 } 180 181 static RISCVException hmode32(CPURISCVState *env, int csrno) 182 { 183 if (!riscv_cpu_is_32bit(env)) { 184 if (riscv_cpu_virt_enabled(env)) { 185 return RISCV_EXCP_ILLEGAL_INST; 186 } else { 187 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 188 } 189 } 190 191 return hmode(env, csrno); 192 193 } 194 195 static RISCVException pmp(CPURISCVState *env, int csrno) 196 { 197 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 198 return RISCV_EXCP_NONE; 199 } 200 201 return RISCV_EXCP_ILLEGAL_INST; 202 } 203 204 static RISCVException epmp(CPURISCVState *env, int csrno) 205 { 206 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 207 return RISCV_EXCP_NONE; 208 } 209 210 return RISCV_EXCP_ILLEGAL_INST; 211 } 212 #endif 213 214 /* User Floating-Point CSRs */ 215 static RISCVException read_fflags(CPURISCVState *env, int csrno, 216 target_ulong *val) 217 { 218 *val = riscv_cpu_get_fflags(env); 219 return RISCV_EXCP_NONE; 220 } 221 222 static RISCVException write_fflags(CPURISCVState *env, int csrno, 223 target_ulong val) 224 { 225 #if !defined(CONFIG_USER_ONLY) 226 env->mstatus |= MSTATUS_FS; 227 #endif 228 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 229 return RISCV_EXCP_NONE; 230 } 231 232 static RISCVException read_frm(CPURISCVState *env, int csrno, 233 target_ulong *val) 234 { 235 *val = env->frm; 236 return RISCV_EXCP_NONE; 237 } 238 239 static RISCVException write_frm(CPURISCVState *env, int csrno, 240 target_ulong val) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 env->mstatus |= MSTATUS_FS; 244 #endif 245 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 246 return RISCV_EXCP_NONE; 247 } 248 249 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 250 target_ulong *val) 251 { 252 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 253 | (env->frm << FSR_RD_SHIFT); 254 if (vs(env, csrno) >= 0) { 255 *val |= (env->vxrm << FSR_VXRM_SHIFT) 256 | (env->vxsat << FSR_VXSAT_SHIFT); 257 } 258 return RISCV_EXCP_NONE; 259 } 260 261 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 262 target_ulong val) 263 { 264 #if !defined(CONFIG_USER_ONLY) 265 env->mstatus |= MSTATUS_FS; 266 #endif 267 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 268 if (vs(env, csrno) >= 0) { 269 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 270 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 271 } 272 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 273 return RISCV_EXCP_NONE; 274 } 275 276 static RISCVException read_vtype(CPURISCVState *env, int csrno, 277 target_ulong *val) 278 { 279 *val = env->vtype; 280 return RISCV_EXCP_NONE; 281 } 282 283 static RISCVException read_vl(CPURISCVState *env, int csrno, 284 target_ulong *val) 285 { 286 *val = env->vl; 287 return RISCV_EXCP_NONE; 288 } 289 290 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 291 target_ulong *val) 292 { 293 *val = env->vxrm; 294 return RISCV_EXCP_NONE; 295 } 296 297 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 298 target_ulong val) 299 { 300 env->vxrm = val; 301 return RISCV_EXCP_NONE; 302 } 303 304 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 305 target_ulong *val) 306 { 307 *val = env->vxsat; 308 return RISCV_EXCP_NONE; 309 } 310 311 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 312 target_ulong val) 313 { 314 env->vxsat = val; 315 return RISCV_EXCP_NONE; 316 } 317 318 static RISCVException read_vstart(CPURISCVState *env, int csrno, 319 target_ulong *val) 320 { 321 *val = env->vstart; 322 return RISCV_EXCP_NONE; 323 } 324 325 static RISCVException write_vstart(CPURISCVState *env, int csrno, 326 target_ulong val) 327 { 328 env->vstart = val; 329 return RISCV_EXCP_NONE; 330 } 331 332 /* User Timers and Counters */ 333 static RISCVException read_instret(CPURISCVState *env, int csrno, 334 target_ulong *val) 335 { 336 #if !defined(CONFIG_USER_ONLY) 337 if (icount_enabled()) { 338 *val = icount_get(); 339 } else { 340 *val = cpu_get_host_ticks(); 341 } 342 #else 343 *val = cpu_get_host_ticks(); 344 #endif 345 return RISCV_EXCP_NONE; 346 } 347 348 static RISCVException read_instreth(CPURISCVState *env, int csrno, 349 target_ulong *val) 350 { 351 #if !defined(CONFIG_USER_ONLY) 352 if (icount_enabled()) { 353 *val = icount_get() >> 32; 354 } else { 355 *val = cpu_get_host_ticks() >> 32; 356 } 357 #else 358 *val = cpu_get_host_ticks() >> 32; 359 #endif 360 return RISCV_EXCP_NONE; 361 } 362 363 #if defined(CONFIG_USER_ONLY) 364 static RISCVException read_time(CPURISCVState *env, int csrno, 365 target_ulong *val) 366 { 367 *val = cpu_get_host_ticks(); 368 return RISCV_EXCP_NONE; 369 } 370 371 static RISCVException read_timeh(CPURISCVState *env, int csrno, 372 target_ulong *val) 373 { 374 *val = cpu_get_host_ticks() >> 32; 375 return RISCV_EXCP_NONE; 376 } 377 378 #else /* CONFIG_USER_ONLY */ 379 380 static RISCVException read_time(CPURISCVState *env, int csrno, 381 target_ulong *val) 382 { 383 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 384 385 if (!env->rdtime_fn) { 386 return RISCV_EXCP_ILLEGAL_INST; 387 } 388 389 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 390 return RISCV_EXCP_NONE; 391 } 392 393 static RISCVException read_timeh(CPURISCVState *env, int csrno, 394 target_ulong *val) 395 { 396 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 397 398 if (!env->rdtime_fn) { 399 return RISCV_EXCP_ILLEGAL_INST; 400 } 401 402 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 403 return RISCV_EXCP_NONE; 404 } 405 406 /* Machine constants */ 407 408 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 409 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 410 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 411 412 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 413 VS_MODE_INTERRUPTS; 414 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; 415 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 416 VS_MODE_INTERRUPTS; 417 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 418 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 419 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 420 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 421 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 422 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 423 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 424 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 425 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 426 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 427 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 428 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 429 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 430 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 431 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 432 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 433 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 434 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 435 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 436 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 437 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 438 (1ULL << (RISCV_EXCP_VS_ECALL)) | 439 (1ULL << (RISCV_EXCP_M_ECALL)) | 440 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 441 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 442 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 443 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 444 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 445 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 446 SSTATUS_SUM | SSTATUS_MXR; 447 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 448 static const target_ulong hip_writable_mask = MIP_VSSIP; 449 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 450 static const target_ulong vsip_writable_mask = MIP_VSSIP; 451 452 static const char valid_vm_1_10_32[16] = { 453 [VM_1_10_MBARE] = 1, 454 [VM_1_10_SV32] = 1 455 }; 456 457 static const char valid_vm_1_10_64[16] = { 458 [VM_1_10_MBARE] = 1, 459 [VM_1_10_SV39] = 1, 460 [VM_1_10_SV48] = 1, 461 [VM_1_10_SV57] = 1 462 }; 463 464 /* Machine Information Registers */ 465 static RISCVException read_zero(CPURISCVState *env, int csrno, 466 target_ulong *val) 467 { 468 *val = 0; 469 return RISCV_EXCP_NONE; 470 } 471 472 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 473 target_ulong *val) 474 { 475 *val = env->mhartid; 476 return RISCV_EXCP_NONE; 477 } 478 479 /* Machine Trap Setup */ 480 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 481 target_ulong *val) 482 { 483 *val = env->mstatus; 484 return RISCV_EXCP_NONE; 485 } 486 487 static int validate_vm(CPURISCVState *env, target_ulong vm) 488 { 489 if (riscv_cpu_is_32bit(env)) { 490 return valid_vm_1_10_32[vm & 0xf]; 491 } else { 492 return valid_vm_1_10_64[vm & 0xf]; 493 } 494 } 495 496 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 497 target_ulong val) 498 { 499 uint64_t mstatus = env->mstatus; 500 uint64_t mask = 0; 501 int dirty; 502 503 /* flush tlb on mstatus fields that affect VM */ 504 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 505 MSTATUS_MPRV | MSTATUS_SUM)) { 506 tlb_flush(env_cpu(env)); 507 } 508 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 509 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 510 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 511 MSTATUS_TW; 512 513 if (!riscv_cpu_is_32bit(env)) { 514 /* 515 * RV32: MPV and GVA are not in mstatus. The current plan is to 516 * add them to mstatush. For now, we just don't support it. 517 */ 518 mask |= MSTATUS_MPV | MSTATUS_GVA; 519 } 520 521 mstatus = (mstatus & ~mask) | (val & mask); 522 523 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 524 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 525 if (riscv_cpu_is_32bit(env)) { 526 mstatus = set_field(mstatus, MSTATUS32_SD, dirty); 527 } else { 528 mstatus = set_field(mstatus, MSTATUS64_SD, dirty); 529 } 530 env->mstatus = mstatus; 531 532 return RISCV_EXCP_NONE; 533 } 534 535 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 536 target_ulong *val) 537 { 538 *val = env->mstatus >> 32; 539 return RISCV_EXCP_NONE; 540 } 541 542 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 543 target_ulong val) 544 { 545 uint64_t valh = (uint64_t)val << 32; 546 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 547 548 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 549 tlb_flush(env_cpu(env)); 550 } 551 552 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 553 554 return RISCV_EXCP_NONE; 555 } 556 557 static RISCVException read_misa(CPURISCVState *env, int csrno, 558 target_ulong *val) 559 { 560 *val = env->misa; 561 return RISCV_EXCP_NONE; 562 } 563 564 static RISCVException write_misa(CPURISCVState *env, int csrno, 565 target_ulong val) 566 { 567 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 568 /* drop write to misa */ 569 return RISCV_EXCP_NONE; 570 } 571 572 /* 'I' or 'E' must be present */ 573 if (!(val & (RVI | RVE))) { 574 /* It is not, drop write to misa */ 575 return RISCV_EXCP_NONE; 576 } 577 578 /* 'E' excludes all other extensions */ 579 if (val & RVE) { 580 /* when we support 'E' we can do "val = RVE;" however 581 * for now we just drop writes if 'E' is present. 582 */ 583 return RISCV_EXCP_NONE; 584 } 585 586 /* Mask extensions that are not supported by this hart */ 587 val &= env->misa_mask; 588 589 /* Mask extensions that are not supported by QEMU */ 590 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 591 592 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 593 if ((val & RVD) && !(val & RVF)) { 594 val &= ~RVD; 595 } 596 597 /* Suppress 'C' if next instruction is not aligned 598 * TODO: this should check next_pc 599 */ 600 if ((val & RVC) && (GETPC() & ~3) != 0) { 601 val &= ~RVC; 602 } 603 604 /* misa.MXL writes are not supported by QEMU */ 605 if (riscv_cpu_is_32bit(env)) { 606 val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); 607 } else { 608 val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); 609 } 610 611 /* flush translation cache */ 612 if (val != env->misa) { 613 tb_flush(env_cpu(env)); 614 } 615 616 env->misa = val; 617 618 return RISCV_EXCP_NONE; 619 } 620 621 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 622 target_ulong *val) 623 { 624 *val = env->medeleg; 625 return RISCV_EXCP_NONE; 626 } 627 628 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 629 target_ulong val) 630 { 631 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 632 return RISCV_EXCP_NONE; 633 } 634 635 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 636 target_ulong *val) 637 { 638 *val = env->mideleg; 639 return RISCV_EXCP_NONE; 640 } 641 642 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 643 target_ulong val) 644 { 645 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 646 if (riscv_has_ext(env, RVH)) { 647 env->mideleg |= VS_MODE_INTERRUPTS; 648 } 649 return RISCV_EXCP_NONE; 650 } 651 652 static RISCVException read_mie(CPURISCVState *env, int csrno, 653 target_ulong *val) 654 { 655 *val = env->mie; 656 return RISCV_EXCP_NONE; 657 } 658 659 static RISCVException write_mie(CPURISCVState *env, int csrno, 660 target_ulong val) 661 { 662 env->mie = (env->mie & ~all_ints) | (val & all_ints); 663 return RISCV_EXCP_NONE; 664 } 665 666 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 667 target_ulong *val) 668 { 669 *val = env->mtvec; 670 return RISCV_EXCP_NONE; 671 } 672 673 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 674 target_ulong val) 675 { 676 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 677 if ((val & 3) < 2) { 678 env->mtvec = val; 679 } else { 680 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 681 } 682 return RISCV_EXCP_NONE; 683 } 684 685 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 686 target_ulong *val) 687 { 688 *val = env->mcounteren; 689 return RISCV_EXCP_NONE; 690 } 691 692 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 693 target_ulong val) 694 { 695 env->mcounteren = val; 696 return RISCV_EXCP_NONE; 697 } 698 699 /* Machine Trap Handling */ 700 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 701 target_ulong *val) 702 { 703 *val = env->mscratch; 704 return RISCV_EXCP_NONE; 705 } 706 707 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 708 target_ulong val) 709 { 710 env->mscratch = val; 711 return RISCV_EXCP_NONE; 712 } 713 714 static RISCVException read_mepc(CPURISCVState *env, int csrno, 715 target_ulong *val) 716 { 717 *val = env->mepc; 718 return RISCV_EXCP_NONE; 719 } 720 721 static RISCVException write_mepc(CPURISCVState *env, int csrno, 722 target_ulong val) 723 { 724 env->mepc = val; 725 return RISCV_EXCP_NONE; 726 } 727 728 static RISCVException read_mcause(CPURISCVState *env, int csrno, 729 target_ulong *val) 730 { 731 *val = env->mcause; 732 return RISCV_EXCP_NONE; 733 } 734 735 static RISCVException write_mcause(CPURISCVState *env, int csrno, 736 target_ulong val) 737 { 738 env->mcause = val; 739 return RISCV_EXCP_NONE; 740 } 741 742 static RISCVException read_mtval(CPURISCVState *env, int csrno, 743 target_ulong *val) 744 { 745 *val = env->mtval; 746 return RISCV_EXCP_NONE; 747 } 748 749 static RISCVException write_mtval(CPURISCVState *env, int csrno, 750 target_ulong val) 751 { 752 env->mtval = val; 753 return RISCV_EXCP_NONE; 754 } 755 756 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 757 target_ulong *ret_value, 758 target_ulong new_value, target_ulong write_mask) 759 { 760 RISCVCPU *cpu = env_archcpu(env); 761 /* Allow software control of delegable interrupts not claimed by hardware */ 762 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 763 uint32_t old_mip; 764 765 if (mask) { 766 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 767 } else { 768 old_mip = env->mip; 769 } 770 771 if (ret_value) { 772 *ret_value = old_mip; 773 } 774 775 return RISCV_EXCP_NONE; 776 } 777 778 /* Supervisor Trap Setup */ 779 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 780 target_ulong *val) 781 { 782 target_ulong mask = (sstatus_v1_10_mask); 783 784 if (riscv_cpu_is_32bit(env)) { 785 mask |= SSTATUS32_SD; 786 } else { 787 mask |= SSTATUS64_SD; 788 } 789 790 *val = env->mstatus & mask; 791 return RISCV_EXCP_NONE; 792 } 793 794 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 795 target_ulong val) 796 { 797 target_ulong mask = (sstatus_v1_10_mask); 798 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 799 return write_mstatus(env, CSR_MSTATUS, newval); 800 } 801 802 static RISCVException read_vsie(CPURISCVState *env, int csrno, 803 target_ulong *val) 804 { 805 /* Shift the VS bits to their S bit location in vsie */ 806 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 807 return RISCV_EXCP_NONE; 808 } 809 810 static RISCVException read_sie(CPURISCVState *env, int csrno, 811 target_ulong *val) 812 { 813 if (riscv_cpu_virt_enabled(env)) { 814 read_vsie(env, CSR_VSIE, val); 815 } else { 816 *val = env->mie & env->mideleg; 817 } 818 return RISCV_EXCP_NONE; 819 } 820 821 static RISCVException write_vsie(CPURISCVState *env, int csrno, 822 target_ulong val) 823 { 824 /* Shift the S bits to their VS bit location in mie */ 825 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 826 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 827 return write_mie(env, CSR_MIE, newval); 828 } 829 830 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 831 { 832 if (riscv_cpu_virt_enabled(env)) { 833 write_vsie(env, CSR_VSIE, val); 834 } else { 835 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 836 (val & S_MODE_INTERRUPTS); 837 write_mie(env, CSR_MIE, newval); 838 } 839 840 return RISCV_EXCP_NONE; 841 } 842 843 static RISCVException read_stvec(CPURISCVState *env, int csrno, 844 target_ulong *val) 845 { 846 *val = env->stvec; 847 return RISCV_EXCP_NONE; 848 } 849 850 static RISCVException write_stvec(CPURISCVState *env, int csrno, 851 target_ulong val) 852 { 853 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 854 if ((val & 3) < 2) { 855 env->stvec = val; 856 } else { 857 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 858 } 859 return RISCV_EXCP_NONE; 860 } 861 862 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 863 target_ulong *val) 864 { 865 *val = env->scounteren; 866 return RISCV_EXCP_NONE; 867 } 868 869 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 870 target_ulong val) 871 { 872 env->scounteren = val; 873 return RISCV_EXCP_NONE; 874 } 875 876 /* Supervisor Trap Handling */ 877 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 878 target_ulong *val) 879 { 880 *val = env->sscratch; 881 return RISCV_EXCP_NONE; 882 } 883 884 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 885 target_ulong val) 886 { 887 env->sscratch = val; 888 return RISCV_EXCP_NONE; 889 } 890 891 static RISCVException read_sepc(CPURISCVState *env, int csrno, 892 target_ulong *val) 893 { 894 *val = env->sepc; 895 return RISCV_EXCP_NONE; 896 } 897 898 static RISCVException write_sepc(CPURISCVState *env, int csrno, 899 target_ulong val) 900 { 901 env->sepc = val; 902 return RISCV_EXCP_NONE; 903 } 904 905 static RISCVException read_scause(CPURISCVState *env, int csrno, 906 target_ulong *val) 907 { 908 *val = env->scause; 909 return RISCV_EXCP_NONE; 910 } 911 912 static RISCVException write_scause(CPURISCVState *env, int csrno, 913 target_ulong val) 914 { 915 env->scause = val; 916 return RISCV_EXCP_NONE; 917 } 918 919 static RISCVException read_stval(CPURISCVState *env, int csrno, 920 target_ulong *val) 921 { 922 *val = env->stval; 923 return RISCV_EXCP_NONE; 924 } 925 926 static RISCVException write_stval(CPURISCVState *env, int csrno, 927 target_ulong val) 928 { 929 env->stval = val; 930 return RISCV_EXCP_NONE; 931 } 932 933 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 934 target_ulong *ret_value, 935 target_ulong new_value, target_ulong write_mask) 936 { 937 /* Shift the S bits to their VS bit location in mip */ 938 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 939 (write_mask << 1) & vsip_writable_mask & env->hideleg); 940 *ret_value &= VS_MODE_INTERRUPTS; 941 /* Shift the VS bits to their S bit location in vsip */ 942 *ret_value >>= 1; 943 return ret; 944 } 945 946 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 947 target_ulong *ret_value, 948 target_ulong new_value, target_ulong write_mask) 949 { 950 int ret; 951 952 if (riscv_cpu_virt_enabled(env)) { 953 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 954 } else { 955 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 956 write_mask & env->mideleg & sip_writable_mask); 957 } 958 959 *ret_value &= env->mideleg; 960 return ret; 961 } 962 963 /* Supervisor Protection and Translation */ 964 static RISCVException read_satp(CPURISCVState *env, int csrno, 965 target_ulong *val) 966 { 967 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 968 *val = 0; 969 return RISCV_EXCP_NONE; 970 } 971 972 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 973 return RISCV_EXCP_ILLEGAL_INST; 974 } else { 975 *val = env->satp; 976 } 977 978 return RISCV_EXCP_NONE; 979 } 980 981 static RISCVException write_satp(CPURISCVState *env, int csrno, 982 target_ulong val) 983 { 984 int vm, mask, asid; 985 986 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 987 return RISCV_EXCP_NONE; 988 } 989 990 if (riscv_cpu_is_32bit(env)) { 991 vm = validate_vm(env, get_field(val, SATP32_MODE)); 992 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 993 asid = (val ^ env->satp) & SATP32_ASID; 994 } else { 995 vm = validate_vm(env, get_field(val, SATP64_MODE)); 996 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 997 asid = (val ^ env->satp) & SATP64_ASID; 998 } 999 1000 if (vm && mask) { 1001 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1002 return RISCV_EXCP_ILLEGAL_INST; 1003 } else { 1004 if (asid) { 1005 tlb_flush(env_cpu(env)); 1006 } 1007 env->satp = val; 1008 } 1009 } 1010 return RISCV_EXCP_NONE; 1011 } 1012 1013 /* Hypervisor Extensions */ 1014 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1015 target_ulong *val) 1016 { 1017 *val = env->hstatus; 1018 if (!riscv_cpu_is_32bit(env)) { 1019 /* We only support 64-bit VSXL */ 1020 *val = set_field(*val, HSTATUS_VSXL, 2); 1021 } 1022 /* We only support little endian */ 1023 *val = set_field(*val, HSTATUS_VSBE, 0); 1024 return RISCV_EXCP_NONE; 1025 } 1026 1027 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1028 target_ulong val) 1029 { 1030 env->hstatus = val; 1031 if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { 1032 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1033 } 1034 if (get_field(val, HSTATUS_VSBE) != 0) { 1035 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1036 } 1037 return RISCV_EXCP_NONE; 1038 } 1039 1040 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1041 target_ulong *val) 1042 { 1043 *val = env->hedeleg; 1044 return RISCV_EXCP_NONE; 1045 } 1046 1047 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1048 target_ulong val) 1049 { 1050 env->hedeleg = val & vs_delegable_excps; 1051 return RISCV_EXCP_NONE; 1052 } 1053 1054 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1055 target_ulong *val) 1056 { 1057 *val = env->hideleg; 1058 return RISCV_EXCP_NONE; 1059 } 1060 1061 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1062 target_ulong val) 1063 { 1064 env->hideleg = val & vs_delegable_ints; 1065 return RISCV_EXCP_NONE; 1066 } 1067 1068 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1069 target_ulong *ret_value, 1070 target_ulong new_value, target_ulong write_mask) 1071 { 1072 int ret = rmw_mip(env, 0, ret_value, new_value, 1073 write_mask & hvip_writable_mask); 1074 1075 *ret_value &= hvip_writable_mask; 1076 1077 return ret; 1078 } 1079 1080 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1081 target_ulong *ret_value, 1082 target_ulong new_value, target_ulong write_mask) 1083 { 1084 int ret = rmw_mip(env, 0, ret_value, new_value, 1085 write_mask & hip_writable_mask); 1086 1087 *ret_value &= hip_writable_mask; 1088 1089 return ret; 1090 } 1091 1092 static RISCVException read_hie(CPURISCVState *env, int csrno, 1093 target_ulong *val) 1094 { 1095 *val = env->mie & VS_MODE_INTERRUPTS; 1096 return RISCV_EXCP_NONE; 1097 } 1098 1099 static RISCVException write_hie(CPURISCVState *env, int csrno, 1100 target_ulong val) 1101 { 1102 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1103 return write_mie(env, CSR_MIE, newval); 1104 } 1105 1106 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1107 target_ulong *val) 1108 { 1109 *val = env->hcounteren; 1110 return RISCV_EXCP_NONE; 1111 } 1112 1113 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1114 target_ulong val) 1115 { 1116 env->hcounteren = val; 1117 return RISCV_EXCP_NONE; 1118 } 1119 1120 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 1121 target_ulong *val) 1122 { 1123 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1124 return RISCV_EXCP_NONE; 1125 } 1126 1127 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1128 target_ulong val) 1129 { 1130 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1131 return RISCV_EXCP_NONE; 1132 } 1133 1134 static RISCVException read_htval(CPURISCVState *env, int csrno, 1135 target_ulong *val) 1136 { 1137 *val = env->htval; 1138 return RISCV_EXCP_NONE; 1139 } 1140 1141 static RISCVException write_htval(CPURISCVState *env, int csrno, 1142 target_ulong val) 1143 { 1144 env->htval = val; 1145 return RISCV_EXCP_NONE; 1146 } 1147 1148 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1149 target_ulong *val) 1150 { 1151 *val = env->htinst; 1152 return RISCV_EXCP_NONE; 1153 } 1154 1155 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1156 target_ulong val) 1157 { 1158 return RISCV_EXCP_NONE; 1159 } 1160 1161 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 1162 target_ulong *val) 1163 { 1164 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1165 return RISCV_EXCP_NONE; 1166 } 1167 1168 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1169 target_ulong val) 1170 { 1171 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1172 return RISCV_EXCP_NONE; 1173 } 1174 1175 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1176 target_ulong *val) 1177 { 1178 *val = env->hgatp; 1179 return RISCV_EXCP_NONE; 1180 } 1181 1182 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1183 target_ulong val) 1184 { 1185 env->hgatp = val; 1186 return RISCV_EXCP_NONE; 1187 } 1188 1189 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1190 target_ulong *val) 1191 { 1192 if (!env->rdtime_fn) { 1193 return RISCV_EXCP_ILLEGAL_INST; 1194 } 1195 1196 *val = env->htimedelta; 1197 return RISCV_EXCP_NONE; 1198 } 1199 1200 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1201 target_ulong val) 1202 { 1203 if (!env->rdtime_fn) { 1204 return RISCV_EXCP_ILLEGAL_INST; 1205 } 1206 1207 if (riscv_cpu_is_32bit(env)) { 1208 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1209 } else { 1210 env->htimedelta = val; 1211 } 1212 return RISCV_EXCP_NONE; 1213 } 1214 1215 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1216 target_ulong *val) 1217 { 1218 if (!env->rdtime_fn) { 1219 return RISCV_EXCP_ILLEGAL_INST; 1220 } 1221 1222 *val = env->htimedelta >> 32; 1223 return RISCV_EXCP_NONE; 1224 } 1225 1226 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1227 target_ulong val) 1228 { 1229 if (!env->rdtime_fn) { 1230 return RISCV_EXCP_ILLEGAL_INST; 1231 } 1232 1233 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1234 return RISCV_EXCP_NONE; 1235 } 1236 1237 /* Virtual CSR Registers */ 1238 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1239 target_ulong *val) 1240 { 1241 *val = env->vsstatus; 1242 return RISCV_EXCP_NONE; 1243 } 1244 1245 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1246 target_ulong val) 1247 { 1248 uint64_t mask = (target_ulong)-1; 1249 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1250 return RISCV_EXCP_NONE; 1251 } 1252 1253 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1254 { 1255 *val = env->vstvec; 1256 return RISCV_EXCP_NONE; 1257 } 1258 1259 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1260 target_ulong val) 1261 { 1262 env->vstvec = val; 1263 return RISCV_EXCP_NONE; 1264 } 1265 1266 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1267 target_ulong *val) 1268 { 1269 *val = env->vsscratch; 1270 return RISCV_EXCP_NONE; 1271 } 1272 1273 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1274 target_ulong val) 1275 { 1276 env->vsscratch = val; 1277 return RISCV_EXCP_NONE; 1278 } 1279 1280 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1281 target_ulong *val) 1282 { 1283 *val = env->vsepc; 1284 return RISCV_EXCP_NONE; 1285 } 1286 1287 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1288 target_ulong val) 1289 { 1290 env->vsepc = val; 1291 return RISCV_EXCP_NONE; 1292 } 1293 1294 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1295 target_ulong *val) 1296 { 1297 *val = env->vscause; 1298 return RISCV_EXCP_NONE; 1299 } 1300 1301 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1302 target_ulong val) 1303 { 1304 env->vscause = val; 1305 return RISCV_EXCP_NONE; 1306 } 1307 1308 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1309 target_ulong *val) 1310 { 1311 *val = env->vstval; 1312 return RISCV_EXCP_NONE; 1313 } 1314 1315 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1316 target_ulong val) 1317 { 1318 env->vstval = val; 1319 return RISCV_EXCP_NONE; 1320 } 1321 1322 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1323 target_ulong *val) 1324 { 1325 *val = env->vsatp; 1326 return RISCV_EXCP_NONE; 1327 } 1328 1329 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1330 target_ulong val) 1331 { 1332 env->vsatp = val; 1333 return RISCV_EXCP_NONE; 1334 } 1335 1336 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1337 target_ulong *val) 1338 { 1339 *val = env->mtval2; 1340 return RISCV_EXCP_NONE; 1341 } 1342 1343 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1344 target_ulong val) 1345 { 1346 env->mtval2 = val; 1347 return RISCV_EXCP_NONE; 1348 } 1349 1350 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1351 target_ulong *val) 1352 { 1353 *val = env->mtinst; 1354 return RISCV_EXCP_NONE; 1355 } 1356 1357 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1358 target_ulong val) 1359 { 1360 env->mtinst = val; 1361 return RISCV_EXCP_NONE; 1362 } 1363 1364 /* Physical Memory Protection */ 1365 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1366 target_ulong *val) 1367 { 1368 *val = mseccfg_csr_read(env); 1369 return RISCV_EXCP_NONE; 1370 } 1371 1372 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1373 target_ulong val) 1374 { 1375 mseccfg_csr_write(env, val); 1376 return RISCV_EXCP_NONE; 1377 } 1378 1379 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1380 target_ulong *val) 1381 { 1382 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1383 return RISCV_EXCP_NONE; 1384 } 1385 1386 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1387 target_ulong val) 1388 { 1389 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1390 return RISCV_EXCP_NONE; 1391 } 1392 1393 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1394 target_ulong *val) 1395 { 1396 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1397 return RISCV_EXCP_NONE; 1398 } 1399 1400 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1401 target_ulong val) 1402 { 1403 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1404 return RISCV_EXCP_NONE; 1405 } 1406 1407 #endif 1408 1409 /* 1410 * riscv_csrrw - read and/or update control and status register 1411 * 1412 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1413 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1414 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1415 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1416 */ 1417 1418 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1419 target_ulong *ret_value, 1420 target_ulong new_value, target_ulong write_mask) 1421 { 1422 RISCVException ret; 1423 target_ulong old_value; 1424 RISCVCPU *cpu = env_archcpu(env); 1425 1426 /* check privileges and return -1 if check fails */ 1427 #if !defined(CONFIG_USER_ONLY) 1428 int effective_priv = env->priv; 1429 int read_only = get_field(csrno, 0xC00) == 3; 1430 1431 if (riscv_has_ext(env, RVH) && 1432 env->priv == PRV_S && 1433 !riscv_cpu_virt_enabled(env)) { 1434 /* 1435 * We are in S mode without virtualisation, therefore we are in HS Mode. 1436 * Add 1 to the effective privledge level to allow us to access the 1437 * Hypervisor CSRs. 1438 */ 1439 effective_priv++; 1440 } 1441 1442 if ((write_mask && read_only) || 1443 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1444 return RISCV_EXCP_ILLEGAL_INST; 1445 } 1446 #endif 1447 1448 /* ensure the CSR extension is enabled. */ 1449 if (!cpu->cfg.ext_icsr) { 1450 return RISCV_EXCP_ILLEGAL_INST; 1451 } 1452 1453 /* check predicate */ 1454 if (!csr_ops[csrno].predicate) { 1455 return RISCV_EXCP_ILLEGAL_INST; 1456 } 1457 ret = csr_ops[csrno].predicate(env, csrno); 1458 if (ret != RISCV_EXCP_NONE) { 1459 return ret; 1460 } 1461 1462 /* execute combined read/write operation if it exists */ 1463 if (csr_ops[csrno].op) { 1464 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1465 } 1466 1467 /* if no accessor exists then return failure */ 1468 if (!csr_ops[csrno].read) { 1469 return RISCV_EXCP_ILLEGAL_INST; 1470 } 1471 /* read old value */ 1472 ret = csr_ops[csrno].read(env, csrno, &old_value); 1473 if (ret != RISCV_EXCP_NONE) { 1474 return ret; 1475 } 1476 1477 /* write value if writable and write mask set, otherwise drop writes */ 1478 if (write_mask) { 1479 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1480 if (csr_ops[csrno].write) { 1481 ret = csr_ops[csrno].write(env, csrno, new_value); 1482 if (ret != RISCV_EXCP_NONE) { 1483 return ret; 1484 } 1485 } 1486 } 1487 1488 /* return old value */ 1489 if (ret_value) { 1490 *ret_value = old_value; 1491 } 1492 1493 return RISCV_EXCP_NONE; 1494 } 1495 1496 /* 1497 * Debugger support. If not in user mode, set env->debugger before the 1498 * riscv_csrrw call and clear it after the call. 1499 */ 1500 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1501 target_ulong *ret_value, 1502 target_ulong new_value, 1503 target_ulong write_mask) 1504 { 1505 RISCVException ret; 1506 #if !defined(CONFIG_USER_ONLY) 1507 env->debugger = true; 1508 #endif 1509 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1510 #if !defined(CONFIG_USER_ONLY) 1511 env->debugger = false; 1512 #endif 1513 return ret; 1514 } 1515 1516 /* Control and Status Register function table */ 1517 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1518 /* User Floating-Point CSRs */ 1519 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1520 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1521 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1522 /* Vector CSRs */ 1523 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1524 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1525 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1526 [CSR_VL] = { "vl", vs, read_vl }, 1527 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1528 /* User Timers and Counters */ 1529 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1530 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1531 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1532 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1533 1534 /* 1535 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1536 * rdtime callback is not provided by machine/platform emulation. 1537 */ 1538 [CSR_TIME] = { "time", ctr, read_time }, 1539 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1540 1541 #if !defined(CONFIG_USER_ONLY) 1542 /* Machine Timers and Counters */ 1543 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1544 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1545 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1546 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1547 1548 /* Machine Information Registers */ 1549 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1550 [CSR_MARCHID] = { "marchid", any, read_zero }, 1551 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1552 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1553 1554 /* Machine Trap Setup */ 1555 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1556 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1557 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1558 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1559 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1560 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1561 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1562 1563 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1564 1565 /* Machine Trap Handling */ 1566 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1567 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1568 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1569 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1570 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1571 1572 /* Supervisor Trap Setup */ 1573 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1574 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1575 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1576 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1577 1578 /* Supervisor Trap Handling */ 1579 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1580 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1581 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1582 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1583 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1584 1585 /* Supervisor Protection and Translation */ 1586 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1587 1588 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1589 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1590 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1591 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1592 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1593 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1594 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1595 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, 1596 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1597 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1598 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, 1599 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1600 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1601 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1602 1603 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1604 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1605 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1606 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1607 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1608 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1609 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1610 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1611 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1612 1613 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1614 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1615 1616 /* Physical Memory Protection */ 1617 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1618 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1619 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1620 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1621 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1622 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1623 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1624 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1625 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1626 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1627 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1628 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1629 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1630 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1631 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1632 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1633 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1634 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1635 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1636 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1637 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1638 1639 /* Performance Counters */ 1640 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1641 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1642 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1643 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1644 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1645 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1646 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1647 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1648 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1649 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1650 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1651 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1652 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1653 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1654 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1655 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1656 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1657 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1658 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1659 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1660 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1661 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1662 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1663 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1664 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1665 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1666 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1667 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1668 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1669 1670 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1671 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1672 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1673 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1674 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1675 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1676 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1677 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1678 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1679 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1680 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1681 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 1682 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 1683 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 1684 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 1685 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 1686 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 1687 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 1688 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 1689 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 1690 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 1691 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 1692 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 1693 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 1694 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 1695 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 1696 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 1697 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 1698 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 1699 1700 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 1701 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 1702 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 1703 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 1704 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 1705 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 1706 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 1707 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 1708 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 1709 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 1710 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 1711 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 1712 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 1713 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 1714 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 1715 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 1716 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 1717 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 1718 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 1719 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 1720 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 1721 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 1722 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 1723 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 1724 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 1725 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 1726 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 1727 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 1728 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 1729 1730 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 1731 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 1732 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 1733 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 1734 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 1735 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 1736 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 1737 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 1738 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 1739 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 1740 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 1741 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 1742 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 1743 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 1744 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 1745 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 1746 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 1747 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 1748 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 1749 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 1750 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 1751 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 1752 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 1753 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 1754 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 1755 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 1756 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 1757 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 1758 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 1759 1760 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 1761 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 1762 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 1763 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 1764 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 1765 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 1766 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 1767 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 1768 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 1769 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 1770 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 1771 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 1772 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 1773 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 1774 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 1775 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 1776 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 1777 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 1778 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 1779 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 1780 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 1781 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 1782 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 1783 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 1784 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 1785 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 1786 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 1787 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 1788 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 1789 #endif /* !CONFIG_USER_ONLY */ 1790 }; 1791