1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { 43 return RISCV_EXCP_NONE; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return RISCV_EXCP_NONE; 50 } 51 52 static RISCVException vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa_ext & RVV) { 55 return RISCV_EXCP_NONE; 56 } 57 return RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static RISCVException ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, COUNTEREN_CY) && 75 get_field(env->mcounteren, COUNTEREN_CY)) { 76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, COUNTEREN_TM) && 81 get_field(env->mcounteren, COUNTEREN_TM)) { 82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, COUNTEREN_IR) && 87 get_field(env->mcounteren, COUNTEREN_IR)) { 88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_mxl(env) == MXL_RV32) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, COUNTEREN_CY) && 102 get_field(env->mcounteren, COUNTEREN_CY)) { 103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, COUNTEREN_TM) && 108 get_field(env->mcounteren, COUNTEREN_TM)) { 109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, COUNTEREN_IR) && 114 get_field(env->mcounteren, COUNTEREN_IR)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return RISCV_EXCP_NONE; 129 } 130 131 static RISCVException ctr32(CPURISCVState *env, int csrno) 132 { 133 if (riscv_cpu_mxl(env) != MXL_RV32) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static RISCVException any(CPURISCVState *env, int csrno) 142 { 143 return RISCV_EXCP_NONE; 144 } 145 146 static RISCVException any32(CPURISCVState *env, int csrno) 147 { 148 if (riscv_cpu_mxl(env) != MXL_RV32) { 149 return RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static RISCVException smode(CPURISCVState *env, int csrno) 157 { 158 if (riscv_has_ext(env, RVS)) { 159 return RISCV_EXCP_NONE; 160 } 161 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 static RISCVException hmode(CPURISCVState *env, int csrno) 166 { 167 if (riscv_has_ext(env, RVS) && 168 riscv_has_ext(env, RVH)) { 169 /* Hypervisor extension is supported */ 170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 171 env->priv == PRV_M) { 172 return RISCV_EXCP_NONE; 173 } else { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 } 177 178 return RISCV_EXCP_ILLEGAL_INST; 179 } 180 181 static RISCVException hmode32(CPURISCVState *env, int csrno) 182 { 183 if (riscv_cpu_mxl(env) != MXL_RV32) { 184 if (riscv_cpu_virt_enabled(env)) { 185 return RISCV_EXCP_ILLEGAL_INST; 186 } else { 187 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 188 } 189 } 190 191 return hmode(env, csrno); 192 193 } 194 195 /* Checks if PointerMasking registers could be accessed */ 196 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 197 { 198 /* Check if j-ext is present */ 199 if (riscv_has_ext(env, RVJ)) { 200 return RISCV_EXCP_NONE; 201 } 202 return RISCV_EXCP_ILLEGAL_INST; 203 } 204 205 static RISCVException pmp(CPURISCVState *env, int csrno) 206 { 207 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 208 return RISCV_EXCP_NONE; 209 } 210 211 return RISCV_EXCP_ILLEGAL_INST; 212 } 213 214 static RISCVException epmp(CPURISCVState *env, int csrno) 215 { 216 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 217 return RISCV_EXCP_NONE; 218 } 219 220 return RISCV_EXCP_ILLEGAL_INST; 221 } 222 #endif 223 224 /* User Floating-Point CSRs */ 225 static RISCVException read_fflags(CPURISCVState *env, int csrno, 226 target_ulong *val) 227 { 228 *val = riscv_cpu_get_fflags(env); 229 return RISCV_EXCP_NONE; 230 } 231 232 static RISCVException write_fflags(CPURISCVState *env, int csrno, 233 target_ulong val) 234 { 235 #if !defined(CONFIG_USER_ONLY) 236 env->mstatus |= MSTATUS_FS; 237 #endif 238 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 239 return RISCV_EXCP_NONE; 240 } 241 242 static RISCVException read_frm(CPURISCVState *env, int csrno, 243 target_ulong *val) 244 { 245 *val = env->frm; 246 return RISCV_EXCP_NONE; 247 } 248 249 static RISCVException write_frm(CPURISCVState *env, int csrno, 250 target_ulong val) 251 { 252 #if !defined(CONFIG_USER_ONLY) 253 env->mstatus |= MSTATUS_FS; 254 #endif 255 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 256 return RISCV_EXCP_NONE; 257 } 258 259 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 260 target_ulong *val) 261 { 262 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 263 | (env->frm << FSR_RD_SHIFT); 264 if (vs(env, csrno) >= 0) { 265 *val |= (env->vxrm << FSR_VXRM_SHIFT) 266 | (env->vxsat << FSR_VXSAT_SHIFT); 267 } 268 return RISCV_EXCP_NONE; 269 } 270 271 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 272 target_ulong val) 273 { 274 #if !defined(CONFIG_USER_ONLY) 275 env->mstatus |= MSTATUS_FS; 276 env->mstatus |= MSTATUS_VS; 277 #endif 278 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 279 if (vs(env, csrno) >= 0) { 280 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 281 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 282 } 283 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 284 return RISCV_EXCP_NONE; 285 } 286 287 static RISCVException read_vtype(CPURISCVState *env, int csrno, 288 target_ulong *val) 289 { 290 *val = env->vtype; 291 return RISCV_EXCP_NONE; 292 } 293 294 static RISCVException read_vl(CPURISCVState *env, int csrno, 295 target_ulong *val) 296 { 297 *val = env->vl; 298 return RISCV_EXCP_NONE; 299 } 300 301 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 302 target_ulong *val) 303 { 304 *val = env->vxrm; 305 return RISCV_EXCP_NONE; 306 } 307 308 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 309 target_ulong val) 310 { 311 #if !defined(CONFIG_USER_ONLY) 312 env->mstatus |= MSTATUS_VS; 313 #endif 314 env->vxrm = val; 315 return RISCV_EXCP_NONE; 316 } 317 318 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 319 target_ulong *val) 320 { 321 *val = env->vxsat; 322 return RISCV_EXCP_NONE; 323 } 324 325 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 326 target_ulong val) 327 { 328 #if !defined(CONFIG_USER_ONLY) 329 env->mstatus |= MSTATUS_VS; 330 #endif 331 env->vxsat = val; 332 return RISCV_EXCP_NONE; 333 } 334 335 static RISCVException read_vstart(CPURISCVState *env, int csrno, 336 target_ulong *val) 337 { 338 *val = env->vstart; 339 return RISCV_EXCP_NONE; 340 } 341 342 static RISCVException write_vstart(CPURISCVState *env, int csrno, 343 target_ulong val) 344 { 345 #if !defined(CONFIG_USER_ONLY) 346 env->mstatus |= MSTATUS_VS; 347 #endif 348 env->vstart = val; 349 return RISCV_EXCP_NONE; 350 } 351 352 /* User Timers and Counters */ 353 static RISCVException read_instret(CPURISCVState *env, int csrno, 354 target_ulong *val) 355 { 356 #if !defined(CONFIG_USER_ONLY) 357 if (icount_enabled()) { 358 *val = icount_get(); 359 } else { 360 *val = cpu_get_host_ticks(); 361 } 362 #else 363 *val = cpu_get_host_ticks(); 364 #endif 365 return RISCV_EXCP_NONE; 366 } 367 368 static RISCVException read_instreth(CPURISCVState *env, int csrno, 369 target_ulong *val) 370 { 371 #if !defined(CONFIG_USER_ONLY) 372 if (icount_enabled()) { 373 *val = icount_get() >> 32; 374 } else { 375 *val = cpu_get_host_ticks() >> 32; 376 } 377 #else 378 *val = cpu_get_host_ticks() >> 32; 379 #endif 380 return RISCV_EXCP_NONE; 381 } 382 383 #if defined(CONFIG_USER_ONLY) 384 static RISCVException read_time(CPURISCVState *env, int csrno, 385 target_ulong *val) 386 { 387 *val = cpu_get_host_ticks(); 388 return RISCV_EXCP_NONE; 389 } 390 391 static RISCVException read_timeh(CPURISCVState *env, int csrno, 392 target_ulong *val) 393 { 394 *val = cpu_get_host_ticks() >> 32; 395 return RISCV_EXCP_NONE; 396 } 397 398 #else /* CONFIG_USER_ONLY */ 399 400 static RISCVException read_time(CPURISCVState *env, int csrno, 401 target_ulong *val) 402 { 403 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 404 405 if (!env->rdtime_fn) { 406 return RISCV_EXCP_ILLEGAL_INST; 407 } 408 409 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 410 return RISCV_EXCP_NONE; 411 } 412 413 static RISCVException read_timeh(CPURISCVState *env, int csrno, 414 target_ulong *val) 415 { 416 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 417 418 if (!env->rdtime_fn) { 419 return RISCV_EXCP_ILLEGAL_INST; 420 } 421 422 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 423 return RISCV_EXCP_NONE; 424 } 425 426 /* Machine constants */ 427 428 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 429 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 430 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 431 432 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 433 VS_MODE_INTERRUPTS; 434 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; 435 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 436 VS_MODE_INTERRUPTS; 437 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 438 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 439 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 440 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 441 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 442 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 443 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 444 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 445 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 446 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 447 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 448 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 449 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 450 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 451 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 452 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 453 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 454 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 455 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 456 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 457 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 458 (1ULL << (RISCV_EXCP_VS_ECALL)) | 459 (1ULL << (RISCV_EXCP_M_ECALL)) | 460 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 461 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 462 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 463 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 464 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 465 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 466 SSTATUS_SUM | SSTATUS_MXR; 467 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 468 static const target_ulong hip_writable_mask = MIP_VSSIP; 469 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 470 static const target_ulong vsip_writable_mask = MIP_VSSIP; 471 472 static const char valid_vm_1_10_32[16] = { 473 [VM_1_10_MBARE] = 1, 474 [VM_1_10_SV32] = 1 475 }; 476 477 static const char valid_vm_1_10_64[16] = { 478 [VM_1_10_MBARE] = 1, 479 [VM_1_10_SV39] = 1, 480 [VM_1_10_SV48] = 1, 481 [VM_1_10_SV57] = 1 482 }; 483 484 /* Machine Information Registers */ 485 static RISCVException read_zero(CPURISCVState *env, int csrno, 486 target_ulong *val) 487 { 488 *val = 0; 489 return RISCV_EXCP_NONE; 490 } 491 492 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 493 target_ulong *val) 494 { 495 *val = env->mhartid; 496 return RISCV_EXCP_NONE; 497 } 498 499 /* Machine Trap Setup */ 500 501 /* We do not store SD explicitly, only compute it on demand. */ 502 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 503 { 504 if ((status & MSTATUS_FS) == MSTATUS_FS || 505 (status & MSTATUS_XS) == MSTATUS_XS) { 506 switch (xl) { 507 case MXL_RV32: 508 return status | MSTATUS32_SD; 509 case MXL_RV64: 510 return status | MSTATUS64_SD; 511 default: 512 g_assert_not_reached(); 513 } 514 } 515 return status; 516 } 517 518 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 519 target_ulong *val) 520 { 521 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 522 return RISCV_EXCP_NONE; 523 } 524 525 static int validate_vm(CPURISCVState *env, target_ulong vm) 526 { 527 if (riscv_cpu_mxl(env) == MXL_RV32) { 528 return valid_vm_1_10_32[vm & 0xf]; 529 } else { 530 return valid_vm_1_10_64[vm & 0xf]; 531 } 532 } 533 534 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 535 target_ulong val) 536 { 537 uint64_t mstatus = env->mstatus; 538 uint64_t mask = 0; 539 540 /* flush tlb on mstatus fields that affect VM */ 541 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 542 MSTATUS_MPRV | MSTATUS_SUM)) { 543 tlb_flush(env_cpu(env)); 544 } 545 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 546 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 547 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 548 MSTATUS_TW | MSTATUS_VS; 549 550 if (riscv_cpu_mxl(env) != MXL_RV32) { 551 /* 552 * RV32: MPV and GVA are not in mstatus. The current plan is to 553 * add them to mstatush. For now, we just don't support it. 554 */ 555 mask |= MSTATUS_MPV | MSTATUS_GVA; 556 } 557 558 mstatus = (mstatus & ~mask) | (val & mask); 559 560 if (riscv_cpu_mxl(env) == MXL_RV64) { 561 /* SXL and UXL fields are for now read only */ 562 mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); 563 mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); 564 } 565 env->mstatus = mstatus; 566 567 return RISCV_EXCP_NONE; 568 } 569 570 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 571 target_ulong *val) 572 { 573 *val = env->mstatus >> 32; 574 return RISCV_EXCP_NONE; 575 } 576 577 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 578 target_ulong val) 579 { 580 uint64_t valh = (uint64_t)val << 32; 581 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 582 583 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 584 tlb_flush(env_cpu(env)); 585 } 586 587 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 588 589 return RISCV_EXCP_NONE; 590 } 591 592 static RISCVException read_misa(CPURISCVState *env, int csrno, 593 target_ulong *val) 594 { 595 target_ulong misa; 596 597 switch (env->misa_mxl) { 598 case MXL_RV32: 599 misa = (target_ulong)MXL_RV32 << 30; 600 break; 601 #ifdef TARGET_RISCV64 602 case MXL_RV64: 603 misa = (target_ulong)MXL_RV64 << 62; 604 break; 605 #endif 606 default: 607 g_assert_not_reached(); 608 } 609 610 *val = misa | env->misa_ext; 611 return RISCV_EXCP_NONE; 612 } 613 614 static RISCVException write_misa(CPURISCVState *env, int csrno, 615 target_ulong val) 616 { 617 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 618 /* drop write to misa */ 619 return RISCV_EXCP_NONE; 620 } 621 622 /* 'I' or 'E' must be present */ 623 if (!(val & (RVI | RVE))) { 624 /* It is not, drop write to misa */ 625 return RISCV_EXCP_NONE; 626 } 627 628 /* 'E' excludes all other extensions */ 629 if (val & RVE) { 630 /* when we support 'E' we can do "val = RVE;" however 631 * for now we just drop writes if 'E' is present. 632 */ 633 return RISCV_EXCP_NONE; 634 } 635 636 /* 637 * misa.MXL writes are not supported by QEMU. 638 * Drop writes to those bits. 639 */ 640 641 /* Mask extensions that are not supported by this hart */ 642 val &= env->misa_ext_mask; 643 644 /* Mask extensions that are not supported by QEMU */ 645 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 646 647 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 648 if ((val & RVD) && !(val & RVF)) { 649 val &= ~RVD; 650 } 651 652 /* Suppress 'C' if next instruction is not aligned 653 * TODO: this should check next_pc 654 */ 655 if ((val & RVC) && (GETPC() & ~3) != 0) { 656 val &= ~RVC; 657 } 658 659 /* If nothing changed, do nothing. */ 660 if (val == env->misa_ext) { 661 return RISCV_EXCP_NONE; 662 } 663 664 /* flush translation cache */ 665 tb_flush(env_cpu(env)); 666 env->misa_ext = val; 667 return RISCV_EXCP_NONE; 668 } 669 670 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 671 target_ulong *val) 672 { 673 *val = env->medeleg; 674 return RISCV_EXCP_NONE; 675 } 676 677 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 678 target_ulong val) 679 { 680 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 681 return RISCV_EXCP_NONE; 682 } 683 684 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 685 target_ulong *val) 686 { 687 *val = env->mideleg; 688 return RISCV_EXCP_NONE; 689 } 690 691 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 692 target_ulong val) 693 { 694 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 695 if (riscv_has_ext(env, RVH)) { 696 env->mideleg |= VS_MODE_INTERRUPTS; 697 } 698 return RISCV_EXCP_NONE; 699 } 700 701 static RISCVException read_mie(CPURISCVState *env, int csrno, 702 target_ulong *val) 703 { 704 *val = env->mie; 705 return RISCV_EXCP_NONE; 706 } 707 708 static RISCVException write_mie(CPURISCVState *env, int csrno, 709 target_ulong val) 710 { 711 env->mie = (env->mie & ~all_ints) | (val & all_ints); 712 return RISCV_EXCP_NONE; 713 } 714 715 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 716 target_ulong *val) 717 { 718 *val = env->mtvec; 719 return RISCV_EXCP_NONE; 720 } 721 722 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 723 target_ulong val) 724 { 725 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 726 if ((val & 3) < 2) { 727 env->mtvec = val; 728 } else { 729 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 730 } 731 return RISCV_EXCP_NONE; 732 } 733 734 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 735 target_ulong *val) 736 { 737 *val = env->mcounteren; 738 return RISCV_EXCP_NONE; 739 } 740 741 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 742 target_ulong val) 743 { 744 env->mcounteren = val; 745 return RISCV_EXCP_NONE; 746 } 747 748 /* Machine Trap Handling */ 749 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 750 target_ulong *val) 751 { 752 *val = env->mscratch; 753 return RISCV_EXCP_NONE; 754 } 755 756 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 757 target_ulong val) 758 { 759 env->mscratch = val; 760 return RISCV_EXCP_NONE; 761 } 762 763 static RISCVException read_mepc(CPURISCVState *env, int csrno, 764 target_ulong *val) 765 { 766 *val = env->mepc; 767 return RISCV_EXCP_NONE; 768 } 769 770 static RISCVException write_mepc(CPURISCVState *env, int csrno, 771 target_ulong val) 772 { 773 env->mepc = val; 774 return RISCV_EXCP_NONE; 775 } 776 777 static RISCVException read_mcause(CPURISCVState *env, int csrno, 778 target_ulong *val) 779 { 780 *val = env->mcause; 781 return RISCV_EXCP_NONE; 782 } 783 784 static RISCVException write_mcause(CPURISCVState *env, int csrno, 785 target_ulong val) 786 { 787 env->mcause = val; 788 return RISCV_EXCP_NONE; 789 } 790 791 static RISCVException read_mtval(CPURISCVState *env, int csrno, 792 target_ulong *val) 793 { 794 *val = env->mtval; 795 return RISCV_EXCP_NONE; 796 } 797 798 static RISCVException write_mtval(CPURISCVState *env, int csrno, 799 target_ulong val) 800 { 801 env->mtval = val; 802 return RISCV_EXCP_NONE; 803 } 804 805 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 806 target_ulong *ret_value, 807 target_ulong new_value, target_ulong write_mask) 808 { 809 RISCVCPU *cpu = env_archcpu(env); 810 /* Allow software control of delegable interrupts not claimed by hardware */ 811 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 812 uint32_t old_mip; 813 814 if (mask) { 815 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 816 } else { 817 old_mip = env->mip; 818 } 819 820 if (ret_value) { 821 *ret_value = old_mip; 822 } 823 824 return RISCV_EXCP_NONE; 825 } 826 827 /* Supervisor Trap Setup */ 828 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 829 target_ulong *val) 830 { 831 target_ulong mask = (sstatus_v1_10_mask); 832 833 /* TODO: Use SXL not MXL. */ 834 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 835 return RISCV_EXCP_NONE; 836 } 837 838 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 839 target_ulong val) 840 { 841 target_ulong mask = (sstatus_v1_10_mask); 842 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 843 return write_mstatus(env, CSR_MSTATUS, newval); 844 } 845 846 static RISCVException read_vsie(CPURISCVState *env, int csrno, 847 target_ulong *val) 848 { 849 /* Shift the VS bits to their S bit location in vsie */ 850 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 851 return RISCV_EXCP_NONE; 852 } 853 854 static RISCVException read_sie(CPURISCVState *env, int csrno, 855 target_ulong *val) 856 { 857 if (riscv_cpu_virt_enabled(env)) { 858 read_vsie(env, CSR_VSIE, val); 859 } else { 860 *val = env->mie & env->mideleg; 861 } 862 return RISCV_EXCP_NONE; 863 } 864 865 static RISCVException write_vsie(CPURISCVState *env, int csrno, 866 target_ulong val) 867 { 868 /* Shift the S bits to their VS bit location in mie */ 869 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 870 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 871 return write_mie(env, CSR_MIE, newval); 872 } 873 874 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 875 { 876 if (riscv_cpu_virt_enabled(env)) { 877 write_vsie(env, CSR_VSIE, val); 878 } else { 879 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 880 (val & S_MODE_INTERRUPTS); 881 write_mie(env, CSR_MIE, newval); 882 } 883 884 return RISCV_EXCP_NONE; 885 } 886 887 static RISCVException read_stvec(CPURISCVState *env, int csrno, 888 target_ulong *val) 889 { 890 *val = env->stvec; 891 return RISCV_EXCP_NONE; 892 } 893 894 static RISCVException write_stvec(CPURISCVState *env, int csrno, 895 target_ulong val) 896 { 897 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 898 if ((val & 3) < 2) { 899 env->stvec = val; 900 } else { 901 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 902 } 903 return RISCV_EXCP_NONE; 904 } 905 906 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 907 target_ulong *val) 908 { 909 *val = env->scounteren; 910 return RISCV_EXCP_NONE; 911 } 912 913 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 914 target_ulong val) 915 { 916 env->scounteren = val; 917 return RISCV_EXCP_NONE; 918 } 919 920 /* Supervisor Trap Handling */ 921 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 922 target_ulong *val) 923 { 924 *val = env->sscratch; 925 return RISCV_EXCP_NONE; 926 } 927 928 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 929 target_ulong val) 930 { 931 env->sscratch = val; 932 return RISCV_EXCP_NONE; 933 } 934 935 static RISCVException read_sepc(CPURISCVState *env, int csrno, 936 target_ulong *val) 937 { 938 *val = env->sepc; 939 return RISCV_EXCP_NONE; 940 } 941 942 static RISCVException write_sepc(CPURISCVState *env, int csrno, 943 target_ulong val) 944 { 945 env->sepc = val; 946 return RISCV_EXCP_NONE; 947 } 948 949 static RISCVException read_scause(CPURISCVState *env, int csrno, 950 target_ulong *val) 951 { 952 *val = env->scause; 953 return RISCV_EXCP_NONE; 954 } 955 956 static RISCVException write_scause(CPURISCVState *env, int csrno, 957 target_ulong val) 958 { 959 env->scause = val; 960 return RISCV_EXCP_NONE; 961 } 962 963 static RISCVException read_stval(CPURISCVState *env, int csrno, 964 target_ulong *val) 965 { 966 *val = env->stval; 967 return RISCV_EXCP_NONE; 968 } 969 970 static RISCVException write_stval(CPURISCVState *env, int csrno, 971 target_ulong val) 972 { 973 env->stval = val; 974 return RISCV_EXCP_NONE; 975 } 976 977 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 978 target_ulong *ret_value, 979 target_ulong new_value, target_ulong write_mask) 980 { 981 /* Shift the S bits to their VS bit location in mip */ 982 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 983 (write_mask << 1) & vsip_writable_mask & env->hideleg); 984 985 if (ret_value) { 986 *ret_value &= VS_MODE_INTERRUPTS; 987 /* Shift the VS bits to their S bit location in vsip */ 988 *ret_value >>= 1; 989 } 990 return ret; 991 } 992 993 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 994 target_ulong *ret_value, 995 target_ulong new_value, target_ulong write_mask) 996 { 997 int ret; 998 999 if (riscv_cpu_virt_enabled(env)) { 1000 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 1001 } else { 1002 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 1003 write_mask & env->mideleg & sip_writable_mask); 1004 } 1005 1006 if (ret_value) { 1007 *ret_value &= env->mideleg; 1008 } 1009 return ret; 1010 } 1011 1012 /* Supervisor Protection and Translation */ 1013 static RISCVException read_satp(CPURISCVState *env, int csrno, 1014 target_ulong *val) 1015 { 1016 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1017 *val = 0; 1018 return RISCV_EXCP_NONE; 1019 } 1020 1021 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1022 return RISCV_EXCP_ILLEGAL_INST; 1023 } else { 1024 *val = env->satp; 1025 } 1026 1027 return RISCV_EXCP_NONE; 1028 } 1029 1030 static RISCVException write_satp(CPURISCVState *env, int csrno, 1031 target_ulong val) 1032 { 1033 target_ulong vm, mask, asid; 1034 1035 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1036 return RISCV_EXCP_NONE; 1037 } 1038 1039 if (riscv_cpu_mxl(env) == MXL_RV32) { 1040 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1041 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1042 asid = (val ^ env->satp) & SATP32_ASID; 1043 } else { 1044 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1045 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1046 asid = (val ^ env->satp) & SATP64_ASID; 1047 } 1048 1049 if (vm && mask) { 1050 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1051 return RISCV_EXCP_ILLEGAL_INST; 1052 } else { 1053 if (asid) { 1054 tlb_flush(env_cpu(env)); 1055 } 1056 env->satp = val; 1057 } 1058 } 1059 return RISCV_EXCP_NONE; 1060 } 1061 1062 /* Hypervisor Extensions */ 1063 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1064 target_ulong *val) 1065 { 1066 *val = env->hstatus; 1067 if (riscv_cpu_mxl(env) != MXL_RV32) { 1068 /* We only support 64-bit VSXL */ 1069 *val = set_field(*val, HSTATUS_VSXL, 2); 1070 } 1071 /* We only support little endian */ 1072 *val = set_field(*val, HSTATUS_VSBE, 0); 1073 return RISCV_EXCP_NONE; 1074 } 1075 1076 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1077 target_ulong val) 1078 { 1079 env->hstatus = val; 1080 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 1081 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1082 } 1083 if (get_field(val, HSTATUS_VSBE) != 0) { 1084 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1085 } 1086 return RISCV_EXCP_NONE; 1087 } 1088 1089 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1090 target_ulong *val) 1091 { 1092 *val = env->hedeleg; 1093 return RISCV_EXCP_NONE; 1094 } 1095 1096 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1097 target_ulong val) 1098 { 1099 env->hedeleg = val & vs_delegable_excps; 1100 return RISCV_EXCP_NONE; 1101 } 1102 1103 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1104 target_ulong *val) 1105 { 1106 *val = env->hideleg; 1107 return RISCV_EXCP_NONE; 1108 } 1109 1110 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1111 target_ulong val) 1112 { 1113 env->hideleg = val & vs_delegable_ints; 1114 return RISCV_EXCP_NONE; 1115 } 1116 1117 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1118 target_ulong *ret_value, 1119 target_ulong new_value, target_ulong write_mask) 1120 { 1121 int ret = rmw_mip(env, 0, ret_value, new_value, 1122 write_mask & hvip_writable_mask); 1123 1124 if (ret_value) { 1125 *ret_value &= hvip_writable_mask; 1126 } 1127 return ret; 1128 } 1129 1130 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1131 target_ulong *ret_value, 1132 target_ulong new_value, target_ulong write_mask) 1133 { 1134 int ret = rmw_mip(env, 0, ret_value, new_value, 1135 write_mask & hip_writable_mask); 1136 1137 if (ret_value) { 1138 *ret_value &= hip_writable_mask; 1139 } 1140 return ret; 1141 } 1142 1143 static RISCVException read_hie(CPURISCVState *env, int csrno, 1144 target_ulong *val) 1145 { 1146 *val = env->mie & VS_MODE_INTERRUPTS; 1147 return RISCV_EXCP_NONE; 1148 } 1149 1150 static RISCVException write_hie(CPURISCVState *env, int csrno, 1151 target_ulong val) 1152 { 1153 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1154 return write_mie(env, CSR_MIE, newval); 1155 } 1156 1157 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1158 target_ulong *val) 1159 { 1160 *val = env->hcounteren; 1161 return RISCV_EXCP_NONE; 1162 } 1163 1164 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1165 target_ulong val) 1166 { 1167 env->hcounteren = val; 1168 return RISCV_EXCP_NONE; 1169 } 1170 1171 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1172 target_ulong val) 1173 { 1174 if (val) { 1175 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1176 } 1177 return RISCV_EXCP_NONE; 1178 } 1179 1180 static RISCVException read_htval(CPURISCVState *env, int csrno, 1181 target_ulong *val) 1182 { 1183 *val = env->htval; 1184 return RISCV_EXCP_NONE; 1185 } 1186 1187 static RISCVException write_htval(CPURISCVState *env, int csrno, 1188 target_ulong val) 1189 { 1190 env->htval = val; 1191 return RISCV_EXCP_NONE; 1192 } 1193 1194 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1195 target_ulong *val) 1196 { 1197 *val = env->htinst; 1198 return RISCV_EXCP_NONE; 1199 } 1200 1201 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1202 target_ulong val) 1203 { 1204 return RISCV_EXCP_NONE; 1205 } 1206 1207 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1208 target_ulong val) 1209 { 1210 if (val) { 1211 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1212 } 1213 return RISCV_EXCP_NONE; 1214 } 1215 1216 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1217 target_ulong *val) 1218 { 1219 *val = env->hgatp; 1220 return RISCV_EXCP_NONE; 1221 } 1222 1223 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1224 target_ulong val) 1225 { 1226 env->hgatp = val; 1227 return RISCV_EXCP_NONE; 1228 } 1229 1230 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1231 target_ulong *val) 1232 { 1233 if (!env->rdtime_fn) { 1234 return RISCV_EXCP_ILLEGAL_INST; 1235 } 1236 1237 *val = env->htimedelta; 1238 return RISCV_EXCP_NONE; 1239 } 1240 1241 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1242 target_ulong val) 1243 { 1244 if (!env->rdtime_fn) { 1245 return RISCV_EXCP_ILLEGAL_INST; 1246 } 1247 1248 if (riscv_cpu_mxl(env) == MXL_RV32) { 1249 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1250 } else { 1251 env->htimedelta = val; 1252 } 1253 return RISCV_EXCP_NONE; 1254 } 1255 1256 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1257 target_ulong *val) 1258 { 1259 if (!env->rdtime_fn) { 1260 return RISCV_EXCP_ILLEGAL_INST; 1261 } 1262 1263 *val = env->htimedelta >> 32; 1264 return RISCV_EXCP_NONE; 1265 } 1266 1267 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1268 target_ulong val) 1269 { 1270 if (!env->rdtime_fn) { 1271 return RISCV_EXCP_ILLEGAL_INST; 1272 } 1273 1274 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1275 return RISCV_EXCP_NONE; 1276 } 1277 1278 /* Virtual CSR Registers */ 1279 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1280 target_ulong *val) 1281 { 1282 *val = env->vsstatus; 1283 return RISCV_EXCP_NONE; 1284 } 1285 1286 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1287 target_ulong val) 1288 { 1289 uint64_t mask = (target_ulong)-1; 1290 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1291 return RISCV_EXCP_NONE; 1292 } 1293 1294 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1295 { 1296 *val = env->vstvec; 1297 return RISCV_EXCP_NONE; 1298 } 1299 1300 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1301 target_ulong val) 1302 { 1303 env->vstvec = val; 1304 return RISCV_EXCP_NONE; 1305 } 1306 1307 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1308 target_ulong *val) 1309 { 1310 *val = env->vsscratch; 1311 return RISCV_EXCP_NONE; 1312 } 1313 1314 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1315 target_ulong val) 1316 { 1317 env->vsscratch = val; 1318 return RISCV_EXCP_NONE; 1319 } 1320 1321 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1322 target_ulong *val) 1323 { 1324 *val = env->vsepc; 1325 return RISCV_EXCP_NONE; 1326 } 1327 1328 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1329 target_ulong val) 1330 { 1331 env->vsepc = val; 1332 return RISCV_EXCP_NONE; 1333 } 1334 1335 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1336 target_ulong *val) 1337 { 1338 *val = env->vscause; 1339 return RISCV_EXCP_NONE; 1340 } 1341 1342 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1343 target_ulong val) 1344 { 1345 env->vscause = val; 1346 return RISCV_EXCP_NONE; 1347 } 1348 1349 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1350 target_ulong *val) 1351 { 1352 *val = env->vstval; 1353 return RISCV_EXCP_NONE; 1354 } 1355 1356 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1357 target_ulong val) 1358 { 1359 env->vstval = val; 1360 return RISCV_EXCP_NONE; 1361 } 1362 1363 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1364 target_ulong *val) 1365 { 1366 *val = env->vsatp; 1367 return RISCV_EXCP_NONE; 1368 } 1369 1370 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1371 target_ulong val) 1372 { 1373 env->vsatp = val; 1374 return RISCV_EXCP_NONE; 1375 } 1376 1377 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1378 target_ulong *val) 1379 { 1380 *val = env->mtval2; 1381 return RISCV_EXCP_NONE; 1382 } 1383 1384 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1385 target_ulong val) 1386 { 1387 env->mtval2 = val; 1388 return RISCV_EXCP_NONE; 1389 } 1390 1391 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1392 target_ulong *val) 1393 { 1394 *val = env->mtinst; 1395 return RISCV_EXCP_NONE; 1396 } 1397 1398 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1399 target_ulong val) 1400 { 1401 env->mtinst = val; 1402 return RISCV_EXCP_NONE; 1403 } 1404 1405 /* Physical Memory Protection */ 1406 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1407 target_ulong *val) 1408 { 1409 *val = mseccfg_csr_read(env); 1410 return RISCV_EXCP_NONE; 1411 } 1412 1413 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1414 target_ulong val) 1415 { 1416 mseccfg_csr_write(env, val); 1417 return RISCV_EXCP_NONE; 1418 } 1419 1420 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1421 target_ulong *val) 1422 { 1423 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1424 return RISCV_EXCP_NONE; 1425 } 1426 1427 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1428 target_ulong val) 1429 { 1430 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1431 return RISCV_EXCP_NONE; 1432 } 1433 1434 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1435 target_ulong *val) 1436 { 1437 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1438 return RISCV_EXCP_NONE; 1439 } 1440 1441 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1442 target_ulong val) 1443 { 1444 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1445 return RISCV_EXCP_NONE; 1446 } 1447 1448 /* 1449 * Functions to access Pointer Masking feature registers 1450 * We have to check if current priv lvl could modify 1451 * csr in given mode 1452 */ 1453 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 1454 { 1455 int csr_priv = get_field(csrno, 0x300); 1456 int pm_current; 1457 1458 /* 1459 * If priv lvls differ that means we're accessing csr from higher priv lvl, 1460 * so allow the access 1461 */ 1462 if (env->priv != csr_priv) { 1463 return false; 1464 } 1465 switch (env->priv) { 1466 case PRV_M: 1467 pm_current = get_field(env->mmte, M_PM_CURRENT); 1468 break; 1469 case PRV_S: 1470 pm_current = get_field(env->mmte, S_PM_CURRENT); 1471 break; 1472 case PRV_U: 1473 pm_current = get_field(env->mmte, U_PM_CURRENT); 1474 break; 1475 default: 1476 g_assert_not_reached(); 1477 } 1478 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 1479 return !pm_current; 1480 } 1481 1482 static RISCVException read_mmte(CPURISCVState *env, int csrno, 1483 target_ulong *val) 1484 { 1485 *val = env->mmte & MMTE_MASK; 1486 return RISCV_EXCP_NONE; 1487 } 1488 1489 static RISCVException write_mmte(CPURISCVState *env, int csrno, 1490 target_ulong val) 1491 { 1492 uint64_t mstatus; 1493 target_ulong wpri_val = val & MMTE_MASK; 1494 1495 if (val != wpri_val) { 1496 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1497 "MMTE: WPRI violation written 0x", val, 1498 "vs expected 0x", wpri_val); 1499 } 1500 /* for machine mode pm.current is hardwired to 1 */ 1501 wpri_val |= MMTE_M_PM_CURRENT; 1502 1503 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 1504 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 1505 env->mmte = wpri_val | PM_EXT_DIRTY; 1506 1507 /* Set XS and SD bits, since PM CSRs are dirty */ 1508 mstatus = env->mstatus | MSTATUS_XS; 1509 write_mstatus(env, csrno, mstatus); 1510 return RISCV_EXCP_NONE; 1511 } 1512 1513 static RISCVException read_smte(CPURISCVState *env, int csrno, 1514 target_ulong *val) 1515 { 1516 *val = env->mmte & SMTE_MASK; 1517 return RISCV_EXCP_NONE; 1518 } 1519 1520 static RISCVException write_smte(CPURISCVState *env, int csrno, 1521 target_ulong val) 1522 { 1523 target_ulong wpri_val = val & SMTE_MASK; 1524 1525 if (val != wpri_val) { 1526 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1527 "SMTE: WPRI violation written 0x", val, 1528 "vs expected 0x", wpri_val); 1529 } 1530 1531 /* if pm.current==0 we can't modify current PM CSRs */ 1532 if (check_pm_current_disabled(env, csrno)) { 1533 return RISCV_EXCP_NONE; 1534 } 1535 1536 wpri_val |= (env->mmte & ~SMTE_MASK); 1537 write_mmte(env, csrno, wpri_val); 1538 return RISCV_EXCP_NONE; 1539 } 1540 1541 static RISCVException read_umte(CPURISCVState *env, int csrno, 1542 target_ulong *val) 1543 { 1544 *val = env->mmte & UMTE_MASK; 1545 return RISCV_EXCP_NONE; 1546 } 1547 1548 static RISCVException write_umte(CPURISCVState *env, int csrno, 1549 target_ulong val) 1550 { 1551 target_ulong wpri_val = val & UMTE_MASK; 1552 1553 if (val != wpri_val) { 1554 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1555 "UMTE: WPRI violation written 0x", val, 1556 "vs expected 0x", wpri_val); 1557 } 1558 1559 if (check_pm_current_disabled(env, csrno)) { 1560 return RISCV_EXCP_NONE; 1561 } 1562 1563 wpri_val |= (env->mmte & ~UMTE_MASK); 1564 write_mmte(env, csrno, wpri_val); 1565 return RISCV_EXCP_NONE; 1566 } 1567 1568 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 1569 target_ulong *val) 1570 { 1571 *val = env->mpmmask; 1572 return RISCV_EXCP_NONE; 1573 } 1574 1575 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 1576 target_ulong val) 1577 { 1578 uint64_t mstatus; 1579 1580 env->mpmmask = val; 1581 env->mmte |= PM_EXT_DIRTY; 1582 1583 /* Set XS and SD bits, since PM CSRs are dirty */ 1584 mstatus = env->mstatus | MSTATUS_XS; 1585 write_mstatus(env, csrno, mstatus); 1586 return RISCV_EXCP_NONE; 1587 } 1588 1589 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 1590 target_ulong *val) 1591 { 1592 *val = env->spmmask; 1593 return RISCV_EXCP_NONE; 1594 } 1595 1596 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 1597 target_ulong val) 1598 { 1599 uint64_t mstatus; 1600 1601 /* if pm.current==0 we can't modify current PM CSRs */ 1602 if (check_pm_current_disabled(env, csrno)) { 1603 return RISCV_EXCP_NONE; 1604 } 1605 env->spmmask = val; 1606 env->mmte |= PM_EXT_DIRTY; 1607 1608 /* Set XS and SD bits, since PM CSRs are dirty */ 1609 mstatus = env->mstatus | MSTATUS_XS; 1610 write_mstatus(env, csrno, mstatus); 1611 return RISCV_EXCP_NONE; 1612 } 1613 1614 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 1615 target_ulong *val) 1616 { 1617 *val = env->upmmask; 1618 return RISCV_EXCP_NONE; 1619 } 1620 1621 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 1622 target_ulong val) 1623 { 1624 uint64_t mstatus; 1625 1626 /* if pm.current==0 we can't modify current PM CSRs */ 1627 if (check_pm_current_disabled(env, csrno)) { 1628 return RISCV_EXCP_NONE; 1629 } 1630 env->upmmask = val; 1631 env->mmte |= PM_EXT_DIRTY; 1632 1633 /* Set XS and SD bits, since PM CSRs are dirty */ 1634 mstatus = env->mstatus | MSTATUS_XS; 1635 write_mstatus(env, csrno, mstatus); 1636 return RISCV_EXCP_NONE; 1637 } 1638 1639 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 1640 target_ulong *val) 1641 { 1642 *val = env->mpmbase; 1643 return RISCV_EXCP_NONE; 1644 } 1645 1646 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 1647 target_ulong val) 1648 { 1649 uint64_t mstatus; 1650 1651 env->mpmbase = val; 1652 env->mmte |= PM_EXT_DIRTY; 1653 1654 /* Set XS and SD bits, since PM CSRs are dirty */ 1655 mstatus = env->mstatus | MSTATUS_XS; 1656 write_mstatus(env, csrno, mstatus); 1657 return RISCV_EXCP_NONE; 1658 } 1659 1660 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 1661 target_ulong *val) 1662 { 1663 *val = env->spmbase; 1664 return RISCV_EXCP_NONE; 1665 } 1666 1667 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 1668 target_ulong val) 1669 { 1670 uint64_t mstatus; 1671 1672 /* if pm.current==0 we can't modify current PM CSRs */ 1673 if (check_pm_current_disabled(env, csrno)) { 1674 return RISCV_EXCP_NONE; 1675 } 1676 env->spmbase = val; 1677 env->mmte |= PM_EXT_DIRTY; 1678 1679 /* Set XS and SD bits, since PM CSRs are dirty */ 1680 mstatus = env->mstatus | MSTATUS_XS; 1681 write_mstatus(env, csrno, mstatus); 1682 return RISCV_EXCP_NONE; 1683 } 1684 1685 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 1686 target_ulong *val) 1687 { 1688 *val = env->upmbase; 1689 return RISCV_EXCP_NONE; 1690 } 1691 1692 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 1693 target_ulong val) 1694 { 1695 uint64_t mstatus; 1696 1697 /* if pm.current==0 we can't modify current PM CSRs */ 1698 if (check_pm_current_disabled(env, csrno)) { 1699 return RISCV_EXCP_NONE; 1700 } 1701 env->upmbase = val; 1702 env->mmte |= PM_EXT_DIRTY; 1703 1704 /* Set XS and SD bits, since PM CSRs are dirty */ 1705 mstatus = env->mstatus | MSTATUS_XS; 1706 write_mstatus(env, csrno, mstatus); 1707 return RISCV_EXCP_NONE; 1708 } 1709 1710 #endif 1711 1712 /* 1713 * riscv_csrrw - read and/or update control and status register 1714 * 1715 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1716 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1717 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1718 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1719 */ 1720 1721 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1722 target_ulong *ret_value, 1723 target_ulong new_value, target_ulong write_mask) 1724 { 1725 RISCVException ret; 1726 target_ulong old_value; 1727 RISCVCPU *cpu = env_archcpu(env); 1728 int read_only = get_field(csrno, 0xC00) == 3; 1729 1730 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 1731 #if !defined(CONFIG_USER_ONLY) 1732 int effective_priv = env->priv; 1733 1734 if (riscv_has_ext(env, RVH) && 1735 env->priv == PRV_S && 1736 !riscv_cpu_virt_enabled(env)) { 1737 /* 1738 * We are in S mode without virtualisation, therefore we are in HS Mode. 1739 * Add 1 to the effective privledge level to allow us to access the 1740 * Hypervisor CSRs. 1741 */ 1742 effective_priv++; 1743 } 1744 1745 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 1746 return RISCV_EXCP_ILLEGAL_INST; 1747 } 1748 #endif 1749 if (write_mask && read_only) { 1750 return RISCV_EXCP_ILLEGAL_INST; 1751 } 1752 1753 /* ensure the CSR extension is enabled. */ 1754 if (!cpu->cfg.ext_icsr) { 1755 return RISCV_EXCP_ILLEGAL_INST; 1756 } 1757 1758 /* check predicate */ 1759 if (!csr_ops[csrno].predicate) { 1760 return RISCV_EXCP_ILLEGAL_INST; 1761 } 1762 ret = csr_ops[csrno].predicate(env, csrno); 1763 if (ret != RISCV_EXCP_NONE) { 1764 return ret; 1765 } 1766 1767 /* execute combined read/write operation if it exists */ 1768 if (csr_ops[csrno].op) { 1769 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1770 } 1771 1772 /* if no accessor exists then return failure */ 1773 if (!csr_ops[csrno].read) { 1774 return RISCV_EXCP_ILLEGAL_INST; 1775 } 1776 /* read old value */ 1777 ret = csr_ops[csrno].read(env, csrno, &old_value); 1778 if (ret != RISCV_EXCP_NONE) { 1779 return ret; 1780 } 1781 1782 /* write value if writable and write mask set, otherwise drop writes */ 1783 if (write_mask) { 1784 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1785 if (csr_ops[csrno].write) { 1786 ret = csr_ops[csrno].write(env, csrno, new_value); 1787 if (ret != RISCV_EXCP_NONE) { 1788 return ret; 1789 } 1790 } 1791 } 1792 1793 /* return old value */ 1794 if (ret_value) { 1795 *ret_value = old_value; 1796 } 1797 1798 return RISCV_EXCP_NONE; 1799 } 1800 1801 /* 1802 * Debugger support. If not in user mode, set env->debugger before the 1803 * riscv_csrrw call and clear it after the call. 1804 */ 1805 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1806 target_ulong *ret_value, 1807 target_ulong new_value, 1808 target_ulong write_mask) 1809 { 1810 RISCVException ret; 1811 #if !defined(CONFIG_USER_ONLY) 1812 env->debugger = true; 1813 #endif 1814 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1815 #if !defined(CONFIG_USER_ONLY) 1816 env->debugger = false; 1817 #endif 1818 return ret; 1819 } 1820 1821 /* Control and Status Register function table */ 1822 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1823 /* User Floating-Point CSRs */ 1824 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1825 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1826 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1827 /* Vector CSRs */ 1828 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1829 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1830 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1831 [CSR_VL] = { "vl", vs, read_vl }, 1832 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1833 /* User Timers and Counters */ 1834 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1835 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1836 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1837 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1838 1839 /* 1840 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1841 * rdtime callback is not provided by machine/platform emulation. 1842 */ 1843 [CSR_TIME] = { "time", ctr, read_time }, 1844 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1845 1846 #if !defined(CONFIG_USER_ONLY) 1847 /* Machine Timers and Counters */ 1848 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1849 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1850 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1851 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1852 1853 /* Machine Information Registers */ 1854 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1855 [CSR_MARCHID] = { "marchid", any, read_zero }, 1856 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1857 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1858 1859 /* Machine Trap Setup */ 1860 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1861 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1862 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1863 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1864 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1865 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1866 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1867 1868 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1869 1870 /* Machine Trap Handling */ 1871 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1872 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1873 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1874 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1875 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1876 1877 /* Supervisor Trap Setup */ 1878 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1879 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1880 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1881 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1882 1883 /* Supervisor Trap Handling */ 1884 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1885 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1886 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1887 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1888 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1889 1890 /* Supervisor Protection and Translation */ 1891 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1892 1893 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1894 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1895 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1896 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1897 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1898 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1899 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1900 [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, 1901 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1902 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1903 [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, 1904 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1905 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1906 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1907 1908 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1909 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1910 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1911 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1912 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1913 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1914 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1915 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1916 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1917 1918 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1919 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1920 1921 /* Physical Memory Protection */ 1922 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1923 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1924 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1925 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1926 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1927 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1928 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1929 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1930 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1931 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1932 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1933 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1934 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1935 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1936 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1937 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1938 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1939 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1940 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1941 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1942 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1943 1944 /* User Pointer Masking */ 1945 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 1946 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 1947 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 1948 /* Machine Pointer Masking */ 1949 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 1950 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 1951 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 1952 /* Supervisor Pointer Masking */ 1953 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 1954 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 1955 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 1956 1957 /* Performance Counters */ 1958 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1959 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1960 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1961 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1962 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1963 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1964 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1965 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1966 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1967 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1968 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1969 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1970 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1971 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1972 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1973 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1974 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1975 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1976 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1977 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1978 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1979 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1980 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1981 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1982 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1983 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1984 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1985 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1986 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1987 1988 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1989 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1990 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1991 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1992 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1993 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1994 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1995 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1996 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1997 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1998 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1999 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 2000 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 2001 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 2002 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 2003 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 2004 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 2005 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 2006 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 2007 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 2008 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 2009 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 2010 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 2011 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 2012 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 2013 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 2014 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 2015 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 2016 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 2017 2018 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 2019 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 2020 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 2021 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 2022 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 2023 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 2024 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 2025 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 2026 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 2027 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 2028 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 2029 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 2030 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 2031 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 2032 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 2033 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 2034 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 2035 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 2036 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 2037 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 2038 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 2039 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 2040 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 2041 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 2042 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 2043 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 2044 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 2045 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 2046 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 2047 2048 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 2049 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 2050 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 2051 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 2052 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 2053 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 2054 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 2055 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 2056 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 2057 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 2058 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 2059 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 2060 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 2061 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 2062 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 2063 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 2064 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 2065 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 2066 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 2067 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 2068 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 2069 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 2070 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 2071 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 2072 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 2073 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 2074 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 2075 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 2076 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 2077 2078 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 2079 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 2080 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 2081 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 2082 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 2083 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 2084 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 2085 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 2086 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 2087 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 2088 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 2089 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 2090 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 2091 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 2092 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 2093 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 2094 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 2095 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 2096 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 2097 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 2098 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 2099 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 2100 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 2101 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 2102 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 2103 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 2104 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 2105 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 2106 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 2107 #endif /* !CONFIG_USER_ONLY */ 2108 }; 2109