1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "qemu/main-loop.h" 25 #include "exec/exec-all.h" 26 #include "sysemu/cpu-timers.h" 27 #include "qemu/guest-random.h" 28 #include "qapi/error.h" 29 30 /* CSR function table public API */ 31 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 32 { 33 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 34 } 35 36 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 37 { 38 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 39 } 40 41 /* Predicates */ 42 static RISCVException fs(CPURISCVState *env, int csrno) 43 { 44 #if !defined(CONFIG_USER_ONLY) 45 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 46 !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 47 return RISCV_EXCP_ILLEGAL_INST; 48 } 49 #endif 50 return RISCV_EXCP_NONE; 51 } 52 53 static RISCVException vs(CPURISCVState *env, int csrno) 54 { 55 CPUState *cs = env_cpu(env); 56 RISCVCPU *cpu = RISCV_CPU(cs); 57 58 if (env->misa_ext & RVV || 59 cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 60 #if !defined(CONFIG_USER_ONLY) 61 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 62 return RISCV_EXCP_ILLEGAL_INST; 63 } 64 #endif 65 return RISCV_EXCP_NONE; 66 } 67 return RISCV_EXCP_ILLEGAL_INST; 68 } 69 70 static RISCVException ctr(CPURISCVState *env, int csrno) 71 { 72 #if !defined(CONFIG_USER_ONLY) 73 CPUState *cs = env_cpu(env); 74 RISCVCPU *cpu = RISCV_CPU(cs); 75 int ctr_index; 76 77 if (!cpu->cfg.ext_counters) { 78 /* The Counters extensions is not enabled */ 79 return RISCV_EXCP_ILLEGAL_INST; 80 } 81 82 if (riscv_cpu_virt_enabled(env)) { 83 switch (csrno) { 84 case CSR_CYCLE: 85 if (!get_field(env->hcounteren, COUNTEREN_CY) && 86 get_field(env->mcounteren, COUNTEREN_CY)) { 87 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 88 } 89 break; 90 case CSR_TIME: 91 if (!get_field(env->hcounteren, COUNTEREN_TM) && 92 get_field(env->mcounteren, COUNTEREN_TM)) { 93 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 94 } 95 break; 96 case CSR_INSTRET: 97 if (!get_field(env->hcounteren, COUNTEREN_IR) && 98 get_field(env->mcounteren, COUNTEREN_IR)) { 99 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 100 } 101 break; 102 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 103 ctr_index = csrno - CSR_CYCLE; 104 if (!get_field(env->hcounteren, 1 << ctr_index) && 105 get_field(env->mcounteren, 1 << ctr_index)) { 106 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 107 } 108 break; 109 } 110 if (riscv_cpu_mxl(env) == MXL_RV32) { 111 switch (csrno) { 112 case CSR_CYCLEH: 113 if (!get_field(env->hcounteren, COUNTEREN_CY) && 114 get_field(env->mcounteren, COUNTEREN_CY)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_TIMEH: 119 if (!get_field(env->hcounteren, COUNTEREN_TM) && 120 get_field(env->mcounteren, COUNTEREN_TM)) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 case CSR_INSTRETH: 125 if (!get_field(env->hcounteren, COUNTEREN_IR) && 126 get_field(env->mcounteren, COUNTEREN_IR)) { 127 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 128 } 129 break; 130 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 131 ctr_index = csrno - CSR_CYCLEH; 132 if (!get_field(env->hcounteren, 1 << ctr_index) && 133 get_field(env->mcounteren, 1 << ctr_index)) { 134 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 135 } 136 break; 137 } 138 } 139 } 140 #endif 141 return RISCV_EXCP_NONE; 142 } 143 144 static RISCVException ctr32(CPURISCVState *env, int csrno) 145 { 146 if (riscv_cpu_mxl(env) != MXL_RV32) { 147 return RISCV_EXCP_ILLEGAL_INST; 148 } 149 150 return ctr(env, csrno); 151 } 152 153 #if !defined(CONFIG_USER_ONLY) 154 static RISCVException any(CPURISCVState *env, int csrno) 155 { 156 return RISCV_EXCP_NONE; 157 } 158 159 static RISCVException any32(CPURISCVState *env, int csrno) 160 { 161 if (riscv_cpu_mxl(env) != MXL_RV32) { 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 return any(env, csrno); 166 167 } 168 169 static int aia_any(CPURISCVState *env, int csrno) 170 { 171 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 172 return RISCV_EXCP_ILLEGAL_INST; 173 } 174 175 return any(env, csrno); 176 } 177 178 static int aia_any32(CPURISCVState *env, int csrno) 179 { 180 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 181 return RISCV_EXCP_ILLEGAL_INST; 182 } 183 184 return any32(env, csrno); 185 } 186 187 static RISCVException smode(CPURISCVState *env, int csrno) 188 { 189 if (riscv_has_ext(env, RVS)) { 190 return RISCV_EXCP_NONE; 191 } 192 193 return RISCV_EXCP_ILLEGAL_INST; 194 } 195 196 static int smode32(CPURISCVState *env, int csrno) 197 { 198 if (riscv_cpu_mxl(env) != MXL_RV32) { 199 return RISCV_EXCP_ILLEGAL_INST; 200 } 201 202 return smode(env, csrno); 203 } 204 205 static int aia_smode(CPURISCVState *env, int csrno) 206 { 207 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 208 return RISCV_EXCP_ILLEGAL_INST; 209 } 210 211 return smode(env, csrno); 212 } 213 214 static int aia_smode32(CPURISCVState *env, int csrno) 215 { 216 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 217 return RISCV_EXCP_ILLEGAL_INST; 218 } 219 220 return smode32(env, csrno); 221 } 222 223 static RISCVException hmode(CPURISCVState *env, int csrno) 224 { 225 if (riscv_has_ext(env, RVS) && 226 riscv_has_ext(env, RVH)) { 227 /* Hypervisor extension is supported */ 228 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 229 env->priv == PRV_M) { 230 return RISCV_EXCP_NONE; 231 } else { 232 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 233 } 234 } 235 236 return RISCV_EXCP_ILLEGAL_INST; 237 } 238 239 static RISCVException hmode32(CPURISCVState *env, int csrno) 240 { 241 if (riscv_cpu_mxl(env) != MXL_RV32) { 242 if (!riscv_cpu_virt_enabled(env)) { 243 return RISCV_EXCP_ILLEGAL_INST; 244 } else { 245 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 246 } 247 } 248 249 return hmode(env, csrno); 250 251 } 252 253 /* Checks if PointerMasking registers could be accessed */ 254 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 255 { 256 /* Check if j-ext is present */ 257 if (riscv_has_ext(env, RVJ)) { 258 return RISCV_EXCP_NONE; 259 } 260 return RISCV_EXCP_ILLEGAL_INST; 261 } 262 263 static int aia_hmode(CPURISCVState *env, int csrno) 264 { 265 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 266 return RISCV_EXCP_ILLEGAL_INST; 267 } 268 269 return hmode(env, csrno); 270 } 271 272 static int aia_hmode32(CPURISCVState *env, int csrno) 273 { 274 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 275 return RISCV_EXCP_ILLEGAL_INST; 276 } 277 278 return hmode32(env, csrno); 279 } 280 281 static RISCVException pmp(CPURISCVState *env, int csrno) 282 { 283 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 284 return RISCV_EXCP_NONE; 285 } 286 287 return RISCV_EXCP_ILLEGAL_INST; 288 } 289 290 static RISCVException epmp(CPURISCVState *env, int csrno) 291 { 292 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 293 return RISCV_EXCP_NONE; 294 } 295 296 return RISCV_EXCP_ILLEGAL_INST; 297 } 298 299 static RISCVException debug(CPURISCVState *env, int csrno) 300 { 301 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 302 return RISCV_EXCP_NONE; 303 } 304 305 return RISCV_EXCP_ILLEGAL_INST; 306 } 307 #endif 308 309 static RISCVException seed(CPURISCVState *env, int csrno) 310 { 311 RISCVCPU *cpu = env_archcpu(env); 312 313 if (!cpu->cfg.ext_zkr) { 314 return RISCV_EXCP_ILLEGAL_INST; 315 } 316 317 #if !defined(CONFIG_USER_ONLY) 318 /* 319 * With a CSR read-write instruction: 320 * 1) The seed CSR is always available in machine mode as normal. 321 * 2) Attempted access to seed from virtual modes VS and VU always raises 322 * an exception(virtual instruction exception only if mseccfg.sseed=1). 323 * 3) Without the corresponding access control bit set to 1, any attempted 324 * access to seed from U, S or HS modes will raise an illegal instruction 325 * exception. 326 */ 327 if (env->priv == PRV_M) { 328 return RISCV_EXCP_NONE; 329 } else if (riscv_cpu_virt_enabled(env)) { 330 if (env->mseccfg & MSECCFG_SSEED) { 331 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 332 } else { 333 return RISCV_EXCP_ILLEGAL_INST; 334 } 335 } else { 336 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { 337 return RISCV_EXCP_NONE; 338 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { 339 return RISCV_EXCP_NONE; 340 } else { 341 return RISCV_EXCP_ILLEGAL_INST; 342 } 343 } 344 #else 345 return RISCV_EXCP_NONE; 346 #endif 347 } 348 349 /* User Floating-Point CSRs */ 350 static RISCVException read_fflags(CPURISCVState *env, int csrno, 351 target_ulong *val) 352 { 353 *val = riscv_cpu_get_fflags(env); 354 return RISCV_EXCP_NONE; 355 } 356 357 static RISCVException write_fflags(CPURISCVState *env, int csrno, 358 target_ulong val) 359 { 360 #if !defined(CONFIG_USER_ONLY) 361 if (riscv_has_ext(env, RVF)) { 362 env->mstatus |= MSTATUS_FS; 363 } 364 #endif 365 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 366 return RISCV_EXCP_NONE; 367 } 368 369 static RISCVException read_frm(CPURISCVState *env, int csrno, 370 target_ulong *val) 371 { 372 *val = env->frm; 373 return RISCV_EXCP_NONE; 374 } 375 376 static RISCVException write_frm(CPURISCVState *env, int csrno, 377 target_ulong val) 378 { 379 #if !defined(CONFIG_USER_ONLY) 380 if (riscv_has_ext(env, RVF)) { 381 env->mstatus |= MSTATUS_FS; 382 } 383 #endif 384 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 385 return RISCV_EXCP_NONE; 386 } 387 388 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 389 target_ulong *val) 390 { 391 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 392 | (env->frm << FSR_RD_SHIFT); 393 return RISCV_EXCP_NONE; 394 } 395 396 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 397 target_ulong val) 398 { 399 #if !defined(CONFIG_USER_ONLY) 400 if (riscv_has_ext(env, RVF)) { 401 env->mstatus |= MSTATUS_FS; 402 } 403 #endif 404 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 405 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 406 return RISCV_EXCP_NONE; 407 } 408 409 static RISCVException read_vtype(CPURISCVState *env, int csrno, 410 target_ulong *val) 411 { 412 uint64_t vill; 413 switch (env->xl) { 414 case MXL_RV32: 415 vill = (uint32_t)env->vill << 31; 416 break; 417 case MXL_RV64: 418 vill = (uint64_t)env->vill << 63; 419 break; 420 default: 421 g_assert_not_reached(); 422 } 423 *val = (target_ulong)vill | env->vtype; 424 return RISCV_EXCP_NONE; 425 } 426 427 static RISCVException read_vl(CPURISCVState *env, int csrno, 428 target_ulong *val) 429 { 430 *val = env->vl; 431 return RISCV_EXCP_NONE; 432 } 433 434 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 435 { 436 *val = env_archcpu(env)->cfg.vlen >> 3; 437 return RISCV_EXCP_NONE; 438 } 439 440 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 441 target_ulong *val) 442 { 443 *val = env->vxrm; 444 return RISCV_EXCP_NONE; 445 } 446 447 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 448 target_ulong val) 449 { 450 #if !defined(CONFIG_USER_ONLY) 451 env->mstatus |= MSTATUS_VS; 452 #endif 453 env->vxrm = val; 454 return RISCV_EXCP_NONE; 455 } 456 457 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 458 target_ulong *val) 459 { 460 *val = env->vxsat; 461 return RISCV_EXCP_NONE; 462 } 463 464 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 465 target_ulong val) 466 { 467 #if !defined(CONFIG_USER_ONLY) 468 env->mstatus |= MSTATUS_VS; 469 #endif 470 env->vxsat = val; 471 return RISCV_EXCP_NONE; 472 } 473 474 static RISCVException read_vstart(CPURISCVState *env, int csrno, 475 target_ulong *val) 476 { 477 *val = env->vstart; 478 return RISCV_EXCP_NONE; 479 } 480 481 static RISCVException write_vstart(CPURISCVState *env, int csrno, 482 target_ulong val) 483 { 484 #if !defined(CONFIG_USER_ONLY) 485 env->mstatus |= MSTATUS_VS; 486 #endif 487 /* 488 * The vstart CSR is defined to have only enough writable bits 489 * to hold the largest element index, i.e. lg2(VLEN) bits. 490 */ 491 env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); 492 return RISCV_EXCP_NONE; 493 } 494 495 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 496 { 497 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 498 return RISCV_EXCP_NONE; 499 } 500 501 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 502 { 503 #if !defined(CONFIG_USER_ONLY) 504 env->mstatus |= MSTATUS_VS; 505 #endif 506 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 507 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 508 return RISCV_EXCP_NONE; 509 } 510 511 /* User Timers and Counters */ 512 static RISCVException read_instret(CPURISCVState *env, int csrno, 513 target_ulong *val) 514 { 515 #if !defined(CONFIG_USER_ONLY) 516 if (icount_enabled()) { 517 *val = icount_get(); 518 } else { 519 *val = cpu_get_host_ticks(); 520 } 521 #else 522 *val = cpu_get_host_ticks(); 523 #endif 524 return RISCV_EXCP_NONE; 525 } 526 527 static RISCVException read_instreth(CPURISCVState *env, int csrno, 528 target_ulong *val) 529 { 530 #if !defined(CONFIG_USER_ONLY) 531 if (icount_enabled()) { 532 *val = icount_get() >> 32; 533 } else { 534 *val = cpu_get_host_ticks() >> 32; 535 } 536 #else 537 *val = cpu_get_host_ticks() >> 32; 538 #endif 539 return RISCV_EXCP_NONE; 540 } 541 542 #if defined(CONFIG_USER_ONLY) 543 static RISCVException read_time(CPURISCVState *env, int csrno, 544 target_ulong *val) 545 { 546 *val = cpu_get_host_ticks(); 547 return RISCV_EXCP_NONE; 548 } 549 550 static RISCVException read_timeh(CPURISCVState *env, int csrno, 551 target_ulong *val) 552 { 553 *val = cpu_get_host_ticks() >> 32; 554 return RISCV_EXCP_NONE; 555 } 556 557 #else /* CONFIG_USER_ONLY */ 558 559 static RISCVException read_time(CPURISCVState *env, int csrno, 560 target_ulong *val) 561 { 562 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 563 564 if (!env->rdtime_fn) { 565 return RISCV_EXCP_ILLEGAL_INST; 566 } 567 568 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 569 return RISCV_EXCP_NONE; 570 } 571 572 static RISCVException read_timeh(CPURISCVState *env, int csrno, 573 target_ulong *val) 574 { 575 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 576 577 if (!env->rdtime_fn) { 578 return RISCV_EXCP_ILLEGAL_INST; 579 } 580 581 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 582 return RISCV_EXCP_NONE; 583 } 584 585 /* Machine constants */ 586 587 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 588 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 589 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 590 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 591 592 #define VSTOPI_NUM_SRCS 5 593 594 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | 595 VS_MODE_INTERRUPTS; 596 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; 597 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 598 HS_MODE_INTERRUPTS; 599 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 600 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 601 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 602 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 603 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 604 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 605 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 606 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 607 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 608 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 609 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 610 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 611 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 612 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 613 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 614 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 615 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 616 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 617 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 618 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 619 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 620 (1ULL << (RISCV_EXCP_VS_ECALL)) | 621 (1ULL << (RISCV_EXCP_M_ECALL)) | 622 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 623 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 624 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 625 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 626 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 627 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 628 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 629 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 630 static const target_ulong hip_writable_mask = MIP_VSSIP; 631 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 632 static const target_ulong vsip_writable_mask = MIP_VSSIP; 633 634 static const char valid_vm_1_10_32[16] = { 635 [VM_1_10_MBARE] = 1, 636 [VM_1_10_SV32] = 1 637 }; 638 639 static const char valid_vm_1_10_64[16] = { 640 [VM_1_10_MBARE] = 1, 641 [VM_1_10_SV39] = 1, 642 [VM_1_10_SV48] = 1, 643 [VM_1_10_SV57] = 1 644 }; 645 646 /* Machine Information Registers */ 647 static RISCVException read_zero(CPURISCVState *env, int csrno, 648 target_ulong *val) 649 { 650 *val = 0; 651 return RISCV_EXCP_NONE; 652 } 653 654 static RISCVException write_ignore(CPURISCVState *env, int csrno, 655 target_ulong val) 656 { 657 return RISCV_EXCP_NONE; 658 } 659 660 static RISCVException read_mvendorid(CPURISCVState *env, int csrno, 661 target_ulong *val) 662 { 663 CPUState *cs = env_cpu(env); 664 RISCVCPU *cpu = RISCV_CPU(cs); 665 666 *val = cpu->cfg.mvendorid; 667 return RISCV_EXCP_NONE; 668 } 669 670 static RISCVException read_marchid(CPURISCVState *env, int csrno, 671 target_ulong *val) 672 { 673 CPUState *cs = env_cpu(env); 674 RISCVCPU *cpu = RISCV_CPU(cs); 675 676 *val = cpu->cfg.marchid; 677 return RISCV_EXCP_NONE; 678 } 679 680 static RISCVException read_mimpid(CPURISCVState *env, int csrno, 681 target_ulong *val) 682 { 683 CPUState *cs = env_cpu(env); 684 RISCVCPU *cpu = RISCV_CPU(cs); 685 686 *val = cpu->cfg.mimpid; 687 return RISCV_EXCP_NONE; 688 } 689 690 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 691 target_ulong *val) 692 { 693 *val = env->mhartid; 694 return RISCV_EXCP_NONE; 695 } 696 697 /* Machine Trap Setup */ 698 699 /* We do not store SD explicitly, only compute it on demand. */ 700 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 701 { 702 if ((status & MSTATUS_FS) == MSTATUS_FS || 703 (status & MSTATUS_VS) == MSTATUS_VS || 704 (status & MSTATUS_XS) == MSTATUS_XS) { 705 switch (xl) { 706 case MXL_RV32: 707 return status | MSTATUS32_SD; 708 case MXL_RV64: 709 return status | MSTATUS64_SD; 710 case MXL_RV128: 711 return MSTATUSH128_SD; 712 default: 713 g_assert_not_reached(); 714 } 715 } 716 return status; 717 } 718 719 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 720 target_ulong *val) 721 { 722 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 723 return RISCV_EXCP_NONE; 724 } 725 726 static int validate_vm(CPURISCVState *env, target_ulong vm) 727 { 728 if (riscv_cpu_mxl(env) == MXL_RV32) { 729 return valid_vm_1_10_32[vm & 0xf]; 730 } else { 731 return valid_vm_1_10_64[vm & 0xf]; 732 } 733 } 734 735 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 736 target_ulong val) 737 { 738 uint64_t mstatus = env->mstatus; 739 uint64_t mask = 0; 740 RISCVMXL xl = riscv_cpu_mxl(env); 741 742 /* flush tlb on mstatus fields that affect VM */ 743 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 744 MSTATUS_MPRV | MSTATUS_SUM)) { 745 tlb_flush(env_cpu(env)); 746 } 747 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 748 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 749 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 750 MSTATUS_TW | MSTATUS_VS; 751 752 if (riscv_has_ext(env, RVF)) { 753 mask |= MSTATUS_FS; 754 } 755 756 if (xl != MXL_RV32 || env->debugger) { 757 /* 758 * RV32: MPV and GVA are not in mstatus. The current plan is to 759 * add them to mstatush. For now, we just don't support it. 760 */ 761 mask |= MSTATUS_MPV | MSTATUS_GVA; 762 if ((val & MSTATUS64_UXL) != 0) { 763 mask |= MSTATUS64_UXL; 764 } 765 } 766 767 mstatus = (mstatus & ~mask) | (val & mask); 768 769 if (xl > MXL_RV32) { 770 /* SXL field is for now read only */ 771 mstatus = set_field(mstatus, MSTATUS64_SXL, xl); 772 } 773 env->mstatus = mstatus; 774 env->xl = cpu_recompute_xl(env); 775 776 return RISCV_EXCP_NONE; 777 } 778 779 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 780 target_ulong *val) 781 { 782 *val = env->mstatus >> 32; 783 return RISCV_EXCP_NONE; 784 } 785 786 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 787 target_ulong val) 788 { 789 uint64_t valh = (uint64_t)val << 32; 790 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 791 792 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 793 tlb_flush(env_cpu(env)); 794 } 795 796 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 797 798 return RISCV_EXCP_NONE; 799 } 800 801 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 802 Int128 *val) 803 { 804 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); 805 return RISCV_EXCP_NONE; 806 } 807 808 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 809 Int128 *val) 810 { 811 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 812 return RISCV_EXCP_NONE; 813 } 814 815 static RISCVException read_misa(CPURISCVState *env, int csrno, 816 target_ulong *val) 817 { 818 target_ulong misa; 819 820 switch (env->misa_mxl) { 821 case MXL_RV32: 822 misa = (target_ulong)MXL_RV32 << 30; 823 break; 824 #ifdef TARGET_RISCV64 825 case MXL_RV64: 826 misa = (target_ulong)MXL_RV64 << 62; 827 break; 828 #endif 829 default: 830 g_assert_not_reached(); 831 } 832 833 *val = misa | env->misa_ext; 834 return RISCV_EXCP_NONE; 835 } 836 837 static RISCVException write_misa(CPURISCVState *env, int csrno, 838 target_ulong val) 839 { 840 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 841 /* drop write to misa */ 842 return RISCV_EXCP_NONE; 843 } 844 845 /* 'I' or 'E' must be present */ 846 if (!(val & (RVI | RVE))) { 847 /* It is not, drop write to misa */ 848 return RISCV_EXCP_NONE; 849 } 850 851 /* 'E' excludes all other extensions */ 852 if (val & RVE) { 853 /* when we support 'E' we can do "val = RVE;" however 854 * for now we just drop writes if 'E' is present. 855 */ 856 return RISCV_EXCP_NONE; 857 } 858 859 /* 860 * misa.MXL writes are not supported by QEMU. 861 * Drop writes to those bits. 862 */ 863 864 /* Mask extensions that are not supported by this hart */ 865 val &= env->misa_ext_mask; 866 867 /* Mask extensions that are not supported by QEMU */ 868 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 869 870 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 871 if ((val & RVD) && !(val & RVF)) { 872 val &= ~RVD; 873 } 874 875 /* Suppress 'C' if next instruction is not aligned 876 * TODO: this should check next_pc 877 */ 878 if ((val & RVC) && (GETPC() & ~3) != 0) { 879 val &= ~RVC; 880 } 881 882 /* If nothing changed, do nothing. */ 883 if (val == env->misa_ext) { 884 return RISCV_EXCP_NONE; 885 } 886 887 if (!(val & RVF)) { 888 env->mstatus &= ~MSTATUS_FS; 889 } 890 891 /* flush translation cache */ 892 tb_flush(env_cpu(env)); 893 env->misa_ext = val; 894 env->xl = riscv_cpu_mxl(env); 895 return RISCV_EXCP_NONE; 896 } 897 898 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 899 target_ulong *val) 900 { 901 *val = env->medeleg; 902 return RISCV_EXCP_NONE; 903 } 904 905 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 906 target_ulong val) 907 { 908 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 909 return RISCV_EXCP_NONE; 910 } 911 912 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 913 uint64_t *ret_val, 914 uint64_t new_val, uint64_t wr_mask) 915 { 916 uint64_t mask = wr_mask & delegable_ints; 917 918 if (ret_val) { 919 *ret_val = env->mideleg; 920 } 921 922 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 923 924 if (riscv_has_ext(env, RVH)) { 925 env->mideleg |= HS_MODE_INTERRUPTS; 926 } 927 928 return RISCV_EXCP_NONE; 929 } 930 931 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 932 target_ulong *ret_val, 933 target_ulong new_val, target_ulong wr_mask) 934 { 935 uint64_t rval; 936 RISCVException ret; 937 938 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 939 if (ret_val) { 940 *ret_val = rval; 941 } 942 943 return ret; 944 } 945 946 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 947 target_ulong *ret_val, 948 target_ulong new_val, 949 target_ulong wr_mask) 950 { 951 uint64_t rval; 952 RISCVException ret; 953 954 ret = rmw_mideleg64(env, csrno, &rval, 955 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 956 if (ret_val) { 957 *ret_val = rval >> 32; 958 } 959 960 return ret; 961 } 962 963 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 964 uint64_t *ret_val, 965 uint64_t new_val, uint64_t wr_mask) 966 { 967 uint64_t mask = wr_mask & all_ints; 968 969 if (ret_val) { 970 *ret_val = env->mie; 971 } 972 973 env->mie = (env->mie & ~mask) | (new_val & mask); 974 975 if (!riscv_has_ext(env, RVH)) { 976 env->mie &= ~((uint64_t)MIP_SGEIP); 977 } 978 979 return RISCV_EXCP_NONE; 980 } 981 982 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 983 target_ulong *ret_val, 984 target_ulong new_val, target_ulong wr_mask) 985 { 986 uint64_t rval; 987 RISCVException ret; 988 989 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 990 if (ret_val) { 991 *ret_val = rval; 992 } 993 994 return ret; 995 } 996 997 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 998 target_ulong *ret_val, 999 target_ulong new_val, target_ulong wr_mask) 1000 { 1001 uint64_t rval; 1002 RISCVException ret; 1003 1004 ret = rmw_mie64(env, csrno, &rval, 1005 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1006 if (ret_val) { 1007 *ret_val = rval >> 32; 1008 } 1009 1010 return ret; 1011 } 1012 1013 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 1014 { 1015 int irq; 1016 uint8_t iprio; 1017 1018 irq = riscv_cpu_mirq_pending(env); 1019 if (irq <= 0 || irq > 63) { 1020 *val = 0; 1021 } else { 1022 iprio = env->miprio[irq]; 1023 if (!iprio) { 1024 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 1025 iprio = IPRIO_MMAXIPRIO; 1026 } 1027 } 1028 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 1029 *val |= iprio; 1030 } 1031 1032 return RISCV_EXCP_NONE; 1033 } 1034 1035 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 1036 { 1037 if (!riscv_cpu_virt_enabled(env)) { 1038 return csrno; 1039 } 1040 1041 switch (csrno) { 1042 case CSR_SISELECT: 1043 return CSR_VSISELECT; 1044 case CSR_SIREG: 1045 return CSR_VSIREG; 1046 case CSR_SSETEIPNUM: 1047 return CSR_VSSETEIPNUM; 1048 case CSR_SCLREIPNUM: 1049 return CSR_VSCLREIPNUM; 1050 case CSR_SSETEIENUM: 1051 return CSR_VSSETEIENUM; 1052 case CSR_SCLREIENUM: 1053 return CSR_VSCLREIENUM; 1054 case CSR_STOPEI: 1055 return CSR_VSTOPEI; 1056 default: 1057 return csrno; 1058 }; 1059 } 1060 1061 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 1062 target_ulong new_val, target_ulong wr_mask) 1063 { 1064 target_ulong *iselect; 1065 1066 /* Translate CSR number for VS-mode */ 1067 csrno = aia_xlate_vs_csrno(env, csrno); 1068 1069 /* Find the iselect CSR based on CSR number */ 1070 switch (csrno) { 1071 case CSR_MISELECT: 1072 iselect = &env->miselect; 1073 break; 1074 case CSR_SISELECT: 1075 iselect = &env->siselect; 1076 break; 1077 case CSR_VSISELECT: 1078 iselect = &env->vsiselect; 1079 break; 1080 default: 1081 return RISCV_EXCP_ILLEGAL_INST; 1082 }; 1083 1084 if (val) { 1085 *val = *iselect; 1086 } 1087 1088 wr_mask &= ISELECT_MASK; 1089 if (wr_mask) { 1090 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1091 } 1092 1093 return RISCV_EXCP_NONE; 1094 } 1095 1096 static int rmw_iprio(target_ulong xlen, 1097 target_ulong iselect, uint8_t *iprio, 1098 target_ulong *val, target_ulong new_val, 1099 target_ulong wr_mask, int ext_irq_no) 1100 { 1101 int i, firq, nirqs; 1102 target_ulong old_val; 1103 1104 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1105 return -EINVAL; 1106 } 1107 if (xlen != 32 && iselect & 0x1) { 1108 return -EINVAL; 1109 } 1110 1111 nirqs = 4 * (xlen / 32); 1112 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1113 1114 old_val = 0; 1115 for (i = 0; i < nirqs; i++) { 1116 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1117 } 1118 1119 if (val) { 1120 *val = old_val; 1121 } 1122 1123 if (wr_mask) { 1124 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1125 for (i = 0; i < nirqs; i++) { 1126 /* 1127 * M-level and S-level external IRQ priority always read-only 1128 * zero. This means default priority order is always preferred 1129 * for M-level and S-level external IRQs. 1130 */ 1131 if ((firq + i) == ext_irq_no) { 1132 continue; 1133 } 1134 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1135 } 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1142 target_ulong new_val, target_ulong wr_mask) 1143 { 1144 bool virt; 1145 uint8_t *iprio; 1146 int ret = -EINVAL; 1147 target_ulong priv, isel, vgein; 1148 1149 /* Translate CSR number for VS-mode */ 1150 csrno = aia_xlate_vs_csrno(env, csrno); 1151 1152 /* Decode register details from CSR number */ 1153 virt = false; 1154 switch (csrno) { 1155 case CSR_MIREG: 1156 iprio = env->miprio; 1157 isel = env->miselect; 1158 priv = PRV_M; 1159 break; 1160 case CSR_SIREG: 1161 iprio = env->siprio; 1162 isel = env->siselect; 1163 priv = PRV_S; 1164 break; 1165 case CSR_VSIREG: 1166 iprio = env->hviprio; 1167 isel = env->vsiselect; 1168 priv = PRV_S; 1169 virt = true; 1170 break; 1171 default: 1172 goto done; 1173 }; 1174 1175 /* Find the selected guest interrupt file */ 1176 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1177 1178 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1179 /* Local interrupt priority registers not available for VS-mode */ 1180 if (!virt) { 1181 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1182 isel, iprio, val, new_val, wr_mask, 1183 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1184 } 1185 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1186 /* IMSIC registers only available when machine implements it. */ 1187 if (env->aia_ireg_rmw_fn[priv]) { 1188 /* Selected guest interrupt file should not be zero */ 1189 if (virt && (!vgein || env->geilen < vgein)) { 1190 goto done; 1191 } 1192 /* Call machine specific IMSIC register emulation */ 1193 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1194 AIA_MAKE_IREG(isel, priv, virt, vgein, 1195 riscv_cpu_mxl_bits(env)), 1196 val, new_val, wr_mask); 1197 } 1198 } 1199 1200 done: 1201 if (ret) { 1202 return (riscv_cpu_virt_enabled(env) && virt) ? 1203 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1204 } 1205 return RISCV_EXCP_NONE; 1206 } 1207 1208 static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val, 1209 target_ulong new_val, target_ulong wr_mask) 1210 { 1211 int ret = -EINVAL; 1212 bool set, pend, virt; 1213 target_ulong priv, isel, vgein, xlen, nval, wmask; 1214 1215 /* Translate CSR number for VS-mode */ 1216 csrno = aia_xlate_vs_csrno(env, csrno); 1217 1218 /* Decode register details from CSR number */ 1219 virt = set = pend = false; 1220 switch (csrno) { 1221 case CSR_MSETEIPNUM: 1222 priv = PRV_M; 1223 set = true; 1224 pend = true; 1225 break; 1226 case CSR_MCLREIPNUM: 1227 priv = PRV_M; 1228 pend = true; 1229 break; 1230 case CSR_MSETEIENUM: 1231 priv = PRV_M; 1232 set = true; 1233 break; 1234 case CSR_MCLREIENUM: 1235 priv = PRV_M; 1236 break; 1237 case CSR_SSETEIPNUM: 1238 priv = PRV_S; 1239 set = true; 1240 pend = true; 1241 break; 1242 case CSR_SCLREIPNUM: 1243 priv = PRV_S; 1244 pend = true; 1245 break; 1246 case CSR_SSETEIENUM: 1247 priv = PRV_S; 1248 set = true; 1249 break; 1250 case CSR_SCLREIENUM: 1251 priv = PRV_S; 1252 break; 1253 case CSR_VSSETEIPNUM: 1254 priv = PRV_S; 1255 virt = true; 1256 set = true; 1257 pend = true; 1258 break; 1259 case CSR_VSCLREIPNUM: 1260 priv = PRV_S; 1261 virt = true; 1262 pend = true; 1263 break; 1264 case CSR_VSSETEIENUM: 1265 priv = PRV_S; 1266 virt = true; 1267 set = true; 1268 break; 1269 case CSR_VSCLREIENUM: 1270 priv = PRV_S; 1271 virt = true; 1272 break; 1273 default: 1274 goto done; 1275 }; 1276 1277 /* IMSIC CSRs only available when machine implements IMSIC. */ 1278 if (!env->aia_ireg_rmw_fn[priv]) { 1279 goto done; 1280 } 1281 1282 /* Find the selected guest interrupt file */ 1283 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1284 1285 /* Selected guest interrupt file should be valid */ 1286 if (virt && (!vgein || env->geilen < vgein)) { 1287 goto done; 1288 } 1289 1290 /* Set/Clear CSRs always read zero */ 1291 if (val) { 1292 *val = 0; 1293 } 1294 1295 if (wr_mask) { 1296 /* Get interrupt number */ 1297 new_val &= wr_mask; 1298 1299 /* Find target interrupt pending/enable register */ 1300 xlen = riscv_cpu_mxl_bits(env); 1301 isel = (new_val / xlen); 1302 isel *= (xlen / IMSIC_EIPx_BITS); 1303 isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; 1304 1305 /* Find the interrupt bit to be set/clear */ 1306 wmask = ((target_ulong)1) << (new_val % xlen); 1307 nval = (set) ? wmask : 0; 1308 1309 /* Call machine specific IMSIC register emulation */ 1310 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1311 AIA_MAKE_IREG(isel, priv, virt, 1312 vgein, xlen), 1313 NULL, nval, wmask); 1314 } else { 1315 ret = 0; 1316 } 1317 1318 done: 1319 if (ret) { 1320 return (riscv_cpu_virt_enabled(env) && virt) ? 1321 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1322 } 1323 return RISCV_EXCP_NONE; 1324 } 1325 1326 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1327 target_ulong new_val, target_ulong wr_mask) 1328 { 1329 bool virt; 1330 int ret = -EINVAL; 1331 target_ulong priv, vgein; 1332 1333 /* Translate CSR number for VS-mode */ 1334 csrno = aia_xlate_vs_csrno(env, csrno); 1335 1336 /* Decode register details from CSR number */ 1337 virt = false; 1338 switch (csrno) { 1339 case CSR_MTOPEI: 1340 priv = PRV_M; 1341 break; 1342 case CSR_STOPEI: 1343 priv = PRV_S; 1344 break; 1345 case CSR_VSTOPEI: 1346 priv = PRV_S; 1347 virt = true; 1348 break; 1349 default: 1350 goto done; 1351 }; 1352 1353 /* IMSIC CSRs only available when machine implements IMSIC. */ 1354 if (!env->aia_ireg_rmw_fn[priv]) { 1355 goto done; 1356 } 1357 1358 /* Find the selected guest interrupt file */ 1359 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1360 1361 /* Selected guest interrupt file should be valid */ 1362 if (virt && (!vgein || env->geilen < vgein)) { 1363 goto done; 1364 } 1365 1366 /* Call machine specific IMSIC register emulation for TOPEI */ 1367 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1368 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1369 riscv_cpu_mxl_bits(env)), 1370 val, new_val, wr_mask); 1371 1372 done: 1373 if (ret) { 1374 return (riscv_cpu_virt_enabled(env) && virt) ? 1375 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1376 } 1377 return RISCV_EXCP_NONE; 1378 } 1379 1380 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1381 target_ulong *val) 1382 { 1383 *val = env->mtvec; 1384 return RISCV_EXCP_NONE; 1385 } 1386 1387 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1388 target_ulong val) 1389 { 1390 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1391 if ((val & 3) < 2) { 1392 env->mtvec = val; 1393 } else { 1394 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1395 } 1396 return RISCV_EXCP_NONE; 1397 } 1398 1399 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1400 target_ulong *val) 1401 { 1402 *val = env->mcounteren; 1403 return RISCV_EXCP_NONE; 1404 } 1405 1406 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1407 target_ulong val) 1408 { 1409 env->mcounteren = val; 1410 return RISCV_EXCP_NONE; 1411 } 1412 1413 /* Machine Trap Handling */ 1414 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1415 Int128 *val) 1416 { 1417 *val = int128_make128(env->mscratch, env->mscratchh); 1418 return RISCV_EXCP_NONE; 1419 } 1420 1421 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1422 Int128 val) 1423 { 1424 env->mscratch = int128_getlo(val); 1425 env->mscratchh = int128_gethi(val); 1426 return RISCV_EXCP_NONE; 1427 } 1428 1429 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1430 target_ulong *val) 1431 { 1432 *val = env->mscratch; 1433 return RISCV_EXCP_NONE; 1434 } 1435 1436 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1437 target_ulong val) 1438 { 1439 env->mscratch = val; 1440 return RISCV_EXCP_NONE; 1441 } 1442 1443 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1444 target_ulong *val) 1445 { 1446 *val = env->mepc; 1447 return RISCV_EXCP_NONE; 1448 } 1449 1450 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1451 target_ulong val) 1452 { 1453 env->mepc = val; 1454 return RISCV_EXCP_NONE; 1455 } 1456 1457 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1458 target_ulong *val) 1459 { 1460 *val = env->mcause; 1461 return RISCV_EXCP_NONE; 1462 } 1463 1464 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1465 target_ulong val) 1466 { 1467 env->mcause = val; 1468 return RISCV_EXCP_NONE; 1469 } 1470 1471 static RISCVException read_mtval(CPURISCVState *env, int csrno, 1472 target_ulong *val) 1473 { 1474 *val = env->mtval; 1475 return RISCV_EXCP_NONE; 1476 } 1477 1478 static RISCVException write_mtval(CPURISCVState *env, int csrno, 1479 target_ulong val) 1480 { 1481 env->mtval = val; 1482 return RISCV_EXCP_NONE; 1483 } 1484 1485 /* Execution environment configuration setup */ 1486 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 1487 target_ulong *val) 1488 { 1489 *val = env->menvcfg; 1490 return RISCV_EXCP_NONE; 1491 } 1492 1493 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 1494 target_ulong val) 1495 { 1496 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 1497 1498 if (riscv_cpu_mxl(env) == MXL_RV64) { 1499 mask |= MENVCFG_PBMTE | MENVCFG_STCE; 1500 } 1501 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 1502 1503 return RISCV_EXCP_NONE; 1504 } 1505 1506 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 1507 target_ulong *val) 1508 { 1509 *val = env->menvcfg >> 32; 1510 return RISCV_EXCP_NONE; 1511 } 1512 1513 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 1514 target_ulong val) 1515 { 1516 uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; 1517 uint64_t valh = (uint64_t)val << 32; 1518 1519 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 1520 1521 return RISCV_EXCP_NONE; 1522 } 1523 1524 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 1525 target_ulong *val) 1526 { 1527 *val = env->senvcfg; 1528 return RISCV_EXCP_NONE; 1529 } 1530 1531 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 1532 target_ulong val) 1533 { 1534 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 1535 1536 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 1537 1538 return RISCV_EXCP_NONE; 1539 } 1540 1541 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 1542 target_ulong *val) 1543 { 1544 *val = env->henvcfg; 1545 return RISCV_EXCP_NONE; 1546 } 1547 1548 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 1549 target_ulong val) 1550 { 1551 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 1552 1553 if (riscv_cpu_mxl(env) == MXL_RV64) { 1554 mask |= HENVCFG_PBMTE | HENVCFG_STCE; 1555 } 1556 1557 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 1558 1559 return RISCV_EXCP_NONE; 1560 } 1561 1562 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 1563 target_ulong *val) 1564 { 1565 *val = env->henvcfg >> 32; 1566 return RISCV_EXCP_NONE; 1567 } 1568 1569 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 1570 target_ulong val) 1571 { 1572 uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; 1573 uint64_t valh = (uint64_t)val << 32; 1574 1575 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 1576 1577 return RISCV_EXCP_NONE; 1578 } 1579 1580 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 1581 uint64_t *ret_val, 1582 uint64_t new_val, uint64_t wr_mask) 1583 { 1584 RISCVCPU *cpu = env_archcpu(env); 1585 uint64_t old_mip, mask = wr_mask & delegable_ints; 1586 uint32_t gin; 1587 1588 if (mask & MIP_SEIP) { 1589 env->software_seip = new_val & MIP_SEIP; 1590 new_val |= env->external_seip * MIP_SEIP; 1591 } 1592 1593 if (mask) { 1594 old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); 1595 } else { 1596 old_mip = env->mip; 1597 } 1598 1599 if (csrno != CSR_HVIP) { 1600 gin = get_field(env->hstatus, HSTATUS_VGEIN); 1601 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 1602 } 1603 1604 if (ret_val) { 1605 *ret_val = old_mip; 1606 } 1607 1608 return RISCV_EXCP_NONE; 1609 } 1610 1611 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 1612 target_ulong *ret_val, 1613 target_ulong new_val, target_ulong wr_mask) 1614 { 1615 uint64_t rval; 1616 RISCVException ret; 1617 1618 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 1619 if (ret_val) { 1620 *ret_val = rval; 1621 } 1622 1623 return ret; 1624 } 1625 1626 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 1627 target_ulong *ret_val, 1628 target_ulong new_val, target_ulong wr_mask) 1629 { 1630 uint64_t rval; 1631 RISCVException ret; 1632 1633 ret = rmw_mip64(env, csrno, &rval, 1634 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1635 if (ret_val) { 1636 *ret_val = rval >> 32; 1637 } 1638 1639 return ret; 1640 } 1641 1642 /* Supervisor Trap Setup */ 1643 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 1644 Int128 *val) 1645 { 1646 uint64_t mask = sstatus_v1_10_mask; 1647 uint64_t sstatus = env->mstatus & mask; 1648 if (env->xl != MXL_RV32 || env->debugger) { 1649 mask |= SSTATUS64_UXL; 1650 } 1651 1652 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 1653 return RISCV_EXCP_NONE; 1654 } 1655 1656 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 1657 target_ulong *val) 1658 { 1659 target_ulong mask = (sstatus_v1_10_mask); 1660 if (env->xl != MXL_RV32 || env->debugger) { 1661 mask |= SSTATUS64_UXL; 1662 } 1663 /* TODO: Use SXL not MXL. */ 1664 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 1665 return RISCV_EXCP_NONE; 1666 } 1667 1668 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 1669 target_ulong val) 1670 { 1671 target_ulong mask = (sstatus_v1_10_mask); 1672 1673 if (env->xl != MXL_RV32 || env->debugger) { 1674 if ((val & SSTATUS64_UXL) != 0) { 1675 mask |= SSTATUS64_UXL; 1676 } 1677 } 1678 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 1679 return write_mstatus(env, CSR_MSTATUS, newval); 1680 } 1681 1682 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 1683 uint64_t *ret_val, 1684 uint64_t new_val, uint64_t wr_mask) 1685 { 1686 RISCVException ret; 1687 uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; 1688 1689 /* Bring VS-level bits to correct position */ 1690 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1691 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1692 new_val |= vsbits << 1; 1693 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1694 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1695 wr_mask |= vsbits << 1; 1696 1697 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); 1698 if (ret_val) { 1699 rval &= mask; 1700 vsbits = rval & VS_MODE_INTERRUPTS; 1701 rval &= ~VS_MODE_INTERRUPTS; 1702 *ret_val = rval | (vsbits >> 1); 1703 } 1704 1705 return ret; 1706 } 1707 1708 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 1709 target_ulong *ret_val, 1710 target_ulong new_val, target_ulong wr_mask) 1711 { 1712 uint64_t rval; 1713 RISCVException ret; 1714 1715 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 1716 if (ret_val) { 1717 *ret_val = rval; 1718 } 1719 1720 return ret; 1721 } 1722 1723 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 1724 target_ulong *ret_val, 1725 target_ulong new_val, target_ulong wr_mask) 1726 { 1727 uint64_t rval; 1728 RISCVException ret; 1729 1730 ret = rmw_vsie64(env, csrno, &rval, 1731 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1732 if (ret_val) { 1733 *ret_val = rval >> 32; 1734 } 1735 1736 return ret; 1737 } 1738 1739 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 1740 uint64_t *ret_val, 1741 uint64_t new_val, uint64_t wr_mask) 1742 { 1743 RISCVException ret; 1744 uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; 1745 1746 if (riscv_cpu_virt_enabled(env)) { 1747 if (env->hvictl & HVICTL_VTI) { 1748 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1749 } 1750 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 1751 } else { 1752 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); 1753 } 1754 1755 if (ret_val) { 1756 *ret_val &= mask; 1757 } 1758 1759 return ret; 1760 } 1761 1762 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 1763 target_ulong *ret_val, 1764 target_ulong new_val, target_ulong wr_mask) 1765 { 1766 uint64_t rval; 1767 RISCVException ret; 1768 1769 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 1770 if (ret == RISCV_EXCP_NONE && ret_val) { 1771 *ret_val = rval; 1772 } 1773 1774 return ret; 1775 } 1776 1777 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 1778 target_ulong *ret_val, 1779 target_ulong new_val, target_ulong wr_mask) 1780 { 1781 uint64_t rval; 1782 RISCVException ret; 1783 1784 ret = rmw_sie64(env, csrno, &rval, 1785 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1786 if (ret_val) { 1787 *ret_val = rval >> 32; 1788 } 1789 1790 return ret; 1791 } 1792 1793 static RISCVException read_stvec(CPURISCVState *env, int csrno, 1794 target_ulong *val) 1795 { 1796 *val = env->stvec; 1797 return RISCV_EXCP_NONE; 1798 } 1799 1800 static RISCVException write_stvec(CPURISCVState *env, int csrno, 1801 target_ulong val) 1802 { 1803 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1804 if ((val & 3) < 2) { 1805 env->stvec = val; 1806 } else { 1807 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 1808 } 1809 return RISCV_EXCP_NONE; 1810 } 1811 1812 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 1813 target_ulong *val) 1814 { 1815 *val = env->scounteren; 1816 return RISCV_EXCP_NONE; 1817 } 1818 1819 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 1820 target_ulong val) 1821 { 1822 env->scounteren = val; 1823 return RISCV_EXCP_NONE; 1824 } 1825 1826 /* Supervisor Trap Handling */ 1827 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 1828 Int128 *val) 1829 { 1830 *val = int128_make128(env->sscratch, env->sscratchh); 1831 return RISCV_EXCP_NONE; 1832 } 1833 1834 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 1835 Int128 val) 1836 { 1837 env->sscratch = int128_getlo(val); 1838 env->sscratchh = int128_gethi(val); 1839 return RISCV_EXCP_NONE; 1840 } 1841 1842 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 1843 target_ulong *val) 1844 { 1845 *val = env->sscratch; 1846 return RISCV_EXCP_NONE; 1847 } 1848 1849 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 1850 target_ulong val) 1851 { 1852 env->sscratch = val; 1853 return RISCV_EXCP_NONE; 1854 } 1855 1856 static RISCVException read_sepc(CPURISCVState *env, int csrno, 1857 target_ulong *val) 1858 { 1859 *val = env->sepc; 1860 return RISCV_EXCP_NONE; 1861 } 1862 1863 static RISCVException write_sepc(CPURISCVState *env, int csrno, 1864 target_ulong val) 1865 { 1866 env->sepc = val; 1867 return RISCV_EXCP_NONE; 1868 } 1869 1870 static RISCVException read_scause(CPURISCVState *env, int csrno, 1871 target_ulong *val) 1872 { 1873 *val = env->scause; 1874 return RISCV_EXCP_NONE; 1875 } 1876 1877 static RISCVException write_scause(CPURISCVState *env, int csrno, 1878 target_ulong val) 1879 { 1880 env->scause = val; 1881 return RISCV_EXCP_NONE; 1882 } 1883 1884 static RISCVException read_stval(CPURISCVState *env, int csrno, 1885 target_ulong *val) 1886 { 1887 *val = env->stval; 1888 return RISCV_EXCP_NONE; 1889 } 1890 1891 static RISCVException write_stval(CPURISCVState *env, int csrno, 1892 target_ulong val) 1893 { 1894 env->stval = val; 1895 return RISCV_EXCP_NONE; 1896 } 1897 1898 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 1899 uint64_t *ret_val, 1900 uint64_t new_val, uint64_t wr_mask) 1901 { 1902 RISCVException ret; 1903 uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; 1904 1905 /* Bring VS-level bits to correct position */ 1906 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1907 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1908 new_val |= vsbits << 1; 1909 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1910 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1911 wr_mask |= vsbits << 1; 1912 1913 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); 1914 if (ret_val) { 1915 rval &= mask; 1916 vsbits = rval & VS_MODE_INTERRUPTS; 1917 rval &= ~VS_MODE_INTERRUPTS; 1918 *ret_val = rval | (vsbits >> 1); 1919 } 1920 1921 return ret; 1922 } 1923 1924 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 1925 target_ulong *ret_val, 1926 target_ulong new_val, target_ulong wr_mask) 1927 { 1928 uint64_t rval; 1929 RISCVException ret; 1930 1931 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 1932 if (ret_val) { 1933 *ret_val = rval; 1934 } 1935 1936 return ret; 1937 } 1938 1939 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 1940 target_ulong *ret_val, 1941 target_ulong new_val, target_ulong wr_mask) 1942 { 1943 uint64_t rval; 1944 RISCVException ret; 1945 1946 ret = rmw_vsip64(env, csrno, &rval, 1947 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1948 if (ret_val) { 1949 *ret_val = rval >> 32; 1950 } 1951 1952 return ret; 1953 } 1954 1955 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 1956 uint64_t *ret_val, 1957 uint64_t new_val, uint64_t wr_mask) 1958 { 1959 RISCVException ret; 1960 uint64_t mask = env->mideleg & sip_writable_mask; 1961 1962 if (riscv_cpu_virt_enabled(env)) { 1963 if (env->hvictl & HVICTL_VTI) { 1964 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1965 } 1966 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 1967 } else { 1968 ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); 1969 } 1970 1971 if (ret_val) { 1972 *ret_val &= env->mideleg & S_MODE_INTERRUPTS; 1973 } 1974 1975 return ret; 1976 } 1977 1978 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 1979 target_ulong *ret_val, 1980 target_ulong new_val, target_ulong wr_mask) 1981 { 1982 uint64_t rval; 1983 RISCVException ret; 1984 1985 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 1986 if (ret_val) { 1987 *ret_val = rval; 1988 } 1989 1990 return ret; 1991 } 1992 1993 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 1994 target_ulong *ret_val, 1995 target_ulong new_val, target_ulong wr_mask) 1996 { 1997 uint64_t rval; 1998 RISCVException ret; 1999 2000 ret = rmw_sip64(env, csrno, &rval, 2001 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2002 if (ret_val) { 2003 *ret_val = rval >> 32; 2004 } 2005 2006 return ret; 2007 } 2008 2009 /* Supervisor Protection and Translation */ 2010 static RISCVException read_satp(CPURISCVState *env, int csrno, 2011 target_ulong *val) 2012 { 2013 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2014 *val = 0; 2015 return RISCV_EXCP_NONE; 2016 } 2017 2018 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2019 return RISCV_EXCP_ILLEGAL_INST; 2020 } else { 2021 *val = env->satp; 2022 } 2023 2024 return RISCV_EXCP_NONE; 2025 } 2026 2027 static RISCVException write_satp(CPURISCVState *env, int csrno, 2028 target_ulong val) 2029 { 2030 target_ulong vm, mask; 2031 2032 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2033 return RISCV_EXCP_NONE; 2034 } 2035 2036 if (riscv_cpu_mxl(env) == MXL_RV32) { 2037 vm = validate_vm(env, get_field(val, SATP32_MODE)); 2038 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 2039 } else { 2040 vm = validate_vm(env, get_field(val, SATP64_MODE)); 2041 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 2042 } 2043 2044 if (vm && mask) { 2045 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2046 return RISCV_EXCP_ILLEGAL_INST; 2047 } else { 2048 /* 2049 * The ISA defines SATP.MODE=Bare as "no translation", but we still 2050 * pass these through QEMU's TLB emulation as it improves 2051 * performance. Flushing the TLB on SATP writes with paging 2052 * enabled avoids leaking those invalid cached mappings. 2053 */ 2054 tlb_flush(env_cpu(env)); 2055 env->satp = val; 2056 } 2057 } 2058 return RISCV_EXCP_NONE; 2059 } 2060 2061 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 2062 { 2063 int irq, ret; 2064 target_ulong topei; 2065 uint64_t vseip, vsgein; 2066 uint32_t iid, iprio, hviid, hviprio, gein; 2067 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 2068 2069 gein = get_field(env->hstatus, HSTATUS_VGEIN); 2070 hviid = get_field(env->hvictl, HVICTL_IID); 2071 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 2072 2073 if (gein) { 2074 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 2075 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 2076 if (gein <= env->geilen && vseip) { 2077 siid[scount] = IRQ_S_EXT; 2078 siprio[scount] = IPRIO_MMAXIPRIO + 1; 2079 if (env->aia_ireg_rmw_fn[PRV_S]) { 2080 /* 2081 * Call machine specific IMSIC register emulation for 2082 * reading TOPEI. 2083 */ 2084 ret = env->aia_ireg_rmw_fn[PRV_S]( 2085 env->aia_ireg_rmw_fn_arg[PRV_S], 2086 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 2087 riscv_cpu_mxl_bits(env)), 2088 &topei, 0, 0); 2089 if (!ret && topei) { 2090 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 2091 } 2092 } 2093 scount++; 2094 } 2095 } else { 2096 if (hviid == IRQ_S_EXT && hviprio) { 2097 siid[scount] = IRQ_S_EXT; 2098 siprio[scount] = hviprio; 2099 scount++; 2100 } 2101 } 2102 2103 if (env->hvictl & HVICTL_VTI) { 2104 if (hviid != IRQ_S_EXT) { 2105 siid[scount] = hviid; 2106 siprio[scount] = hviprio; 2107 scount++; 2108 } 2109 } else { 2110 irq = riscv_cpu_vsirq_pending(env); 2111 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 2112 siid[scount] = irq; 2113 siprio[scount] = env->hviprio[irq]; 2114 scount++; 2115 } 2116 } 2117 2118 iid = 0; 2119 iprio = UINT_MAX; 2120 for (s = 0; s < scount; s++) { 2121 if (siprio[s] < iprio) { 2122 iid = siid[s]; 2123 iprio = siprio[s]; 2124 } 2125 } 2126 2127 if (iid) { 2128 if (env->hvictl & HVICTL_IPRIOM) { 2129 if (iprio > IPRIO_MMAXIPRIO) { 2130 iprio = IPRIO_MMAXIPRIO; 2131 } 2132 if (!iprio) { 2133 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 2134 iprio = IPRIO_MMAXIPRIO; 2135 } 2136 } 2137 } else { 2138 iprio = 1; 2139 } 2140 } else { 2141 iprio = 0; 2142 } 2143 2144 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2145 *val |= iprio; 2146 return RISCV_EXCP_NONE; 2147 } 2148 2149 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 2150 { 2151 int irq; 2152 uint8_t iprio; 2153 2154 if (riscv_cpu_virt_enabled(env)) { 2155 return read_vstopi(env, CSR_VSTOPI, val); 2156 } 2157 2158 irq = riscv_cpu_sirq_pending(env); 2159 if (irq <= 0 || irq > 63) { 2160 *val = 0; 2161 } else { 2162 iprio = env->siprio[irq]; 2163 if (!iprio) { 2164 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 2165 iprio = IPRIO_MMAXIPRIO; 2166 } 2167 } 2168 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2169 *val |= iprio; 2170 } 2171 2172 return RISCV_EXCP_NONE; 2173 } 2174 2175 /* Hypervisor Extensions */ 2176 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 2177 target_ulong *val) 2178 { 2179 *val = env->hstatus; 2180 if (riscv_cpu_mxl(env) != MXL_RV32) { 2181 /* We only support 64-bit VSXL */ 2182 *val = set_field(*val, HSTATUS_VSXL, 2); 2183 } 2184 /* We only support little endian */ 2185 *val = set_field(*val, HSTATUS_VSBE, 0); 2186 return RISCV_EXCP_NONE; 2187 } 2188 2189 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 2190 target_ulong val) 2191 { 2192 env->hstatus = val; 2193 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 2194 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 2195 } 2196 if (get_field(val, HSTATUS_VSBE) != 0) { 2197 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 2198 } 2199 return RISCV_EXCP_NONE; 2200 } 2201 2202 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 2203 target_ulong *val) 2204 { 2205 *val = env->hedeleg; 2206 return RISCV_EXCP_NONE; 2207 } 2208 2209 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 2210 target_ulong val) 2211 { 2212 env->hedeleg = val & vs_delegable_excps; 2213 return RISCV_EXCP_NONE; 2214 } 2215 2216 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 2217 uint64_t *ret_val, 2218 uint64_t new_val, uint64_t wr_mask) 2219 { 2220 uint64_t mask = wr_mask & vs_delegable_ints; 2221 2222 if (ret_val) { 2223 *ret_val = env->hideleg & vs_delegable_ints; 2224 } 2225 2226 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 2227 return RISCV_EXCP_NONE; 2228 } 2229 2230 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 2231 target_ulong *ret_val, 2232 target_ulong new_val, target_ulong wr_mask) 2233 { 2234 uint64_t rval; 2235 RISCVException ret; 2236 2237 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 2238 if (ret_val) { 2239 *ret_val = rval; 2240 } 2241 2242 return ret; 2243 } 2244 2245 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 2246 target_ulong *ret_val, 2247 target_ulong new_val, target_ulong wr_mask) 2248 { 2249 uint64_t rval; 2250 RISCVException ret; 2251 2252 ret = rmw_hideleg64(env, csrno, &rval, 2253 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2254 if (ret_val) { 2255 *ret_val = rval >> 32; 2256 } 2257 2258 return ret; 2259 } 2260 2261 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2262 uint64_t *ret_val, 2263 uint64_t new_val, uint64_t wr_mask) 2264 { 2265 RISCVException ret; 2266 2267 ret = rmw_mip64(env, csrno, ret_val, new_val, 2268 wr_mask & hvip_writable_mask); 2269 if (ret_val) { 2270 *ret_val &= VS_MODE_INTERRUPTS; 2271 } 2272 2273 return ret; 2274 } 2275 2276 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 2277 target_ulong *ret_val, 2278 target_ulong new_val, target_ulong wr_mask) 2279 { 2280 uint64_t rval; 2281 RISCVException ret; 2282 2283 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 2284 if (ret_val) { 2285 *ret_val = rval; 2286 } 2287 2288 return ret; 2289 } 2290 2291 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 2292 target_ulong *ret_val, 2293 target_ulong new_val, target_ulong wr_mask) 2294 { 2295 uint64_t rval; 2296 RISCVException ret; 2297 2298 ret = rmw_hvip64(env, csrno, &rval, 2299 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2300 if (ret_val) { 2301 *ret_val = rval >> 32; 2302 } 2303 2304 return ret; 2305 } 2306 2307 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 2308 target_ulong *ret_value, 2309 target_ulong new_value, target_ulong write_mask) 2310 { 2311 int ret = rmw_mip(env, csrno, ret_value, new_value, 2312 write_mask & hip_writable_mask); 2313 2314 if (ret_value) { 2315 *ret_value &= HS_MODE_INTERRUPTS; 2316 } 2317 return ret; 2318 } 2319 2320 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 2321 target_ulong *ret_val, 2322 target_ulong new_val, target_ulong wr_mask) 2323 { 2324 uint64_t rval; 2325 RISCVException ret; 2326 2327 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 2328 if (ret_val) { 2329 *ret_val = rval & HS_MODE_INTERRUPTS; 2330 } 2331 2332 return ret; 2333 } 2334 2335 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 2336 target_ulong *val) 2337 { 2338 *val = env->hcounteren; 2339 return RISCV_EXCP_NONE; 2340 } 2341 2342 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 2343 target_ulong val) 2344 { 2345 env->hcounteren = val; 2346 return RISCV_EXCP_NONE; 2347 } 2348 2349 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 2350 target_ulong *val) 2351 { 2352 if (val) { 2353 *val = env->hgeie; 2354 } 2355 return RISCV_EXCP_NONE; 2356 } 2357 2358 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 2359 target_ulong val) 2360 { 2361 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 2362 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 2363 env->hgeie = val; 2364 /* Update mip.SGEIP bit */ 2365 riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, 2366 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 2367 return RISCV_EXCP_NONE; 2368 } 2369 2370 static RISCVException read_htval(CPURISCVState *env, int csrno, 2371 target_ulong *val) 2372 { 2373 *val = env->htval; 2374 return RISCV_EXCP_NONE; 2375 } 2376 2377 static RISCVException write_htval(CPURISCVState *env, int csrno, 2378 target_ulong val) 2379 { 2380 env->htval = val; 2381 return RISCV_EXCP_NONE; 2382 } 2383 2384 static RISCVException read_htinst(CPURISCVState *env, int csrno, 2385 target_ulong *val) 2386 { 2387 *val = env->htinst; 2388 return RISCV_EXCP_NONE; 2389 } 2390 2391 static RISCVException write_htinst(CPURISCVState *env, int csrno, 2392 target_ulong val) 2393 { 2394 return RISCV_EXCP_NONE; 2395 } 2396 2397 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 2398 target_ulong *val) 2399 { 2400 if (val) { 2401 *val = env->hgeip; 2402 } 2403 return RISCV_EXCP_NONE; 2404 } 2405 2406 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 2407 target_ulong *val) 2408 { 2409 *val = env->hgatp; 2410 return RISCV_EXCP_NONE; 2411 } 2412 2413 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 2414 target_ulong val) 2415 { 2416 env->hgatp = val; 2417 return RISCV_EXCP_NONE; 2418 } 2419 2420 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 2421 target_ulong *val) 2422 { 2423 if (!env->rdtime_fn) { 2424 return RISCV_EXCP_ILLEGAL_INST; 2425 } 2426 2427 *val = env->htimedelta; 2428 return RISCV_EXCP_NONE; 2429 } 2430 2431 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 2432 target_ulong val) 2433 { 2434 if (!env->rdtime_fn) { 2435 return RISCV_EXCP_ILLEGAL_INST; 2436 } 2437 2438 if (riscv_cpu_mxl(env) == MXL_RV32) { 2439 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 2440 } else { 2441 env->htimedelta = val; 2442 } 2443 return RISCV_EXCP_NONE; 2444 } 2445 2446 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 2447 target_ulong *val) 2448 { 2449 if (!env->rdtime_fn) { 2450 return RISCV_EXCP_ILLEGAL_INST; 2451 } 2452 2453 *val = env->htimedelta >> 32; 2454 return RISCV_EXCP_NONE; 2455 } 2456 2457 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 2458 target_ulong val) 2459 { 2460 if (!env->rdtime_fn) { 2461 return RISCV_EXCP_ILLEGAL_INST; 2462 } 2463 2464 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 2465 return RISCV_EXCP_NONE; 2466 } 2467 2468 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 2469 { 2470 *val = env->hvictl; 2471 return RISCV_EXCP_NONE; 2472 } 2473 2474 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 2475 { 2476 env->hvictl = val & HVICTL_VALID_MASK; 2477 return RISCV_EXCP_NONE; 2478 } 2479 2480 static int read_hvipriox(CPURISCVState *env, int first_index, 2481 uint8_t *iprio, target_ulong *val) 2482 { 2483 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2484 2485 /* First index has to be a multiple of number of irqs per register */ 2486 if (first_index % num_irqs) { 2487 return (riscv_cpu_virt_enabled(env)) ? 2488 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2489 } 2490 2491 /* Fill-up return value */ 2492 *val = 0; 2493 for (i = 0; i < num_irqs; i++) { 2494 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2495 continue; 2496 } 2497 if (rdzero) { 2498 continue; 2499 } 2500 *val |= ((target_ulong)iprio[irq]) << (i * 8); 2501 } 2502 2503 return RISCV_EXCP_NONE; 2504 } 2505 2506 static int write_hvipriox(CPURISCVState *env, int first_index, 2507 uint8_t *iprio, target_ulong val) 2508 { 2509 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2510 2511 /* First index has to be a multiple of number of irqs per register */ 2512 if (first_index % num_irqs) { 2513 return (riscv_cpu_virt_enabled(env)) ? 2514 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2515 } 2516 2517 /* Fill-up priority arrary */ 2518 for (i = 0; i < num_irqs; i++) { 2519 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2520 continue; 2521 } 2522 if (rdzero) { 2523 iprio[irq] = 0; 2524 } else { 2525 iprio[irq] = (val >> (i * 8)) & 0xff; 2526 } 2527 } 2528 2529 return RISCV_EXCP_NONE; 2530 } 2531 2532 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 2533 { 2534 return read_hvipriox(env, 0, env->hviprio, val); 2535 } 2536 2537 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 2538 { 2539 return write_hvipriox(env, 0, env->hviprio, val); 2540 } 2541 2542 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 2543 { 2544 return read_hvipriox(env, 4, env->hviprio, val); 2545 } 2546 2547 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 2548 { 2549 return write_hvipriox(env, 4, env->hviprio, val); 2550 } 2551 2552 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 2553 { 2554 return read_hvipriox(env, 8, env->hviprio, val); 2555 } 2556 2557 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 2558 { 2559 return write_hvipriox(env, 8, env->hviprio, val); 2560 } 2561 2562 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 2563 { 2564 return read_hvipriox(env, 12, env->hviprio, val); 2565 } 2566 2567 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 2568 { 2569 return write_hvipriox(env, 12, env->hviprio, val); 2570 } 2571 2572 /* Virtual CSR Registers */ 2573 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 2574 target_ulong *val) 2575 { 2576 *val = env->vsstatus; 2577 return RISCV_EXCP_NONE; 2578 } 2579 2580 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 2581 target_ulong val) 2582 { 2583 uint64_t mask = (target_ulong)-1; 2584 if ((val & VSSTATUS64_UXL) == 0) { 2585 mask &= ~VSSTATUS64_UXL; 2586 } 2587 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 2588 return RISCV_EXCP_NONE; 2589 } 2590 2591 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 2592 { 2593 *val = env->vstvec; 2594 return RISCV_EXCP_NONE; 2595 } 2596 2597 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 2598 target_ulong val) 2599 { 2600 env->vstvec = val; 2601 return RISCV_EXCP_NONE; 2602 } 2603 2604 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 2605 target_ulong *val) 2606 { 2607 *val = env->vsscratch; 2608 return RISCV_EXCP_NONE; 2609 } 2610 2611 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 2612 target_ulong val) 2613 { 2614 env->vsscratch = val; 2615 return RISCV_EXCP_NONE; 2616 } 2617 2618 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 2619 target_ulong *val) 2620 { 2621 *val = env->vsepc; 2622 return RISCV_EXCP_NONE; 2623 } 2624 2625 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 2626 target_ulong val) 2627 { 2628 env->vsepc = val; 2629 return RISCV_EXCP_NONE; 2630 } 2631 2632 static RISCVException read_vscause(CPURISCVState *env, int csrno, 2633 target_ulong *val) 2634 { 2635 *val = env->vscause; 2636 return RISCV_EXCP_NONE; 2637 } 2638 2639 static RISCVException write_vscause(CPURISCVState *env, int csrno, 2640 target_ulong val) 2641 { 2642 env->vscause = val; 2643 return RISCV_EXCP_NONE; 2644 } 2645 2646 static RISCVException read_vstval(CPURISCVState *env, int csrno, 2647 target_ulong *val) 2648 { 2649 *val = env->vstval; 2650 return RISCV_EXCP_NONE; 2651 } 2652 2653 static RISCVException write_vstval(CPURISCVState *env, int csrno, 2654 target_ulong val) 2655 { 2656 env->vstval = val; 2657 return RISCV_EXCP_NONE; 2658 } 2659 2660 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 2661 target_ulong *val) 2662 { 2663 *val = env->vsatp; 2664 return RISCV_EXCP_NONE; 2665 } 2666 2667 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 2668 target_ulong val) 2669 { 2670 env->vsatp = val; 2671 return RISCV_EXCP_NONE; 2672 } 2673 2674 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 2675 target_ulong *val) 2676 { 2677 *val = env->mtval2; 2678 return RISCV_EXCP_NONE; 2679 } 2680 2681 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 2682 target_ulong val) 2683 { 2684 env->mtval2 = val; 2685 return RISCV_EXCP_NONE; 2686 } 2687 2688 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 2689 target_ulong *val) 2690 { 2691 *val = env->mtinst; 2692 return RISCV_EXCP_NONE; 2693 } 2694 2695 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 2696 target_ulong val) 2697 { 2698 env->mtinst = val; 2699 return RISCV_EXCP_NONE; 2700 } 2701 2702 /* Physical Memory Protection */ 2703 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 2704 target_ulong *val) 2705 { 2706 *val = mseccfg_csr_read(env); 2707 return RISCV_EXCP_NONE; 2708 } 2709 2710 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 2711 target_ulong val) 2712 { 2713 mseccfg_csr_write(env, val); 2714 return RISCV_EXCP_NONE; 2715 } 2716 2717 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) 2718 { 2719 /* TODO: RV128 restriction check */ 2720 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 2721 return false; 2722 } 2723 return true; 2724 } 2725 2726 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 2727 target_ulong *val) 2728 { 2729 uint32_t reg_index = csrno - CSR_PMPCFG0; 2730 2731 if (!check_pmp_reg_index(env, reg_index)) { 2732 return RISCV_EXCP_ILLEGAL_INST; 2733 } 2734 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 2735 return RISCV_EXCP_NONE; 2736 } 2737 2738 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 2739 target_ulong val) 2740 { 2741 uint32_t reg_index = csrno - CSR_PMPCFG0; 2742 2743 if (!check_pmp_reg_index(env, reg_index)) { 2744 return RISCV_EXCP_ILLEGAL_INST; 2745 } 2746 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 2747 return RISCV_EXCP_NONE; 2748 } 2749 2750 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 2751 target_ulong *val) 2752 { 2753 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 2754 return RISCV_EXCP_NONE; 2755 } 2756 2757 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 2758 target_ulong val) 2759 { 2760 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 2761 return RISCV_EXCP_NONE; 2762 } 2763 2764 static RISCVException read_tselect(CPURISCVState *env, int csrno, 2765 target_ulong *val) 2766 { 2767 *val = tselect_csr_read(env); 2768 return RISCV_EXCP_NONE; 2769 } 2770 2771 static RISCVException write_tselect(CPURISCVState *env, int csrno, 2772 target_ulong val) 2773 { 2774 tselect_csr_write(env, val); 2775 return RISCV_EXCP_NONE; 2776 } 2777 2778 static RISCVException read_tdata(CPURISCVState *env, int csrno, 2779 target_ulong *val) 2780 { 2781 /* return 0 in tdata1 to end the trigger enumeration */ 2782 if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { 2783 *val = 0; 2784 return RISCV_EXCP_NONE; 2785 } 2786 2787 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2788 return RISCV_EXCP_ILLEGAL_INST; 2789 } 2790 2791 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 2792 return RISCV_EXCP_NONE; 2793 } 2794 2795 static RISCVException write_tdata(CPURISCVState *env, int csrno, 2796 target_ulong val) 2797 { 2798 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2799 return RISCV_EXCP_ILLEGAL_INST; 2800 } 2801 2802 tdata_csr_write(env, csrno - CSR_TDATA1, val); 2803 return RISCV_EXCP_NONE; 2804 } 2805 2806 /* 2807 * Functions to access Pointer Masking feature registers 2808 * We have to check if current priv lvl could modify 2809 * csr in given mode 2810 */ 2811 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 2812 { 2813 int csr_priv = get_field(csrno, 0x300); 2814 int pm_current; 2815 2816 if (env->debugger) { 2817 return false; 2818 } 2819 /* 2820 * If priv lvls differ that means we're accessing csr from higher priv lvl, 2821 * so allow the access 2822 */ 2823 if (env->priv != csr_priv) { 2824 return false; 2825 } 2826 switch (env->priv) { 2827 case PRV_M: 2828 pm_current = get_field(env->mmte, M_PM_CURRENT); 2829 break; 2830 case PRV_S: 2831 pm_current = get_field(env->mmte, S_PM_CURRENT); 2832 break; 2833 case PRV_U: 2834 pm_current = get_field(env->mmte, U_PM_CURRENT); 2835 break; 2836 default: 2837 g_assert_not_reached(); 2838 } 2839 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 2840 return !pm_current; 2841 } 2842 2843 static RISCVException read_mmte(CPURISCVState *env, int csrno, 2844 target_ulong *val) 2845 { 2846 *val = env->mmte & MMTE_MASK; 2847 return RISCV_EXCP_NONE; 2848 } 2849 2850 static RISCVException write_mmte(CPURISCVState *env, int csrno, 2851 target_ulong val) 2852 { 2853 uint64_t mstatus; 2854 target_ulong wpri_val = val & MMTE_MASK; 2855 2856 if (val != wpri_val) { 2857 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2858 "MMTE: WPRI violation written 0x", val, 2859 "vs expected 0x", wpri_val); 2860 } 2861 /* for machine mode pm.current is hardwired to 1 */ 2862 wpri_val |= MMTE_M_PM_CURRENT; 2863 2864 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 2865 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 2866 env->mmte = wpri_val | PM_EXT_DIRTY; 2867 riscv_cpu_update_mask(env); 2868 2869 /* Set XS and SD bits, since PM CSRs are dirty */ 2870 mstatus = env->mstatus | MSTATUS_XS; 2871 write_mstatus(env, csrno, mstatus); 2872 return RISCV_EXCP_NONE; 2873 } 2874 2875 static RISCVException read_smte(CPURISCVState *env, int csrno, 2876 target_ulong *val) 2877 { 2878 *val = env->mmte & SMTE_MASK; 2879 return RISCV_EXCP_NONE; 2880 } 2881 2882 static RISCVException write_smte(CPURISCVState *env, int csrno, 2883 target_ulong val) 2884 { 2885 target_ulong wpri_val = val & SMTE_MASK; 2886 2887 if (val != wpri_val) { 2888 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2889 "SMTE: WPRI violation written 0x", val, 2890 "vs expected 0x", wpri_val); 2891 } 2892 2893 /* if pm.current==0 we can't modify current PM CSRs */ 2894 if (check_pm_current_disabled(env, csrno)) { 2895 return RISCV_EXCP_NONE; 2896 } 2897 2898 wpri_val |= (env->mmte & ~SMTE_MASK); 2899 write_mmte(env, csrno, wpri_val); 2900 return RISCV_EXCP_NONE; 2901 } 2902 2903 static RISCVException read_umte(CPURISCVState *env, int csrno, 2904 target_ulong *val) 2905 { 2906 *val = env->mmte & UMTE_MASK; 2907 return RISCV_EXCP_NONE; 2908 } 2909 2910 static RISCVException write_umte(CPURISCVState *env, int csrno, 2911 target_ulong val) 2912 { 2913 target_ulong wpri_val = val & UMTE_MASK; 2914 2915 if (val != wpri_val) { 2916 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2917 "UMTE: WPRI violation written 0x", val, 2918 "vs expected 0x", wpri_val); 2919 } 2920 2921 if (check_pm_current_disabled(env, csrno)) { 2922 return RISCV_EXCP_NONE; 2923 } 2924 2925 wpri_val |= (env->mmte & ~UMTE_MASK); 2926 write_mmte(env, csrno, wpri_val); 2927 return RISCV_EXCP_NONE; 2928 } 2929 2930 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 2931 target_ulong *val) 2932 { 2933 *val = env->mpmmask; 2934 return RISCV_EXCP_NONE; 2935 } 2936 2937 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 2938 target_ulong val) 2939 { 2940 uint64_t mstatus; 2941 2942 env->mpmmask = val; 2943 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 2944 env->cur_pmmask = val; 2945 } 2946 env->mmte |= PM_EXT_DIRTY; 2947 2948 /* Set XS and SD bits, since PM CSRs are dirty */ 2949 mstatus = env->mstatus | MSTATUS_XS; 2950 write_mstatus(env, csrno, mstatus); 2951 return RISCV_EXCP_NONE; 2952 } 2953 2954 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 2955 target_ulong *val) 2956 { 2957 *val = env->spmmask; 2958 return RISCV_EXCP_NONE; 2959 } 2960 2961 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 2962 target_ulong val) 2963 { 2964 uint64_t mstatus; 2965 2966 /* if pm.current==0 we can't modify current PM CSRs */ 2967 if (check_pm_current_disabled(env, csrno)) { 2968 return RISCV_EXCP_NONE; 2969 } 2970 env->spmmask = val; 2971 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 2972 env->cur_pmmask = val; 2973 } 2974 env->mmte |= PM_EXT_DIRTY; 2975 2976 /* Set XS and SD bits, since PM CSRs are dirty */ 2977 mstatus = env->mstatus | MSTATUS_XS; 2978 write_mstatus(env, csrno, mstatus); 2979 return RISCV_EXCP_NONE; 2980 } 2981 2982 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 2983 target_ulong *val) 2984 { 2985 *val = env->upmmask; 2986 return RISCV_EXCP_NONE; 2987 } 2988 2989 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 2990 target_ulong val) 2991 { 2992 uint64_t mstatus; 2993 2994 /* if pm.current==0 we can't modify current PM CSRs */ 2995 if (check_pm_current_disabled(env, csrno)) { 2996 return RISCV_EXCP_NONE; 2997 } 2998 env->upmmask = val; 2999 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3000 env->cur_pmmask = val; 3001 } 3002 env->mmte |= PM_EXT_DIRTY; 3003 3004 /* Set XS and SD bits, since PM CSRs are dirty */ 3005 mstatus = env->mstatus | MSTATUS_XS; 3006 write_mstatus(env, csrno, mstatus); 3007 return RISCV_EXCP_NONE; 3008 } 3009 3010 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 3011 target_ulong *val) 3012 { 3013 *val = env->mpmbase; 3014 return RISCV_EXCP_NONE; 3015 } 3016 3017 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 3018 target_ulong val) 3019 { 3020 uint64_t mstatus; 3021 3022 env->mpmbase = val; 3023 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 3024 env->cur_pmbase = val; 3025 } 3026 env->mmte |= PM_EXT_DIRTY; 3027 3028 /* Set XS and SD bits, since PM CSRs are dirty */ 3029 mstatus = env->mstatus | MSTATUS_XS; 3030 write_mstatus(env, csrno, mstatus); 3031 return RISCV_EXCP_NONE; 3032 } 3033 3034 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 3035 target_ulong *val) 3036 { 3037 *val = env->spmbase; 3038 return RISCV_EXCP_NONE; 3039 } 3040 3041 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 3042 target_ulong val) 3043 { 3044 uint64_t mstatus; 3045 3046 /* if pm.current==0 we can't modify current PM CSRs */ 3047 if (check_pm_current_disabled(env, csrno)) { 3048 return RISCV_EXCP_NONE; 3049 } 3050 env->spmbase = val; 3051 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3052 env->cur_pmbase = val; 3053 } 3054 env->mmte |= PM_EXT_DIRTY; 3055 3056 /* Set XS and SD bits, since PM CSRs are dirty */ 3057 mstatus = env->mstatus | MSTATUS_XS; 3058 write_mstatus(env, csrno, mstatus); 3059 return RISCV_EXCP_NONE; 3060 } 3061 3062 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 3063 target_ulong *val) 3064 { 3065 *val = env->upmbase; 3066 return RISCV_EXCP_NONE; 3067 } 3068 3069 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 3070 target_ulong val) 3071 { 3072 uint64_t mstatus; 3073 3074 /* if pm.current==0 we can't modify current PM CSRs */ 3075 if (check_pm_current_disabled(env, csrno)) { 3076 return RISCV_EXCP_NONE; 3077 } 3078 env->upmbase = val; 3079 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3080 env->cur_pmbase = val; 3081 } 3082 env->mmte |= PM_EXT_DIRTY; 3083 3084 /* Set XS and SD bits, since PM CSRs are dirty */ 3085 mstatus = env->mstatus | MSTATUS_XS; 3086 write_mstatus(env, csrno, mstatus); 3087 return RISCV_EXCP_NONE; 3088 } 3089 3090 #endif 3091 3092 /* Crypto Extension */ 3093 static RISCVException rmw_seed(CPURISCVState *env, int csrno, 3094 target_ulong *ret_value, 3095 target_ulong new_value, 3096 target_ulong write_mask) 3097 { 3098 uint16_t random_v; 3099 Error *random_e = NULL; 3100 int random_r; 3101 target_ulong rval; 3102 3103 random_r = qemu_guest_getrandom(&random_v, 2, &random_e); 3104 if (unlikely(random_r < 0)) { 3105 /* 3106 * Failed, for unknown reasons in the crypto subsystem. 3107 * The best we can do is log the reason and return a 3108 * failure indication to the guest. There is no reason 3109 * we know to expect the failure to be transitory, so 3110 * indicate DEAD to avoid having the guest spin on WAIT. 3111 */ 3112 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 3113 __func__, error_get_pretty(random_e)); 3114 error_free(random_e); 3115 rval = SEED_OPST_DEAD; 3116 } else { 3117 rval = random_v | SEED_OPST_ES16; 3118 } 3119 3120 if (ret_value) { 3121 *ret_value = rval; 3122 } 3123 3124 return RISCV_EXCP_NONE; 3125 } 3126 3127 /* 3128 * riscv_csrrw - read and/or update control and status register 3129 * 3130 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 3131 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 3132 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 3133 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 3134 */ 3135 3136 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 3137 int csrno, 3138 bool write_mask, 3139 RISCVCPU *cpu) 3140 { 3141 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 3142 int read_only = get_field(csrno, 0xC00) == 3; 3143 int csr_min_priv = csr_ops[csrno].min_priv_ver; 3144 #if !defined(CONFIG_USER_ONLY) 3145 int csr_priv, effective_priv = env->priv; 3146 3147 if (riscv_has_ext(env, RVH) && env->priv == PRV_S) { 3148 /* 3149 * We are in either HS or VS mode. 3150 * Add 1 to the effective privledge level to allow us to access the 3151 * Hypervisor CSRs. The `hmode` predicate will determine if access 3152 * should be allowed(HS) or if a virtual instruction exception should be 3153 * raised(VS). 3154 */ 3155 effective_priv++; 3156 } 3157 3158 csr_priv = get_field(csrno, 0x300); 3159 if (!env->debugger && (effective_priv < csr_priv)) { 3160 if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { 3161 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 3162 } 3163 return RISCV_EXCP_ILLEGAL_INST; 3164 } 3165 #endif 3166 if (write_mask && read_only) { 3167 return RISCV_EXCP_ILLEGAL_INST; 3168 } 3169 3170 /* ensure the CSR extension is enabled. */ 3171 if (!cpu->cfg.ext_icsr) { 3172 return RISCV_EXCP_ILLEGAL_INST; 3173 } 3174 3175 /* check predicate */ 3176 if (!csr_ops[csrno].predicate) { 3177 return RISCV_EXCP_ILLEGAL_INST; 3178 } 3179 3180 if (env->priv_ver < csr_min_priv) { 3181 return RISCV_EXCP_ILLEGAL_INST; 3182 } 3183 3184 return csr_ops[csrno].predicate(env, csrno); 3185 } 3186 3187 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 3188 target_ulong *ret_value, 3189 target_ulong new_value, 3190 target_ulong write_mask) 3191 { 3192 RISCVException ret; 3193 target_ulong old_value; 3194 3195 /* execute combined read/write operation if it exists */ 3196 if (csr_ops[csrno].op) { 3197 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 3198 } 3199 3200 /* if no accessor exists then return failure */ 3201 if (!csr_ops[csrno].read) { 3202 return RISCV_EXCP_ILLEGAL_INST; 3203 } 3204 /* read old value */ 3205 ret = csr_ops[csrno].read(env, csrno, &old_value); 3206 if (ret != RISCV_EXCP_NONE) { 3207 return ret; 3208 } 3209 3210 /* write value if writable and write mask set, otherwise drop writes */ 3211 if (write_mask) { 3212 new_value = (old_value & ~write_mask) | (new_value & write_mask); 3213 if (csr_ops[csrno].write) { 3214 ret = csr_ops[csrno].write(env, csrno, new_value); 3215 if (ret != RISCV_EXCP_NONE) { 3216 return ret; 3217 } 3218 } 3219 } 3220 3221 /* return old value */ 3222 if (ret_value) { 3223 *ret_value = old_value; 3224 } 3225 3226 return RISCV_EXCP_NONE; 3227 } 3228 3229 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 3230 target_ulong *ret_value, 3231 target_ulong new_value, target_ulong write_mask) 3232 { 3233 RISCVCPU *cpu = env_archcpu(env); 3234 3235 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); 3236 if (ret != RISCV_EXCP_NONE) { 3237 return ret; 3238 } 3239 3240 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 3241 } 3242 3243 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 3244 Int128 *ret_value, 3245 Int128 new_value, 3246 Int128 write_mask) 3247 { 3248 RISCVException ret; 3249 Int128 old_value; 3250 3251 /* read old value */ 3252 ret = csr_ops[csrno].read128(env, csrno, &old_value); 3253 if (ret != RISCV_EXCP_NONE) { 3254 return ret; 3255 } 3256 3257 /* write value if writable and write mask set, otherwise drop writes */ 3258 if (int128_nz(write_mask)) { 3259 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 3260 int128_and(new_value, write_mask)); 3261 if (csr_ops[csrno].write128) { 3262 ret = csr_ops[csrno].write128(env, csrno, new_value); 3263 if (ret != RISCV_EXCP_NONE) { 3264 return ret; 3265 } 3266 } else if (csr_ops[csrno].write) { 3267 /* avoids having to write wrappers for all registers */ 3268 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 3269 if (ret != RISCV_EXCP_NONE) { 3270 return ret; 3271 } 3272 } 3273 } 3274 3275 /* return old value */ 3276 if (ret_value) { 3277 *ret_value = old_value; 3278 } 3279 3280 return RISCV_EXCP_NONE; 3281 } 3282 3283 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 3284 Int128 *ret_value, 3285 Int128 new_value, Int128 write_mask) 3286 { 3287 RISCVException ret; 3288 RISCVCPU *cpu = env_archcpu(env); 3289 3290 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); 3291 if (ret != RISCV_EXCP_NONE) { 3292 return ret; 3293 } 3294 3295 if (csr_ops[csrno].read128) { 3296 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 3297 } 3298 3299 /* 3300 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 3301 * at all defined. 3302 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 3303 * significant), for those, this fallback is correctly handling the accesses 3304 */ 3305 target_ulong old_value; 3306 ret = riscv_csrrw_do64(env, csrno, &old_value, 3307 int128_getlo(new_value), 3308 int128_getlo(write_mask)); 3309 if (ret == RISCV_EXCP_NONE && ret_value) { 3310 *ret_value = int128_make64(old_value); 3311 } 3312 return ret; 3313 } 3314 3315 /* 3316 * Debugger support. If not in user mode, set env->debugger before the 3317 * riscv_csrrw call and clear it after the call. 3318 */ 3319 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 3320 target_ulong *ret_value, 3321 target_ulong new_value, 3322 target_ulong write_mask) 3323 { 3324 RISCVException ret; 3325 #if !defined(CONFIG_USER_ONLY) 3326 env->debugger = true; 3327 #endif 3328 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 3329 #if !defined(CONFIG_USER_ONLY) 3330 env->debugger = false; 3331 #endif 3332 return ret; 3333 } 3334 3335 /* Control and Status Register function table */ 3336 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 3337 /* User Floating-Point CSRs */ 3338 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 3339 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 3340 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 3341 /* Vector CSRs */ 3342 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, 3343 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3344 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, 3345 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3346 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, 3347 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3348 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, 3349 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3350 [CSR_VL] = { "vl", vs, read_vl, 3351 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3352 [CSR_VTYPE] = { "vtype", vs, read_vtype, 3353 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3354 [CSR_VLENB] = { "vlenb", vs, read_vlenb, 3355 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3356 /* User Timers and Counters */ 3357 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 3358 [CSR_INSTRET] = { "instret", ctr, read_instret }, 3359 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 3360 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 3361 3362 /* 3363 * In privileged mode, the monitor will have to emulate TIME CSRs only if 3364 * rdtime callback is not provided by machine/platform emulation. 3365 */ 3366 [CSR_TIME] = { "time", ctr, read_time }, 3367 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 3368 3369 /* Crypto Extension */ 3370 [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, 3371 3372 #if !defined(CONFIG_USER_ONLY) 3373 /* Machine Timers and Counters */ 3374 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 3375 [CSR_MINSTRET] = { "minstret", any, read_instret }, 3376 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 3377 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 3378 3379 /* Machine Information Registers */ 3380 [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, 3381 [CSR_MARCHID] = { "marchid", any, read_marchid }, 3382 [CSR_MIMPID] = { "mimpid", any, read_mimpid }, 3383 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 3384 3385 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 3386 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3387 /* Machine Trap Setup */ 3388 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, 3389 read_mstatus_i128 }, 3390 [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, 3391 read_misa_i128 }, 3392 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 3393 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 3394 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 3395 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 3396 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 3397 3398 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 3399 3400 /* Machine Trap Handling */ 3401 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, 3402 read_mscratch_i128, write_mscratch_i128 }, 3403 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 3404 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 3405 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 3406 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 3407 3408 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 3409 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 3410 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 3411 3412 /* Machine-Level Interrupts (AIA) */ 3413 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 3414 3415 /* Machine-Level IMSIC Interface (AIA) */ 3416 [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3417 [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3418 [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3419 [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3420 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 3421 3422 /* Virtual Interrupts for Supervisor Level (AIA) */ 3423 [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, 3424 [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, 3425 3426 /* Machine-Level High-Half CSRs (AIA) */ 3427 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 3428 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 3429 [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, 3430 [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, 3431 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 3432 3433 /* Execution environment configuration */ 3434 [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, 3435 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3436 [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, 3437 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3438 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 3439 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3440 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 3441 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3442 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 3443 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3444 3445 /* Supervisor Trap Setup */ 3446 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, 3447 read_sstatus_i128 }, 3448 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 3449 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 3450 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 3451 3452 /* Supervisor Trap Handling */ 3453 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, 3454 read_sscratch_i128, write_sscratch_i128 }, 3455 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 3456 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 3457 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 3458 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 3459 3460 /* Supervisor Protection and Translation */ 3461 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 3462 3463 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 3464 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 3465 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 3466 3467 /* Supervisor-Level Interrupts (AIA) */ 3468 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 3469 3470 /* Supervisor-Level IMSIC Interface (AIA) */ 3471 [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3472 [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3473 [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3474 [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3475 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 3476 3477 /* Supervisor-Level High-Half CSRs (AIA) */ 3478 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 3479 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 3480 3481 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 3482 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3483 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 3484 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3485 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 3486 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3487 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 3488 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3489 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 3490 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3491 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 3492 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3493 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, 3494 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3495 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 3496 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3497 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 3498 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3499 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 3500 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3501 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 3502 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3503 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, 3504 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3505 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, 3506 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3507 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, 3508 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3509 3510 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, 3511 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3512 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 3513 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3514 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 3515 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3516 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 3517 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3518 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, 3519 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3520 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 3521 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3522 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 3523 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3524 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 3525 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3526 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 3527 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3528 3529 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 3530 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3531 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 3532 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3533 3534 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 3535 [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, 3536 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, 3537 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, 3538 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, 3539 3540 /* 3541 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 3542 */ 3543 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, 3544 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 3545 3546 /* VS-Level Interrupts (H-extension with AIA) */ 3547 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 3548 3549 /* VS-Level IMSIC Interface (H-extension with AIA) */ 3550 [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3551 [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3552 [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3553 [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3554 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 3555 3556 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 3557 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, 3558 [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, 3559 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 3560 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, 3561 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, 3562 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 3563 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 3564 3565 /* Physical Memory Protection */ 3566 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 3567 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3568 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 3569 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 3570 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 3571 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 3572 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 3573 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 3574 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 3575 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 3576 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 3577 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 3578 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 3579 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 3580 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 3581 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 3582 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 3583 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 3584 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 3585 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 3586 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 3587 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 3588 3589 /* Debug CSRs */ 3590 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 3591 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 3592 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 3593 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 3594 3595 /* User Pointer Masking */ 3596 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 3597 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 3598 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 3599 /* Machine Pointer Masking */ 3600 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 3601 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 3602 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 3603 /* Supervisor Pointer Masking */ 3604 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 3605 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 3606 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 3607 3608 /* Performance Counters */ 3609 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 3610 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 3611 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 3612 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 3613 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 3614 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 3615 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 3616 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 3617 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 3618 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 3619 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 3620 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 3621 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 3622 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 3623 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 3624 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 3625 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 3626 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 3627 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 3628 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 3629 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 3630 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 3631 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 3632 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 3633 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 3634 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 3635 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 3636 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 3637 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 3638 3639 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 3640 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 3641 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 3642 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 3643 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 3644 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 3645 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 3646 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 3647 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 3648 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 3649 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 3650 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 3651 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 3652 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 3653 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 3654 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 3655 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 3656 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 3657 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 3658 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 3659 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 3660 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 3661 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 3662 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 3663 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 3664 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 3665 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 3666 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 3667 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 3668 3669 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 3670 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 3671 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 3672 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 3673 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 3674 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 3675 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 3676 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 3677 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 3678 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 3679 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 3680 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 3681 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 3682 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 3683 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 3684 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 3685 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 3686 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 3687 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 3688 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 3689 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 3690 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 3691 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 3692 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 3693 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 3694 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 3695 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 3696 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 3697 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 3698 3699 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 3700 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 3701 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 3702 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 3703 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 3704 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 3705 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 3706 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 3707 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 3708 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 3709 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 3710 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 3711 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 3712 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 3713 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 3714 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 3715 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 3716 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 3717 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 3718 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 3719 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 3720 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 3721 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 3722 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 3723 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 3724 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 3725 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 3726 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 3727 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 3728 3729 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 3730 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 3731 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 3732 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 3733 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 3734 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 3735 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 3736 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 3737 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 3738 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 3739 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 3740 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 3741 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 3742 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 3743 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 3744 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 3745 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 3746 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 3747 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 3748 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 3749 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 3750 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 3751 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 3752 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 3753 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 3754 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 3755 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 3756 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 3757 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 3758 #endif /* !CONFIG_USER_ONLY */ 3759 }; 3760