1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 50 return -1; 51 } 52 #endif 53 return 0; 54 } 55 56 static int ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 CPUState *cs = env_cpu(env); 60 RISCVCPU *cpu = RISCV_CPU(cs); 61 uint32_t ctr_en = ~0u; 62 63 if (!cpu->cfg.ext_counters) { 64 /* The Counters extensions is not enabled */ 65 return -1; 66 } 67 68 /* 69 * The counters are always enabled at run time on newer priv specs, as the 70 * CSR has changed from controlling that the counters can be read to 71 * controlling that the counters increment. 72 */ 73 if (env->priv_ver > PRIV_VERSION_1_09_1) { 74 return 0; 75 } 76 77 if (env->priv < PRV_M) { 78 ctr_en &= env->mcounteren; 79 } 80 if (env->priv < PRV_S) { 81 ctr_en &= env->scounteren; 82 } 83 if (!(ctr_en & (1u << (csrno & 31)))) { 84 return -1; 85 } 86 #endif 87 return 0; 88 } 89 90 #if !defined(CONFIG_USER_ONLY) 91 static int any(CPURISCVState *env, int csrno) 92 { 93 return 0; 94 } 95 96 static int smode(CPURISCVState *env, int csrno) 97 { 98 return -!riscv_has_ext(env, RVS); 99 } 100 101 static int hmode(CPURISCVState *env, int csrno) 102 { 103 if (riscv_has_ext(env, RVS) && 104 riscv_has_ext(env, RVH)) { 105 /* Hypervisor extension is supported */ 106 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 107 env->priv == PRV_M) { 108 return 0; 109 } 110 } 111 112 return -1; 113 } 114 115 static int pmp(CPURISCVState *env, int csrno) 116 { 117 return -!riscv_feature(env, RISCV_FEATURE_PMP); 118 } 119 #endif 120 121 /* User Floating-Point CSRs */ 122 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 123 { 124 #if !defined(CONFIG_USER_ONLY) 125 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 126 return -1; 127 } 128 #endif 129 *val = riscv_cpu_get_fflags(env); 130 return 0; 131 } 132 133 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 134 { 135 #if !defined(CONFIG_USER_ONLY) 136 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 137 return -1; 138 } 139 env->mstatus |= MSTATUS_FS; 140 #endif 141 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 142 return 0; 143 } 144 145 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 146 { 147 #if !defined(CONFIG_USER_ONLY) 148 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 149 return -1; 150 } 151 #endif 152 *val = env->frm; 153 return 0; 154 } 155 156 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 157 { 158 #if !defined(CONFIG_USER_ONLY) 159 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 160 return -1; 161 } 162 env->mstatus |= MSTATUS_FS; 163 #endif 164 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 165 return 0; 166 } 167 168 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 169 { 170 #if !defined(CONFIG_USER_ONLY) 171 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 172 return -1; 173 } 174 #endif 175 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 176 | (env->frm << FSR_RD_SHIFT); 177 return 0; 178 } 179 180 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 181 { 182 #if !defined(CONFIG_USER_ONLY) 183 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 184 return -1; 185 } 186 env->mstatus |= MSTATUS_FS; 187 #endif 188 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 189 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 190 return 0; 191 } 192 193 /* User Timers and Counters */ 194 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 195 { 196 #if !defined(CONFIG_USER_ONLY) 197 if (use_icount) { 198 *val = cpu_get_icount(); 199 } else { 200 *val = cpu_get_host_ticks(); 201 } 202 #else 203 *val = cpu_get_host_ticks(); 204 #endif 205 return 0; 206 } 207 208 #if defined(TARGET_RISCV32) 209 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 210 { 211 #if !defined(CONFIG_USER_ONLY) 212 if (use_icount) { 213 *val = cpu_get_icount() >> 32; 214 } else { 215 *val = cpu_get_host_ticks() >> 32; 216 } 217 #else 218 *val = cpu_get_host_ticks() >> 32; 219 #endif 220 return 0; 221 } 222 #endif /* TARGET_RISCV32 */ 223 224 #if defined(CONFIG_USER_ONLY) 225 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 226 { 227 *val = cpu_get_host_ticks(); 228 return 0; 229 } 230 231 #if defined(TARGET_RISCV32) 232 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 233 { 234 *val = cpu_get_host_ticks() >> 32; 235 return 0; 236 } 237 #endif 238 239 #else /* CONFIG_USER_ONLY */ 240 241 /* Machine constants */ 242 243 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 244 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 245 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 246 247 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 248 VS_MODE_INTERRUPTS; 249 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 250 VS_MODE_INTERRUPTS; 251 static const target_ulong delegable_excps = 252 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 253 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 254 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 255 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 256 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 257 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 258 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 259 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 260 (1ULL << (RISCV_EXCP_U_ECALL)) | 261 (1ULL << (RISCV_EXCP_S_ECALL)) | 262 (1ULL << (RISCV_EXCP_VS_ECALL)) | 263 (1ULL << (RISCV_EXCP_M_ECALL)) | 264 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 265 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 266 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 267 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 268 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 269 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 270 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 271 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 272 SSTATUS_SUM | SSTATUS_SD; 273 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 274 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 275 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 276 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 277 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 278 static const target_ulong vsip_writable_mask = MIP_VSSIP; 279 280 #if defined(TARGET_RISCV32) 281 static const char valid_vm_1_09[16] = { 282 [VM_1_09_MBARE] = 1, 283 [VM_1_09_SV32] = 1, 284 }; 285 static const char valid_vm_1_10[16] = { 286 [VM_1_10_MBARE] = 1, 287 [VM_1_10_SV32] = 1 288 }; 289 #elif defined(TARGET_RISCV64) 290 static const char valid_vm_1_09[16] = { 291 [VM_1_09_MBARE] = 1, 292 [VM_1_09_SV39] = 1, 293 [VM_1_09_SV48] = 1, 294 }; 295 static const char valid_vm_1_10[16] = { 296 [VM_1_10_MBARE] = 1, 297 [VM_1_10_SV39] = 1, 298 [VM_1_10_SV48] = 1, 299 [VM_1_10_SV57] = 1 300 }; 301 #endif /* CONFIG_USER_ONLY */ 302 303 /* Machine Information Registers */ 304 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 305 { 306 return *val = 0; 307 } 308 309 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 310 { 311 *val = env->mhartid; 312 return 0; 313 } 314 315 /* Machine Trap Setup */ 316 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 317 { 318 *val = env->mstatus; 319 return 0; 320 } 321 322 static int validate_vm(CPURISCVState *env, target_ulong vm) 323 { 324 return (env->priv_ver >= PRIV_VERSION_1_10_0) ? 325 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; 326 } 327 328 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 329 { 330 target_ulong mstatus = env->mstatus; 331 target_ulong mask = 0; 332 int dirty; 333 334 /* flush tlb on mstatus fields that affect VM */ 335 if (env->priv_ver <= PRIV_VERSION_1_09_1) { 336 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 337 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { 338 tlb_flush(env_cpu(env)); 339 } 340 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 341 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 342 MSTATUS_MPP | MSTATUS_MXR | 343 (validate_vm(env, get_field(val, MSTATUS_VM)) ? 344 MSTATUS_VM : 0); 345 } 346 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 347 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 348 MSTATUS_MPRV | MSTATUS_SUM)) { 349 tlb_flush(env_cpu(env)); 350 } 351 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 352 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 353 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 354 MSTATUS_TW; 355 #if defined(TARGET_RISCV64) 356 /* 357 * RV32: MPV and MTL are not in mstatus. The current plan is to 358 * add them to mstatush. For now, we just don't support it. 359 */ 360 mask |= MSTATUS_MTL | MSTATUS_MPV; 361 #endif 362 } 363 364 mstatus = (mstatus & ~mask) | (val & mask); 365 366 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 367 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 368 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 369 env->mstatus = mstatus; 370 371 return 0; 372 } 373 374 #ifdef TARGET_RISCV32 375 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) 376 { 377 *val = env->mstatush; 378 return 0; 379 } 380 381 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) 382 { 383 if ((val ^ env->mstatush) & (MSTATUS_MPV)) { 384 tlb_flush(env_cpu(env)); 385 } 386 387 val &= MSTATUS_MPV | MSTATUS_MTL; 388 389 env->mstatush = val; 390 391 return 0; 392 } 393 #endif 394 395 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 396 { 397 *val = env->misa; 398 return 0; 399 } 400 401 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 402 { 403 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 404 /* drop write to misa */ 405 return 0; 406 } 407 408 /* 'I' or 'E' must be present */ 409 if (!(val & (RVI | RVE))) { 410 /* It is not, drop write to misa */ 411 return 0; 412 } 413 414 /* 'E' excludes all other extensions */ 415 if (val & RVE) { 416 /* when we support 'E' we can do "val = RVE;" however 417 * for now we just drop writes if 'E' is present. 418 */ 419 return 0; 420 } 421 422 /* Mask extensions that are not supported by this hart */ 423 val &= env->misa_mask; 424 425 /* Mask extensions that are not supported by QEMU */ 426 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 427 428 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 429 if ((val & RVD) && !(val & RVF)) { 430 val &= ~RVD; 431 } 432 433 /* Suppress 'C' if next instruction is not aligned 434 * TODO: this should check next_pc 435 */ 436 if ((val & RVC) && (GETPC() & ~3) != 0) { 437 val &= ~RVC; 438 } 439 440 /* misa.MXL writes are not supported by QEMU */ 441 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 442 443 /* flush translation cache */ 444 if (val != env->misa) { 445 tb_flush(env_cpu(env)); 446 } 447 448 env->misa = val; 449 450 return 0; 451 } 452 453 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 454 { 455 *val = env->medeleg; 456 return 0; 457 } 458 459 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 460 { 461 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 462 return 0; 463 } 464 465 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 466 { 467 *val = env->mideleg; 468 return 0; 469 } 470 471 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 472 { 473 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 474 if (riscv_has_ext(env, RVH)) { 475 env->mideleg |= VS_MODE_INTERRUPTS; 476 } 477 return 0; 478 } 479 480 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 481 { 482 *val = env->mie; 483 return 0; 484 } 485 486 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 487 { 488 env->mie = (env->mie & ~all_ints) | (val & all_ints); 489 return 0; 490 } 491 492 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 493 { 494 *val = env->mtvec; 495 return 0; 496 } 497 498 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 499 { 500 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 501 if ((val & 3) < 2) { 502 env->mtvec = val; 503 } else { 504 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 505 } 506 return 0; 507 } 508 509 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 510 { 511 if (env->priv_ver < PRIV_VERSION_1_10_0) { 512 return -1; 513 } 514 *val = env->mcounteren; 515 return 0; 516 } 517 518 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 519 { 520 if (env->priv_ver < PRIV_VERSION_1_10_0) { 521 return -1; 522 } 523 env->mcounteren = val; 524 return 0; 525 } 526 527 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ 528 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 529 { 530 if (env->priv_ver > PRIV_VERSION_1_09_1 531 && env->priv_ver < PRIV_VERSION_1_11_0) { 532 return -1; 533 } 534 *val = env->mcounteren; 535 return 0; 536 } 537 538 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ 539 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 540 { 541 if (env->priv_ver > PRIV_VERSION_1_09_1 542 && env->priv_ver < PRIV_VERSION_1_11_0) { 543 return -1; 544 } 545 env->mcounteren = val; 546 return 0; 547 } 548 549 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) 550 { 551 if (env->priv_ver > PRIV_VERSION_1_09_1) { 552 return -1; 553 } 554 *val = env->scounteren; 555 return 0; 556 } 557 558 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) 559 { 560 if (env->priv_ver > PRIV_VERSION_1_09_1) { 561 return -1; 562 } 563 env->scounteren = val; 564 return 0; 565 } 566 567 /* Machine Trap Handling */ 568 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 569 { 570 *val = env->mscratch; 571 return 0; 572 } 573 574 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 575 { 576 env->mscratch = val; 577 return 0; 578 } 579 580 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 581 { 582 *val = env->mepc; 583 return 0; 584 } 585 586 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 587 { 588 env->mepc = val; 589 return 0; 590 } 591 592 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 593 { 594 *val = env->mcause; 595 return 0; 596 } 597 598 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 599 { 600 env->mcause = val; 601 return 0; 602 } 603 604 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 605 { 606 *val = env->mbadaddr; 607 return 0; 608 } 609 610 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 611 { 612 env->mbadaddr = val; 613 return 0; 614 } 615 616 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 617 target_ulong new_value, target_ulong write_mask) 618 { 619 RISCVCPU *cpu = env_archcpu(env); 620 /* Allow software control of delegable interrupts not claimed by hardware */ 621 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 622 uint32_t old_mip; 623 624 if (mask) { 625 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 626 } else { 627 old_mip = env->mip; 628 } 629 630 if (ret_value) { 631 *ret_value = old_mip; 632 } 633 634 return 0; 635 } 636 637 /* Supervisor Trap Setup */ 638 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 639 { 640 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 641 sstatus_v1_10_mask : sstatus_v1_9_mask); 642 *val = env->mstatus & mask; 643 return 0; 644 } 645 646 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 647 { 648 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 649 sstatus_v1_10_mask : sstatus_v1_9_mask); 650 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 651 return write_mstatus(env, CSR_MSTATUS, newval); 652 } 653 654 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 655 { 656 if (riscv_cpu_virt_enabled(env)) { 657 /* Tell the guest the VS bits, shifted to the S bit locations */ 658 *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; 659 } else { 660 *val = env->mie & env->mideleg; 661 } 662 return 0; 663 } 664 665 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 666 { 667 target_ulong newval; 668 669 if (riscv_cpu_virt_enabled(env)) { 670 /* Shift the guests S bits to VS */ 671 newval = (env->mie & ~VS_MODE_INTERRUPTS) | 672 ((val << 1) & VS_MODE_INTERRUPTS); 673 } else { 674 newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); 675 } 676 677 return write_mie(env, CSR_MIE, newval); 678 } 679 680 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 681 { 682 *val = env->stvec; 683 return 0; 684 } 685 686 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 687 { 688 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 689 if ((val & 3) < 2) { 690 env->stvec = val; 691 } else { 692 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 693 } 694 return 0; 695 } 696 697 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 698 { 699 if (env->priv_ver < PRIV_VERSION_1_10_0) { 700 return -1; 701 } 702 *val = env->scounteren; 703 return 0; 704 } 705 706 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 707 { 708 if (env->priv_ver < PRIV_VERSION_1_10_0) { 709 return -1; 710 } 711 env->scounteren = val; 712 return 0; 713 } 714 715 /* Supervisor Trap Handling */ 716 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 717 { 718 *val = env->sscratch; 719 return 0; 720 } 721 722 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 723 { 724 env->sscratch = val; 725 return 0; 726 } 727 728 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 729 { 730 *val = env->sepc; 731 return 0; 732 } 733 734 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 735 { 736 env->sepc = val; 737 return 0; 738 } 739 740 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 741 { 742 *val = env->scause; 743 return 0; 744 } 745 746 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 747 { 748 env->scause = val; 749 return 0; 750 } 751 752 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 753 { 754 *val = env->sbadaddr; 755 return 0; 756 } 757 758 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 759 { 760 env->sbadaddr = val; 761 return 0; 762 } 763 764 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 765 target_ulong new_value, target_ulong write_mask) 766 { 767 int ret; 768 769 if (riscv_cpu_virt_enabled(env)) { 770 /* Shift the new values to line up with the VS bits */ 771 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, 772 (write_mask & sip_writable_mask) << 1 & env->mideleg); 773 ret &= vsip_writable_mask; 774 ret >>= 1; 775 } else { 776 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 777 write_mask & env->mideleg & sip_writable_mask); 778 } 779 780 *ret_value &= env->mideleg; 781 return ret; 782 } 783 784 /* Supervisor Protection and Translation */ 785 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 786 { 787 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 788 *val = 0; 789 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { 790 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 791 return -1; 792 } else { 793 *val = env->satp; 794 } 795 } else { 796 *val = env->sptbr; 797 } 798 return 0; 799 } 800 801 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 802 { 803 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 804 return 0; 805 } 806 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { 807 tlb_flush(env_cpu(env)); 808 env->sptbr = val & (((target_ulong) 809 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); 810 } 811 if (env->priv_ver >= PRIV_VERSION_1_10_0 && 812 validate_vm(env, get_field(val, SATP_MODE)) && 813 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 814 { 815 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 816 return -1; 817 } else { 818 if((val ^ env->satp) & SATP_ASID) { 819 tlb_flush(env_cpu(env)); 820 } 821 env->satp = val; 822 } 823 } 824 return 0; 825 } 826 827 /* Hypervisor Extensions */ 828 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) 829 { 830 *val = env->hstatus; 831 return 0; 832 } 833 834 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) 835 { 836 env->hstatus = val; 837 return 0; 838 } 839 840 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) 841 { 842 *val = env->hedeleg; 843 return 0; 844 } 845 846 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) 847 { 848 env->hedeleg = val; 849 return 0; 850 } 851 852 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) 853 { 854 *val = env->hideleg; 855 return 0; 856 } 857 858 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) 859 { 860 env->hideleg = val; 861 return 0; 862 } 863 864 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, 865 target_ulong new_value, target_ulong write_mask) 866 { 867 int ret = rmw_mip(env, 0, ret_value, new_value, 868 write_mask & hip_writable_mask); 869 870 return ret; 871 } 872 873 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) 874 { 875 *val = env->mie & VS_MODE_INTERRUPTS; 876 return 0; 877 } 878 879 static int write_hie(CPURISCVState *env, int csrno, target_ulong val) 880 { 881 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 882 return write_mie(env, CSR_MIE, newval); 883 } 884 885 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val) 886 { 887 *val = env->hcounteren; 888 return 0; 889 } 890 891 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) 892 { 893 env->hcounteren = val; 894 return 0; 895 } 896 897 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) 898 { 899 *val = env->htval; 900 return 0; 901 } 902 903 static int write_htval(CPURISCVState *env, int csrno, target_ulong val) 904 { 905 env->htval = val; 906 return 0; 907 } 908 909 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) 910 { 911 *val = env->htinst; 912 return 0; 913 } 914 915 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) 916 { 917 env->htinst = val; 918 return 0; 919 } 920 921 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) 922 { 923 *val = env->hgatp; 924 return 0; 925 } 926 927 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) 928 { 929 env->hgatp = val; 930 return 0; 931 } 932 933 /* Virtual CSR Registers */ 934 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) 935 { 936 *val = env->vsstatus; 937 return 0; 938 } 939 940 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) 941 { 942 env->vsstatus = val; 943 return 0; 944 } 945 946 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, 947 target_ulong new_value, target_ulong write_mask) 948 { 949 int ret = rmw_mip(env, 0, ret_value, new_value, 950 write_mask & env->mideleg & vsip_writable_mask); 951 return ret; 952 } 953 954 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) 955 { 956 *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; 957 return 0; 958 } 959 960 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) 961 { 962 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); 963 return write_mie(env, CSR_MIE, newval); 964 } 965 966 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 967 { 968 *val = env->vstvec; 969 return 0; 970 } 971 972 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) 973 { 974 env->vstvec = val; 975 return 0; 976 } 977 978 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) 979 { 980 *val = env->vsscratch; 981 return 0; 982 } 983 984 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) 985 { 986 env->vsscratch = val; 987 return 0; 988 } 989 990 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) 991 { 992 *val = env->vsepc; 993 return 0; 994 } 995 996 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) 997 { 998 env->vsepc = val; 999 return 0; 1000 } 1001 1002 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) 1003 { 1004 *val = env->vscause; 1005 return 0; 1006 } 1007 1008 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) 1009 { 1010 env->vscause = val; 1011 return 0; 1012 } 1013 1014 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) 1015 { 1016 *val = env->vstval; 1017 return 0; 1018 } 1019 1020 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) 1021 { 1022 env->vstval = val; 1023 return 0; 1024 } 1025 1026 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) 1027 { 1028 *val = env->vsatp; 1029 return 0; 1030 } 1031 1032 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) 1033 { 1034 env->vsatp = val; 1035 return 0; 1036 } 1037 1038 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) 1039 { 1040 *val = env->mtval2; 1041 return 0; 1042 } 1043 1044 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) 1045 { 1046 env->mtval2 = val; 1047 return 0; 1048 } 1049 1050 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) 1051 { 1052 *val = env->mtinst; 1053 return 0; 1054 } 1055 1056 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) 1057 { 1058 env->mtinst = val; 1059 return 0; 1060 } 1061 1062 /* Physical Memory Protection */ 1063 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 1064 { 1065 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1066 return 0; 1067 } 1068 1069 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 1070 { 1071 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1072 return 0; 1073 } 1074 1075 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 1076 { 1077 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1078 return 0; 1079 } 1080 1081 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 1082 { 1083 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1084 return 0; 1085 } 1086 1087 #endif 1088 1089 /* 1090 * riscv_csrrw - read and/or update control and status register 1091 * 1092 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1093 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1094 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1095 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1096 */ 1097 1098 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 1099 target_ulong new_value, target_ulong write_mask) 1100 { 1101 int ret; 1102 target_ulong old_value; 1103 RISCVCPU *cpu = env_archcpu(env); 1104 1105 /* check privileges and return -1 if check fails */ 1106 #if !defined(CONFIG_USER_ONLY) 1107 int effective_priv = env->priv; 1108 int read_only = get_field(csrno, 0xC00) == 3; 1109 1110 if (riscv_has_ext(env, RVH) && 1111 env->priv == PRV_S && 1112 !riscv_cpu_virt_enabled(env)) { 1113 /* 1114 * We are in S mode without virtualisation, therefore we are in HS Mode. 1115 * Add 1 to the effective privledge level to allow us to access the 1116 * Hypervisor CSRs. 1117 */ 1118 effective_priv++; 1119 } 1120 1121 if ((write_mask && read_only) || 1122 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1123 return -1; 1124 } 1125 #endif 1126 1127 /* ensure the CSR extension is enabled. */ 1128 if (!cpu->cfg.ext_icsr) { 1129 return -1; 1130 } 1131 1132 /* check predicate */ 1133 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { 1134 return -1; 1135 } 1136 1137 /* execute combined read/write operation if it exists */ 1138 if (csr_ops[csrno].op) { 1139 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1140 } 1141 1142 /* if no accessor exists then return failure */ 1143 if (!csr_ops[csrno].read) { 1144 return -1; 1145 } 1146 1147 /* read old value */ 1148 ret = csr_ops[csrno].read(env, csrno, &old_value); 1149 if (ret < 0) { 1150 return ret; 1151 } 1152 1153 /* write value if writable and write mask set, otherwise drop writes */ 1154 if (write_mask) { 1155 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1156 if (csr_ops[csrno].write) { 1157 ret = csr_ops[csrno].write(env, csrno, new_value); 1158 if (ret < 0) { 1159 return ret; 1160 } 1161 } 1162 } 1163 1164 /* return old value */ 1165 if (ret_value) { 1166 *ret_value = old_value; 1167 } 1168 1169 return 0; 1170 } 1171 1172 /* 1173 * Debugger support. If not in user mode, set env->debugger before the 1174 * riscv_csrrw call and clear it after the call. 1175 */ 1176 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 1177 target_ulong new_value, target_ulong write_mask) 1178 { 1179 int ret; 1180 #if !defined(CONFIG_USER_ONLY) 1181 env->debugger = true; 1182 #endif 1183 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1184 #if !defined(CONFIG_USER_ONLY) 1185 env->debugger = false; 1186 #endif 1187 return ret; 1188 } 1189 1190 /* Control and Status Register function table */ 1191 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1192 /* User Floating-Point CSRs */ 1193 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 1194 [CSR_FRM] = { fs, read_frm, write_frm }, 1195 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 1196 1197 /* User Timers and Counters */ 1198 [CSR_CYCLE] = { ctr, read_instret }, 1199 [CSR_INSTRET] = { ctr, read_instret }, 1200 #if defined(TARGET_RISCV32) 1201 [CSR_CYCLEH] = { ctr, read_instreth }, 1202 [CSR_INSTRETH] = { ctr, read_instreth }, 1203 #endif 1204 1205 /* User-level time CSRs are only available in linux-user 1206 * In privileged mode, the monitor emulates these CSRs */ 1207 #if defined(CONFIG_USER_ONLY) 1208 [CSR_TIME] = { ctr, read_time }, 1209 #if defined(TARGET_RISCV32) 1210 [CSR_TIMEH] = { ctr, read_timeh }, 1211 #endif 1212 #endif 1213 1214 #if !defined(CONFIG_USER_ONLY) 1215 /* Machine Timers and Counters */ 1216 [CSR_MCYCLE] = { any, read_instret }, 1217 [CSR_MINSTRET] = { any, read_instret }, 1218 #if defined(TARGET_RISCV32) 1219 [CSR_MCYCLEH] = { any, read_instreth }, 1220 [CSR_MINSTRETH] = { any, read_instreth }, 1221 #endif 1222 1223 /* Machine Information Registers */ 1224 [CSR_MVENDORID] = { any, read_zero }, 1225 [CSR_MARCHID] = { any, read_zero }, 1226 [CSR_MIMPID] = { any, read_zero }, 1227 [CSR_MHARTID] = { any, read_mhartid }, 1228 1229 /* Machine Trap Setup */ 1230 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 1231 [CSR_MISA] = { any, read_misa, write_misa }, 1232 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 1233 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 1234 [CSR_MIE] = { any, read_mie, write_mie }, 1235 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 1236 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 1237 1238 #if defined(TARGET_RISCV32) 1239 [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush }, 1240 #endif 1241 1242 /* Legacy Counter Setup (priv v1.9.1) */ 1243 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, 1244 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 1245 1246 /* Machine Trap Handling */ 1247 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 1248 [CSR_MEPC] = { any, read_mepc, write_mepc }, 1249 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 1250 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 1251 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 1252 1253 /* Supervisor Trap Setup */ 1254 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 1255 [CSR_SIE] = { smode, read_sie, write_sie }, 1256 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 1257 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 1258 1259 /* Supervisor Trap Handling */ 1260 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 1261 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 1262 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 1263 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 1264 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 1265 1266 /* Supervisor Protection and Translation */ 1267 [CSR_SATP] = { smode, read_satp, write_satp }, 1268 1269 [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, 1270 [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, 1271 [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, 1272 [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, 1273 [CSR_HIE] = { hmode, read_hie, write_hie }, 1274 [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, 1275 [CSR_HTVAL] = { hmode, read_htval, write_htval }, 1276 [CSR_HTINST] = { hmode, read_htinst, write_htinst }, 1277 [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, 1278 1279 [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, 1280 [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip }, 1281 [CSR_VSIE] = { hmode, read_vsie, write_vsie }, 1282 [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, 1283 [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, 1284 [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, 1285 [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, 1286 [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, 1287 [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, 1288 1289 [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 }, 1290 [CSR_MTINST] = { hmode, read_mtinst, write_mtinst }, 1291 1292 /* Physical Memory Protection */ 1293 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, 1294 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 1295 1296 /* Performance Counters */ 1297 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 1298 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 1299 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 1300 #if defined(TARGET_RISCV32) 1301 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 1302 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 1303 #endif 1304 #endif /* !CONFIG_USER_ONLY */ 1305 }; 1306