1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 if (!(env->mstatus & MSTATUS_FS)) { 50 return -1; 51 } 52 #endif 53 return 0; 54 } 55 56 static int ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : 60 env->priv == PRV_S ? env->mcounteren : -1U; 61 if (!(ctr_en & (1 << (csrno & 31)))) { 62 return -1; 63 } 64 #endif 65 return 0; 66 } 67 68 #if !defined(CONFIG_USER_ONLY) 69 static int any(CPURISCVState *env, int csrno) 70 { 71 return 0; 72 } 73 74 static int smode(CPURISCVState *env, int csrno) 75 { 76 return -!riscv_has_ext(env, RVS); 77 } 78 79 static int pmp(CPURISCVState *env, int csrno) 80 { 81 return -!riscv_feature(env, RISCV_FEATURE_PMP); 82 } 83 #endif 84 85 /* User Floating-Point CSRs */ 86 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 87 { 88 #if !defined(CONFIG_USER_ONLY) 89 if (!(env->mstatus & MSTATUS_FS)) { 90 return -1; 91 } 92 #endif 93 *val = cpu_riscv_get_fflags(env); 94 return 0; 95 } 96 97 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 98 { 99 #if !defined(CONFIG_USER_ONLY) 100 if (!(env->mstatus & MSTATUS_FS)) { 101 return -1; 102 } 103 env->mstatus |= MSTATUS_FS; 104 #endif 105 cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 106 return 0; 107 } 108 109 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 110 { 111 #if !defined(CONFIG_USER_ONLY) 112 if (!(env->mstatus & MSTATUS_FS)) { 113 return -1; 114 } 115 #endif 116 *val = env->frm; 117 return 0; 118 } 119 120 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 121 { 122 #if !defined(CONFIG_USER_ONLY) 123 if (!(env->mstatus & MSTATUS_FS)) { 124 return -1; 125 } 126 env->mstatus |= MSTATUS_FS; 127 #endif 128 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 129 return 0; 130 } 131 132 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 133 { 134 #if !defined(CONFIG_USER_ONLY) 135 if (!(env->mstatus & MSTATUS_FS)) { 136 return -1; 137 } 138 #endif 139 *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT) 140 | (env->frm << FSR_RD_SHIFT); 141 return 0; 142 } 143 144 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 145 { 146 #if !defined(CONFIG_USER_ONLY) 147 if (!(env->mstatus & MSTATUS_FS)) { 148 return -1; 149 } 150 env->mstatus |= MSTATUS_FS; 151 #endif 152 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 153 cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 154 return 0; 155 } 156 157 /* User Timers and Counters */ 158 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 159 { 160 #if !defined(CONFIG_USER_ONLY) 161 if (use_icount) { 162 *val = cpu_get_icount(); 163 } else { 164 *val = cpu_get_host_ticks(); 165 } 166 #else 167 *val = cpu_get_host_ticks(); 168 #endif 169 return 0; 170 } 171 172 #if defined(TARGET_RISCV32) 173 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 174 { 175 #if !defined(CONFIG_USER_ONLY) 176 if (use_icount) { 177 *val = cpu_get_icount() >> 32; 178 } else { 179 *val = cpu_get_host_ticks() >> 32; 180 } 181 #else 182 *val = cpu_get_host_ticks() >> 32; 183 #endif 184 return 0; 185 } 186 #endif /* TARGET_RISCV32 */ 187 188 #if defined(CONFIG_USER_ONLY) 189 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 190 { 191 *val = cpu_get_host_ticks(); 192 return 0; 193 } 194 195 #if defined(TARGET_RISCV32) 196 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 197 { 198 *val = cpu_get_host_ticks() >> 32; 199 return 0; 200 } 201 #endif 202 203 #else /* CONFIG_USER_ONLY */ 204 205 /* Machine constants */ 206 207 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 208 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 209 210 static const target_ulong delegable_ints = S_MODE_INTERRUPTS; 211 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; 212 static const target_ulong delegable_excps = 213 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 214 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 215 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 216 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 217 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 218 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 219 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 220 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 221 (1ULL << (RISCV_EXCP_U_ECALL)) | 222 (1ULL << (RISCV_EXCP_S_ECALL)) | 223 (1ULL << (RISCV_EXCP_H_ECALL)) | 224 (1ULL << (RISCV_EXCP_M_ECALL)) | 225 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 226 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 227 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); 228 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 229 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 230 SSTATUS_SUM | SSTATUS_SD; 231 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 232 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 233 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 234 235 #if defined(TARGET_RISCV32) 236 static const char valid_vm_1_09[16] = { 237 [VM_1_09_MBARE] = 1, 238 [VM_1_09_SV32] = 1, 239 }; 240 static const char valid_vm_1_10[16] = { 241 [VM_1_10_MBARE] = 1, 242 [VM_1_10_SV32] = 1 243 }; 244 #elif defined(TARGET_RISCV64) 245 static const char valid_vm_1_09[16] = { 246 [VM_1_09_MBARE] = 1, 247 [VM_1_09_SV39] = 1, 248 [VM_1_09_SV48] = 1, 249 }; 250 static const char valid_vm_1_10[16] = { 251 [VM_1_10_MBARE] = 1, 252 [VM_1_10_SV39] = 1, 253 [VM_1_10_SV48] = 1, 254 [VM_1_10_SV57] = 1 255 }; 256 #endif /* CONFIG_USER_ONLY */ 257 258 /* Machine Information Registers */ 259 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 260 { 261 return *val = 0; 262 } 263 264 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 265 { 266 *val = env->mhartid; 267 return 0; 268 } 269 270 /* Machine Trap Setup */ 271 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 272 { 273 *val = env->mstatus; 274 return 0; 275 } 276 277 static int validate_vm(CPURISCVState *env, target_ulong vm) 278 { 279 return (env->priv_ver >= PRIV_VERSION_1_10_0) ? 280 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; 281 } 282 283 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 284 { 285 target_ulong mstatus = env->mstatus; 286 target_ulong mask = 0; 287 target_ulong mpp = get_field(val, MSTATUS_MPP); 288 289 /* flush tlb on mstatus fields that affect VM */ 290 if (env->priv_ver <= PRIV_VERSION_1_09_1) { 291 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 292 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { 293 tlb_flush(CPU(riscv_env_get_cpu(env))); 294 } 295 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 296 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 297 MSTATUS_MPP | MSTATUS_MXR | 298 (validate_vm(env, get_field(val, MSTATUS_VM)) ? 299 MSTATUS_VM : 0); 300 } 301 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 302 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 303 MSTATUS_MPRV | MSTATUS_SUM)) { 304 tlb_flush(CPU(riscv_env_get_cpu(env))); 305 } 306 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 307 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 308 MSTATUS_MPP | MSTATUS_MXR; 309 } 310 311 /* silenty discard mstatus.mpp writes for unsupported modes */ 312 if (mpp == PRV_H || 313 (!riscv_has_ext(env, RVS) && mpp == PRV_S) || 314 (!riscv_has_ext(env, RVU) && mpp == PRV_U)) { 315 mask &= ~MSTATUS_MPP; 316 } 317 318 mstatus = (mstatus & ~mask) | (val & mask); 319 320 int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 321 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 322 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 323 env->mstatus = mstatus; 324 325 return 0; 326 } 327 328 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 329 { 330 *val = env->misa; 331 return 0; 332 } 333 334 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 335 { 336 *val = env->medeleg; 337 return 0; 338 } 339 340 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 341 { 342 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 343 return 0; 344 } 345 346 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 347 { 348 *val = env->mideleg; 349 return 0; 350 } 351 352 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 353 { 354 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 355 return 0; 356 } 357 358 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 359 { 360 *val = env->mie; 361 return 0; 362 } 363 364 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 365 { 366 env->mie = (env->mie & ~all_ints) | (val & all_ints); 367 return 0; 368 } 369 370 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 371 { 372 *val = env->mtvec; 373 return 0; 374 } 375 376 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 377 { 378 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 379 if ((val & 3) == 0) { 380 env->mtvec = val >> 2 << 2; 381 } else { 382 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); 383 } 384 return 0; 385 } 386 387 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 388 { 389 if (env->priv_ver < PRIV_VERSION_1_10_0) { 390 return -1; 391 } 392 *val = env->mcounteren; 393 return 0; 394 } 395 396 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 397 { 398 if (env->priv_ver < PRIV_VERSION_1_10_0) { 399 return -1; 400 } 401 env->mcounteren = val; 402 return 0; 403 } 404 405 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 406 { 407 if (env->priv_ver > PRIV_VERSION_1_09_1) { 408 return -1; 409 } 410 *val = env->mcounteren; 411 return 0; 412 } 413 414 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 415 { 416 if (env->priv_ver > PRIV_VERSION_1_09_1) { 417 return -1; 418 } 419 env->mcounteren = val; 420 return 0; 421 } 422 423 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) 424 { 425 if (env->priv_ver > PRIV_VERSION_1_09_1) { 426 return -1; 427 } 428 *val = env->scounteren; 429 return 0; 430 } 431 432 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) 433 { 434 if (env->priv_ver > PRIV_VERSION_1_09_1) { 435 return -1; 436 } 437 env->scounteren = val; 438 return 0; 439 } 440 441 /* Machine Trap Handling */ 442 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 443 { 444 *val = env->mscratch; 445 return 0; 446 } 447 448 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 449 { 450 env->mscratch = val; 451 return 0; 452 } 453 454 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 455 { 456 *val = env->mepc; 457 return 0; 458 } 459 460 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 461 { 462 env->mepc = val; 463 return 0; 464 } 465 466 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 467 { 468 *val = env->mcause; 469 return 0; 470 } 471 472 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 473 { 474 env->mcause = val; 475 return 0; 476 } 477 478 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 479 { 480 *val = env->mbadaddr; 481 return 0; 482 } 483 484 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 485 { 486 env->mbadaddr = val; 487 return 0; 488 } 489 490 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 491 target_ulong new_value, target_ulong write_mask) 492 { 493 RISCVCPU *cpu = riscv_env_get_cpu(env); 494 target_ulong mask = write_mask & delegable_ints; 495 uint32_t old_mip; 496 497 /* We can't allow the supervisor to control SEIP as this would allow the 498 * supervisor to clear a pending external interrupt which will result in 499 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be 500 * hardware controlled when a PLIC is attached. This should be an option 501 * for CPUs with software-delegated Supervisor External Interrupts. */ 502 mask &= ~MIP_SEIP; 503 504 if (mask) { 505 qemu_mutex_lock_iothread(); 506 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 507 qemu_mutex_unlock_iothread(); 508 } else { 509 old_mip = atomic_read(&env->mip); 510 } 511 512 if (ret_value) { 513 *ret_value = old_mip; 514 } 515 516 return 0; 517 } 518 519 /* Supervisor Trap Setup */ 520 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 521 { 522 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 523 sstatus_v1_10_mask : sstatus_v1_9_mask); 524 *val = env->mstatus & mask; 525 return 0; 526 } 527 528 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 529 { 530 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 531 sstatus_v1_10_mask : sstatus_v1_9_mask); 532 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 533 return write_mstatus(env, CSR_MSTATUS, newval); 534 } 535 536 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 537 { 538 *val = env->mie & env->mideleg; 539 return 0; 540 } 541 542 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 543 { 544 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); 545 return write_mie(env, CSR_MIE, newval); 546 } 547 548 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 549 { 550 *val = env->stvec; 551 return 0; 552 } 553 554 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 555 { 556 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 557 if ((val & 3) == 0) { 558 env->stvec = val >> 2 << 2; 559 } else { 560 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); 561 } 562 return 0; 563 } 564 565 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 566 { 567 if (env->priv_ver < PRIV_VERSION_1_10_0) { 568 return -1; 569 } 570 *val = env->scounteren; 571 return 0; 572 } 573 574 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 575 { 576 if (env->priv_ver < PRIV_VERSION_1_10_0) { 577 return -1; 578 } 579 env->scounteren = val; 580 return 0; 581 } 582 583 /* Supervisor Trap Handling */ 584 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 585 { 586 *val = env->sscratch; 587 return 0; 588 } 589 590 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 591 { 592 env->sscratch = val; 593 return 0; 594 } 595 596 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 597 { 598 *val = env->sepc; 599 return 0; 600 } 601 602 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 603 { 604 env->sepc = val; 605 return 0; 606 } 607 608 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 609 { 610 *val = env->scause; 611 return 0; 612 } 613 614 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 615 { 616 env->scause = val; 617 return 0; 618 } 619 620 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 621 { 622 *val = env->sbadaddr; 623 return 0; 624 } 625 626 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 627 { 628 env->sbadaddr = val; 629 return 0; 630 } 631 632 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 633 target_ulong new_value, target_ulong write_mask) 634 { 635 return rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 636 write_mask & env->mideleg); 637 } 638 639 /* Supervisor Protection and Translation */ 640 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 641 { 642 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 643 *val = 0; 644 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { 645 *val = env->satp; 646 } else { 647 *val = env->sptbr; 648 } 649 return 0; 650 } 651 652 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 653 { 654 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 655 return 0; 656 } 657 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { 658 tlb_flush(CPU(riscv_env_get_cpu(env))); 659 env->sptbr = val & (((target_ulong) 660 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); 661 } 662 if (env->priv_ver >= PRIV_VERSION_1_10_0 && 663 validate_vm(env, get_field(val, SATP_MODE)) && 664 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 665 { 666 tlb_flush(CPU(riscv_env_get_cpu(env))); 667 env->satp = val; 668 } 669 return 0; 670 } 671 672 /* Physical Memory Protection */ 673 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 674 { 675 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 676 return 0; 677 } 678 679 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 680 { 681 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 682 return 0; 683 } 684 685 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 686 { 687 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 688 return 0; 689 } 690 691 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 692 { 693 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 694 return 0; 695 } 696 697 #endif 698 699 /* 700 * riscv_csrrw - read and/or update control and status register 701 * 702 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 703 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 704 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 705 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 706 */ 707 708 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 709 target_ulong new_value, target_ulong write_mask) 710 { 711 int ret; 712 target_ulong old_value; 713 714 /* check privileges and return -1 if check fails */ 715 #if !defined(CONFIG_USER_ONLY) 716 int csr_priv = get_field(csrno, 0x300); 717 int read_only = get_field(csrno, 0xC00) == 3; 718 if ((write_mask && read_only) || (env->priv < csr_priv)) { 719 return -1; 720 } 721 #endif 722 723 /* check predicate */ 724 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { 725 return -1; 726 } 727 728 /* execute combined read/write operation if it exists */ 729 if (csr_ops[csrno].op) { 730 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 731 } 732 733 /* if no accessor exists then return failure */ 734 if (!csr_ops[csrno].read) { 735 return -1; 736 } 737 738 /* read old value */ 739 ret = csr_ops[csrno].read(env, csrno, &old_value); 740 if (ret < 0) { 741 return ret; 742 } 743 744 /* write value if writable and write mask set, otherwise drop writes */ 745 if (write_mask) { 746 new_value = (old_value & ~write_mask) | (new_value & write_mask); 747 if (csr_ops[csrno].write) { 748 ret = csr_ops[csrno].write(env, csrno, new_value); 749 if (ret < 0) { 750 return ret; 751 } 752 } 753 } 754 755 /* return old value */ 756 if (ret_value) { 757 *ret_value = old_value; 758 } 759 760 return 0; 761 } 762 763 /* Control and Status Register function table */ 764 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 765 /* User Floating-Point CSRs */ 766 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 767 [CSR_FRM] = { fs, read_frm, write_frm }, 768 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 769 770 /* User Timers and Counters */ 771 [CSR_CYCLE] = { ctr, read_instret }, 772 [CSR_INSTRET] = { ctr, read_instret }, 773 #if defined(TARGET_RISCV32) 774 [CSR_CYCLEH] = { ctr, read_instreth }, 775 [CSR_INSTRETH] = { ctr, read_instreth }, 776 #endif 777 778 /* User-level time CSRs are only available in linux-user 779 * In privileged mode, the monitor emulates these CSRs */ 780 #if defined(CONFIG_USER_ONLY) 781 [CSR_TIME] = { ctr, read_time }, 782 #if defined(TARGET_RISCV32) 783 [CSR_TIMEH] = { ctr, read_timeh }, 784 #endif 785 #endif 786 787 #if !defined(CONFIG_USER_ONLY) 788 /* Machine Timers and Counters */ 789 [CSR_MCYCLE] = { any, read_instret }, 790 [CSR_MINSTRET] = { any, read_instret }, 791 #if defined(TARGET_RISCV32) 792 [CSR_MCYCLEH] = { any, read_instreth }, 793 [CSR_MINSTRETH] = { any, read_instreth }, 794 #endif 795 796 /* Machine Information Registers */ 797 [CSR_MVENDORID] = { any, read_zero }, 798 [CSR_MARCHID] = { any, read_zero }, 799 [CSR_MIMPID] = { any, read_zero }, 800 [CSR_MHARTID] = { any, read_mhartid }, 801 802 /* Machine Trap Setup */ 803 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 804 [CSR_MISA] = { any, read_misa }, 805 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 806 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 807 [CSR_MIE] = { any, read_mie, write_mie }, 808 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 809 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 810 811 /* Legacy Counter Setup (priv v1.9.1) */ 812 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, 813 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 814 815 /* Machine Trap Handling */ 816 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 817 [CSR_MEPC] = { any, read_mepc, write_mepc }, 818 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 819 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 820 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 821 822 /* Supervisor Trap Setup */ 823 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 824 [CSR_SIE] = { smode, read_sie, write_sie }, 825 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 826 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 827 828 /* Supervisor Trap Handling */ 829 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 830 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 831 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 832 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 833 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 834 835 /* Supervisor Protection and Translation */ 836 [CSR_SATP] = { smode, read_satp, write_satp }, 837 838 /* Physical Memory Protection */ 839 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, 840 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 841 842 /* Performance Counters */ 843 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 844 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 845 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 846 #if defined(TARGET_RISCV32) 847 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 848 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 849 #endif 850 #endif /* !CONFIG_USER_ONLY */ 851 }; 852