1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 42 return RISCV_EXCP_ILLEGAL_INST; 43 } 44 #endif 45 return RISCV_EXCP_NONE; 46 } 47 48 static RISCVException vs(CPURISCVState *env, int csrno) 49 { 50 if (env->misa_ext & RVV) { 51 return RISCV_EXCP_NONE; 52 } 53 return RISCV_EXCP_ILLEGAL_INST; 54 } 55 56 static RISCVException ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 CPUState *cs = env_cpu(env); 60 RISCVCPU *cpu = RISCV_CPU(cs); 61 62 if (!cpu->cfg.ext_counters) { 63 /* The Counters extensions is not enabled */ 64 return RISCV_EXCP_ILLEGAL_INST; 65 } 66 67 if (riscv_cpu_virt_enabled(env)) { 68 switch (csrno) { 69 case CSR_CYCLE: 70 if (!get_field(env->hcounteren, COUNTEREN_CY) && 71 get_field(env->mcounteren, COUNTEREN_CY)) { 72 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 73 } 74 break; 75 case CSR_TIME: 76 if (!get_field(env->hcounteren, COUNTEREN_TM) && 77 get_field(env->mcounteren, COUNTEREN_TM)) { 78 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 79 } 80 break; 81 case CSR_INSTRET: 82 if (!get_field(env->hcounteren, COUNTEREN_IR) && 83 get_field(env->mcounteren, COUNTEREN_IR)) { 84 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 85 } 86 break; 87 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 88 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 89 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 90 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 91 } 92 break; 93 } 94 if (riscv_cpu_mxl(env) == MXL_RV32) { 95 switch (csrno) { 96 case CSR_CYCLEH: 97 if (!get_field(env->hcounteren, COUNTEREN_CY) && 98 get_field(env->mcounteren, COUNTEREN_CY)) { 99 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 100 } 101 break; 102 case CSR_TIMEH: 103 if (!get_field(env->hcounteren, COUNTEREN_TM) && 104 get_field(env->mcounteren, COUNTEREN_TM)) { 105 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 106 } 107 break; 108 case CSR_INSTRETH: 109 if (!get_field(env->hcounteren, COUNTEREN_IR) && 110 get_field(env->mcounteren, COUNTEREN_IR)) { 111 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 112 } 113 break; 114 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 115 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 116 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 117 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 118 } 119 break; 120 } 121 } 122 } 123 #endif 124 return RISCV_EXCP_NONE; 125 } 126 127 static RISCVException ctr32(CPURISCVState *env, int csrno) 128 { 129 if (riscv_cpu_mxl(env) != MXL_RV32) { 130 return RISCV_EXCP_ILLEGAL_INST; 131 } 132 133 return ctr(env, csrno); 134 } 135 136 #if !defined(CONFIG_USER_ONLY) 137 static RISCVException any(CPURISCVState *env, int csrno) 138 { 139 return RISCV_EXCP_NONE; 140 } 141 142 static RISCVException any32(CPURISCVState *env, int csrno) 143 { 144 if (riscv_cpu_mxl(env) != MXL_RV32) { 145 return RISCV_EXCP_ILLEGAL_INST; 146 } 147 148 return any(env, csrno); 149 150 } 151 152 static RISCVException smode(CPURISCVState *env, int csrno) 153 { 154 if (riscv_has_ext(env, RVS)) { 155 return RISCV_EXCP_NONE; 156 } 157 158 return RISCV_EXCP_ILLEGAL_INST; 159 } 160 161 static RISCVException hmode(CPURISCVState *env, int csrno) 162 { 163 if (riscv_has_ext(env, RVS) && 164 riscv_has_ext(env, RVH)) { 165 /* Hypervisor extension is supported */ 166 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 167 env->priv == PRV_M) { 168 return RISCV_EXCP_NONE; 169 } else { 170 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 171 } 172 } 173 174 return RISCV_EXCP_ILLEGAL_INST; 175 } 176 177 static RISCVException hmode32(CPURISCVState *env, int csrno) 178 { 179 if (riscv_cpu_mxl(env) != MXL_RV32) { 180 if (riscv_cpu_virt_enabled(env)) { 181 return RISCV_EXCP_ILLEGAL_INST; 182 } else { 183 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 184 } 185 } 186 187 return hmode(env, csrno); 188 189 } 190 191 /* Checks if PointerMasking registers could be accessed */ 192 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 193 { 194 /* Check if j-ext is present */ 195 if (riscv_has_ext(env, RVJ)) { 196 return RISCV_EXCP_NONE; 197 } 198 return RISCV_EXCP_ILLEGAL_INST; 199 } 200 201 static RISCVException pmp(CPURISCVState *env, int csrno) 202 { 203 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 204 return RISCV_EXCP_NONE; 205 } 206 207 return RISCV_EXCP_ILLEGAL_INST; 208 } 209 210 static RISCVException epmp(CPURISCVState *env, int csrno) 211 { 212 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 213 return RISCV_EXCP_NONE; 214 } 215 216 return RISCV_EXCP_ILLEGAL_INST; 217 } 218 #endif 219 220 /* User Floating-Point CSRs */ 221 static RISCVException read_fflags(CPURISCVState *env, int csrno, 222 target_ulong *val) 223 { 224 *val = riscv_cpu_get_fflags(env); 225 return RISCV_EXCP_NONE; 226 } 227 228 static RISCVException write_fflags(CPURISCVState *env, int csrno, 229 target_ulong val) 230 { 231 #if !defined(CONFIG_USER_ONLY) 232 env->mstatus |= MSTATUS_FS; 233 #endif 234 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 235 return RISCV_EXCP_NONE; 236 } 237 238 static RISCVException read_frm(CPURISCVState *env, int csrno, 239 target_ulong *val) 240 { 241 *val = env->frm; 242 return RISCV_EXCP_NONE; 243 } 244 245 static RISCVException write_frm(CPURISCVState *env, int csrno, 246 target_ulong val) 247 { 248 #if !defined(CONFIG_USER_ONLY) 249 env->mstatus |= MSTATUS_FS; 250 #endif 251 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 252 return RISCV_EXCP_NONE; 253 } 254 255 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 256 target_ulong *val) 257 { 258 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 259 | (env->frm << FSR_RD_SHIFT); 260 return RISCV_EXCP_NONE; 261 } 262 263 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 264 target_ulong val) 265 { 266 #if !defined(CONFIG_USER_ONLY) 267 env->mstatus |= MSTATUS_FS; 268 #endif 269 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 270 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 271 return RISCV_EXCP_NONE; 272 } 273 274 static RISCVException read_vtype(CPURISCVState *env, int csrno, 275 target_ulong *val) 276 { 277 *val = env->vtype; 278 return RISCV_EXCP_NONE; 279 } 280 281 static RISCVException read_vl(CPURISCVState *env, int csrno, 282 target_ulong *val) 283 { 284 *val = env->vl; 285 return RISCV_EXCP_NONE; 286 } 287 288 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 289 target_ulong *val) 290 { 291 *val = env->vxrm; 292 return RISCV_EXCP_NONE; 293 } 294 295 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 296 target_ulong val) 297 { 298 #if !defined(CONFIG_USER_ONLY) 299 env->mstatus |= MSTATUS_VS; 300 #endif 301 env->vxrm = val; 302 return RISCV_EXCP_NONE; 303 } 304 305 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 306 target_ulong *val) 307 { 308 *val = env->vxsat; 309 return RISCV_EXCP_NONE; 310 } 311 312 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 313 target_ulong val) 314 { 315 #if !defined(CONFIG_USER_ONLY) 316 env->mstatus |= MSTATUS_VS; 317 #endif 318 env->vxsat = val; 319 return RISCV_EXCP_NONE; 320 } 321 322 static RISCVException read_vstart(CPURISCVState *env, int csrno, 323 target_ulong *val) 324 { 325 *val = env->vstart; 326 return RISCV_EXCP_NONE; 327 } 328 329 static RISCVException write_vstart(CPURISCVState *env, int csrno, 330 target_ulong val) 331 { 332 #if !defined(CONFIG_USER_ONLY) 333 env->mstatus |= MSTATUS_VS; 334 #endif 335 env->vstart = val; 336 return RISCV_EXCP_NONE; 337 } 338 339 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 340 { 341 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 342 return RISCV_EXCP_NONE; 343 } 344 345 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 346 { 347 #if !defined(CONFIG_USER_ONLY) 348 env->mstatus |= MSTATUS_VS; 349 #endif 350 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 351 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 352 return RISCV_EXCP_NONE; 353 } 354 355 /* User Timers and Counters */ 356 static RISCVException read_instret(CPURISCVState *env, int csrno, 357 target_ulong *val) 358 { 359 #if !defined(CONFIG_USER_ONLY) 360 if (icount_enabled()) { 361 *val = icount_get(); 362 } else { 363 *val = cpu_get_host_ticks(); 364 } 365 #else 366 *val = cpu_get_host_ticks(); 367 #endif 368 return RISCV_EXCP_NONE; 369 } 370 371 static RISCVException read_instreth(CPURISCVState *env, int csrno, 372 target_ulong *val) 373 { 374 #if !defined(CONFIG_USER_ONLY) 375 if (icount_enabled()) { 376 *val = icount_get() >> 32; 377 } else { 378 *val = cpu_get_host_ticks() >> 32; 379 } 380 #else 381 *val = cpu_get_host_ticks() >> 32; 382 #endif 383 return RISCV_EXCP_NONE; 384 } 385 386 #if defined(CONFIG_USER_ONLY) 387 static RISCVException read_time(CPURISCVState *env, int csrno, 388 target_ulong *val) 389 { 390 *val = cpu_get_host_ticks(); 391 return RISCV_EXCP_NONE; 392 } 393 394 static RISCVException read_timeh(CPURISCVState *env, int csrno, 395 target_ulong *val) 396 { 397 *val = cpu_get_host_ticks() >> 32; 398 return RISCV_EXCP_NONE; 399 } 400 401 #else /* CONFIG_USER_ONLY */ 402 403 static RISCVException read_time(CPURISCVState *env, int csrno, 404 target_ulong *val) 405 { 406 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 407 408 if (!env->rdtime_fn) { 409 return RISCV_EXCP_ILLEGAL_INST; 410 } 411 412 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 413 return RISCV_EXCP_NONE; 414 } 415 416 static RISCVException read_timeh(CPURISCVState *env, int csrno, 417 target_ulong *val) 418 { 419 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 420 421 if (!env->rdtime_fn) { 422 return RISCV_EXCP_ILLEGAL_INST; 423 } 424 425 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 426 return RISCV_EXCP_NONE; 427 } 428 429 /* Machine constants */ 430 431 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 432 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 433 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 434 435 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 436 VS_MODE_INTERRUPTS; 437 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; 438 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 439 VS_MODE_INTERRUPTS; 440 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 441 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 442 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 443 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 444 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 445 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 446 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 447 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 448 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 449 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 450 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 451 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 452 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 453 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 454 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 455 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 456 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 457 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 458 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 459 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 460 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 461 (1ULL << (RISCV_EXCP_VS_ECALL)) | 462 (1ULL << (RISCV_EXCP_M_ECALL)) | 463 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 464 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 465 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 466 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 467 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 468 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 469 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 470 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 471 static const target_ulong hip_writable_mask = MIP_VSSIP; 472 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 473 static const target_ulong vsip_writable_mask = MIP_VSSIP; 474 475 static const char valid_vm_1_10_32[16] = { 476 [VM_1_10_MBARE] = 1, 477 [VM_1_10_SV32] = 1 478 }; 479 480 static const char valid_vm_1_10_64[16] = { 481 [VM_1_10_MBARE] = 1, 482 [VM_1_10_SV39] = 1, 483 [VM_1_10_SV48] = 1, 484 [VM_1_10_SV57] = 1 485 }; 486 487 /* Machine Information Registers */ 488 static RISCVException read_zero(CPURISCVState *env, int csrno, 489 target_ulong *val) 490 { 491 *val = 0; 492 return RISCV_EXCP_NONE; 493 } 494 495 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 496 target_ulong *val) 497 { 498 *val = env->mhartid; 499 return RISCV_EXCP_NONE; 500 } 501 502 /* Machine Trap Setup */ 503 504 /* We do not store SD explicitly, only compute it on demand. */ 505 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 506 { 507 if ((status & MSTATUS_FS) == MSTATUS_FS || 508 (status & MSTATUS_VS) == MSTATUS_VS || 509 (status & MSTATUS_XS) == MSTATUS_XS) { 510 switch (xl) { 511 case MXL_RV32: 512 return status | MSTATUS32_SD; 513 case MXL_RV64: 514 return status | MSTATUS64_SD; 515 default: 516 g_assert_not_reached(); 517 } 518 } 519 return status; 520 } 521 522 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 523 target_ulong *val) 524 { 525 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 526 return RISCV_EXCP_NONE; 527 } 528 529 static int validate_vm(CPURISCVState *env, target_ulong vm) 530 { 531 if (riscv_cpu_mxl(env) == MXL_RV32) { 532 return valid_vm_1_10_32[vm & 0xf]; 533 } else { 534 return valid_vm_1_10_64[vm & 0xf]; 535 } 536 } 537 538 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 539 target_ulong val) 540 { 541 uint64_t mstatus = env->mstatus; 542 uint64_t mask = 0; 543 544 /* flush tlb on mstatus fields that affect VM */ 545 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 546 MSTATUS_MPRV | MSTATUS_SUM)) { 547 tlb_flush(env_cpu(env)); 548 } 549 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 550 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 551 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 552 MSTATUS_TW | MSTATUS_VS; 553 554 if (riscv_cpu_mxl(env) != MXL_RV32) { 555 /* 556 * RV32: MPV and GVA are not in mstatus. The current plan is to 557 * add them to mstatush. For now, we just don't support it. 558 */ 559 mask |= MSTATUS_MPV | MSTATUS_GVA; 560 } 561 562 mstatus = (mstatus & ~mask) | (val & mask); 563 564 if (riscv_cpu_mxl(env) == MXL_RV64) { 565 /* SXL and UXL fields are for now read only */ 566 mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64); 567 mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64); 568 } 569 env->mstatus = mstatus; 570 571 return RISCV_EXCP_NONE; 572 } 573 574 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 575 target_ulong *val) 576 { 577 *val = env->mstatus >> 32; 578 return RISCV_EXCP_NONE; 579 } 580 581 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 582 target_ulong val) 583 { 584 uint64_t valh = (uint64_t)val << 32; 585 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 586 587 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 588 tlb_flush(env_cpu(env)); 589 } 590 591 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 592 593 return RISCV_EXCP_NONE; 594 } 595 596 static RISCVException read_misa(CPURISCVState *env, int csrno, 597 target_ulong *val) 598 { 599 target_ulong misa; 600 601 switch (env->misa_mxl) { 602 case MXL_RV32: 603 misa = (target_ulong)MXL_RV32 << 30; 604 break; 605 #ifdef TARGET_RISCV64 606 case MXL_RV64: 607 misa = (target_ulong)MXL_RV64 << 62; 608 break; 609 #endif 610 default: 611 g_assert_not_reached(); 612 } 613 614 *val = misa | env->misa_ext; 615 return RISCV_EXCP_NONE; 616 } 617 618 static RISCVException write_misa(CPURISCVState *env, int csrno, 619 target_ulong val) 620 { 621 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 622 /* drop write to misa */ 623 return RISCV_EXCP_NONE; 624 } 625 626 /* 'I' or 'E' must be present */ 627 if (!(val & (RVI | RVE))) { 628 /* It is not, drop write to misa */ 629 return RISCV_EXCP_NONE; 630 } 631 632 /* 'E' excludes all other extensions */ 633 if (val & RVE) { 634 /* when we support 'E' we can do "val = RVE;" however 635 * for now we just drop writes if 'E' is present. 636 */ 637 return RISCV_EXCP_NONE; 638 } 639 640 /* 641 * misa.MXL writes are not supported by QEMU. 642 * Drop writes to those bits. 643 */ 644 645 /* Mask extensions that are not supported by this hart */ 646 val &= env->misa_ext_mask; 647 648 /* Mask extensions that are not supported by QEMU */ 649 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 650 651 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 652 if ((val & RVD) && !(val & RVF)) { 653 val &= ~RVD; 654 } 655 656 /* Suppress 'C' if next instruction is not aligned 657 * TODO: this should check next_pc 658 */ 659 if ((val & RVC) && (GETPC() & ~3) != 0) { 660 val &= ~RVC; 661 } 662 663 /* If nothing changed, do nothing. */ 664 if (val == env->misa_ext) { 665 return RISCV_EXCP_NONE; 666 } 667 668 /* flush translation cache */ 669 tb_flush(env_cpu(env)); 670 env->misa_ext = val; 671 return RISCV_EXCP_NONE; 672 } 673 674 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 675 target_ulong *val) 676 { 677 *val = env->medeleg; 678 return RISCV_EXCP_NONE; 679 } 680 681 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 682 target_ulong val) 683 { 684 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 685 return RISCV_EXCP_NONE; 686 } 687 688 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 689 target_ulong *val) 690 { 691 *val = env->mideleg; 692 return RISCV_EXCP_NONE; 693 } 694 695 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 696 target_ulong val) 697 { 698 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 699 if (riscv_has_ext(env, RVH)) { 700 env->mideleg |= VS_MODE_INTERRUPTS; 701 } 702 return RISCV_EXCP_NONE; 703 } 704 705 static RISCVException read_mie(CPURISCVState *env, int csrno, 706 target_ulong *val) 707 { 708 *val = env->mie; 709 return RISCV_EXCP_NONE; 710 } 711 712 static RISCVException write_mie(CPURISCVState *env, int csrno, 713 target_ulong val) 714 { 715 env->mie = (env->mie & ~all_ints) | (val & all_ints); 716 return RISCV_EXCP_NONE; 717 } 718 719 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 720 target_ulong *val) 721 { 722 *val = env->mtvec; 723 return RISCV_EXCP_NONE; 724 } 725 726 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 727 target_ulong val) 728 { 729 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 730 if ((val & 3) < 2) { 731 env->mtvec = val; 732 } else { 733 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 734 } 735 return RISCV_EXCP_NONE; 736 } 737 738 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 739 target_ulong *val) 740 { 741 *val = env->mcounteren; 742 return RISCV_EXCP_NONE; 743 } 744 745 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 746 target_ulong val) 747 { 748 env->mcounteren = val; 749 return RISCV_EXCP_NONE; 750 } 751 752 /* Machine Trap Handling */ 753 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 754 target_ulong *val) 755 { 756 *val = env->mscratch; 757 return RISCV_EXCP_NONE; 758 } 759 760 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 761 target_ulong val) 762 { 763 env->mscratch = val; 764 return RISCV_EXCP_NONE; 765 } 766 767 static RISCVException read_mepc(CPURISCVState *env, int csrno, 768 target_ulong *val) 769 { 770 *val = env->mepc; 771 return RISCV_EXCP_NONE; 772 } 773 774 static RISCVException write_mepc(CPURISCVState *env, int csrno, 775 target_ulong val) 776 { 777 env->mepc = val; 778 return RISCV_EXCP_NONE; 779 } 780 781 static RISCVException read_mcause(CPURISCVState *env, int csrno, 782 target_ulong *val) 783 { 784 *val = env->mcause; 785 return RISCV_EXCP_NONE; 786 } 787 788 static RISCVException write_mcause(CPURISCVState *env, int csrno, 789 target_ulong val) 790 { 791 env->mcause = val; 792 return RISCV_EXCP_NONE; 793 } 794 795 static RISCVException read_mtval(CPURISCVState *env, int csrno, 796 target_ulong *val) 797 { 798 *val = env->mtval; 799 return RISCV_EXCP_NONE; 800 } 801 802 static RISCVException write_mtval(CPURISCVState *env, int csrno, 803 target_ulong val) 804 { 805 env->mtval = val; 806 return RISCV_EXCP_NONE; 807 } 808 809 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 810 target_ulong *ret_value, 811 target_ulong new_value, target_ulong write_mask) 812 { 813 RISCVCPU *cpu = env_archcpu(env); 814 /* Allow software control of delegable interrupts not claimed by hardware */ 815 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 816 uint32_t old_mip; 817 818 if (mask) { 819 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 820 } else { 821 old_mip = env->mip; 822 } 823 824 if (ret_value) { 825 *ret_value = old_mip; 826 } 827 828 return RISCV_EXCP_NONE; 829 } 830 831 /* Supervisor Trap Setup */ 832 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 833 target_ulong *val) 834 { 835 target_ulong mask = (sstatus_v1_10_mask); 836 837 /* TODO: Use SXL not MXL. */ 838 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 839 return RISCV_EXCP_NONE; 840 } 841 842 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 843 target_ulong val) 844 { 845 target_ulong mask = (sstatus_v1_10_mask); 846 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 847 return write_mstatus(env, CSR_MSTATUS, newval); 848 } 849 850 static RISCVException read_vsie(CPURISCVState *env, int csrno, 851 target_ulong *val) 852 { 853 /* Shift the VS bits to their S bit location in vsie */ 854 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 855 return RISCV_EXCP_NONE; 856 } 857 858 static RISCVException read_sie(CPURISCVState *env, int csrno, 859 target_ulong *val) 860 { 861 if (riscv_cpu_virt_enabled(env)) { 862 read_vsie(env, CSR_VSIE, val); 863 } else { 864 *val = env->mie & env->mideleg; 865 } 866 return RISCV_EXCP_NONE; 867 } 868 869 static RISCVException write_vsie(CPURISCVState *env, int csrno, 870 target_ulong val) 871 { 872 /* Shift the S bits to their VS bit location in mie */ 873 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 874 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 875 return write_mie(env, CSR_MIE, newval); 876 } 877 878 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 879 { 880 if (riscv_cpu_virt_enabled(env)) { 881 write_vsie(env, CSR_VSIE, val); 882 } else { 883 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 884 (val & S_MODE_INTERRUPTS); 885 write_mie(env, CSR_MIE, newval); 886 } 887 888 return RISCV_EXCP_NONE; 889 } 890 891 static RISCVException read_stvec(CPURISCVState *env, int csrno, 892 target_ulong *val) 893 { 894 *val = env->stvec; 895 return RISCV_EXCP_NONE; 896 } 897 898 static RISCVException write_stvec(CPURISCVState *env, int csrno, 899 target_ulong val) 900 { 901 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 902 if ((val & 3) < 2) { 903 env->stvec = val; 904 } else { 905 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 906 } 907 return RISCV_EXCP_NONE; 908 } 909 910 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 911 target_ulong *val) 912 { 913 *val = env->scounteren; 914 return RISCV_EXCP_NONE; 915 } 916 917 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 918 target_ulong val) 919 { 920 env->scounteren = val; 921 return RISCV_EXCP_NONE; 922 } 923 924 /* Supervisor Trap Handling */ 925 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 926 target_ulong *val) 927 { 928 *val = env->sscratch; 929 return RISCV_EXCP_NONE; 930 } 931 932 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 933 target_ulong val) 934 { 935 env->sscratch = val; 936 return RISCV_EXCP_NONE; 937 } 938 939 static RISCVException read_sepc(CPURISCVState *env, int csrno, 940 target_ulong *val) 941 { 942 *val = env->sepc; 943 return RISCV_EXCP_NONE; 944 } 945 946 static RISCVException write_sepc(CPURISCVState *env, int csrno, 947 target_ulong val) 948 { 949 env->sepc = val; 950 return RISCV_EXCP_NONE; 951 } 952 953 static RISCVException read_scause(CPURISCVState *env, int csrno, 954 target_ulong *val) 955 { 956 *val = env->scause; 957 return RISCV_EXCP_NONE; 958 } 959 960 static RISCVException write_scause(CPURISCVState *env, int csrno, 961 target_ulong val) 962 { 963 env->scause = val; 964 return RISCV_EXCP_NONE; 965 } 966 967 static RISCVException read_stval(CPURISCVState *env, int csrno, 968 target_ulong *val) 969 { 970 *val = env->stval; 971 return RISCV_EXCP_NONE; 972 } 973 974 static RISCVException write_stval(CPURISCVState *env, int csrno, 975 target_ulong val) 976 { 977 env->stval = val; 978 return RISCV_EXCP_NONE; 979 } 980 981 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 982 target_ulong *ret_value, 983 target_ulong new_value, target_ulong write_mask) 984 { 985 /* Shift the S bits to their VS bit location in mip */ 986 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 987 (write_mask << 1) & vsip_writable_mask & env->hideleg); 988 989 if (ret_value) { 990 *ret_value &= VS_MODE_INTERRUPTS; 991 /* Shift the VS bits to their S bit location in vsip */ 992 *ret_value >>= 1; 993 } 994 return ret; 995 } 996 997 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 998 target_ulong *ret_value, 999 target_ulong new_value, target_ulong write_mask) 1000 { 1001 int ret; 1002 1003 if (riscv_cpu_virt_enabled(env)) { 1004 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 1005 } else { 1006 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 1007 write_mask & env->mideleg & sip_writable_mask); 1008 } 1009 1010 if (ret_value) { 1011 *ret_value &= env->mideleg; 1012 } 1013 return ret; 1014 } 1015 1016 /* Supervisor Protection and Translation */ 1017 static RISCVException read_satp(CPURISCVState *env, int csrno, 1018 target_ulong *val) 1019 { 1020 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1021 *val = 0; 1022 return RISCV_EXCP_NONE; 1023 } 1024 1025 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1026 return RISCV_EXCP_ILLEGAL_INST; 1027 } else { 1028 *val = env->satp; 1029 } 1030 1031 return RISCV_EXCP_NONE; 1032 } 1033 1034 static RISCVException write_satp(CPURISCVState *env, int csrno, 1035 target_ulong val) 1036 { 1037 target_ulong vm, mask, asid; 1038 1039 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1040 return RISCV_EXCP_NONE; 1041 } 1042 1043 if (riscv_cpu_mxl(env) == MXL_RV32) { 1044 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1045 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1046 asid = (val ^ env->satp) & SATP32_ASID; 1047 } else { 1048 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1049 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1050 asid = (val ^ env->satp) & SATP64_ASID; 1051 } 1052 1053 if (vm && mask) { 1054 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1055 return RISCV_EXCP_ILLEGAL_INST; 1056 } else { 1057 if (asid) { 1058 tlb_flush(env_cpu(env)); 1059 } 1060 env->satp = val; 1061 } 1062 } 1063 return RISCV_EXCP_NONE; 1064 } 1065 1066 /* Hypervisor Extensions */ 1067 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1068 target_ulong *val) 1069 { 1070 *val = env->hstatus; 1071 if (riscv_cpu_mxl(env) != MXL_RV32) { 1072 /* We only support 64-bit VSXL */ 1073 *val = set_field(*val, HSTATUS_VSXL, 2); 1074 } 1075 /* We only support little endian */ 1076 *val = set_field(*val, HSTATUS_VSBE, 0); 1077 return RISCV_EXCP_NONE; 1078 } 1079 1080 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1081 target_ulong val) 1082 { 1083 env->hstatus = val; 1084 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 1085 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1086 } 1087 if (get_field(val, HSTATUS_VSBE) != 0) { 1088 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1089 } 1090 return RISCV_EXCP_NONE; 1091 } 1092 1093 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1094 target_ulong *val) 1095 { 1096 *val = env->hedeleg; 1097 return RISCV_EXCP_NONE; 1098 } 1099 1100 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1101 target_ulong val) 1102 { 1103 env->hedeleg = val & vs_delegable_excps; 1104 return RISCV_EXCP_NONE; 1105 } 1106 1107 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1108 target_ulong *val) 1109 { 1110 *val = env->hideleg; 1111 return RISCV_EXCP_NONE; 1112 } 1113 1114 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1115 target_ulong val) 1116 { 1117 env->hideleg = val & vs_delegable_ints; 1118 return RISCV_EXCP_NONE; 1119 } 1120 1121 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1122 target_ulong *ret_value, 1123 target_ulong new_value, target_ulong write_mask) 1124 { 1125 int ret = rmw_mip(env, 0, ret_value, new_value, 1126 write_mask & hvip_writable_mask); 1127 1128 if (ret_value) { 1129 *ret_value &= hvip_writable_mask; 1130 } 1131 return ret; 1132 } 1133 1134 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1135 target_ulong *ret_value, 1136 target_ulong new_value, target_ulong write_mask) 1137 { 1138 int ret = rmw_mip(env, 0, ret_value, new_value, 1139 write_mask & hip_writable_mask); 1140 1141 if (ret_value) { 1142 *ret_value &= hip_writable_mask; 1143 } 1144 return ret; 1145 } 1146 1147 static RISCVException read_hie(CPURISCVState *env, int csrno, 1148 target_ulong *val) 1149 { 1150 *val = env->mie & VS_MODE_INTERRUPTS; 1151 return RISCV_EXCP_NONE; 1152 } 1153 1154 static RISCVException write_hie(CPURISCVState *env, int csrno, 1155 target_ulong val) 1156 { 1157 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1158 return write_mie(env, CSR_MIE, newval); 1159 } 1160 1161 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1162 target_ulong *val) 1163 { 1164 *val = env->hcounteren; 1165 return RISCV_EXCP_NONE; 1166 } 1167 1168 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1169 target_ulong val) 1170 { 1171 env->hcounteren = val; 1172 return RISCV_EXCP_NONE; 1173 } 1174 1175 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1176 target_ulong val) 1177 { 1178 if (val) { 1179 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1180 } 1181 return RISCV_EXCP_NONE; 1182 } 1183 1184 static RISCVException read_htval(CPURISCVState *env, int csrno, 1185 target_ulong *val) 1186 { 1187 *val = env->htval; 1188 return RISCV_EXCP_NONE; 1189 } 1190 1191 static RISCVException write_htval(CPURISCVState *env, int csrno, 1192 target_ulong val) 1193 { 1194 env->htval = val; 1195 return RISCV_EXCP_NONE; 1196 } 1197 1198 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1199 target_ulong *val) 1200 { 1201 *val = env->htinst; 1202 return RISCV_EXCP_NONE; 1203 } 1204 1205 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1206 target_ulong val) 1207 { 1208 return RISCV_EXCP_NONE; 1209 } 1210 1211 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1212 target_ulong val) 1213 { 1214 if (val) { 1215 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1216 } 1217 return RISCV_EXCP_NONE; 1218 } 1219 1220 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1221 target_ulong *val) 1222 { 1223 *val = env->hgatp; 1224 return RISCV_EXCP_NONE; 1225 } 1226 1227 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1228 target_ulong val) 1229 { 1230 env->hgatp = val; 1231 return RISCV_EXCP_NONE; 1232 } 1233 1234 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1235 target_ulong *val) 1236 { 1237 if (!env->rdtime_fn) { 1238 return RISCV_EXCP_ILLEGAL_INST; 1239 } 1240 1241 *val = env->htimedelta; 1242 return RISCV_EXCP_NONE; 1243 } 1244 1245 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1246 target_ulong val) 1247 { 1248 if (!env->rdtime_fn) { 1249 return RISCV_EXCP_ILLEGAL_INST; 1250 } 1251 1252 if (riscv_cpu_mxl(env) == MXL_RV32) { 1253 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1254 } else { 1255 env->htimedelta = val; 1256 } 1257 return RISCV_EXCP_NONE; 1258 } 1259 1260 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1261 target_ulong *val) 1262 { 1263 if (!env->rdtime_fn) { 1264 return RISCV_EXCP_ILLEGAL_INST; 1265 } 1266 1267 *val = env->htimedelta >> 32; 1268 return RISCV_EXCP_NONE; 1269 } 1270 1271 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1272 target_ulong val) 1273 { 1274 if (!env->rdtime_fn) { 1275 return RISCV_EXCP_ILLEGAL_INST; 1276 } 1277 1278 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1279 return RISCV_EXCP_NONE; 1280 } 1281 1282 /* Virtual CSR Registers */ 1283 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1284 target_ulong *val) 1285 { 1286 *val = env->vsstatus; 1287 return RISCV_EXCP_NONE; 1288 } 1289 1290 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1291 target_ulong val) 1292 { 1293 uint64_t mask = (target_ulong)-1; 1294 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1295 return RISCV_EXCP_NONE; 1296 } 1297 1298 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1299 { 1300 *val = env->vstvec; 1301 return RISCV_EXCP_NONE; 1302 } 1303 1304 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1305 target_ulong val) 1306 { 1307 env->vstvec = val; 1308 return RISCV_EXCP_NONE; 1309 } 1310 1311 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1312 target_ulong *val) 1313 { 1314 *val = env->vsscratch; 1315 return RISCV_EXCP_NONE; 1316 } 1317 1318 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1319 target_ulong val) 1320 { 1321 env->vsscratch = val; 1322 return RISCV_EXCP_NONE; 1323 } 1324 1325 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1326 target_ulong *val) 1327 { 1328 *val = env->vsepc; 1329 return RISCV_EXCP_NONE; 1330 } 1331 1332 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1333 target_ulong val) 1334 { 1335 env->vsepc = val; 1336 return RISCV_EXCP_NONE; 1337 } 1338 1339 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1340 target_ulong *val) 1341 { 1342 *val = env->vscause; 1343 return RISCV_EXCP_NONE; 1344 } 1345 1346 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1347 target_ulong val) 1348 { 1349 env->vscause = val; 1350 return RISCV_EXCP_NONE; 1351 } 1352 1353 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1354 target_ulong *val) 1355 { 1356 *val = env->vstval; 1357 return RISCV_EXCP_NONE; 1358 } 1359 1360 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1361 target_ulong val) 1362 { 1363 env->vstval = val; 1364 return RISCV_EXCP_NONE; 1365 } 1366 1367 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1368 target_ulong *val) 1369 { 1370 *val = env->vsatp; 1371 return RISCV_EXCP_NONE; 1372 } 1373 1374 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1375 target_ulong val) 1376 { 1377 env->vsatp = val; 1378 return RISCV_EXCP_NONE; 1379 } 1380 1381 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1382 target_ulong *val) 1383 { 1384 *val = env->mtval2; 1385 return RISCV_EXCP_NONE; 1386 } 1387 1388 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1389 target_ulong val) 1390 { 1391 env->mtval2 = val; 1392 return RISCV_EXCP_NONE; 1393 } 1394 1395 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1396 target_ulong *val) 1397 { 1398 *val = env->mtinst; 1399 return RISCV_EXCP_NONE; 1400 } 1401 1402 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1403 target_ulong val) 1404 { 1405 env->mtinst = val; 1406 return RISCV_EXCP_NONE; 1407 } 1408 1409 /* Physical Memory Protection */ 1410 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1411 target_ulong *val) 1412 { 1413 *val = mseccfg_csr_read(env); 1414 return RISCV_EXCP_NONE; 1415 } 1416 1417 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1418 target_ulong val) 1419 { 1420 mseccfg_csr_write(env, val); 1421 return RISCV_EXCP_NONE; 1422 } 1423 1424 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1425 target_ulong *val) 1426 { 1427 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1428 return RISCV_EXCP_NONE; 1429 } 1430 1431 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1432 target_ulong val) 1433 { 1434 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1435 return RISCV_EXCP_NONE; 1436 } 1437 1438 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1439 target_ulong *val) 1440 { 1441 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1442 return RISCV_EXCP_NONE; 1443 } 1444 1445 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1446 target_ulong val) 1447 { 1448 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1449 return RISCV_EXCP_NONE; 1450 } 1451 1452 /* 1453 * Functions to access Pointer Masking feature registers 1454 * We have to check if current priv lvl could modify 1455 * csr in given mode 1456 */ 1457 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 1458 { 1459 int csr_priv = get_field(csrno, 0x300); 1460 int pm_current; 1461 1462 /* 1463 * If priv lvls differ that means we're accessing csr from higher priv lvl, 1464 * so allow the access 1465 */ 1466 if (env->priv != csr_priv) { 1467 return false; 1468 } 1469 switch (env->priv) { 1470 case PRV_M: 1471 pm_current = get_field(env->mmte, M_PM_CURRENT); 1472 break; 1473 case PRV_S: 1474 pm_current = get_field(env->mmte, S_PM_CURRENT); 1475 break; 1476 case PRV_U: 1477 pm_current = get_field(env->mmte, U_PM_CURRENT); 1478 break; 1479 default: 1480 g_assert_not_reached(); 1481 } 1482 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 1483 return !pm_current; 1484 } 1485 1486 static RISCVException read_mmte(CPURISCVState *env, int csrno, 1487 target_ulong *val) 1488 { 1489 *val = env->mmte & MMTE_MASK; 1490 return RISCV_EXCP_NONE; 1491 } 1492 1493 static RISCVException write_mmte(CPURISCVState *env, int csrno, 1494 target_ulong val) 1495 { 1496 uint64_t mstatus; 1497 target_ulong wpri_val = val & MMTE_MASK; 1498 1499 if (val != wpri_val) { 1500 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1501 "MMTE: WPRI violation written 0x", val, 1502 "vs expected 0x", wpri_val); 1503 } 1504 /* for machine mode pm.current is hardwired to 1 */ 1505 wpri_val |= MMTE_M_PM_CURRENT; 1506 1507 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 1508 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 1509 env->mmte = wpri_val | PM_EXT_DIRTY; 1510 1511 /* Set XS and SD bits, since PM CSRs are dirty */ 1512 mstatus = env->mstatus | MSTATUS_XS; 1513 write_mstatus(env, csrno, mstatus); 1514 return RISCV_EXCP_NONE; 1515 } 1516 1517 static RISCVException read_smte(CPURISCVState *env, int csrno, 1518 target_ulong *val) 1519 { 1520 *val = env->mmte & SMTE_MASK; 1521 return RISCV_EXCP_NONE; 1522 } 1523 1524 static RISCVException write_smte(CPURISCVState *env, int csrno, 1525 target_ulong val) 1526 { 1527 target_ulong wpri_val = val & SMTE_MASK; 1528 1529 if (val != wpri_val) { 1530 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1531 "SMTE: WPRI violation written 0x", val, 1532 "vs expected 0x", wpri_val); 1533 } 1534 1535 /* if pm.current==0 we can't modify current PM CSRs */ 1536 if (check_pm_current_disabled(env, csrno)) { 1537 return RISCV_EXCP_NONE; 1538 } 1539 1540 wpri_val |= (env->mmte & ~SMTE_MASK); 1541 write_mmte(env, csrno, wpri_val); 1542 return RISCV_EXCP_NONE; 1543 } 1544 1545 static RISCVException read_umte(CPURISCVState *env, int csrno, 1546 target_ulong *val) 1547 { 1548 *val = env->mmte & UMTE_MASK; 1549 return RISCV_EXCP_NONE; 1550 } 1551 1552 static RISCVException write_umte(CPURISCVState *env, int csrno, 1553 target_ulong val) 1554 { 1555 target_ulong wpri_val = val & UMTE_MASK; 1556 1557 if (val != wpri_val) { 1558 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 1559 "UMTE: WPRI violation written 0x", val, 1560 "vs expected 0x", wpri_val); 1561 } 1562 1563 if (check_pm_current_disabled(env, csrno)) { 1564 return RISCV_EXCP_NONE; 1565 } 1566 1567 wpri_val |= (env->mmte & ~UMTE_MASK); 1568 write_mmte(env, csrno, wpri_val); 1569 return RISCV_EXCP_NONE; 1570 } 1571 1572 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 1573 target_ulong *val) 1574 { 1575 *val = env->mpmmask; 1576 return RISCV_EXCP_NONE; 1577 } 1578 1579 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 1580 target_ulong val) 1581 { 1582 uint64_t mstatus; 1583 1584 env->mpmmask = val; 1585 env->mmte |= PM_EXT_DIRTY; 1586 1587 /* Set XS and SD bits, since PM CSRs are dirty */ 1588 mstatus = env->mstatus | MSTATUS_XS; 1589 write_mstatus(env, csrno, mstatus); 1590 return RISCV_EXCP_NONE; 1591 } 1592 1593 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 1594 target_ulong *val) 1595 { 1596 *val = env->spmmask; 1597 return RISCV_EXCP_NONE; 1598 } 1599 1600 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 1601 target_ulong val) 1602 { 1603 uint64_t mstatus; 1604 1605 /* if pm.current==0 we can't modify current PM CSRs */ 1606 if (check_pm_current_disabled(env, csrno)) { 1607 return RISCV_EXCP_NONE; 1608 } 1609 env->spmmask = val; 1610 env->mmte |= PM_EXT_DIRTY; 1611 1612 /* Set XS and SD bits, since PM CSRs are dirty */ 1613 mstatus = env->mstatus | MSTATUS_XS; 1614 write_mstatus(env, csrno, mstatus); 1615 return RISCV_EXCP_NONE; 1616 } 1617 1618 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 1619 target_ulong *val) 1620 { 1621 *val = env->upmmask; 1622 return RISCV_EXCP_NONE; 1623 } 1624 1625 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 1626 target_ulong val) 1627 { 1628 uint64_t mstatus; 1629 1630 /* if pm.current==0 we can't modify current PM CSRs */ 1631 if (check_pm_current_disabled(env, csrno)) { 1632 return RISCV_EXCP_NONE; 1633 } 1634 env->upmmask = val; 1635 env->mmte |= PM_EXT_DIRTY; 1636 1637 /* Set XS and SD bits, since PM CSRs are dirty */ 1638 mstatus = env->mstatus | MSTATUS_XS; 1639 write_mstatus(env, csrno, mstatus); 1640 return RISCV_EXCP_NONE; 1641 } 1642 1643 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 1644 target_ulong *val) 1645 { 1646 *val = env->mpmbase; 1647 return RISCV_EXCP_NONE; 1648 } 1649 1650 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 1651 target_ulong val) 1652 { 1653 uint64_t mstatus; 1654 1655 env->mpmbase = val; 1656 env->mmte |= PM_EXT_DIRTY; 1657 1658 /* Set XS and SD bits, since PM CSRs are dirty */ 1659 mstatus = env->mstatus | MSTATUS_XS; 1660 write_mstatus(env, csrno, mstatus); 1661 return RISCV_EXCP_NONE; 1662 } 1663 1664 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 1665 target_ulong *val) 1666 { 1667 *val = env->spmbase; 1668 return RISCV_EXCP_NONE; 1669 } 1670 1671 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 1672 target_ulong val) 1673 { 1674 uint64_t mstatus; 1675 1676 /* if pm.current==0 we can't modify current PM CSRs */ 1677 if (check_pm_current_disabled(env, csrno)) { 1678 return RISCV_EXCP_NONE; 1679 } 1680 env->spmbase = val; 1681 env->mmte |= PM_EXT_DIRTY; 1682 1683 /* Set XS and SD bits, since PM CSRs are dirty */ 1684 mstatus = env->mstatus | MSTATUS_XS; 1685 write_mstatus(env, csrno, mstatus); 1686 return RISCV_EXCP_NONE; 1687 } 1688 1689 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 1690 target_ulong *val) 1691 { 1692 *val = env->upmbase; 1693 return RISCV_EXCP_NONE; 1694 } 1695 1696 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 1697 target_ulong val) 1698 { 1699 uint64_t mstatus; 1700 1701 /* if pm.current==0 we can't modify current PM CSRs */ 1702 if (check_pm_current_disabled(env, csrno)) { 1703 return RISCV_EXCP_NONE; 1704 } 1705 env->upmbase = val; 1706 env->mmte |= PM_EXT_DIRTY; 1707 1708 /* Set XS and SD bits, since PM CSRs are dirty */ 1709 mstatus = env->mstatus | MSTATUS_XS; 1710 write_mstatus(env, csrno, mstatus); 1711 return RISCV_EXCP_NONE; 1712 } 1713 1714 #endif 1715 1716 /* 1717 * riscv_csrrw - read and/or update control and status register 1718 * 1719 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1720 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1721 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1722 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1723 */ 1724 1725 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1726 target_ulong *ret_value, 1727 target_ulong new_value, target_ulong write_mask) 1728 { 1729 RISCVException ret; 1730 target_ulong old_value; 1731 RISCVCPU *cpu = env_archcpu(env); 1732 int read_only = get_field(csrno, 0xC00) == 3; 1733 1734 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 1735 #if !defined(CONFIG_USER_ONLY) 1736 int effective_priv = env->priv; 1737 1738 if (riscv_has_ext(env, RVH) && 1739 env->priv == PRV_S && 1740 !riscv_cpu_virt_enabled(env)) { 1741 /* 1742 * We are in S mode without virtualisation, therefore we are in HS Mode. 1743 * Add 1 to the effective privledge level to allow us to access the 1744 * Hypervisor CSRs. 1745 */ 1746 effective_priv++; 1747 } 1748 1749 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 1750 return RISCV_EXCP_ILLEGAL_INST; 1751 } 1752 #endif 1753 if (write_mask && read_only) { 1754 return RISCV_EXCP_ILLEGAL_INST; 1755 } 1756 1757 /* ensure the CSR extension is enabled. */ 1758 if (!cpu->cfg.ext_icsr) { 1759 return RISCV_EXCP_ILLEGAL_INST; 1760 } 1761 1762 /* check predicate */ 1763 if (!csr_ops[csrno].predicate) { 1764 return RISCV_EXCP_ILLEGAL_INST; 1765 } 1766 ret = csr_ops[csrno].predicate(env, csrno); 1767 if (ret != RISCV_EXCP_NONE) { 1768 return ret; 1769 } 1770 1771 /* execute combined read/write operation if it exists */ 1772 if (csr_ops[csrno].op) { 1773 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1774 } 1775 1776 /* if no accessor exists then return failure */ 1777 if (!csr_ops[csrno].read) { 1778 return RISCV_EXCP_ILLEGAL_INST; 1779 } 1780 /* read old value */ 1781 ret = csr_ops[csrno].read(env, csrno, &old_value); 1782 if (ret != RISCV_EXCP_NONE) { 1783 return ret; 1784 } 1785 1786 /* write value if writable and write mask set, otherwise drop writes */ 1787 if (write_mask) { 1788 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1789 if (csr_ops[csrno].write) { 1790 ret = csr_ops[csrno].write(env, csrno, new_value); 1791 if (ret != RISCV_EXCP_NONE) { 1792 return ret; 1793 } 1794 } 1795 } 1796 1797 /* return old value */ 1798 if (ret_value) { 1799 *ret_value = old_value; 1800 } 1801 1802 return RISCV_EXCP_NONE; 1803 } 1804 1805 /* 1806 * Debugger support. If not in user mode, set env->debugger before the 1807 * riscv_csrrw call and clear it after the call. 1808 */ 1809 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1810 target_ulong *ret_value, 1811 target_ulong new_value, 1812 target_ulong write_mask) 1813 { 1814 RISCVException ret; 1815 #if !defined(CONFIG_USER_ONLY) 1816 env->debugger = true; 1817 #endif 1818 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1819 #if !defined(CONFIG_USER_ONLY) 1820 env->debugger = false; 1821 #endif 1822 return ret; 1823 } 1824 1825 /* Control and Status Register function table */ 1826 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1827 /* User Floating-Point CSRs */ 1828 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1829 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1830 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1831 /* Vector CSRs */ 1832 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1833 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1834 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1835 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, 1836 [CSR_VL] = { "vl", vs, read_vl }, 1837 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1838 /* User Timers and Counters */ 1839 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1840 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1841 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1842 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1843 1844 /* 1845 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1846 * rdtime callback is not provided by machine/platform emulation. 1847 */ 1848 [CSR_TIME] = { "time", ctr, read_time }, 1849 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1850 1851 #if !defined(CONFIG_USER_ONLY) 1852 /* Machine Timers and Counters */ 1853 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1854 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1855 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1856 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1857 1858 /* Machine Information Registers */ 1859 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1860 [CSR_MARCHID] = { "marchid", any, read_zero }, 1861 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1862 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1863 1864 /* Machine Trap Setup */ 1865 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1866 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1867 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1868 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1869 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1870 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1871 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1872 1873 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1874 1875 /* Machine Trap Handling */ 1876 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1877 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1878 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1879 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1880 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1881 1882 /* Supervisor Trap Setup */ 1883 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1884 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1885 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1886 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1887 1888 /* Supervisor Trap Handling */ 1889 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1890 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1891 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1892 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1893 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1894 1895 /* Supervisor Protection and Translation */ 1896 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1897 1898 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1899 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1900 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1901 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1902 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1903 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1904 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1905 [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie }, 1906 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1907 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1908 [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip }, 1909 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1910 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1911 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1912 1913 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1914 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1915 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1916 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1917 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1918 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1919 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1920 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1921 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1922 1923 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1924 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1925 1926 /* Physical Memory Protection */ 1927 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1928 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1929 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1930 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1931 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1932 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1933 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1934 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1935 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1936 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1937 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1938 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1939 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1940 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1941 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1942 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1943 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1944 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1945 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1946 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1947 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1948 1949 /* User Pointer Masking */ 1950 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 1951 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 1952 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 1953 /* Machine Pointer Masking */ 1954 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 1955 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 1956 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 1957 /* Supervisor Pointer Masking */ 1958 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 1959 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 1960 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 1961 1962 /* Performance Counters */ 1963 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1964 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1965 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1966 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1967 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1968 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1969 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1970 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1971 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1972 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1973 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1974 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1975 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1976 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1977 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1978 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1979 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1980 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1981 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1982 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1983 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1984 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1985 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1986 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1987 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1988 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1989 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1990 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1991 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1992 1993 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1994 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1995 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1996 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1997 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1998 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1999 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 2000 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 2001 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 2002 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 2003 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 2004 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 2005 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 2006 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 2007 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 2008 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 2009 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 2010 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 2011 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 2012 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 2013 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 2014 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 2015 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 2016 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 2017 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 2018 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 2019 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 2020 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 2021 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 2022 2023 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 2024 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 2025 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 2026 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 2027 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 2028 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 2029 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 2030 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 2031 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 2032 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 2033 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 2034 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 2035 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 2036 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 2037 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 2038 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 2039 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 2040 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 2041 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 2042 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 2043 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 2044 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 2045 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 2046 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 2047 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 2048 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 2049 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 2050 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 2051 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 2052 2053 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 2054 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 2055 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 2056 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 2057 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 2058 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 2059 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 2060 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 2061 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 2062 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 2063 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 2064 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 2065 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 2066 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 2067 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 2068 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 2069 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 2070 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 2071 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 2072 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 2073 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 2074 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 2075 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 2076 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 2077 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 2078 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 2079 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 2080 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 2081 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 2082 2083 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 2084 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 2085 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 2086 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 2087 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 2088 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 2089 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 2090 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 2091 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 2092 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 2093 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 2094 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 2095 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 2096 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 2097 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 2098 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 2099 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 2100 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 2101 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 2102 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 2103 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 2104 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 2105 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 2106 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 2107 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 2108 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 2109 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 2110 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 2111 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 2112 #endif /* !CONFIG_USER_ONLY */ 2113 }; 2114