1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qemu/main-loop.h" 27 #include "exec/exec-all.h" 28 #include "sysemu/cpu-timers.h" 29 #include "qemu/guest-random.h" 30 #include "qapi/error.h" 31 32 /* CSR function table public API */ 33 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 34 { 35 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 36 } 37 38 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 39 { 40 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 41 } 42 43 /* Predicates */ 44 static RISCVException fs(CPURISCVState *env, int csrno) 45 { 46 #if !defined(CONFIG_USER_ONLY) 47 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 48 !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 49 return RISCV_EXCP_ILLEGAL_INST; 50 } 51 #endif 52 return RISCV_EXCP_NONE; 53 } 54 55 static RISCVException vs(CPURISCVState *env, int csrno) 56 { 57 CPUState *cs = env_cpu(env); 58 RISCVCPU *cpu = RISCV_CPU(cs); 59 60 if (env->misa_ext & RVV || 61 cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 62 #if !defined(CONFIG_USER_ONLY) 63 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 64 return RISCV_EXCP_ILLEGAL_INST; 65 } 66 #endif 67 return RISCV_EXCP_NONE; 68 } 69 return RISCV_EXCP_ILLEGAL_INST; 70 } 71 72 static RISCVException ctr(CPURISCVState *env, int csrno) 73 { 74 #if !defined(CONFIG_USER_ONLY) 75 CPUState *cs = env_cpu(env); 76 RISCVCPU *cpu = RISCV_CPU(cs); 77 int ctr_index; 78 int base_csrno = CSR_HPMCOUNTER3; 79 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; 80 81 if (rv32 && csrno >= CSR_CYCLEH) { 82 /* Offset for RV32 hpmcounternh counters */ 83 base_csrno += 0x80; 84 } 85 ctr_index = csrno - base_csrno; 86 87 if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num)) { 88 /* No counter is enabled in PMU or the counter is out of range */ 89 return RISCV_EXCP_ILLEGAL_INST; 90 } 91 92 if (env->priv == PRV_S) { 93 switch (csrno) { 94 case CSR_CYCLE: 95 if (!get_field(env->mcounteren, COUNTEREN_CY)) { 96 return RISCV_EXCP_ILLEGAL_INST; 97 } 98 break; 99 case CSR_TIME: 100 if (!get_field(env->mcounteren, COUNTEREN_TM)) { 101 return RISCV_EXCP_ILLEGAL_INST; 102 } 103 break; 104 case CSR_INSTRET: 105 if (!get_field(env->mcounteren, COUNTEREN_IR)) { 106 return RISCV_EXCP_ILLEGAL_INST; 107 } 108 break; 109 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 110 ctr_index = csrno - CSR_CYCLE; 111 if (!get_field(env->mcounteren, 1 << ctr_index)) { 112 return RISCV_EXCP_ILLEGAL_INST; 113 } 114 break; 115 } 116 if (rv32) { 117 switch (csrno) { 118 case CSR_CYCLEH: 119 if (!get_field(env->mcounteren, COUNTEREN_CY)) { 120 return RISCV_EXCP_ILLEGAL_INST; 121 } 122 break; 123 case CSR_TIMEH: 124 if (!get_field(env->mcounteren, COUNTEREN_TM)) { 125 return RISCV_EXCP_ILLEGAL_INST; 126 } 127 break; 128 case CSR_INSTRETH: 129 if (!get_field(env->mcounteren, COUNTEREN_IR)) { 130 return RISCV_EXCP_ILLEGAL_INST; 131 } 132 break; 133 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 134 ctr_index = csrno - CSR_CYCLEH; 135 if (!get_field(env->mcounteren, 1 << ctr_index)) { 136 return RISCV_EXCP_ILLEGAL_INST; 137 } 138 break; 139 } 140 } 141 } 142 143 if (riscv_cpu_virt_enabled(env)) { 144 switch (csrno) { 145 case CSR_CYCLE: 146 if (!get_field(env->hcounteren, COUNTEREN_CY) && 147 get_field(env->mcounteren, COUNTEREN_CY)) { 148 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 149 } 150 break; 151 case CSR_TIME: 152 if (!get_field(env->hcounteren, COUNTEREN_TM) && 153 get_field(env->mcounteren, COUNTEREN_TM)) { 154 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 155 } 156 break; 157 case CSR_INSTRET: 158 if (!get_field(env->hcounteren, COUNTEREN_IR) && 159 get_field(env->mcounteren, COUNTEREN_IR)) { 160 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 161 } 162 break; 163 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 164 ctr_index = csrno - CSR_CYCLE; 165 if (!get_field(env->hcounteren, 1 << ctr_index) && 166 get_field(env->mcounteren, 1 << ctr_index)) { 167 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 168 } 169 break; 170 } 171 if (rv32) { 172 switch (csrno) { 173 case CSR_CYCLEH: 174 if (!get_field(env->hcounteren, COUNTEREN_CY) && 175 get_field(env->mcounteren, COUNTEREN_CY)) { 176 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 177 } 178 break; 179 case CSR_TIMEH: 180 if (!get_field(env->hcounteren, COUNTEREN_TM) && 181 get_field(env->mcounteren, COUNTEREN_TM)) { 182 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 183 } 184 break; 185 case CSR_INSTRETH: 186 if (!get_field(env->hcounteren, COUNTEREN_IR) && 187 get_field(env->mcounteren, COUNTEREN_IR)) { 188 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 189 } 190 break; 191 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 192 ctr_index = csrno - CSR_CYCLEH; 193 if (!get_field(env->hcounteren, 1 << ctr_index) && 194 get_field(env->mcounteren, 1 << ctr_index)) { 195 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 196 } 197 break; 198 } 199 } 200 } 201 #endif 202 return RISCV_EXCP_NONE; 203 } 204 205 static RISCVException ctr32(CPURISCVState *env, int csrno) 206 { 207 if (riscv_cpu_mxl(env) != MXL_RV32) { 208 return RISCV_EXCP_ILLEGAL_INST; 209 } 210 211 return ctr(env, csrno); 212 } 213 214 #if !defined(CONFIG_USER_ONLY) 215 static RISCVException mctr(CPURISCVState *env, int csrno) 216 { 217 CPUState *cs = env_cpu(env); 218 RISCVCPU *cpu = RISCV_CPU(cs); 219 int ctr_index; 220 int base_csrno = CSR_MHPMCOUNTER3; 221 222 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { 223 /* Offset for RV32 mhpmcounternh counters */ 224 base_csrno += 0x80; 225 } 226 ctr_index = csrno - base_csrno; 227 if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) { 228 /* The PMU is not enabled or counter is out of range*/ 229 return RISCV_EXCP_ILLEGAL_INST; 230 } 231 232 return RISCV_EXCP_NONE; 233 } 234 235 static RISCVException mctr32(CPURISCVState *env, int csrno) 236 { 237 if (riscv_cpu_mxl(env) != MXL_RV32) { 238 return RISCV_EXCP_ILLEGAL_INST; 239 } 240 241 return mctr(env, csrno); 242 } 243 244 static RISCVException any(CPURISCVState *env, int csrno) 245 { 246 return RISCV_EXCP_NONE; 247 } 248 249 static RISCVException any32(CPURISCVState *env, int csrno) 250 { 251 if (riscv_cpu_mxl(env) != MXL_RV32) { 252 return RISCV_EXCP_ILLEGAL_INST; 253 } 254 255 return any(env, csrno); 256 257 } 258 259 static int aia_any(CPURISCVState *env, int csrno) 260 { 261 RISCVCPU *cpu = env_archcpu(env); 262 263 if (!cpu->cfg.ext_smaia) { 264 return RISCV_EXCP_ILLEGAL_INST; 265 } 266 267 return any(env, csrno); 268 } 269 270 static int aia_any32(CPURISCVState *env, int csrno) 271 { 272 RISCVCPU *cpu = env_archcpu(env); 273 274 if (!cpu->cfg.ext_smaia) { 275 return RISCV_EXCP_ILLEGAL_INST; 276 } 277 278 return any32(env, csrno); 279 } 280 281 static RISCVException smode(CPURISCVState *env, int csrno) 282 { 283 if (riscv_has_ext(env, RVS)) { 284 return RISCV_EXCP_NONE; 285 } 286 287 return RISCV_EXCP_ILLEGAL_INST; 288 } 289 290 static int smode32(CPURISCVState *env, int csrno) 291 { 292 if (riscv_cpu_mxl(env) != MXL_RV32) { 293 return RISCV_EXCP_ILLEGAL_INST; 294 } 295 296 return smode(env, csrno); 297 } 298 299 static int aia_smode(CPURISCVState *env, int csrno) 300 { 301 RISCVCPU *cpu = env_archcpu(env); 302 303 if (!cpu->cfg.ext_ssaia) { 304 return RISCV_EXCP_ILLEGAL_INST; 305 } 306 307 return smode(env, csrno); 308 } 309 310 static int aia_smode32(CPURISCVState *env, int csrno) 311 { 312 RISCVCPU *cpu = env_archcpu(env); 313 314 if (!cpu->cfg.ext_ssaia) { 315 return RISCV_EXCP_ILLEGAL_INST; 316 } 317 318 return smode32(env, csrno); 319 } 320 321 static RISCVException hmode(CPURISCVState *env, int csrno) 322 { 323 if (riscv_has_ext(env, RVH)) { 324 return RISCV_EXCP_NONE; 325 } 326 327 return RISCV_EXCP_ILLEGAL_INST; 328 } 329 330 static RISCVException hmode32(CPURISCVState *env, int csrno) 331 { 332 if (riscv_cpu_mxl(env) != MXL_RV32) { 333 return RISCV_EXCP_ILLEGAL_INST; 334 } 335 336 return hmode(env, csrno); 337 338 } 339 340 static RISCVException umode(CPURISCVState *env, int csrno) 341 { 342 if (riscv_has_ext(env, RVU)) { 343 return RISCV_EXCP_NONE; 344 } 345 346 return RISCV_EXCP_ILLEGAL_INST; 347 } 348 349 static RISCVException umode32(CPURISCVState *env, int csrno) 350 { 351 if (riscv_cpu_mxl(env) != MXL_RV32) { 352 return RISCV_EXCP_ILLEGAL_INST; 353 } 354 355 return umode(env, csrno); 356 } 357 358 /* Checks if PointerMasking registers could be accessed */ 359 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 360 { 361 /* Check if j-ext is present */ 362 if (riscv_has_ext(env, RVJ)) { 363 return RISCV_EXCP_NONE; 364 } 365 return RISCV_EXCP_ILLEGAL_INST; 366 } 367 368 static int aia_hmode(CPURISCVState *env, int csrno) 369 { 370 RISCVCPU *cpu = env_archcpu(env); 371 372 if (!cpu->cfg.ext_ssaia) { 373 return RISCV_EXCP_ILLEGAL_INST; 374 } 375 376 return hmode(env, csrno); 377 } 378 379 static int aia_hmode32(CPURISCVState *env, int csrno) 380 { 381 RISCVCPU *cpu = env_archcpu(env); 382 383 if (!cpu->cfg.ext_ssaia) { 384 return RISCV_EXCP_ILLEGAL_INST; 385 } 386 387 return hmode32(env, csrno); 388 } 389 390 static RISCVException pmp(CPURISCVState *env, int csrno) 391 { 392 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 393 return RISCV_EXCP_NONE; 394 } 395 396 return RISCV_EXCP_ILLEGAL_INST; 397 } 398 399 static RISCVException epmp(CPURISCVState *env, int csrno) 400 { 401 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 402 return RISCV_EXCP_NONE; 403 } 404 405 return RISCV_EXCP_ILLEGAL_INST; 406 } 407 408 static RISCVException debug(CPURISCVState *env, int csrno) 409 { 410 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 411 return RISCV_EXCP_NONE; 412 } 413 414 return RISCV_EXCP_ILLEGAL_INST; 415 } 416 #endif 417 418 static RISCVException seed(CPURISCVState *env, int csrno) 419 { 420 RISCVCPU *cpu = env_archcpu(env); 421 422 if (!cpu->cfg.ext_zkr) { 423 return RISCV_EXCP_ILLEGAL_INST; 424 } 425 426 #if !defined(CONFIG_USER_ONLY) 427 /* 428 * With a CSR read-write instruction: 429 * 1) The seed CSR is always available in machine mode as normal. 430 * 2) Attempted access to seed from virtual modes VS and VU always raises 431 * an exception(virtual instruction exception only if mseccfg.sseed=1). 432 * 3) Without the corresponding access control bit set to 1, any attempted 433 * access to seed from U, S or HS modes will raise an illegal instruction 434 * exception. 435 */ 436 if (env->priv == PRV_M) { 437 return RISCV_EXCP_NONE; 438 } else if (riscv_cpu_virt_enabled(env)) { 439 if (env->mseccfg & MSECCFG_SSEED) { 440 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 441 } else { 442 return RISCV_EXCP_ILLEGAL_INST; 443 } 444 } else { 445 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { 446 return RISCV_EXCP_NONE; 447 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { 448 return RISCV_EXCP_NONE; 449 } else { 450 return RISCV_EXCP_ILLEGAL_INST; 451 } 452 } 453 #else 454 return RISCV_EXCP_NONE; 455 #endif 456 } 457 458 /* User Floating-Point CSRs */ 459 static RISCVException read_fflags(CPURISCVState *env, int csrno, 460 target_ulong *val) 461 { 462 *val = riscv_cpu_get_fflags(env); 463 return RISCV_EXCP_NONE; 464 } 465 466 static RISCVException write_fflags(CPURISCVState *env, int csrno, 467 target_ulong val) 468 { 469 #if !defined(CONFIG_USER_ONLY) 470 if (riscv_has_ext(env, RVF)) { 471 env->mstatus |= MSTATUS_FS; 472 } 473 #endif 474 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 475 return RISCV_EXCP_NONE; 476 } 477 478 static RISCVException read_frm(CPURISCVState *env, int csrno, 479 target_ulong *val) 480 { 481 *val = env->frm; 482 return RISCV_EXCP_NONE; 483 } 484 485 static RISCVException write_frm(CPURISCVState *env, int csrno, 486 target_ulong val) 487 { 488 #if !defined(CONFIG_USER_ONLY) 489 if (riscv_has_ext(env, RVF)) { 490 env->mstatus |= MSTATUS_FS; 491 } 492 #endif 493 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 494 return RISCV_EXCP_NONE; 495 } 496 497 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 498 target_ulong *val) 499 { 500 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 501 | (env->frm << FSR_RD_SHIFT); 502 return RISCV_EXCP_NONE; 503 } 504 505 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 506 target_ulong val) 507 { 508 #if !defined(CONFIG_USER_ONLY) 509 if (riscv_has_ext(env, RVF)) { 510 env->mstatus |= MSTATUS_FS; 511 } 512 #endif 513 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 514 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 515 return RISCV_EXCP_NONE; 516 } 517 518 static RISCVException read_vtype(CPURISCVState *env, int csrno, 519 target_ulong *val) 520 { 521 uint64_t vill; 522 switch (env->xl) { 523 case MXL_RV32: 524 vill = (uint32_t)env->vill << 31; 525 break; 526 case MXL_RV64: 527 vill = (uint64_t)env->vill << 63; 528 break; 529 default: 530 g_assert_not_reached(); 531 } 532 *val = (target_ulong)vill | env->vtype; 533 return RISCV_EXCP_NONE; 534 } 535 536 static RISCVException read_vl(CPURISCVState *env, int csrno, 537 target_ulong *val) 538 { 539 *val = env->vl; 540 return RISCV_EXCP_NONE; 541 } 542 543 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 544 { 545 *val = env_archcpu(env)->cfg.vlen >> 3; 546 return RISCV_EXCP_NONE; 547 } 548 549 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 550 target_ulong *val) 551 { 552 *val = env->vxrm; 553 return RISCV_EXCP_NONE; 554 } 555 556 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 557 target_ulong val) 558 { 559 #if !defined(CONFIG_USER_ONLY) 560 env->mstatus |= MSTATUS_VS; 561 #endif 562 env->vxrm = val; 563 return RISCV_EXCP_NONE; 564 } 565 566 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 567 target_ulong *val) 568 { 569 *val = env->vxsat; 570 return RISCV_EXCP_NONE; 571 } 572 573 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 574 target_ulong val) 575 { 576 #if !defined(CONFIG_USER_ONLY) 577 env->mstatus |= MSTATUS_VS; 578 #endif 579 env->vxsat = val; 580 return RISCV_EXCP_NONE; 581 } 582 583 static RISCVException read_vstart(CPURISCVState *env, int csrno, 584 target_ulong *val) 585 { 586 *val = env->vstart; 587 return RISCV_EXCP_NONE; 588 } 589 590 static RISCVException write_vstart(CPURISCVState *env, int csrno, 591 target_ulong val) 592 { 593 #if !defined(CONFIG_USER_ONLY) 594 env->mstatus |= MSTATUS_VS; 595 #endif 596 /* 597 * The vstart CSR is defined to have only enough writable bits 598 * to hold the largest element index, i.e. lg2(VLEN) bits. 599 */ 600 env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); 601 return RISCV_EXCP_NONE; 602 } 603 604 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 605 { 606 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 607 return RISCV_EXCP_NONE; 608 } 609 610 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 611 { 612 #if !defined(CONFIG_USER_ONLY) 613 env->mstatus |= MSTATUS_VS; 614 #endif 615 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 616 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 617 return RISCV_EXCP_NONE; 618 } 619 620 /* User Timers and Counters */ 621 static target_ulong get_ticks(bool shift) 622 { 623 int64_t val; 624 target_ulong result; 625 626 #if !defined(CONFIG_USER_ONLY) 627 if (icount_enabled()) { 628 val = icount_get(); 629 } else { 630 val = cpu_get_host_ticks(); 631 } 632 #else 633 val = cpu_get_host_ticks(); 634 #endif 635 636 if (shift) { 637 result = val >> 32; 638 } else { 639 result = val; 640 } 641 642 return result; 643 } 644 645 #if defined(CONFIG_USER_ONLY) 646 static RISCVException read_time(CPURISCVState *env, int csrno, 647 target_ulong *val) 648 { 649 *val = cpu_get_host_ticks(); 650 return RISCV_EXCP_NONE; 651 } 652 653 static RISCVException read_timeh(CPURISCVState *env, int csrno, 654 target_ulong *val) 655 { 656 *val = cpu_get_host_ticks() >> 32; 657 return RISCV_EXCP_NONE; 658 } 659 660 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) 661 { 662 *val = get_ticks(false); 663 return RISCV_EXCP_NONE; 664 } 665 666 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) 667 { 668 *val = get_ticks(true); 669 return RISCV_EXCP_NONE; 670 } 671 672 #else /* CONFIG_USER_ONLY */ 673 674 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) 675 { 676 int evt_index = csrno - CSR_MCOUNTINHIBIT; 677 678 *val = env->mhpmevent_val[evt_index]; 679 680 return RISCV_EXCP_NONE; 681 } 682 683 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) 684 { 685 int evt_index = csrno - CSR_MCOUNTINHIBIT; 686 687 env->mhpmevent_val[evt_index] = val; 688 689 return RISCV_EXCP_NONE; 690 } 691 692 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) 693 { 694 int ctr_idx = csrno - CSR_MCYCLE; 695 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 696 697 counter->mhpmcounter_val = val; 698 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 699 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 700 counter->mhpmcounter_prev = get_ticks(false); 701 } else { 702 /* Other counters can keep incrementing from the given value */ 703 counter->mhpmcounter_prev = val; 704 } 705 706 return RISCV_EXCP_NONE; 707 } 708 709 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val) 710 { 711 int ctr_idx = csrno - CSR_MCYCLEH; 712 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 713 714 counter->mhpmcounterh_val = val; 715 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 716 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 717 counter->mhpmcounterh_prev = get_ticks(true); 718 } else { 719 counter->mhpmcounterh_prev = val; 720 } 721 722 return RISCV_EXCP_NONE; 723 } 724 725 static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, 726 bool upper_half, uint32_t ctr_idx) 727 { 728 PMUCTRState counter = env->pmu_ctrs[ctr_idx]; 729 target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev : 730 counter.mhpmcounter_prev; 731 target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val : 732 counter.mhpmcounter_val; 733 734 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { 735 /** 736 * Counter should not increment if inhibit bit is set. We can't really 737 * stop the icount counting. Just return the counter value written by 738 * the supervisor to indicate that counter was not incremented. 739 */ 740 if (!counter.started) { 741 *val = ctr_val; 742 return RISCV_EXCP_NONE; 743 } else { 744 /* Mark that the counter has been stopped */ 745 counter.started = false; 746 } 747 } 748 749 /** 750 * The kernel computes the perf delta by subtracting the current value from 751 * the value it initialized previously (ctr_val). 752 */ 753 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 754 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 755 *val = get_ticks(upper_half) - ctr_prev + ctr_val; 756 } else { 757 *val = ctr_val; 758 } 759 760 return RISCV_EXCP_NONE; 761 } 762 763 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) 764 { 765 uint16_t ctr_index; 766 767 if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) { 768 ctr_index = csrno - CSR_MCYCLE; 769 } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) { 770 ctr_index = csrno - CSR_CYCLE; 771 } else { 772 return RISCV_EXCP_ILLEGAL_INST; 773 } 774 775 return riscv_pmu_read_ctr(env, val, false, ctr_index); 776 } 777 778 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) 779 { 780 uint16_t ctr_index; 781 782 if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) { 783 ctr_index = csrno - CSR_MCYCLEH; 784 } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) { 785 ctr_index = csrno - CSR_CYCLEH; 786 } else { 787 return RISCV_EXCP_ILLEGAL_INST; 788 } 789 790 return riscv_pmu_read_ctr(env, val, true, ctr_index); 791 } 792 793 static RISCVException read_time(CPURISCVState *env, int csrno, 794 target_ulong *val) 795 { 796 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 797 798 if (!env->rdtime_fn) { 799 return RISCV_EXCP_ILLEGAL_INST; 800 } 801 802 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 803 return RISCV_EXCP_NONE; 804 } 805 806 static RISCVException read_timeh(CPURISCVState *env, int csrno, 807 target_ulong *val) 808 { 809 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 810 811 if (!env->rdtime_fn) { 812 return RISCV_EXCP_ILLEGAL_INST; 813 } 814 815 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 816 return RISCV_EXCP_NONE; 817 } 818 819 static RISCVException sstc(CPURISCVState *env, int csrno) 820 { 821 CPUState *cs = env_cpu(env); 822 RISCVCPU *cpu = RISCV_CPU(cs); 823 824 if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { 825 return RISCV_EXCP_ILLEGAL_INST; 826 } 827 828 if (env->priv == PRV_M) { 829 return RISCV_EXCP_NONE; 830 } 831 832 /* 833 * No need of separate function for rv32 as menvcfg stores both menvcfg 834 * menvcfgh for RV32. 835 */ 836 if (!(get_field(env->mcounteren, COUNTEREN_TM) && 837 get_field(env->menvcfg, MENVCFG_STCE))) { 838 return RISCV_EXCP_ILLEGAL_INST; 839 } 840 841 return smode(env, csrno); 842 } 843 844 static RISCVException sstc_32(CPURISCVState *env, int csrno) 845 { 846 if (riscv_cpu_mxl(env) != MXL_RV32) { 847 return RISCV_EXCP_ILLEGAL_INST; 848 } 849 850 return sstc(env, csrno); 851 } 852 853 static RISCVException read_stimecmp(CPURISCVState *env, int csrno, 854 target_ulong *val) 855 { 856 *val = env->stimecmp; 857 return RISCV_EXCP_NONE; 858 } 859 860 static RISCVException read_stimecmph(CPURISCVState *env, int csrno, 861 target_ulong *val) 862 { 863 *val = env->stimecmp >> 32; 864 return RISCV_EXCP_NONE; 865 } 866 867 static RISCVException write_stimecmp(CPURISCVState *env, int csrno, 868 target_ulong val) 869 { 870 RISCVCPU *cpu = env_archcpu(env); 871 872 if (riscv_cpu_mxl(env) == MXL_RV32) { 873 env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val); 874 } else { 875 env->stimecmp = val; 876 } 877 878 riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP); 879 880 return RISCV_EXCP_NONE; 881 } 882 883 static RISCVException write_stimecmph(CPURISCVState *env, int csrno, 884 target_ulong val) 885 { 886 RISCVCPU *cpu = env_archcpu(env); 887 888 env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val); 889 riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP); 890 891 return RISCV_EXCP_NONE; 892 } 893 894 /* Machine constants */ 895 896 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 897 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 898 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 899 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 900 901 #define VSTOPI_NUM_SRCS 5 902 903 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | 904 VS_MODE_INTERRUPTS; 905 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; 906 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 907 HS_MODE_INTERRUPTS; 908 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 909 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 910 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 911 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 912 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 913 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 914 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 915 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 916 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 917 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 918 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 919 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 920 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 921 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 922 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 923 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 924 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 925 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 926 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 927 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 928 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 929 (1ULL << (RISCV_EXCP_VS_ECALL)) | 930 (1ULL << (RISCV_EXCP_M_ECALL)) | 931 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 932 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 933 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 934 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 935 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 936 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 937 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 938 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 939 static const target_ulong hip_writable_mask = MIP_VSSIP; 940 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 941 static const target_ulong vsip_writable_mask = MIP_VSSIP; 942 943 static const char valid_vm_1_10_32[16] = { 944 [VM_1_10_MBARE] = 1, 945 [VM_1_10_SV32] = 1 946 }; 947 948 static const char valid_vm_1_10_64[16] = { 949 [VM_1_10_MBARE] = 1, 950 [VM_1_10_SV39] = 1, 951 [VM_1_10_SV48] = 1, 952 [VM_1_10_SV57] = 1 953 }; 954 955 /* Machine Information Registers */ 956 static RISCVException read_zero(CPURISCVState *env, int csrno, 957 target_ulong *val) 958 { 959 *val = 0; 960 return RISCV_EXCP_NONE; 961 } 962 963 static RISCVException write_ignore(CPURISCVState *env, int csrno, 964 target_ulong val) 965 { 966 return RISCV_EXCP_NONE; 967 } 968 969 static RISCVException read_mvendorid(CPURISCVState *env, int csrno, 970 target_ulong *val) 971 { 972 CPUState *cs = env_cpu(env); 973 RISCVCPU *cpu = RISCV_CPU(cs); 974 975 *val = cpu->cfg.mvendorid; 976 return RISCV_EXCP_NONE; 977 } 978 979 static RISCVException read_marchid(CPURISCVState *env, int csrno, 980 target_ulong *val) 981 { 982 CPUState *cs = env_cpu(env); 983 RISCVCPU *cpu = RISCV_CPU(cs); 984 985 *val = cpu->cfg.marchid; 986 return RISCV_EXCP_NONE; 987 } 988 989 static RISCVException read_mimpid(CPURISCVState *env, int csrno, 990 target_ulong *val) 991 { 992 CPUState *cs = env_cpu(env); 993 RISCVCPU *cpu = RISCV_CPU(cs); 994 995 *val = cpu->cfg.mimpid; 996 return RISCV_EXCP_NONE; 997 } 998 999 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 1000 target_ulong *val) 1001 { 1002 *val = env->mhartid; 1003 return RISCV_EXCP_NONE; 1004 } 1005 1006 /* Machine Trap Setup */ 1007 1008 /* We do not store SD explicitly, only compute it on demand. */ 1009 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 1010 { 1011 if ((status & MSTATUS_FS) == MSTATUS_FS || 1012 (status & MSTATUS_VS) == MSTATUS_VS || 1013 (status & MSTATUS_XS) == MSTATUS_XS) { 1014 switch (xl) { 1015 case MXL_RV32: 1016 return status | MSTATUS32_SD; 1017 case MXL_RV64: 1018 return status | MSTATUS64_SD; 1019 case MXL_RV128: 1020 return MSTATUSH128_SD; 1021 default: 1022 g_assert_not_reached(); 1023 } 1024 } 1025 return status; 1026 } 1027 1028 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 1029 target_ulong *val) 1030 { 1031 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 1032 return RISCV_EXCP_NONE; 1033 } 1034 1035 static int validate_vm(CPURISCVState *env, target_ulong vm) 1036 { 1037 if (riscv_cpu_mxl(env) == MXL_RV32) { 1038 return valid_vm_1_10_32[vm & 0xf]; 1039 } else { 1040 return valid_vm_1_10_64[vm & 0xf]; 1041 } 1042 } 1043 1044 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 1045 target_ulong val) 1046 { 1047 uint64_t mstatus = env->mstatus; 1048 uint64_t mask = 0; 1049 RISCVMXL xl = riscv_cpu_mxl(env); 1050 1051 /* flush tlb on mstatus fields that affect VM */ 1052 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 1053 MSTATUS_MPRV | MSTATUS_SUM)) { 1054 tlb_flush(env_cpu(env)); 1055 } 1056 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 1057 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 1058 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 1059 MSTATUS_TW | MSTATUS_VS; 1060 1061 if (riscv_has_ext(env, RVF)) { 1062 mask |= MSTATUS_FS; 1063 } 1064 1065 if (xl != MXL_RV32 || env->debugger) { 1066 /* 1067 * RV32: MPV and GVA are not in mstatus. The current plan is to 1068 * add them to mstatush. For now, we just don't support it. 1069 */ 1070 mask |= MSTATUS_MPV | MSTATUS_GVA; 1071 if ((val & MSTATUS64_UXL) != 0) { 1072 mask |= MSTATUS64_UXL; 1073 } 1074 } 1075 1076 mstatus = (mstatus & ~mask) | (val & mask); 1077 1078 if (xl > MXL_RV32) { 1079 /* SXL field is for now read only */ 1080 mstatus = set_field(mstatus, MSTATUS64_SXL, xl); 1081 } 1082 env->mstatus = mstatus; 1083 env->xl = cpu_recompute_xl(env); 1084 1085 return RISCV_EXCP_NONE; 1086 } 1087 1088 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 1089 target_ulong *val) 1090 { 1091 *val = env->mstatus >> 32; 1092 return RISCV_EXCP_NONE; 1093 } 1094 1095 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 1096 target_ulong val) 1097 { 1098 uint64_t valh = (uint64_t)val << 32; 1099 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 1100 1101 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 1102 tlb_flush(env_cpu(env)); 1103 } 1104 1105 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 1106 1107 return RISCV_EXCP_NONE; 1108 } 1109 1110 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 1111 Int128 *val) 1112 { 1113 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); 1114 return RISCV_EXCP_NONE; 1115 } 1116 1117 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 1118 Int128 *val) 1119 { 1120 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 1121 return RISCV_EXCP_NONE; 1122 } 1123 1124 static RISCVException read_misa(CPURISCVState *env, int csrno, 1125 target_ulong *val) 1126 { 1127 target_ulong misa; 1128 1129 switch (env->misa_mxl) { 1130 case MXL_RV32: 1131 misa = (target_ulong)MXL_RV32 << 30; 1132 break; 1133 #ifdef TARGET_RISCV64 1134 case MXL_RV64: 1135 misa = (target_ulong)MXL_RV64 << 62; 1136 break; 1137 #endif 1138 default: 1139 g_assert_not_reached(); 1140 } 1141 1142 *val = misa | env->misa_ext; 1143 return RISCV_EXCP_NONE; 1144 } 1145 1146 static RISCVException write_misa(CPURISCVState *env, int csrno, 1147 target_ulong val) 1148 { 1149 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 1150 /* drop write to misa */ 1151 return RISCV_EXCP_NONE; 1152 } 1153 1154 /* 'I' or 'E' must be present */ 1155 if (!(val & (RVI | RVE))) { 1156 /* It is not, drop write to misa */ 1157 return RISCV_EXCP_NONE; 1158 } 1159 1160 /* 'E' excludes all other extensions */ 1161 if (val & RVE) { 1162 /* when we support 'E' we can do "val = RVE;" however 1163 * for now we just drop writes if 'E' is present. 1164 */ 1165 return RISCV_EXCP_NONE; 1166 } 1167 1168 /* 1169 * misa.MXL writes are not supported by QEMU. 1170 * Drop writes to those bits. 1171 */ 1172 1173 /* Mask extensions that are not supported by this hart */ 1174 val &= env->misa_ext_mask; 1175 1176 /* Mask extensions that are not supported by QEMU */ 1177 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 1178 1179 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 1180 if ((val & RVD) && !(val & RVF)) { 1181 val &= ~RVD; 1182 } 1183 1184 /* Suppress 'C' if next instruction is not aligned 1185 * TODO: this should check next_pc 1186 */ 1187 if ((val & RVC) && (GETPC() & ~3) != 0) { 1188 val &= ~RVC; 1189 } 1190 1191 /* If nothing changed, do nothing. */ 1192 if (val == env->misa_ext) { 1193 return RISCV_EXCP_NONE; 1194 } 1195 1196 if (!(val & RVF)) { 1197 env->mstatus &= ~MSTATUS_FS; 1198 } 1199 1200 /* flush translation cache */ 1201 tb_flush(env_cpu(env)); 1202 env->misa_ext = val; 1203 env->xl = riscv_cpu_mxl(env); 1204 return RISCV_EXCP_NONE; 1205 } 1206 1207 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 1208 target_ulong *val) 1209 { 1210 *val = env->medeleg; 1211 return RISCV_EXCP_NONE; 1212 } 1213 1214 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 1215 target_ulong val) 1216 { 1217 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 1218 return RISCV_EXCP_NONE; 1219 } 1220 1221 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 1222 uint64_t *ret_val, 1223 uint64_t new_val, uint64_t wr_mask) 1224 { 1225 uint64_t mask = wr_mask & delegable_ints; 1226 1227 if (ret_val) { 1228 *ret_val = env->mideleg; 1229 } 1230 1231 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 1232 1233 if (riscv_has_ext(env, RVH)) { 1234 env->mideleg |= HS_MODE_INTERRUPTS; 1235 } 1236 1237 return RISCV_EXCP_NONE; 1238 } 1239 1240 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 1241 target_ulong *ret_val, 1242 target_ulong new_val, target_ulong wr_mask) 1243 { 1244 uint64_t rval; 1245 RISCVException ret; 1246 1247 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 1248 if (ret_val) { 1249 *ret_val = rval; 1250 } 1251 1252 return ret; 1253 } 1254 1255 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 1256 target_ulong *ret_val, 1257 target_ulong new_val, 1258 target_ulong wr_mask) 1259 { 1260 uint64_t rval; 1261 RISCVException ret; 1262 1263 ret = rmw_mideleg64(env, csrno, &rval, 1264 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1265 if (ret_val) { 1266 *ret_val = rval >> 32; 1267 } 1268 1269 return ret; 1270 } 1271 1272 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 1273 uint64_t *ret_val, 1274 uint64_t new_val, uint64_t wr_mask) 1275 { 1276 uint64_t mask = wr_mask & all_ints; 1277 1278 if (ret_val) { 1279 *ret_val = env->mie; 1280 } 1281 1282 env->mie = (env->mie & ~mask) | (new_val & mask); 1283 1284 if (!riscv_has_ext(env, RVH)) { 1285 env->mie &= ~((uint64_t)MIP_SGEIP); 1286 } 1287 1288 return RISCV_EXCP_NONE; 1289 } 1290 1291 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 1292 target_ulong *ret_val, 1293 target_ulong new_val, target_ulong wr_mask) 1294 { 1295 uint64_t rval; 1296 RISCVException ret; 1297 1298 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 1299 if (ret_val) { 1300 *ret_val = rval; 1301 } 1302 1303 return ret; 1304 } 1305 1306 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 1307 target_ulong *ret_val, 1308 target_ulong new_val, target_ulong wr_mask) 1309 { 1310 uint64_t rval; 1311 RISCVException ret; 1312 1313 ret = rmw_mie64(env, csrno, &rval, 1314 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1315 if (ret_val) { 1316 *ret_val = rval >> 32; 1317 } 1318 1319 return ret; 1320 } 1321 1322 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 1323 { 1324 int irq; 1325 uint8_t iprio; 1326 1327 irq = riscv_cpu_mirq_pending(env); 1328 if (irq <= 0 || irq > 63) { 1329 *val = 0; 1330 } else { 1331 iprio = env->miprio[irq]; 1332 if (!iprio) { 1333 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 1334 iprio = IPRIO_MMAXIPRIO; 1335 } 1336 } 1337 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 1338 *val |= iprio; 1339 } 1340 1341 return RISCV_EXCP_NONE; 1342 } 1343 1344 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 1345 { 1346 if (!riscv_cpu_virt_enabled(env)) { 1347 return csrno; 1348 } 1349 1350 switch (csrno) { 1351 case CSR_SISELECT: 1352 return CSR_VSISELECT; 1353 case CSR_SIREG: 1354 return CSR_VSIREG; 1355 case CSR_STOPEI: 1356 return CSR_VSTOPEI; 1357 default: 1358 return csrno; 1359 }; 1360 } 1361 1362 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 1363 target_ulong new_val, target_ulong wr_mask) 1364 { 1365 target_ulong *iselect; 1366 1367 /* Translate CSR number for VS-mode */ 1368 csrno = aia_xlate_vs_csrno(env, csrno); 1369 1370 /* Find the iselect CSR based on CSR number */ 1371 switch (csrno) { 1372 case CSR_MISELECT: 1373 iselect = &env->miselect; 1374 break; 1375 case CSR_SISELECT: 1376 iselect = &env->siselect; 1377 break; 1378 case CSR_VSISELECT: 1379 iselect = &env->vsiselect; 1380 break; 1381 default: 1382 return RISCV_EXCP_ILLEGAL_INST; 1383 }; 1384 1385 if (val) { 1386 *val = *iselect; 1387 } 1388 1389 wr_mask &= ISELECT_MASK; 1390 if (wr_mask) { 1391 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1392 } 1393 1394 return RISCV_EXCP_NONE; 1395 } 1396 1397 static int rmw_iprio(target_ulong xlen, 1398 target_ulong iselect, uint8_t *iprio, 1399 target_ulong *val, target_ulong new_val, 1400 target_ulong wr_mask, int ext_irq_no) 1401 { 1402 int i, firq, nirqs; 1403 target_ulong old_val; 1404 1405 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1406 return -EINVAL; 1407 } 1408 if (xlen != 32 && iselect & 0x1) { 1409 return -EINVAL; 1410 } 1411 1412 nirqs = 4 * (xlen / 32); 1413 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1414 1415 old_val = 0; 1416 for (i = 0; i < nirqs; i++) { 1417 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1418 } 1419 1420 if (val) { 1421 *val = old_val; 1422 } 1423 1424 if (wr_mask) { 1425 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1426 for (i = 0; i < nirqs; i++) { 1427 /* 1428 * M-level and S-level external IRQ priority always read-only 1429 * zero. This means default priority order is always preferred 1430 * for M-level and S-level external IRQs. 1431 */ 1432 if ((firq + i) == ext_irq_no) { 1433 continue; 1434 } 1435 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1436 } 1437 } 1438 1439 return 0; 1440 } 1441 1442 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1443 target_ulong new_val, target_ulong wr_mask) 1444 { 1445 bool virt; 1446 uint8_t *iprio; 1447 int ret = -EINVAL; 1448 target_ulong priv, isel, vgein; 1449 1450 /* Translate CSR number for VS-mode */ 1451 csrno = aia_xlate_vs_csrno(env, csrno); 1452 1453 /* Decode register details from CSR number */ 1454 virt = false; 1455 switch (csrno) { 1456 case CSR_MIREG: 1457 iprio = env->miprio; 1458 isel = env->miselect; 1459 priv = PRV_M; 1460 break; 1461 case CSR_SIREG: 1462 iprio = env->siprio; 1463 isel = env->siselect; 1464 priv = PRV_S; 1465 break; 1466 case CSR_VSIREG: 1467 iprio = env->hviprio; 1468 isel = env->vsiselect; 1469 priv = PRV_S; 1470 virt = true; 1471 break; 1472 default: 1473 goto done; 1474 }; 1475 1476 /* Find the selected guest interrupt file */ 1477 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1478 1479 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1480 /* Local interrupt priority registers not available for VS-mode */ 1481 if (!virt) { 1482 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1483 isel, iprio, val, new_val, wr_mask, 1484 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1485 } 1486 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1487 /* IMSIC registers only available when machine implements it. */ 1488 if (env->aia_ireg_rmw_fn[priv]) { 1489 /* Selected guest interrupt file should not be zero */ 1490 if (virt && (!vgein || env->geilen < vgein)) { 1491 goto done; 1492 } 1493 /* Call machine specific IMSIC register emulation */ 1494 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1495 AIA_MAKE_IREG(isel, priv, virt, vgein, 1496 riscv_cpu_mxl_bits(env)), 1497 val, new_val, wr_mask); 1498 } 1499 } 1500 1501 done: 1502 if (ret) { 1503 return (riscv_cpu_virt_enabled(env) && virt) ? 1504 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1505 } 1506 return RISCV_EXCP_NONE; 1507 } 1508 1509 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1510 target_ulong new_val, target_ulong wr_mask) 1511 { 1512 bool virt; 1513 int ret = -EINVAL; 1514 target_ulong priv, vgein; 1515 1516 /* Translate CSR number for VS-mode */ 1517 csrno = aia_xlate_vs_csrno(env, csrno); 1518 1519 /* Decode register details from CSR number */ 1520 virt = false; 1521 switch (csrno) { 1522 case CSR_MTOPEI: 1523 priv = PRV_M; 1524 break; 1525 case CSR_STOPEI: 1526 priv = PRV_S; 1527 break; 1528 case CSR_VSTOPEI: 1529 priv = PRV_S; 1530 virt = true; 1531 break; 1532 default: 1533 goto done; 1534 }; 1535 1536 /* IMSIC CSRs only available when machine implements IMSIC. */ 1537 if (!env->aia_ireg_rmw_fn[priv]) { 1538 goto done; 1539 } 1540 1541 /* Find the selected guest interrupt file */ 1542 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1543 1544 /* Selected guest interrupt file should be valid */ 1545 if (virt && (!vgein || env->geilen < vgein)) { 1546 goto done; 1547 } 1548 1549 /* Call machine specific IMSIC register emulation for TOPEI */ 1550 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1551 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1552 riscv_cpu_mxl_bits(env)), 1553 val, new_val, wr_mask); 1554 1555 done: 1556 if (ret) { 1557 return (riscv_cpu_virt_enabled(env) && virt) ? 1558 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1559 } 1560 return RISCV_EXCP_NONE; 1561 } 1562 1563 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1564 target_ulong *val) 1565 { 1566 *val = env->mtvec; 1567 return RISCV_EXCP_NONE; 1568 } 1569 1570 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1571 target_ulong val) 1572 { 1573 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1574 if ((val & 3) < 2) { 1575 env->mtvec = val; 1576 } else { 1577 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1578 } 1579 return RISCV_EXCP_NONE; 1580 } 1581 1582 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, 1583 target_ulong *val) 1584 { 1585 *val = env->mcountinhibit; 1586 return RISCV_EXCP_NONE; 1587 } 1588 1589 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, 1590 target_ulong val) 1591 { 1592 int cidx; 1593 PMUCTRState *counter; 1594 1595 env->mcountinhibit = val; 1596 1597 /* Check if any other counter is also monitoring cycles/instructions */ 1598 for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { 1599 if (!get_field(env->mcountinhibit, BIT(cidx))) { 1600 counter = &env->pmu_ctrs[cidx]; 1601 counter->started = true; 1602 } 1603 } 1604 1605 return RISCV_EXCP_NONE; 1606 } 1607 1608 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1609 target_ulong *val) 1610 { 1611 *val = env->mcounteren; 1612 return RISCV_EXCP_NONE; 1613 } 1614 1615 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1616 target_ulong val) 1617 { 1618 env->mcounteren = val; 1619 return RISCV_EXCP_NONE; 1620 } 1621 1622 /* Machine Trap Handling */ 1623 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1624 Int128 *val) 1625 { 1626 *val = int128_make128(env->mscratch, env->mscratchh); 1627 return RISCV_EXCP_NONE; 1628 } 1629 1630 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1631 Int128 val) 1632 { 1633 env->mscratch = int128_getlo(val); 1634 env->mscratchh = int128_gethi(val); 1635 return RISCV_EXCP_NONE; 1636 } 1637 1638 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1639 target_ulong *val) 1640 { 1641 *val = env->mscratch; 1642 return RISCV_EXCP_NONE; 1643 } 1644 1645 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1646 target_ulong val) 1647 { 1648 env->mscratch = val; 1649 return RISCV_EXCP_NONE; 1650 } 1651 1652 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1653 target_ulong *val) 1654 { 1655 *val = env->mepc; 1656 return RISCV_EXCP_NONE; 1657 } 1658 1659 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1660 target_ulong val) 1661 { 1662 env->mepc = val; 1663 return RISCV_EXCP_NONE; 1664 } 1665 1666 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1667 target_ulong *val) 1668 { 1669 *val = env->mcause; 1670 return RISCV_EXCP_NONE; 1671 } 1672 1673 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1674 target_ulong val) 1675 { 1676 env->mcause = val; 1677 return RISCV_EXCP_NONE; 1678 } 1679 1680 static RISCVException read_mtval(CPURISCVState *env, int csrno, 1681 target_ulong *val) 1682 { 1683 *val = env->mtval; 1684 return RISCV_EXCP_NONE; 1685 } 1686 1687 static RISCVException write_mtval(CPURISCVState *env, int csrno, 1688 target_ulong val) 1689 { 1690 env->mtval = val; 1691 return RISCV_EXCP_NONE; 1692 } 1693 1694 /* Execution environment configuration setup */ 1695 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 1696 target_ulong *val) 1697 { 1698 *val = env->menvcfg; 1699 return RISCV_EXCP_NONE; 1700 } 1701 1702 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 1703 target_ulong val) 1704 { 1705 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 1706 1707 if (riscv_cpu_mxl(env) == MXL_RV64) { 1708 mask |= MENVCFG_PBMTE | MENVCFG_STCE; 1709 } 1710 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 1711 1712 return RISCV_EXCP_NONE; 1713 } 1714 1715 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 1716 target_ulong *val) 1717 { 1718 *val = env->menvcfg >> 32; 1719 return RISCV_EXCP_NONE; 1720 } 1721 1722 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 1723 target_ulong val) 1724 { 1725 uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; 1726 uint64_t valh = (uint64_t)val << 32; 1727 1728 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 1729 1730 return RISCV_EXCP_NONE; 1731 } 1732 1733 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 1734 target_ulong *val) 1735 { 1736 *val = env->senvcfg; 1737 return RISCV_EXCP_NONE; 1738 } 1739 1740 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 1741 target_ulong val) 1742 { 1743 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 1744 1745 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 1746 1747 return RISCV_EXCP_NONE; 1748 } 1749 1750 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 1751 target_ulong *val) 1752 { 1753 *val = env->henvcfg; 1754 return RISCV_EXCP_NONE; 1755 } 1756 1757 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 1758 target_ulong val) 1759 { 1760 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 1761 1762 if (riscv_cpu_mxl(env) == MXL_RV64) { 1763 mask |= HENVCFG_PBMTE | HENVCFG_STCE; 1764 } 1765 1766 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 1767 1768 return RISCV_EXCP_NONE; 1769 } 1770 1771 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 1772 target_ulong *val) 1773 { 1774 *val = env->henvcfg >> 32; 1775 return RISCV_EXCP_NONE; 1776 } 1777 1778 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 1779 target_ulong val) 1780 { 1781 uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; 1782 uint64_t valh = (uint64_t)val << 32; 1783 1784 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 1785 1786 return RISCV_EXCP_NONE; 1787 } 1788 1789 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 1790 uint64_t *ret_val, 1791 uint64_t new_val, uint64_t wr_mask) 1792 { 1793 RISCVCPU *cpu = env_archcpu(env); 1794 uint64_t old_mip, mask = wr_mask & delegable_ints; 1795 uint32_t gin; 1796 1797 if (mask & MIP_SEIP) { 1798 env->software_seip = new_val & MIP_SEIP; 1799 new_val |= env->external_seip * MIP_SEIP; 1800 } 1801 1802 if (cpu->cfg.ext_sstc && (env->priv == PRV_M) && 1803 get_field(env->menvcfg, MENVCFG_STCE)) { 1804 /* sstc extension forbids STIP & VSTIP to be writeable in mip */ 1805 mask = mask & ~(MIP_STIP | MIP_VSTIP); 1806 } 1807 1808 if (mask) { 1809 old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); 1810 } else { 1811 old_mip = env->mip; 1812 } 1813 1814 if (csrno != CSR_HVIP) { 1815 gin = get_field(env->hstatus, HSTATUS_VGEIN); 1816 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 1817 } 1818 1819 if (ret_val) { 1820 *ret_val = old_mip; 1821 } 1822 1823 return RISCV_EXCP_NONE; 1824 } 1825 1826 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 1827 target_ulong *ret_val, 1828 target_ulong new_val, target_ulong wr_mask) 1829 { 1830 uint64_t rval; 1831 RISCVException ret; 1832 1833 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 1834 if (ret_val) { 1835 *ret_val = rval; 1836 } 1837 1838 return ret; 1839 } 1840 1841 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 1842 target_ulong *ret_val, 1843 target_ulong new_val, target_ulong wr_mask) 1844 { 1845 uint64_t rval; 1846 RISCVException ret; 1847 1848 ret = rmw_mip64(env, csrno, &rval, 1849 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1850 if (ret_val) { 1851 *ret_val = rval >> 32; 1852 } 1853 1854 return ret; 1855 } 1856 1857 /* Supervisor Trap Setup */ 1858 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 1859 Int128 *val) 1860 { 1861 uint64_t mask = sstatus_v1_10_mask; 1862 uint64_t sstatus = env->mstatus & mask; 1863 if (env->xl != MXL_RV32 || env->debugger) { 1864 mask |= SSTATUS64_UXL; 1865 } 1866 1867 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 1868 return RISCV_EXCP_NONE; 1869 } 1870 1871 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 1872 target_ulong *val) 1873 { 1874 target_ulong mask = (sstatus_v1_10_mask); 1875 if (env->xl != MXL_RV32 || env->debugger) { 1876 mask |= SSTATUS64_UXL; 1877 } 1878 /* TODO: Use SXL not MXL. */ 1879 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 1880 return RISCV_EXCP_NONE; 1881 } 1882 1883 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 1884 target_ulong val) 1885 { 1886 target_ulong mask = (sstatus_v1_10_mask); 1887 1888 if (env->xl != MXL_RV32 || env->debugger) { 1889 if ((val & SSTATUS64_UXL) != 0) { 1890 mask |= SSTATUS64_UXL; 1891 } 1892 } 1893 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 1894 return write_mstatus(env, CSR_MSTATUS, newval); 1895 } 1896 1897 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 1898 uint64_t *ret_val, 1899 uint64_t new_val, uint64_t wr_mask) 1900 { 1901 RISCVException ret; 1902 uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; 1903 1904 /* Bring VS-level bits to correct position */ 1905 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1906 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1907 new_val |= vsbits << 1; 1908 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1909 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1910 wr_mask |= vsbits << 1; 1911 1912 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); 1913 if (ret_val) { 1914 rval &= mask; 1915 vsbits = rval & VS_MODE_INTERRUPTS; 1916 rval &= ~VS_MODE_INTERRUPTS; 1917 *ret_val = rval | (vsbits >> 1); 1918 } 1919 1920 return ret; 1921 } 1922 1923 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 1924 target_ulong *ret_val, 1925 target_ulong new_val, target_ulong wr_mask) 1926 { 1927 uint64_t rval; 1928 RISCVException ret; 1929 1930 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 1931 if (ret_val) { 1932 *ret_val = rval; 1933 } 1934 1935 return ret; 1936 } 1937 1938 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 1939 target_ulong *ret_val, 1940 target_ulong new_val, target_ulong wr_mask) 1941 { 1942 uint64_t rval; 1943 RISCVException ret; 1944 1945 ret = rmw_vsie64(env, csrno, &rval, 1946 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1947 if (ret_val) { 1948 *ret_val = rval >> 32; 1949 } 1950 1951 return ret; 1952 } 1953 1954 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 1955 uint64_t *ret_val, 1956 uint64_t new_val, uint64_t wr_mask) 1957 { 1958 RISCVException ret; 1959 uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; 1960 1961 if (riscv_cpu_virt_enabled(env)) { 1962 if (env->hvictl & HVICTL_VTI) { 1963 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1964 } 1965 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 1966 } else { 1967 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); 1968 } 1969 1970 if (ret_val) { 1971 *ret_val &= mask; 1972 } 1973 1974 return ret; 1975 } 1976 1977 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 1978 target_ulong *ret_val, 1979 target_ulong new_val, target_ulong wr_mask) 1980 { 1981 uint64_t rval; 1982 RISCVException ret; 1983 1984 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 1985 if (ret == RISCV_EXCP_NONE && ret_val) { 1986 *ret_val = rval; 1987 } 1988 1989 return ret; 1990 } 1991 1992 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 1993 target_ulong *ret_val, 1994 target_ulong new_val, target_ulong wr_mask) 1995 { 1996 uint64_t rval; 1997 RISCVException ret; 1998 1999 ret = rmw_sie64(env, csrno, &rval, 2000 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2001 if (ret_val) { 2002 *ret_val = rval >> 32; 2003 } 2004 2005 return ret; 2006 } 2007 2008 static RISCVException read_stvec(CPURISCVState *env, int csrno, 2009 target_ulong *val) 2010 { 2011 *val = env->stvec; 2012 return RISCV_EXCP_NONE; 2013 } 2014 2015 static RISCVException write_stvec(CPURISCVState *env, int csrno, 2016 target_ulong val) 2017 { 2018 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 2019 if ((val & 3) < 2) { 2020 env->stvec = val; 2021 } else { 2022 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 2023 } 2024 return RISCV_EXCP_NONE; 2025 } 2026 2027 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 2028 target_ulong *val) 2029 { 2030 *val = env->scounteren; 2031 return RISCV_EXCP_NONE; 2032 } 2033 2034 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 2035 target_ulong val) 2036 { 2037 env->scounteren = val; 2038 return RISCV_EXCP_NONE; 2039 } 2040 2041 /* Supervisor Trap Handling */ 2042 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 2043 Int128 *val) 2044 { 2045 *val = int128_make128(env->sscratch, env->sscratchh); 2046 return RISCV_EXCP_NONE; 2047 } 2048 2049 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 2050 Int128 val) 2051 { 2052 env->sscratch = int128_getlo(val); 2053 env->sscratchh = int128_gethi(val); 2054 return RISCV_EXCP_NONE; 2055 } 2056 2057 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 2058 target_ulong *val) 2059 { 2060 *val = env->sscratch; 2061 return RISCV_EXCP_NONE; 2062 } 2063 2064 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 2065 target_ulong val) 2066 { 2067 env->sscratch = val; 2068 return RISCV_EXCP_NONE; 2069 } 2070 2071 static RISCVException read_sepc(CPURISCVState *env, int csrno, 2072 target_ulong *val) 2073 { 2074 *val = env->sepc; 2075 return RISCV_EXCP_NONE; 2076 } 2077 2078 static RISCVException write_sepc(CPURISCVState *env, int csrno, 2079 target_ulong val) 2080 { 2081 env->sepc = val; 2082 return RISCV_EXCP_NONE; 2083 } 2084 2085 static RISCVException read_scause(CPURISCVState *env, int csrno, 2086 target_ulong *val) 2087 { 2088 *val = env->scause; 2089 return RISCV_EXCP_NONE; 2090 } 2091 2092 static RISCVException write_scause(CPURISCVState *env, int csrno, 2093 target_ulong val) 2094 { 2095 env->scause = val; 2096 return RISCV_EXCP_NONE; 2097 } 2098 2099 static RISCVException read_stval(CPURISCVState *env, int csrno, 2100 target_ulong *val) 2101 { 2102 *val = env->stval; 2103 return RISCV_EXCP_NONE; 2104 } 2105 2106 static RISCVException write_stval(CPURISCVState *env, int csrno, 2107 target_ulong val) 2108 { 2109 env->stval = val; 2110 return RISCV_EXCP_NONE; 2111 } 2112 2113 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 2114 uint64_t *ret_val, 2115 uint64_t new_val, uint64_t wr_mask) 2116 { 2117 RISCVException ret; 2118 uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; 2119 2120 /* Bring VS-level bits to correct position */ 2121 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 2122 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 2123 new_val |= vsbits << 1; 2124 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 2125 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 2126 wr_mask |= vsbits << 1; 2127 2128 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); 2129 if (ret_val) { 2130 rval &= mask; 2131 vsbits = rval & VS_MODE_INTERRUPTS; 2132 rval &= ~VS_MODE_INTERRUPTS; 2133 *ret_val = rval | (vsbits >> 1); 2134 } 2135 2136 return ret; 2137 } 2138 2139 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 2140 target_ulong *ret_val, 2141 target_ulong new_val, target_ulong wr_mask) 2142 { 2143 uint64_t rval; 2144 RISCVException ret; 2145 2146 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 2147 if (ret_val) { 2148 *ret_val = rval; 2149 } 2150 2151 return ret; 2152 } 2153 2154 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 2155 target_ulong *ret_val, 2156 target_ulong new_val, target_ulong wr_mask) 2157 { 2158 uint64_t rval; 2159 RISCVException ret; 2160 2161 ret = rmw_vsip64(env, csrno, &rval, 2162 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2163 if (ret_val) { 2164 *ret_val = rval >> 32; 2165 } 2166 2167 return ret; 2168 } 2169 2170 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 2171 uint64_t *ret_val, 2172 uint64_t new_val, uint64_t wr_mask) 2173 { 2174 RISCVException ret; 2175 uint64_t mask = env->mideleg & sip_writable_mask; 2176 2177 if (riscv_cpu_virt_enabled(env)) { 2178 if (env->hvictl & HVICTL_VTI) { 2179 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2180 } 2181 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 2182 } else { 2183 ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); 2184 } 2185 2186 if (ret_val) { 2187 *ret_val &= env->mideleg & S_MODE_INTERRUPTS; 2188 } 2189 2190 return ret; 2191 } 2192 2193 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 2194 target_ulong *ret_val, 2195 target_ulong new_val, target_ulong wr_mask) 2196 { 2197 uint64_t rval; 2198 RISCVException ret; 2199 2200 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 2201 if (ret_val) { 2202 *ret_val = rval; 2203 } 2204 2205 return ret; 2206 } 2207 2208 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 2209 target_ulong *ret_val, 2210 target_ulong new_val, target_ulong wr_mask) 2211 { 2212 uint64_t rval; 2213 RISCVException ret; 2214 2215 ret = rmw_sip64(env, csrno, &rval, 2216 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2217 if (ret_val) { 2218 *ret_val = rval >> 32; 2219 } 2220 2221 return ret; 2222 } 2223 2224 /* Supervisor Protection and Translation */ 2225 static RISCVException read_satp(CPURISCVState *env, int csrno, 2226 target_ulong *val) 2227 { 2228 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2229 *val = 0; 2230 return RISCV_EXCP_NONE; 2231 } 2232 2233 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2234 return RISCV_EXCP_ILLEGAL_INST; 2235 } else { 2236 *val = env->satp; 2237 } 2238 2239 return RISCV_EXCP_NONE; 2240 } 2241 2242 static RISCVException write_satp(CPURISCVState *env, int csrno, 2243 target_ulong val) 2244 { 2245 target_ulong vm, mask; 2246 2247 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2248 return RISCV_EXCP_NONE; 2249 } 2250 2251 if (riscv_cpu_mxl(env) == MXL_RV32) { 2252 vm = validate_vm(env, get_field(val, SATP32_MODE)); 2253 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 2254 } else { 2255 vm = validate_vm(env, get_field(val, SATP64_MODE)); 2256 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 2257 } 2258 2259 if (vm && mask) { 2260 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2261 return RISCV_EXCP_ILLEGAL_INST; 2262 } else { 2263 /* 2264 * The ISA defines SATP.MODE=Bare as "no translation", but we still 2265 * pass these through QEMU's TLB emulation as it improves 2266 * performance. Flushing the TLB on SATP writes with paging 2267 * enabled avoids leaking those invalid cached mappings. 2268 */ 2269 tlb_flush(env_cpu(env)); 2270 env->satp = val; 2271 } 2272 } 2273 return RISCV_EXCP_NONE; 2274 } 2275 2276 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 2277 { 2278 int irq, ret; 2279 target_ulong topei; 2280 uint64_t vseip, vsgein; 2281 uint32_t iid, iprio, hviid, hviprio, gein; 2282 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 2283 2284 gein = get_field(env->hstatus, HSTATUS_VGEIN); 2285 hviid = get_field(env->hvictl, HVICTL_IID); 2286 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 2287 2288 if (gein) { 2289 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 2290 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 2291 if (gein <= env->geilen && vseip) { 2292 siid[scount] = IRQ_S_EXT; 2293 siprio[scount] = IPRIO_MMAXIPRIO + 1; 2294 if (env->aia_ireg_rmw_fn[PRV_S]) { 2295 /* 2296 * Call machine specific IMSIC register emulation for 2297 * reading TOPEI. 2298 */ 2299 ret = env->aia_ireg_rmw_fn[PRV_S]( 2300 env->aia_ireg_rmw_fn_arg[PRV_S], 2301 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 2302 riscv_cpu_mxl_bits(env)), 2303 &topei, 0, 0); 2304 if (!ret && topei) { 2305 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 2306 } 2307 } 2308 scount++; 2309 } 2310 } else { 2311 if (hviid == IRQ_S_EXT && hviprio) { 2312 siid[scount] = IRQ_S_EXT; 2313 siprio[scount] = hviprio; 2314 scount++; 2315 } 2316 } 2317 2318 if (env->hvictl & HVICTL_VTI) { 2319 if (hviid != IRQ_S_EXT) { 2320 siid[scount] = hviid; 2321 siprio[scount] = hviprio; 2322 scount++; 2323 } 2324 } else { 2325 irq = riscv_cpu_vsirq_pending(env); 2326 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 2327 siid[scount] = irq; 2328 siprio[scount] = env->hviprio[irq]; 2329 scount++; 2330 } 2331 } 2332 2333 iid = 0; 2334 iprio = UINT_MAX; 2335 for (s = 0; s < scount; s++) { 2336 if (siprio[s] < iprio) { 2337 iid = siid[s]; 2338 iprio = siprio[s]; 2339 } 2340 } 2341 2342 if (iid) { 2343 if (env->hvictl & HVICTL_IPRIOM) { 2344 if (iprio > IPRIO_MMAXIPRIO) { 2345 iprio = IPRIO_MMAXIPRIO; 2346 } 2347 if (!iprio) { 2348 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 2349 iprio = IPRIO_MMAXIPRIO; 2350 } 2351 } 2352 } else { 2353 iprio = 1; 2354 } 2355 } else { 2356 iprio = 0; 2357 } 2358 2359 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2360 *val |= iprio; 2361 return RISCV_EXCP_NONE; 2362 } 2363 2364 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 2365 { 2366 int irq; 2367 uint8_t iprio; 2368 2369 if (riscv_cpu_virt_enabled(env)) { 2370 return read_vstopi(env, CSR_VSTOPI, val); 2371 } 2372 2373 irq = riscv_cpu_sirq_pending(env); 2374 if (irq <= 0 || irq > 63) { 2375 *val = 0; 2376 } else { 2377 iprio = env->siprio[irq]; 2378 if (!iprio) { 2379 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 2380 iprio = IPRIO_MMAXIPRIO; 2381 } 2382 } 2383 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2384 *val |= iprio; 2385 } 2386 2387 return RISCV_EXCP_NONE; 2388 } 2389 2390 /* Hypervisor Extensions */ 2391 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 2392 target_ulong *val) 2393 { 2394 *val = env->hstatus; 2395 if (riscv_cpu_mxl(env) != MXL_RV32) { 2396 /* We only support 64-bit VSXL */ 2397 *val = set_field(*val, HSTATUS_VSXL, 2); 2398 } 2399 /* We only support little endian */ 2400 *val = set_field(*val, HSTATUS_VSBE, 0); 2401 return RISCV_EXCP_NONE; 2402 } 2403 2404 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 2405 target_ulong val) 2406 { 2407 env->hstatus = val; 2408 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 2409 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 2410 } 2411 if (get_field(val, HSTATUS_VSBE) != 0) { 2412 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 2413 } 2414 return RISCV_EXCP_NONE; 2415 } 2416 2417 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 2418 target_ulong *val) 2419 { 2420 *val = env->hedeleg; 2421 return RISCV_EXCP_NONE; 2422 } 2423 2424 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 2425 target_ulong val) 2426 { 2427 env->hedeleg = val & vs_delegable_excps; 2428 return RISCV_EXCP_NONE; 2429 } 2430 2431 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 2432 uint64_t *ret_val, 2433 uint64_t new_val, uint64_t wr_mask) 2434 { 2435 uint64_t mask = wr_mask & vs_delegable_ints; 2436 2437 if (ret_val) { 2438 *ret_val = env->hideleg & vs_delegable_ints; 2439 } 2440 2441 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 2442 return RISCV_EXCP_NONE; 2443 } 2444 2445 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 2446 target_ulong *ret_val, 2447 target_ulong new_val, target_ulong wr_mask) 2448 { 2449 uint64_t rval; 2450 RISCVException ret; 2451 2452 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 2453 if (ret_val) { 2454 *ret_val = rval; 2455 } 2456 2457 return ret; 2458 } 2459 2460 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 2461 target_ulong *ret_val, 2462 target_ulong new_val, target_ulong wr_mask) 2463 { 2464 uint64_t rval; 2465 RISCVException ret; 2466 2467 ret = rmw_hideleg64(env, csrno, &rval, 2468 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2469 if (ret_val) { 2470 *ret_val = rval >> 32; 2471 } 2472 2473 return ret; 2474 } 2475 2476 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2477 uint64_t *ret_val, 2478 uint64_t new_val, uint64_t wr_mask) 2479 { 2480 RISCVException ret; 2481 2482 ret = rmw_mip64(env, csrno, ret_val, new_val, 2483 wr_mask & hvip_writable_mask); 2484 if (ret_val) { 2485 *ret_val &= VS_MODE_INTERRUPTS; 2486 } 2487 2488 return ret; 2489 } 2490 2491 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 2492 target_ulong *ret_val, 2493 target_ulong new_val, target_ulong wr_mask) 2494 { 2495 uint64_t rval; 2496 RISCVException ret; 2497 2498 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 2499 if (ret_val) { 2500 *ret_val = rval; 2501 } 2502 2503 return ret; 2504 } 2505 2506 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 2507 target_ulong *ret_val, 2508 target_ulong new_val, target_ulong wr_mask) 2509 { 2510 uint64_t rval; 2511 RISCVException ret; 2512 2513 ret = rmw_hvip64(env, csrno, &rval, 2514 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2515 if (ret_val) { 2516 *ret_val = rval >> 32; 2517 } 2518 2519 return ret; 2520 } 2521 2522 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 2523 target_ulong *ret_value, 2524 target_ulong new_value, target_ulong write_mask) 2525 { 2526 int ret = rmw_mip(env, csrno, ret_value, new_value, 2527 write_mask & hip_writable_mask); 2528 2529 if (ret_value) { 2530 *ret_value &= HS_MODE_INTERRUPTS; 2531 } 2532 return ret; 2533 } 2534 2535 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 2536 target_ulong *ret_val, 2537 target_ulong new_val, target_ulong wr_mask) 2538 { 2539 uint64_t rval; 2540 RISCVException ret; 2541 2542 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 2543 if (ret_val) { 2544 *ret_val = rval & HS_MODE_INTERRUPTS; 2545 } 2546 2547 return ret; 2548 } 2549 2550 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 2551 target_ulong *val) 2552 { 2553 *val = env->hcounteren; 2554 return RISCV_EXCP_NONE; 2555 } 2556 2557 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 2558 target_ulong val) 2559 { 2560 env->hcounteren = val; 2561 return RISCV_EXCP_NONE; 2562 } 2563 2564 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 2565 target_ulong *val) 2566 { 2567 if (val) { 2568 *val = env->hgeie; 2569 } 2570 return RISCV_EXCP_NONE; 2571 } 2572 2573 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 2574 target_ulong val) 2575 { 2576 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 2577 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 2578 env->hgeie = val; 2579 /* Update mip.SGEIP bit */ 2580 riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, 2581 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 2582 return RISCV_EXCP_NONE; 2583 } 2584 2585 static RISCVException read_htval(CPURISCVState *env, int csrno, 2586 target_ulong *val) 2587 { 2588 *val = env->htval; 2589 return RISCV_EXCP_NONE; 2590 } 2591 2592 static RISCVException write_htval(CPURISCVState *env, int csrno, 2593 target_ulong val) 2594 { 2595 env->htval = val; 2596 return RISCV_EXCP_NONE; 2597 } 2598 2599 static RISCVException read_htinst(CPURISCVState *env, int csrno, 2600 target_ulong *val) 2601 { 2602 *val = env->htinst; 2603 return RISCV_EXCP_NONE; 2604 } 2605 2606 static RISCVException write_htinst(CPURISCVState *env, int csrno, 2607 target_ulong val) 2608 { 2609 return RISCV_EXCP_NONE; 2610 } 2611 2612 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 2613 target_ulong *val) 2614 { 2615 if (val) { 2616 *val = env->hgeip; 2617 } 2618 return RISCV_EXCP_NONE; 2619 } 2620 2621 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 2622 target_ulong *val) 2623 { 2624 *val = env->hgatp; 2625 return RISCV_EXCP_NONE; 2626 } 2627 2628 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 2629 target_ulong val) 2630 { 2631 env->hgatp = val; 2632 return RISCV_EXCP_NONE; 2633 } 2634 2635 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 2636 target_ulong *val) 2637 { 2638 if (!env->rdtime_fn) { 2639 return RISCV_EXCP_ILLEGAL_INST; 2640 } 2641 2642 *val = env->htimedelta; 2643 return RISCV_EXCP_NONE; 2644 } 2645 2646 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 2647 target_ulong val) 2648 { 2649 if (!env->rdtime_fn) { 2650 return RISCV_EXCP_ILLEGAL_INST; 2651 } 2652 2653 if (riscv_cpu_mxl(env) == MXL_RV32) { 2654 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 2655 } else { 2656 env->htimedelta = val; 2657 } 2658 return RISCV_EXCP_NONE; 2659 } 2660 2661 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 2662 target_ulong *val) 2663 { 2664 if (!env->rdtime_fn) { 2665 return RISCV_EXCP_ILLEGAL_INST; 2666 } 2667 2668 *val = env->htimedelta >> 32; 2669 return RISCV_EXCP_NONE; 2670 } 2671 2672 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 2673 target_ulong val) 2674 { 2675 if (!env->rdtime_fn) { 2676 return RISCV_EXCP_ILLEGAL_INST; 2677 } 2678 2679 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 2680 return RISCV_EXCP_NONE; 2681 } 2682 2683 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 2684 { 2685 *val = env->hvictl; 2686 return RISCV_EXCP_NONE; 2687 } 2688 2689 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 2690 { 2691 env->hvictl = val & HVICTL_VALID_MASK; 2692 return RISCV_EXCP_NONE; 2693 } 2694 2695 static int read_hvipriox(CPURISCVState *env, int first_index, 2696 uint8_t *iprio, target_ulong *val) 2697 { 2698 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2699 2700 /* First index has to be a multiple of number of irqs per register */ 2701 if (first_index % num_irqs) { 2702 return (riscv_cpu_virt_enabled(env)) ? 2703 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2704 } 2705 2706 /* Fill-up return value */ 2707 *val = 0; 2708 for (i = 0; i < num_irqs; i++) { 2709 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2710 continue; 2711 } 2712 if (rdzero) { 2713 continue; 2714 } 2715 *val |= ((target_ulong)iprio[irq]) << (i * 8); 2716 } 2717 2718 return RISCV_EXCP_NONE; 2719 } 2720 2721 static int write_hvipriox(CPURISCVState *env, int first_index, 2722 uint8_t *iprio, target_ulong val) 2723 { 2724 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2725 2726 /* First index has to be a multiple of number of irqs per register */ 2727 if (first_index % num_irqs) { 2728 return (riscv_cpu_virt_enabled(env)) ? 2729 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2730 } 2731 2732 /* Fill-up priority arrary */ 2733 for (i = 0; i < num_irqs; i++) { 2734 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2735 continue; 2736 } 2737 if (rdzero) { 2738 iprio[irq] = 0; 2739 } else { 2740 iprio[irq] = (val >> (i * 8)) & 0xff; 2741 } 2742 } 2743 2744 return RISCV_EXCP_NONE; 2745 } 2746 2747 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 2748 { 2749 return read_hvipriox(env, 0, env->hviprio, val); 2750 } 2751 2752 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 2753 { 2754 return write_hvipriox(env, 0, env->hviprio, val); 2755 } 2756 2757 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 2758 { 2759 return read_hvipriox(env, 4, env->hviprio, val); 2760 } 2761 2762 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 2763 { 2764 return write_hvipriox(env, 4, env->hviprio, val); 2765 } 2766 2767 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 2768 { 2769 return read_hvipriox(env, 8, env->hviprio, val); 2770 } 2771 2772 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 2773 { 2774 return write_hvipriox(env, 8, env->hviprio, val); 2775 } 2776 2777 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 2778 { 2779 return read_hvipriox(env, 12, env->hviprio, val); 2780 } 2781 2782 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 2783 { 2784 return write_hvipriox(env, 12, env->hviprio, val); 2785 } 2786 2787 /* Virtual CSR Registers */ 2788 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 2789 target_ulong *val) 2790 { 2791 *val = env->vsstatus; 2792 return RISCV_EXCP_NONE; 2793 } 2794 2795 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 2796 target_ulong val) 2797 { 2798 uint64_t mask = (target_ulong)-1; 2799 if ((val & VSSTATUS64_UXL) == 0) { 2800 mask &= ~VSSTATUS64_UXL; 2801 } 2802 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 2803 return RISCV_EXCP_NONE; 2804 } 2805 2806 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 2807 { 2808 *val = env->vstvec; 2809 return RISCV_EXCP_NONE; 2810 } 2811 2812 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 2813 target_ulong val) 2814 { 2815 env->vstvec = val; 2816 return RISCV_EXCP_NONE; 2817 } 2818 2819 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 2820 target_ulong *val) 2821 { 2822 *val = env->vsscratch; 2823 return RISCV_EXCP_NONE; 2824 } 2825 2826 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 2827 target_ulong val) 2828 { 2829 env->vsscratch = val; 2830 return RISCV_EXCP_NONE; 2831 } 2832 2833 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 2834 target_ulong *val) 2835 { 2836 *val = env->vsepc; 2837 return RISCV_EXCP_NONE; 2838 } 2839 2840 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 2841 target_ulong val) 2842 { 2843 env->vsepc = val; 2844 return RISCV_EXCP_NONE; 2845 } 2846 2847 static RISCVException read_vscause(CPURISCVState *env, int csrno, 2848 target_ulong *val) 2849 { 2850 *val = env->vscause; 2851 return RISCV_EXCP_NONE; 2852 } 2853 2854 static RISCVException write_vscause(CPURISCVState *env, int csrno, 2855 target_ulong val) 2856 { 2857 env->vscause = val; 2858 return RISCV_EXCP_NONE; 2859 } 2860 2861 static RISCVException read_vstval(CPURISCVState *env, int csrno, 2862 target_ulong *val) 2863 { 2864 *val = env->vstval; 2865 return RISCV_EXCP_NONE; 2866 } 2867 2868 static RISCVException write_vstval(CPURISCVState *env, int csrno, 2869 target_ulong val) 2870 { 2871 env->vstval = val; 2872 return RISCV_EXCP_NONE; 2873 } 2874 2875 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 2876 target_ulong *val) 2877 { 2878 *val = env->vsatp; 2879 return RISCV_EXCP_NONE; 2880 } 2881 2882 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 2883 target_ulong val) 2884 { 2885 env->vsatp = val; 2886 return RISCV_EXCP_NONE; 2887 } 2888 2889 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 2890 target_ulong *val) 2891 { 2892 *val = env->mtval2; 2893 return RISCV_EXCP_NONE; 2894 } 2895 2896 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 2897 target_ulong val) 2898 { 2899 env->mtval2 = val; 2900 return RISCV_EXCP_NONE; 2901 } 2902 2903 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 2904 target_ulong *val) 2905 { 2906 *val = env->mtinst; 2907 return RISCV_EXCP_NONE; 2908 } 2909 2910 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 2911 target_ulong val) 2912 { 2913 env->mtinst = val; 2914 return RISCV_EXCP_NONE; 2915 } 2916 2917 /* Physical Memory Protection */ 2918 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 2919 target_ulong *val) 2920 { 2921 *val = mseccfg_csr_read(env); 2922 return RISCV_EXCP_NONE; 2923 } 2924 2925 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 2926 target_ulong val) 2927 { 2928 mseccfg_csr_write(env, val); 2929 return RISCV_EXCP_NONE; 2930 } 2931 2932 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) 2933 { 2934 /* TODO: RV128 restriction check */ 2935 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 2936 return false; 2937 } 2938 return true; 2939 } 2940 2941 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 2942 target_ulong *val) 2943 { 2944 uint32_t reg_index = csrno - CSR_PMPCFG0; 2945 2946 if (!check_pmp_reg_index(env, reg_index)) { 2947 return RISCV_EXCP_ILLEGAL_INST; 2948 } 2949 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 2950 return RISCV_EXCP_NONE; 2951 } 2952 2953 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 2954 target_ulong val) 2955 { 2956 uint32_t reg_index = csrno - CSR_PMPCFG0; 2957 2958 if (!check_pmp_reg_index(env, reg_index)) { 2959 return RISCV_EXCP_ILLEGAL_INST; 2960 } 2961 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 2962 return RISCV_EXCP_NONE; 2963 } 2964 2965 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 2966 target_ulong *val) 2967 { 2968 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 2969 return RISCV_EXCP_NONE; 2970 } 2971 2972 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 2973 target_ulong val) 2974 { 2975 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 2976 return RISCV_EXCP_NONE; 2977 } 2978 2979 static RISCVException read_tselect(CPURISCVState *env, int csrno, 2980 target_ulong *val) 2981 { 2982 *val = tselect_csr_read(env); 2983 return RISCV_EXCP_NONE; 2984 } 2985 2986 static RISCVException write_tselect(CPURISCVState *env, int csrno, 2987 target_ulong val) 2988 { 2989 tselect_csr_write(env, val); 2990 return RISCV_EXCP_NONE; 2991 } 2992 2993 static RISCVException read_tdata(CPURISCVState *env, int csrno, 2994 target_ulong *val) 2995 { 2996 /* return 0 in tdata1 to end the trigger enumeration */ 2997 if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { 2998 *val = 0; 2999 return RISCV_EXCP_NONE; 3000 } 3001 3002 if (!tdata_available(env, csrno - CSR_TDATA1)) { 3003 return RISCV_EXCP_ILLEGAL_INST; 3004 } 3005 3006 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 3007 return RISCV_EXCP_NONE; 3008 } 3009 3010 static RISCVException write_tdata(CPURISCVState *env, int csrno, 3011 target_ulong val) 3012 { 3013 if (!tdata_available(env, csrno - CSR_TDATA1)) { 3014 return RISCV_EXCP_ILLEGAL_INST; 3015 } 3016 3017 tdata_csr_write(env, csrno - CSR_TDATA1, val); 3018 return RISCV_EXCP_NONE; 3019 } 3020 3021 /* 3022 * Functions to access Pointer Masking feature registers 3023 * We have to check if current priv lvl could modify 3024 * csr in given mode 3025 */ 3026 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 3027 { 3028 int csr_priv = get_field(csrno, 0x300); 3029 int pm_current; 3030 3031 if (env->debugger) { 3032 return false; 3033 } 3034 /* 3035 * If priv lvls differ that means we're accessing csr from higher priv lvl, 3036 * so allow the access 3037 */ 3038 if (env->priv != csr_priv) { 3039 return false; 3040 } 3041 switch (env->priv) { 3042 case PRV_M: 3043 pm_current = get_field(env->mmte, M_PM_CURRENT); 3044 break; 3045 case PRV_S: 3046 pm_current = get_field(env->mmte, S_PM_CURRENT); 3047 break; 3048 case PRV_U: 3049 pm_current = get_field(env->mmte, U_PM_CURRENT); 3050 break; 3051 default: 3052 g_assert_not_reached(); 3053 } 3054 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 3055 return !pm_current; 3056 } 3057 3058 static RISCVException read_mmte(CPURISCVState *env, int csrno, 3059 target_ulong *val) 3060 { 3061 *val = env->mmte & MMTE_MASK; 3062 return RISCV_EXCP_NONE; 3063 } 3064 3065 static RISCVException write_mmte(CPURISCVState *env, int csrno, 3066 target_ulong val) 3067 { 3068 uint64_t mstatus; 3069 target_ulong wpri_val = val & MMTE_MASK; 3070 3071 if (val != wpri_val) { 3072 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 3073 "MMTE: WPRI violation written 0x", val, 3074 "vs expected 0x", wpri_val); 3075 } 3076 /* for machine mode pm.current is hardwired to 1 */ 3077 wpri_val |= MMTE_M_PM_CURRENT; 3078 3079 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 3080 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 3081 env->mmte = wpri_val | PM_EXT_DIRTY; 3082 riscv_cpu_update_mask(env); 3083 3084 /* Set XS and SD bits, since PM CSRs are dirty */ 3085 mstatus = env->mstatus | MSTATUS_XS; 3086 write_mstatus(env, csrno, mstatus); 3087 return RISCV_EXCP_NONE; 3088 } 3089 3090 static RISCVException read_smte(CPURISCVState *env, int csrno, 3091 target_ulong *val) 3092 { 3093 *val = env->mmte & SMTE_MASK; 3094 return RISCV_EXCP_NONE; 3095 } 3096 3097 static RISCVException write_smte(CPURISCVState *env, int csrno, 3098 target_ulong val) 3099 { 3100 target_ulong wpri_val = val & SMTE_MASK; 3101 3102 if (val != wpri_val) { 3103 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 3104 "SMTE: WPRI violation written 0x", val, 3105 "vs expected 0x", wpri_val); 3106 } 3107 3108 /* if pm.current==0 we can't modify current PM CSRs */ 3109 if (check_pm_current_disabled(env, csrno)) { 3110 return RISCV_EXCP_NONE; 3111 } 3112 3113 wpri_val |= (env->mmte & ~SMTE_MASK); 3114 write_mmte(env, csrno, wpri_val); 3115 return RISCV_EXCP_NONE; 3116 } 3117 3118 static RISCVException read_umte(CPURISCVState *env, int csrno, 3119 target_ulong *val) 3120 { 3121 *val = env->mmte & UMTE_MASK; 3122 return RISCV_EXCP_NONE; 3123 } 3124 3125 static RISCVException write_umte(CPURISCVState *env, int csrno, 3126 target_ulong val) 3127 { 3128 target_ulong wpri_val = val & UMTE_MASK; 3129 3130 if (val != wpri_val) { 3131 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 3132 "UMTE: WPRI violation written 0x", val, 3133 "vs expected 0x", wpri_val); 3134 } 3135 3136 if (check_pm_current_disabled(env, csrno)) { 3137 return RISCV_EXCP_NONE; 3138 } 3139 3140 wpri_val |= (env->mmte & ~UMTE_MASK); 3141 write_mmte(env, csrno, wpri_val); 3142 return RISCV_EXCP_NONE; 3143 } 3144 3145 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 3146 target_ulong *val) 3147 { 3148 *val = env->mpmmask; 3149 return RISCV_EXCP_NONE; 3150 } 3151 3152 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 3153 target_ulong val) 3154 { 3155 uint64_t mstatus; 3156 3157 env->mpmmask = val; 3158 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 3159 env->cur_pmmask = val; 3160 } 3161 env->mmte |= PM_EXT_DIRTY; 3162 3163 /* Set XS and SD bits, since PM CSRs are dirty */ 3164 mstatus = env->mstatus | MSTATUS_XS; 3165 write_mstatus(env, csrno, mstatus); 3166 return RISCV_EXCP_NONE; 3167 } 3168 3169 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 3170 target_ulong *val) 3171 { 3172 *val = env->spmmask; 3173 return RISCV_EXCP_NONE; 3174 } 3175 3176 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 3177 target_ulong val) 3178 { 3179 uint64_t mstatus; 3180 3181 /* if pm.current==0 we can't modify current PM CSRs */ 3182 if (check_pm_current_disabled(env, csrno)) { 3183 return RISCV_EXCP_NONE; 3184 } 3185 env->spmmask = val; 3186 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3187 env->cur_pmmask = val; 3188 } 3189 env->mmte |= PM_EXT_DIRTY; 3190 3191 /* Set XS and SD bits, since PM CSRs are dirty */ 3192 mstatus = env->mstatus | MSTATUS_XS; 3193 write_mstatus(env, csrno, mstatus); 3194 return RISCV_EXCP_NONE; 3195 } 3196 3197 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 3198 target_ulong *val) 3199 { 3200 *val = env->upmmask; 3201 return RISCV_EXCP_NONE; 3202 } 3203 3204 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 3205 target_ulong val) 3206 { 3207 uint64_t mstatus; 3208 3209 /* if pm.current==0 we can't modify current PM CSRs */ 3210 if (check_pm_current_disabled(env, csrno)) { 3211 return RISCV_EXCP_NONE; 3212 } 3213 env->upmmask = val; 3214 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3215 env->cur_pmmask = val; 3216 } 3217 env->mmte |= PM_EXT_DIRTY; 3218 3219 /* Set XS and SD bits, since PM CSRs are dirty */ 3220 mstatus = env->mstatus | MSTATUS_XS; 3221 write_mstatus(env, csrno, mstatus); 3222 return RISCV_EXCP_NONE; 3223 } 3224 3225 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 3226 target_ulong *val) 3227 { 3228 *val = env->mpmbase; 3229 return RISCV_EXCP_NONE; 3230 } 3231 3232 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 3233 target_ulong val) 3234 { 3235 uint64_t mstatus; 3236 3237 env->mpmbase = val; 3238 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 3239 env->cur_pmbase = val; 3240 } 3241 env->mmte |= PM_EXT_DIRTY; 3242 3243 /* Set XS and SD bits, since PM CSRs are dirty */ 3244 mstatus = env->mstatus | MSTATUS_XS; 3245 write_mstatus(env, csrno, mstatus); 3246 return RISCV_EXCP_NONE; 3247 } 3248 3249 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 3250 target_ulong *val) 3251 { 3252 *val = env->spmbase; 3253 return RISCV_EXCP_NONE; 3254 } 3255 3256 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 3257 target_ulong val) 3258 { 3259 uint64_t mstatus; 3260 3261 /* if pm.current==0 we can't modify current PM CSRs */ 3262 if (check_pm_current_disabled(env, csrno)) { 3263 return RISCV_EXCP_NONE; 3264 } 3265 env->spmbase = val; 3266 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3267 env->cur_pmbase = val; 3268 } 3269 env->mmte |= PM_EXT_DIRTY; 3270 3271 /* Set XS and SD bits, since PM CSRs are dirty */ 3272 mstatus = env->mstatus | MSTATUS_XS; 3273 write_mstatus(env, csrno, mstatus); 3274 return RISCV_EXCP_NONE; 3275 } 3276 3277 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 3278 target_ulong *val) 3279 { 3280 *val = env->upmbase; 3281 return RISCV_EXCP_NONE; 3282 } 3283 3284 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 3285 target_ulong val) 3286 { 3287 uint64_t mstatus; 3288 3289 /* if pm.current==0 we can't modify current PM CSRs */ 3290 if (check_pm_current_disabled(env, csrno)) { 3291 return RISCV_EXCP_NONE; 3292 } 3293 env->upmbase = val; 3294 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3295 env->cur_pmbase = val; 3296 } 3297 env->mmte |= PM_EXT_DIRTY; 3298 3299 /* Set XS and SD bits, since PM CSRs are dirty */ 3300 mstatus = env->mstatus | MSTATUS_XS; 3301 write_mstatus(env, csrno, mstatus); 3302 return RISCV_EXCP_NONE; 3303 } 3304 3305 #endif 3306 3307 /* Crypto Extension */ 3308 static RISCVException rmw_seed(CPURISCVState *env, int csrno, 3309 target_ulong *ret_value, 3310 target_ulong new_value, 3311 target_ulong write_mask) 3312 { 3313 uint16_t random_v; 3314 Error *random_e = NULL; 3315 int random_r; 3316 target_ulong rval; 3317 3318 random_r = qemu_guest_getrandom(&random_v, 2, &random_e); 3319 if (unlikely(random_r < 0)) { 3320 /* 3321 * Failed, for unknown reasons in the crypto subsystem. 3322 * The best we can do is log the reason and return a 3323 * failure indication to the guest. There is no reason 3324 * we know to expect the failure to be transitory, so 3325 * indicate DEAD to avoid having the guest spin on WAIT. 3326 */ 3327 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 3328 __func__, error_get_pretty(random_e)); 3329 error_free(random_e); 3330 rval = SEED_OPST_DEAD; 3331 } else { 3332 rval = random_v | SEED_OPST_ES16; 3333 } 3334 3335 if (ret_value) { 3336 *ret_value = rval; 3337 } 3338 3339 return RISCV_EXCP_NONE; 3340 } 3341 3342 /* 3343 * riscv_csrrw - read and/or update control and status register 3344 * 3345 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 3346 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 3347 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 3348 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 3349 */ 3350 3351 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 3352 int csrno, 3353 bool write_mask, 3354 RISCVCPU *cpu) 3355 { 3356 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 3357 int read_only = get_field(csrno, 0xC00) == 3; 3358 int csr_min_priv = csr_ops[csrno].min_priv_ver; 3359 3360 /* ensure the CSR extension is enabled. */ 3361 if (!cpu->cfg.ext_icsr) { 3362 return RISCV_EXCP_ILLEGAL_INST; 3363 } 3364 3365 if (env->priv_ver < csr_min_priv) { 3366 return RISCV_EXCP_ILLEGAL_INST; 3367 } 3368 3369 /* check predicate */ 3370 if (!csr_ops[csrno].predicate) { 3371 return RISCV_EXCP_ILLEGAL_INST; 3372 } 3373 3374 if (write_mask && read_only) { 3375 return RISCV_EXCP_ILLEGAL_INST; 3376 } 3377 3378 RISCVException ret = csr_ops[csrno].predicate(env, csrno); 3379 if (ret != RISCV_EXCP_NONE) { 3380 return ret; 3381 } 3382 3383 #if !defined(CONFIG_USER_ONLY) 3384 int csr_priv, effective_priv = env->priv; 3385 3386 if (riscv_has_ext(env, RVH) && env->priv == PRV_S && 3387 !riscv_cpu_virt_enabled(env)) { 3388 /* 3389 * We are in HS mode. Add 1 to the effective privledge level to 3390 * allow us to access the Hypervisor CSRs. 3391 */ 3392 effective_priv++; 3393 } 3394 3395 csr_priv = get_field(csrno, 0x300); 3396 if (!env->debugger && (effective_priv < csr_priv)) { 3397 if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { 3398 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 3399 } 3400 return RISCV_EXCP_ILLEGAL_INST; 3401 } 3402 #endif 3403 return RISCV_EXCP_NONE; 3404 } 3405 3406 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 3407 target_ulong *ret_value, 3408 target_ulong new_value, 3409 target_ulong write_mask) 3410 { 3411 RISCVException ret; 3412 target_ulong old_value; 3413 3414 /* execute combined read/write operation if it exists */ 3415 if (csr_ops[csrno].op) { 3416 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 3417 } 3418 3419 /* if no accessor exists then return failure */ 3420 if (!csr_ops[csrno].read) { 3421 return RISCV_EXCP_ILLEGAL_INST; 3422 } 3423 /* read old value */ 3424 ret = csr_ops[csrno].read(env, csrno, &old_value); 3425 if (ret != RISCV_EXCP_NONE) { 3426 return ret; 3427 } 3428 3429 /* write value if writable and write mask set, otherwise drop writes */ 3430 if (write_mask) { 3431 new_value = (old_value & ~write_mask) | (new_value & write_mask); 3432 if (csr_ops[csrno].write) { 3433 ret = csr_ops[csrno].write(env, csrno, new_value); 3434 if (ret != RISCV_EXCP_NONE) { 3435 return ret; 3436 } 3437 } 3438 } 3439 3440 /* return old value */ 3441 if (ret_value) { 3442 *ret_value = old_value; 3443 } 3444 3445 return RISCV_EXCP_NONE; 3446 } 3447 3448 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 3449 target_ulong *ret_value, 3450 target_ulong new_value, target_ulong write_mask) 3451 { 3452 RISCVCPU *cpu = env_archcpu(env); 3453 3454 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); 3455 if (ret != RISCV_EXCP_NONE) { 3456 return ret; 3457 } 3458 3459 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 3460 } 3461 3462 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 3463 Int128 *ret_value, 3464 Int128 new_value, 3465 Int128 write_mask) 3466 { 3467 RISCVException ret; 3468 Int128 old_value; 3469 3470 /* read old value */ 3471 ret = csr_ops[csrno].read128(env, csrno, &old_value); 3472 if (ret != RISCV_EXCP_NONE) { 3473 return ret; 3474 } 3475 3476 /* write value if writable and write mask set, otherwise drop writes */ 3477 if (int128_nz(write_mask)) { 3478 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 3479 int128_and(new_value, write_mask)); 3480 if (csr_ops[csrno].write128) { 3481 ret = csr_ops[csrno].write128(env, csrno, new_value); 3482 if (ret != RISCV_EXCP_NONE) { 3483 return ret; 3484 } 3485 } else if (csr_ops[csrno].write) { 3486 /* avoids having to write wrappers for all registers */ 3487 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 3488 if (ret != RISCV_EXCP_NONE) { 3489 return ret; 3490 } 3491 } 3492 } 3493 3494 /* return old value */ 3495 if (ret_value) { 3496 *ret_value = old_value; 3497 } 3498 3499 return RISCV_EXCP_NONE; 3500 } 3501 3502 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 3503 Int128 *ret_value, 3504 Int128 new_value, Int128 write_mask) 3505 { 3506 RISCVException ret; 3507 RISCVCPU *cpu = env_archcpu(env); 3508 3509 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); 3510 if (ret != RISCV_EXCP_NONE) { 3511 return ret; 3512 } 3513 3514 if (csr_ops[csrno].read128) { 3515 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 3516 } 3517 3518 /* 3519 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 3520 * at all defined. 3521 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 3522 * significant), for those, this fallback is correctly handling the accesses 3523 */ 3524 target_ulong old_value; 3525 ret = riscv_csrrw_do64(env, csrno, &old_value, 3526 int128_getlo(new_value), 3527 int128_getlo(write_mask)); 3528 if (ret == RISCV_EXCP_NONE && ret_value) { 3529 *ret_value = int128_make64(old_value); 3530 } 3531 return ret; 3532 } 3533 3534 /* 3535 * Debugger support. If not in user mode, set env->debugger before the 3536 * riscv_csrrw call and clear it after the call. 3537 */ 3538 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 3539 target_ulong *ret_value, 3540 target_ulong new_value, 3541 target_ulong write_mask) 3542 { 3543 RISCVException ret; 3544 #if !defined(CONFIG_USER_ONLY) 3545 env->debugger = true; 3546 #endif 3547 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 3548 #if !defined(CONFIG_USER_ONLY) 3549 env->debugger = false; 3550 #endif 3551 return ret; 3552 } 3553 3554 /* Control and Status Register function table */ 3555 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 3556 /* User Floating-Point CSRs */ 3557 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 3558 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 3559 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 3560 /* Vector CSRs */ 3561 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, 3562 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3563 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, 3564 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3565 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, 3566 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3567 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, 3568 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3569 [CSR_VL] = { "vl", vs, read_vl, 3570 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3571 [CSR_VTYPE] = { "vtype", vs, read_vtype, 3572 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3573 [CSR_VLENB] = { "vlenb", vs, read_vlenb, 3574 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3575 /* User Timers and Counters */ 3576 [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, 3577 [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, 3578 [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh }, 3579 [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh }, 3580 3581 /* 3582 * In privileged mode, the monitor will have to emulate TIME CSRs only if 3583 * rdtime callback is not provided by machine/platform emulation. 3584 */ 3585 [CSR_TIME] = { "time", ctr, read_time }, 3586 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 3587 3588 /* Crypto Extension */ 3589 [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, 3590 3591 #if !defined(CONFIG_USER_ONLY) 3592 /* Machine Timers and Counters */ 3593 [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, 3594 write_mhpmcounter }, 3595 [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, 3596 write_mhpmcounter }, 3597 [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, 3598 write_mhpmcounterh }, 3599 [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, 3600 write_mhpmcounterh }, 3601 3602 /* Machine Information Registers */ 3603 [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, 3604 [CSR_MARCHID] = { "marchid", any, read_marchid }, 3605 [CSR_MIMPID] = { "mimpid", any, read_mimpid }, 3606 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 3607 3608 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 3609 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3610 /* Machine Trap Setup */ 3611 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, 3612 NULL, read_mstatus_i128 }, 3613 [CSR_MISA] = { "misa", any, read_misa, write_misa, 3614 NULL, read_misa_i128 }, 3615 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 3616 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 3617 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 3618 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 3619 [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, 3620 write_mcounteren }, 3621 3622 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, 3623 write_mstatush }, 3624 3625 /* Machine Trap Handling */ 3626 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, 3627 NULL, read_mscratch_i128, write_mscratch_i128 }, 3628 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 3629 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 3630 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 3631 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 3632 3633 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 3634 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 3635 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 3636 3637 /* Machine-Level Interrupts (AIA) */ 3638 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 3639 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 3640 3641 /* Virtual Interrupts for Supervisor Level (AIA) */ 3642 [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, 3643 [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, 3644 3645 /* Machine-Level High-Half CSRs (AIA) */ 3646 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 3647 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 3648 [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, 3649 [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, 3650 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 3651 3652 /* Execution environment configuration */ 3653 [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, 3654 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3655 [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, 3656 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3657 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 3658 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3659 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 3660 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3661 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 3662 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3663 3664 /* Supervisor Trap Setup */ 3665 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, 3666 NULL, read_sstatus_i128 }, 3667 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 3668 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 3669 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, 3670 write_scounteren }, 3671 3672 /* Supervisor Trap Handling */ 3673 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, 3674 NULL, read_sscratch_i128, write_sscratch_i128 }, 3675 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 3676 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 3677 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 3678 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 3679 [CSR_STIMECMP] = { "stimecmp", sstc, read_stimecmp, write_stimecmp, 3680 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3681 [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph, 3682 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3683 3684 /* Supervisor Protection and Translation */ 3685 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 3686 3687 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 3688 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 3689 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 3690 3691 /* Supervisor-Level Interrupts (AIA) */ 3692 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 3693 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 3694 3695 /* Supervisor-Level High-Half CSRs (AIA) */ 3696 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 3697 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 3698 3699 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 3700 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3701 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 3702 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3703 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 3704 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3705 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 3706 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3707 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 3708 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3709 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 3710 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3711 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, 3712 write_hcounteren, 3713 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3714 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 3715 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3716 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 3717 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3718 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 3719 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3720 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 3721 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3722 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, 3723 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3724 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, 3725 write_htimedelta, 3726 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3727 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, 3728 write_htimedeltah, 3729 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3730 3731 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, 3732 write_vsstatus, 3733 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3734 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 3735 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3736 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 3737 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3738 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 3739 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3740 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, 3741 write_vsscratch, 3742 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3743 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 3744 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3745 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 3746 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3747 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 3748 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3749 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 3750 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3751 3752 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 3753 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3754 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 3755 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3756 3757 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 3758 [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, 3759 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, 3760 write_hvictl }, 3761 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, 3762 write_hviprio1 }, 3763 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, 3764 write_hviprio2 }, 3765 3766 /* 3767 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 3768 */ 3769 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, 3770 rmw_xiselect }, 3771 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 3772 3773 /* VS-Level Interrupts (H-extension with AIA) */ 3774 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 3775 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 3776 3777 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 3778 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, 3779 rmw_hidelegh }, 3780 [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, 3781 write_ignore }, 3782 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 3783 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, 3784 write_hviprio1h }, 3785 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, 3786 write_hviprio2h }, 3787 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 3788 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 3789 3790 /* Physical Memory Protection */ 3791 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 3792 .min_priv_ver = PRIV_VERSION_1_11_0 }, 3793 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 3794 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 3795 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 3796 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 3797 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 3798 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 3799 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 3800 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 3801 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 3802 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 3803 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 3804 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 3805 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 3806 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 3807 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 3808 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 3809 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 3810 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 3811 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 3812 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 3813 3814 /* Debug CSRs */ 3815 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 3816 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 3817 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 3818 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 3819 3820 /* User Pointer Masking */ 3821 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 3822 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, 3823 write_upmmask }, 3824 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, 3825 write_upmbase }, 3826 /* Machine Pointer Masking */ 3827 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 3828 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, 3829 write_mpmmask }, 3830 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, 3831 write_mpmbase }, 3832 /* Supervisor Pointer Masking */ 3833 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 3834 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, 3835 write_spmmask }, 3836 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, 3837 write_spmbase }, 3838 3839 /* Performance Counters */ 3840 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, 3841 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter }, 3842 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter }, 3843 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter }, 3844 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter }, 3845 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter }, 3846 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter }, 3847 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter }, 3848 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter }, 3849 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter }, 3850 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter }, 3851 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter }, 3852 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter }, 3853 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter }, 3854 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter }, 3855 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter }, 3856 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter }, 3857 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter }, 3858 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter }, 3859 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter }, 3860 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter }, 3861 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter }, 3862 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter }, 3863 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter }, 3864 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter }, 3865 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter }, 3866 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter }, 3867 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, 3868 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, 3869 3870 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, 3871 write_mhpmcounter }, 3872 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, 3873 write_mhpmcounter }, 3874 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, 3875 write_mhpmcounter }, 3876 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, 3877 write_mhpmcounter }, 3878 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, 3879 write_mhpmcounter }, 3880 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, 3881 write_mhpmcounter }, 3882 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, 3883 write_mhpmcounter }, 3884 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, 3885 write_mhpmcounter }, 3886 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, 3887 write_mhpmcounter }, 3888 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, 3889 write_mhpmcounter }, 3890 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, 3891 write_mhpmcounter }, 3892 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, 3893 write_mhpmcounter }, 3894 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, 3895 write_mhpmcounter }, 3896 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, 3897 write_mhpmcounter }, 3898 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, 3899 write_mhpmcounter }, 3900 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, 3901 write_mhpmcounter }, 3902 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, 3903 write_mhpmcounter }, 3904 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, 3905 write_mhpmcounter }, 3906 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, 3907 write_mhpmcounter }, 3908 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, 3909 write_mhpmcounter }, 3910 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, 3911 write_mhpmcounter }, 3912 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, 3913 write_mhpmcounter }, 3914 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, 3915 write_mhpmcounter }, 3916 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, 3917 write_mhpmcounter }, 3918 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, 3919 write_mhpmcounter }, 3920 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, 3921 write_mhpmcounter }, 3922 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, 3923 write_mhpmcounter }, 3924 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, 3925 write_mhpmcounter }, 3926 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, 3927 write_mhpmcounter }, 3928 3929 [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, 3930 write_mcountinhibit, 3931 .min_priv_ver = PRIV_VERSION_1_11_0 }, 3932 3933 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, 3934 write_mhpmevent }, 3935 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, 3936 write_mhpmevent }, 3937 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent, 3938 write_mhpmevent }, 3939 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent, 3940 write_mhpmevent }, 3941 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent, 3942 write_mhpmevent }, 3943 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent, 3944 write_mhpmevent }, 3945 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent, 3946 write_mhpmevent }, 3947 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent, 3948 write_mhpmevent }, 3949 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent, 3950 write_mhpmevent }, 3951 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent, 3952 write_mhpmevent }, 3953 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent, 3954 write_mhpmevent }, 3955 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent, 3956 write_mhpmevent }, 3957 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent, 3958 write_mhpmevent }, 3959 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent, 3960 write_mhpmevent }, 3961 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent, 3962 write_mhpmevent }, 3963 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent, 3964 write_mhpmevent }, 3965 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent, 3966 write_mhpmevent }, 3967 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent, 3968 write_mhpmevent }, 3969 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent, 3970 write_mhpmevent }, 3971 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent, 3972 write_mhpmevent }, 3973 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent, 3974 write_mhpmevent }, 3975 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent, 3976 write_mhpmevent }, 3977 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent, 3978 write_mhpmevent }, 3979 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent, 3980 write_mhpmevent }, 3981 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent, 3982 write_mhpmevent }, 3983 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent, 3984 write_mhpmevent }, 3985 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent, 3986 write_mhpmevent }, 3987 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent, 3988 write_mhpmevent }, 3989 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, 3990 write_mhpmevent }, 3991 3992 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh }, 3993 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh }, 3994 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh }, 3995 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh }, 3996 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh }, 3997 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh }, 3998 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh }, 3999 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh }, 4000 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh }, 4001 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh }, 4002 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh }, 4003 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh }, 4004 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh }, 4005 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh }, 4006 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh }, 4007 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh }, 4008 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh }, 4009 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh }, 4010 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh }, 4011 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh }, 4012 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh }, 4013 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh }, 4014 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh }, 4015 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh }, 4016 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh }, 4017 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh }, 4018 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh }, 4019 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, 4020 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, 4021 4022 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, 4023 write_mhpmcounterh }, 4024 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, 4025 write_mhpmcounterh }, 4026 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, 4027 write_mhpmcounterh }, 4028 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, 4029 write_mhpmcounterh }, 4030 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, 4031 write_mhpmcounterh }, 4032 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, 4033 write_mhpmcounterh }, 4034 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, 4035 write_mhpmcounterh }, 4036 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, 4037 write_mhpmcounterh }, 4038 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, 4039 write_mhpmcounterh }, 4040 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, 4041 write_mhpmcounterh }, 4042 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, 4043 write_mhpmcounterh }, 4044 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, 4045 write_mhpmcounterh }, 4046 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, 4047 write_mhpmcounterh }, 4048 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, 4049 write_mhpmcounterh }, 4050 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, 4051 write_mhpmcounterh }, 4052 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, 4053 write_mhpmcounterh }, 4054 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, 4055 write_mhpmcounterh }, 4056 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, 4057 write_mhpmcounterh }, 4058 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, 4059 write_mhpmcounterh }, 4060 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, 4061 write_mhpmcounterh }, 4062 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, 4063 write_mhpmcounterh }, 4064 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, 4065 write_mhpmcounterh }, 4066 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, 4067 write_mhpmcounterh }, 4068 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, 4069 write_mhpmcounterh }, 4070 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, 4071 write_mhpmcounterh }, 4072 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, 4073 write_mhpmcounterh }, 4074 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, 4075 write_mhpmcounterh }, 4076 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, 4077 write_mhpmcounterh }, 4078 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, 4079 write_mhpmcounterh }, 4080 #endif /* !CONFIG_USER_ONLY */ 4081 }; 4082