1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa & RVV)) { 43 return RISCV_EXCP_NONE; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return RISCV_EXCP_NONE; 50 } 51 52 static RISCVException vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa & RVV) { 55 return RISCV_EXCP_NONE; 56 } 57 return RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static RISCVException ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 75 get_field(env->mcounteren, HCOUNTEREN_CY)) { 76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 81 get_field(env->mcounteren, HCOUNTEREN_TM)) { 82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 87 get_field(env->mcounteren, HCOUNTEREN_IR)) { 88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_is_32bit(env)) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 102 get_field(env->mcounteren, HCOUNTEREN_CY)) { 103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 108 get_field(env->mcounteren, HCOUNTEREN_TM)) { 109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 114 get_field(env->mcounteren, HCOUNTEREN_IR)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return RISCV_EXCP_NONE; 129 } 130 131 static RISCVException ctr32(CPURISCVState *env, int csrno) 132 { 133 if (!riscv_cpu_is_32bit(env)) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static RISCVException any(CPURISCVState *env, int csrno) 142 { 143 return RISCV_EXCP_NONE; 144 } 145 146 static RISCVException any32(CPURISCVState *env, int csrno) 147 { 148 if (!riscv_cpu_is_32bit(env)) { 149 return RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static RISCVException smode(CPURISCVState *env, int csrno) 157 { 158 if (riscv_has_ext(env, RVS)) { 159 return RISCV_EXCP_NONE; 160 } 161 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 static RISCVException hmode(CPURISCVState *env, int csrno) 166 { 167 if (riscv_has_ext(env, RVS) && 168 riscv_has_ext(env, RVH)) { 169 /* Hypervisor extension is supported */ 170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 171 env->priv == PRV_M) { 172 return RISCV_EXCP_NONE; 173 } else { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 } 177 178 return RISCV_EXCP_ILLEGAL_INST; 179 } 180 181 static RISCVException hmode32(CPURISCVState *env, int csrno) 182 { 183 if (!riscv_cpu_is_32bit(env)) { 184 if (riscv_cpu_virt_enabled(env)) { 185 return RISCV_EXCP_ILLEGAL_INST; 186 } else { 187 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 188 } 189 } 190 191 return hmode(env, csrno); 192 193 } 194 195 static RISCVException pmp(CPURISCVState *env, int csrno) 196 { 197 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 198 return RISCV_EXCP_NONE; 199 } 200 201 return RISCV_EXCP_ILLEGAL_INST; 202 } 203 204 static RISCVException epmp(CPURISCVState *env, int csrno) 205 { 206 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 207 return RISCV_EXCP_NONE; 208 } 209 210 return RISCV_EXCP_ILLEGAL_INST; 211 } 212 #endif 213 214 /* User Floating-Point CSRs */ 215 static RISCVException read_fflags(CPURISCVState *env, int csrno, 216 target_ulong *val) 217 { 218 #if !defined(CONFIG_USER_ONLY) 219 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 220 return RISCV_EXCP_ILLEGAL_INST; 221 } 222 #endif 223 *val = riscv_cpu_get_fflags(env); 224 return RISCV_EXCP_NONE; 225 } 226 227 static RISCVException write_fflags(CPURISCVState *env, int csrno, 228 target_ulong val) 229 { 230 #if !defined(CONFIG_USER_ONLY) 231 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 232 return RISCV_EXCP_ILLEGAL_INST; 233 } 234 env->mstatus |= MSTATUS_FS; 235 #endif 236 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 237 return RISCV_EXCP_NONE; 238 } 239 240 static RISCVException read_frm(CPURISCVState *env, int csrno, 241 target_ulong *val) 242 { 243 #if !defined(CONFIG_USER_ONLY) 244 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 245 return RISCV_EXCP_ILLEGAL_INST; 246 } 247 #endif 248 *val = env->frm; 249 return RISCV_EXCP_NONE; 250 } 251 252 static RISCVException write_frm(CPURISCVState *env, int csrno, 253 target_ulong val) 254 { 255 #if !defined(CONFIG_USER_ONLY) 256 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 257 return RISCV_EXCP_ILLEGAL_INST; 258 } 259 env->mstatus |= MSTATUS_FS; 260 #endif 261 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 262 return RISCV_EXCP_NONE; 263 } 264 265 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 266 target_ulong *val) 267 { 268 #if !defined(CONFIG_USER_ONLY) 269 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 270 return RISCV_EXCP_ILLEGAL_INST; 271 } 272 #endif 273 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 274 | (env->frm << FSR_RD_SHIFT); 275 if (vs(env, csrno) >= 0) { 276 *val |= (env->vxrm << FSR_VXRM_SHIFT) 277 | (env->vxsat << FSR_VXSAT_SHIFT); 278 } 279 return RISCV_EXCP_NONE; 280 } 281 282 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 283 target_ulong val) 284 { 285 #if !defined(CONFIG_USER_ONLY) 286 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 287 return RISCV_EXCP_ILLEGAL_INST; 288 } 289 env->mstatus |= MSTATUS_FS; 290 #endif 291 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 292 if (vs(env, csrno) >= 0) { 293 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 294 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 295 } 296 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 297 return RISCV_EXCP_NONE; 298 } 299 300 static RISCVException read_vtype(CPURISCVState *env, int csrno, 301 target_ulong *val) 302 { 303 *val = env->vtype; 304 return RISCV_EXCP_NONE; 305 } 306 307 static RISCVException read_vl(CPURISCVState *env, int csrno, 308 target_ulong *val) 309 { 310 *val = env->vl; 311 return RISCV_EXCP_NONE; 312 } 313 314 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 315 target_ulong *val) 316 { 317 *val = env->vxrm; 318 return RISCV_EXCP_NONE; 319 } 320 321 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 322 target_ulong val) 323 { 324 env->vxrm = val; 325 return RISCV_EXCP_NONE; 326 } 327 328 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 329 target_ulong *val) 330 { 331 *val = env->vxsat; 332 return RISCV_EXCP_NONE; 333 } 334 335 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 336 target_ulong val) 337 { 338 env->vxsat = val; 339 return RISCV_EXCP_NONE; 340 } 341 342 static RISCVException read_vstart(CPURISCVState *env, int csrno, 343 target_ulong *val) 344 { 345 *val = env->vstart; 346 return RISCV_EXCP_NONE; 347 } 348 349 static RISCVException write_vstart(CPURISCVState *env, int csrno, 350 target_ulong val) 351 { 352 env->vstart = val; 353 return RISCV_EXCP_NONE; 354 } 355 356 /* User Timers and Counters */ 357 static RISCVException read_instret(CPURISCVState *env, int csrno, 358 target_ulong *val) 359 { 360 #if !defined(CONFIG_USER_ONLY) 361 if (icount_enabled()) { 362 *val = icount_get(); 363 } else { 364 *val = cpu_get_host_ticks(); 365 } 366 #else 367 *val = cpu_get_host_ticks(); 368 #endif 369 return RISCV_EXCP_NONE; 370 } 371 372 static RISCVException read_instreth(CPURISCVState *env, int csrno, 373 target_ulong *val) 374 { 375 #if !defined(CONFIG_USER_ONLY) 376 if (icount_enabled()) { 377 *val = icount_get() >> 32; 378 } else { 379 *val = cpu_get_host_ticks() >> 32; 380 } 381 #else 382 *val = cpu_get_host_ticks() >> 32; 383 #endif 384 return RISCV_EXCP_NONE; 385 } 386 387 #if defined(CONFIG_USER_ONLY) 388 static RISCVException read_time(CPURISCVState *env, int csrno, 389 target_ulong *val) 390 { 391 *val = cpu_get_host_ticks(); 392 return RISCV_EXCP_NONE; 393 } 394 395 static RISCVException read_timeh(CPURISCVState *env, int csrno, 396 target_ulong *val) 397 { 398 *val = cpu_get_host_ticks() >> 32; 399 return RISCV_EXCP_NONE; 400 } 401 402 #else /* CONFIG_USER_ONLY */ 403 404 static RISCVException read_time(CPURISCVState *env, int csrno, 405 target_ulong *val) 406 { 407 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 408 409 if (!env->rdtime_fn) { 410 return RISCV_EXCP_ILLEGAL_INST; 411 } 412 413 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 414 return RISCV_EXCP_NONE; 415 } 416 417 static RISCVException read_timeh(CPURISCVState *env, int csrno, 418 target_ulong *val) 419 { 420 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 421 422 if (!env->rdtime_fn) { 423 return RISCV_EXCP_ILLEGAL_INST; 424 } 425 426 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 427 return RISCV_EXCP_NONE; 428 } 429 430 /* Machine constants */ 431 432 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 433 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 434 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 435 436 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 437 VS_MODE_INTERRUPTS; 438 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 439 VS_MODE_INTERRUPTS; 440 static const target_ulong delegable_excps = 441 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 442 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 443 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 444 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 445 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 446 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 447 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 448 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 449 (1ULL << (RISCV_EXCP_U_ECALL)) | 450 (1ULL << (RISCV_EXCP_S_ECALL)) | 451 (1ULL << (RISCV_EXCP_VS_ECALL)) | 452 (1ULL << (RISCV_EXCP_M_ECALL)) | 453 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 454 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 455 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 456 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 457 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 458 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 459 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 460 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 461 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 462 SSTATUS_SUM | SSTATUS_MXR; 463 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 464 static const target_ulong hip_writable_mask = MIP_VSSIP; 465 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 466 static const target_ulong vsip_writable_mask = MIP_VSSIP; 467 468 static const char valid_vm_1_10_32[16] = { 469 [VM_1_10_MBARE] = 1, 470 [VM_1_10_SV32] = 1 471 }; 472 473 static const char valid_vm_1_10_64[16] = { 474 [VM_1_10_MBARE] = 1, 475 [VM_1_10_SV39] = 1, 476 [VM_1_10_SV48] = 1, 477 [VM_1_10_SV57] = 1 478 }; 479 480 /* Machine Information Registers */ 481 static RISCVException read_zero(CPURISCVState *env, int csrno, 482 target_ulong *val) 483 { 484 *val = 0; 485 return RISCV_EXCP_NONE; 486 } 487 488 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 489 target_ulong *val) 490 { 491 *val = env->mhartid; 492 return RISCV_EXCP_NONE; 493 } 494 495 /* Machine Trap Setup */ 496 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 497 target_ulong *val) 498 { 499 *val = env->mstatus; 500 return RISCV_EXCP_NONE; 501 } 502 503 static int validate_vm(CPURISCVState *env, target_ulong vm) 504 { 505 if (riscv_cpu_is_32bit(env)) { 506 return valid_vm_1_10_32[vm & 0xf]; 507 } else { 508 return valid_vm_1_10_64[vm & 0xf]; 509 } 510 } 511 512 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 513 target_ulong val) 514 { 515 uint64_t mstatus = env->mstatus; 516 uint64_t mask = 0; 517 int dirty; 518 519 /* flush tlb on mstatus fields that affect VM */ 520 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 521 MSTATUS_MPRV | MSTATUS_SUM)) { 522 tlb_flush(env_cpu(env)); 523 } 524 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 525 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 526 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 527 MSTATUS_TW; 528 529 if (!riscv_cpu_is_32bit(env)) { 530 /* 531 * RV32: MPV and GVA are not in mstatus. The current plan is to 532 * add them to mstatush. For now, we just don't support it. 533 */ 534 mask |= MSTATUS_MPV | MSTATUS_GVA; 535 } 536 537 mstatus = (mstatus & ~mask) | (val & mask); 538 539 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 540 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 541 if (riscv_cpu_is_32bit(env)) { 542 mstatus = set_field(mstatus, MSTATUS32_SD, dirty); 543 } else { 544 mstatus = set_field(mstatus, MSTATUS64_SD, dirty); 545 } 546 env->mstatus = mstatus; 547 548 return RISCV_EXCP_NONE; 549 } 550 551 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 552 target_ulong *val) 553 { 554 *val = env->mstatus >> 32; 555 return RISCV_EXCP_NONE; 556 } 557 558 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 559 target_ulong val) 560 { 561 uint64_t valh = (uint64_t)val << 32; 562 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 563 564 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 565 tlb_flush(env_cpu(env)); 566 } 567 568 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 569 570 return RISCV_EXCP_NONE; 571 } 572 573 static RISCVException read_misa(CPURISCVState *env, int csrno, 574 target_ulong *val) 575 { 576 *val = env->misa; 577 return RISCV_EXCP_NONE; 578 } 579 580 static RISCVException write_misa(CPURISCVState *env, int csrno, 581 target_ulong val) 582 { 583 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 584 /* drop write to misa */ 585 return RISCV_EXCP_NONE; 586 } 587 588 /* 'I' or 'E' must be present */ 589 if (!(val & (RVI | RVE))) { 590 /* It is not, drop write to misa */ 591 return RISCV_EXCP_NONE; 592 } 593 594 /* 'E' excludes all other extensions */ 595 if (val & RVE) { 596 /* when we support 'E' we can do "val = RVE;" however 597 * for now we just drop writes if 'E' is present. 598 */ 599 return RISCV_EXCP_NONE; 600 } 601 602 /* Mask extensions that are not supported by this hart */ 603 val &= env->misa_mask; 604 605 /* Mask extensions that are not supported by QEMU */ 606 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 607 608 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 609 if ((val & RVD) && !(val & RVF)) { 610 val &= ~RVD; 611 } 612 613 /* Suppress 'C' if next instruction is not aligned 614 * TODO: this should check next_pc 615 */ 616 if ((val & RVC) && (GETPC() & ~3) != 0) { 617 val &= ~RVC; 618 } 619 620 /* misa.MXL writes are not supported by QEMU */ 621 if (riscv_cpu_is_32bit(env)) { 622 val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); 623 } else { 624 val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); 625 } 626 627 /* flush translation cache */ 628 if (val != env->misa) { 629 tb_flush(env_cpu(env)); 630 } 631 632 env->misa = val; 633 634 return RISCV_EXCP_NONE; 635 } 636 637 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 638 target_ulong *val) 639 { 640 *val = env->medeleg; 641 return RISCV_EXCP_NONE; 642 } 643 644 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 645 target_ulong val) 646 { 647 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 648 return RISCV_EXCP_NONE; 649 } 650 651 static RISCVException read_mideleg(CPURISCVState *env, int csrno, 652 target_ulong *val) 653 { 654 *val = env->mideleg; 655 return RISCV_EXCP_NONE; 656 } 657 658 static RISCVException write_mideleg(CPURISCVState *env, int csrno, 659 target_ulong val) 660 { 661 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 662 if (riscv_has_ext(env, RVH)) { 663 env->mideleg |= VS_MODE_INTERRUPTS; 664 } 665 return RISCV_EXCP_NONE; 666 } 667 668 static RISCVException read_mie(CPURISCVState *env, int csrno, 669 target_ulong *val) 670 { 671 *val = env->mie; 672 return RISCV_EXCP_NONE; 673 } 674 675 static RISCVException write_mie(CPURISCVState *env, int csrno, 676 target_ulong val) 677 { 678 env->mie = (env->mie & ~all_ints) | (val & all_ints); 679 return RISCV_EXCP_NONE; 680 } 681 682 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 683 target_ulong *val) 684 { 685 *val = env->mtvec; 686 return RISCV_EXCP_NONE; 687 } 688 689 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 690 target_ulong val) 691 { 692 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 693 if ((val & 3) < 2) { 694 env->mtvec = val; 695 } else { 696 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 697 } 698 return RISCV_EXCP_NONE; 699 } 700 701 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 702 target_ulong *val) 703 { 704 *val = env->mcounteren; 705 return RISCV_EXCP_NONE; 706 } 707 708 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 709 target_ulong val) 710 { 711 env->mcounteren = val; 712 return RISCV_EXCP_NONE; 713 } 714 715 /* Machine Trap Handling */ 716 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 717 target_ulong *val) 718 { 719 *val = env->mscratch; 720 return RISCV_EXCP_NONE; 721 } 722 723 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 724 target_ulong val) 725 { 726 env->mscratch = val; 727 return RISCV_EXCP_NONE; 728 } 729 730 static RISCVException read_mepc(CPURISCVState *env, int csrno, 731 target_ulong *val) 732 { 733 *val = env->mepc; 734 return RISCV_EXCP_NONE; 735 } 736 737 static RISCVException write_mepc(CPURISCVState *env, int csrno, 738 target_ulong val) 739 { 740 env->mepc = val; 741 return RISCV_EXCP_NONE; 742 } 743 744 static RISCVException read_mcause(CPURISCVState *env, int csrno, 745 target_ulong *val) 746 { 747 *val = env->mcause; 748 return RISCV_EXCP_NONE; 749 } 750 751 static RISCVException write_mcause(CPURISCVState *env, int csrno, 752 target_ulong val) 753 { 754 env->mcause = val; 755 return RISCV_EXCP_NONE; 756 } 757 758 static RISCVException read_mtval(CPURISCVState *env, int csrno, 759 target_ulong *val) 760 { 761 *val = env->mtval; 762 return RISCV_EXCP_NONE; 763 } 764 765 static RISCVException write_mtval(CPURISCVState *env, int csrno, 766 target_ulong val) 767 { 768 env->mtval = val; 769 return RISCV_EXCP_NONE; 770 } 771 772 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 773 target_ulong *ret_value, 774 target_ulong new_value, target_ulong write_mask) 775 { 776 RISCVCPU *cpu = env_archcpu(env); 777 /* Allow software control of delegable interrupts not claimed by hardware */ 778 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 779 uint32_t old_mip; 780 781 if (mask) { 782 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 783 } else { 784 old_mip = env->mip; 785 } 786 787 if (ret_value) { 788 *ret_value = old_mip; 789 } 790 791 return RISCV_EXCP_NONE; 792 } 793 794 /* Supervisor Trap Setup */ 795 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 796 target_ulong *val) 797 { 798 target_ulong mask = (sstatus_v1_10_mask); 799 800 if (riscv_cpu_is_32bit(env)) { 801 mask |= SSTATUS32_SD; 802 } else { 803 mask |= SSTATUS64_SD; 804 } 805 806 *val = env->mstatus & mask; 807 return RISCV_EXCP_NONE; 808 } 809 810 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 811 target_ulong val) 812 { 813 target_ulong mask = (sstatus_v1_10_mask); 814 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 815 return write_mstatus(env, CSR_MSTATUS, newval); 816 } 817 818 static RISCVException read_vsie(CPURISCVState *env, int csrno, 819 target_ulong *val) 820 { 821 /* Shift the VS bits to their S bit location in vsie */ 822 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 823 return RISCV_EXCP_NONE; 824 } 825 826 static RISCVException read_sie(CPURISCVState *env, int csrno, 827 target_ulong *val) 828 { 829 if (riscv_cpu_virt_enabled(env)) { 830 read_vsie(env, CSR_VSIE, val); 831 } else { 832 *val = env->mie & env->mideleg; 833 } 834 return RISCV_EXCP_NONE; 835 } 836 837 static RISCVException write_vsie(CPURISCVState *env, int csrno, 838 target_ulong val) 839 { 840 /* Shift the S bits to their VS bit location in mie */ 841 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 842 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 843 return write_mie(env, CSR_MIE, newval); 844 } 845 846 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 847 { 848 if (riscv_cpu_virt_enabled(env)) { 849 write_vsie(env, CSR_VSIE, val); 850 } else { 851 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 852 (val & S_MODE_INTERRUPTS); 853 write_mie(env, CSR_MIE, newval); 854 } 855 856 return RISCV_EXCP_NONE; 857 } 858 859 static RISCVException read_stvec(CPURISCVState *env, int csrno, 860 target_ulong *val) 861 { 862 *val = env->stvec; 863 return RISCV_EXCP_NONE; 864 } 865 866 static RISCVException write_stvec(CPURISCVState *env, int csrno, 867 target_ulong val) 868 { 869 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 870 if ((val & 3) < 2) { 871 env->stvec = val; 872 } else { 873 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 874 } 875 return RISCV_EXCP_NONE; 876 } 877 878 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 879 target_ulong *val) 880 { 881 *val = env->scounteren; 882 return RISCV_EXCP_NONE; 883 } 884 885 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 886 target_ulong val) 887 { 888 env->scounteren = val; 889 return RISCV_EXCP_NONE; 890 } 891 892 /* Supervisor Trap Handling */ 893 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 894 target_ulong *val) 895 { 896 *val = env->sscratch; 897 return RISCV_EXCP_NONE; 898 } 899 900 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 901 target_ulong val) 902 { 903 env->sscratch = val; 904 return RISCV_EXCP_NONE; 905 } 906 907 static RISCVException read_sepc(CPURISCVState *env, int csrno, 908 target_ulong *val) 909 { 910 *val = env->sepc; 911 return RISCV_EXCP_NONE; 912 } 913 914 static RISCVException write_sepc(CPURISCVState *env, int csrno, 915 target_ulong val) 916 { 917 env->sepc = val; 918 return RISCV_EXCP_NONE; 919 } 920 921 static RISCVException read_scause(CPURISCVState *env, int csrno, 922 target_ulong *val) 923 { 924 *val = env->scause; 925 return RISCV_EXCP_NONE; 926 } 927 928 static RISCVException write_scause(CPURISCVState *env, int csrno, 929 target_ulong val) 930 { 931 env->scause = val; 932 return RISCV_EXCP_NONE; 933 } 934 935 static RISCVException read_stval(CPURISCVState *env, int csrno, 936 target_ulong *val) 937 { 938 *val = env->stval; 939 return RISCV_EXCP_NONE; 940 } 941 942 static RISCVException write_stval(CPURISCVState *env, int csrno, 943 target_ulong val) 944 { 945 env->stval = val; 946 return RISCV_EXCP_NONE; 947 } 948 949 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 950 target_ulong *ret_value, 951 target_ulong new_value, target_ulong write_mask) 952 { 953 /* Shift the S bits to their VS bit location in mip */ 954 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 955 (write_mask << 1) & vsip_writable_mask & env->hideleg); 956 *ret_value &= VS_MODE_INTERRUPTS; 957 /* Shift the VS bits to their S bit location in vsip */ 958 *ret_value >>= 1; 959 return ret; 960 } 961 962 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 963 target_ulong *ret_value, 964 target_ulong new_value, target_ulong write_mask) 965 { 966 int ret; 967 968 if (riscv_cpu_virt_enabled(env)) { 969 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 970 } else { 971 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 972 write_mask & env->mideleg & sip_writable_mask); 973 } 974 975 *ret_value &= env->mideleg; 976 return ret; 977 } 978 979 /* Supervisor Protection and Translation */ 980 static RISCVException read_satp(CPURISCVState *env, int csrno, 981 target_ulong *val) 982 { 983 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 984 *val = 0; 985 return RISCV_EXCP_NONE; 986 } 987 988 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 989 return RISCV_EXCP_ILLEGAL_INST; 990 } else { 991 *val = env->satp; 992 } 993 994 return RISCV_EXCP_NONE; 995 } 996 997 static RISCVException write_satp(CPURISCVState *env, int csrno, 998 target_ulong val) 999 { 1000 int vm, mask, asid; 1001 1002 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1003 return RISCV_EXCP_NONE; 1004 } 1005 1006 if (riscv_cpu_is_32bit(env)) { 1007 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1008 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1009 asid = (val ^ env->satp) & SATP32_ASID; 1010 } else { 1011 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1012 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1013 asid = (val ^ env->satp) & SATP64_ASID; 1014 } 1015 1016 if (vm && mask) { 1017 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1018 return RISCV_EXCP_ILLEGAL_INST; 1019 } else { 1020 if (asid) { 1021 tlb_flush(env_cpu(env)); 1022 } 1023 env->satp = val; 1024 } 1025 } 1026 return RISCV_EXCP_NONE; 1027 } 1028 1029 /* Hypervisor Extensions */ 1030 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 1031 target_ulong *val) 1032 { 1033 *val = env->hstatus; 1034 if (!riscv_cpu_is_32bit(env)) { 1035 /* We only support 64-bit VSXL */ 1036 *val = set_field(*val, HSTATUS_VSXL, 2); 1037 } 1038 /* We only support little endian */ 1039 *val = set_field(*val, HSTATUS_VSBE, 0); 1040 return RISCV_EXCP_NONE; 1041 } 1042 1043 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 1044 target_ulong val) 1045 { 1046 env->hstatus = val; 1047 if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { 1048 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 1049 } 1050 if (get_field(val, HSTATUS_VSBE) != 0) { 1051 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 1052 } 1053 return RISCV_EXCP_NONE; 1054 } 1055 1056 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 1057 target_ulong *val) 1058 { 1059 *val = env->hedeleg; 1060 return RISCV_EXCP_NONE; 1061 } 1062 1063 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 1064 target_ulong val) 1065 { 1066 env->hedeleg = val; 1067 return RISCV_EXCP_NONE; 1068 } 1069 1070 static RISCVException read_hideleg(CPURISCVState *env, int csrno, 1071 target_ulong *val) 1072 { 1073 *val = env->hideleg; 1074 return RISCV_EXCP_NONE; 1075 } 1076 1077 static RISCVException write_hideleg(CPURISCVState *env, int csrno, 1078 target_ulong val) 1079 { 1080 env->hideleg = val; 1081 return RISCV_EXCP_NONE; 1082 } 1083 1084 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 1085 target_ulong *ret_value, 1086 target_ulong new_value, target_ulong write_mask) 1087 { 1088 int ret = rmw_mip(env, 0, ret_value, new_value, 1089 write_mask & hvip_writable_mask); 1090 1091 *ret_value &= hvip_writable_mask; 1092 1093 return ret; 1094 } 1095 1096 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 1097 target_ulong *ret_value, 1098 target_ulong new_value, target_ulong write_mask) 1099 { 1100 int ret = rmw_mip(env, 0, ret_value, new_value, 1101 write_mask & hip_writable_mask); 1102 1103 *ret_value &= hip_writable_mask; 1104 1105 return ret; 1106 } 1107 1108 static RISCVException read_hie(CPURISCVState *env, int csrno, 1109 target_ulong *val) 1110 { 1111 *val = env->mie & VS_MODE_INTERRUPTS; 1112 return RISCV_EXCP_NONE; 1113 } 1114 1115 static RISCVException write_hie(CPURISCVState *env, int csrno, 1116 target_ulong val) 1117 { 1118 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1119 return write_mie(env, CSR_MIE, newval); 1120 } 1121 1122 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 1123 target_ulong *val) 1124 { 1125 *val = env->hcounteren; 1126 return RISCV_EXCP_NONE; 1127 } 1128 1129 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 1130 target_ulong val) 1131 { 1132 env->hcounteren = val; 1133 return RISCV_EXCP_NONE; 1134 } 1135 1136 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 1137 target_ulong *val) 1138 { 1139 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1140 return RISCV_EXCP_NONE; 1141 } 1142 1143 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 1144 target_ulong val) 1145 { 1146 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1147 return RISCV_EXCP_NONE; 1148 } 1149 1150 static RISCVException read_htval(CPURISCVState *env, int csrno, 1151 target_ulong *val) 1152 { 1153 *val = env->htval; 1154 return RISCV_EXCP_NONE; 1155 } 1156 1157 static RISCVException write_htval(CPURISCVState *env, int csrno, 1158 target_ulong val) 1159 { 1160 env->htval = val; 1161 return RISCV_EXCP_NONE; 1162 } 1163 1164 static RISCVException read_htinst(CPURISCVState *env, int csrno, 1165 target_ulong *val) 1166 { 1167 *val = env->htinst; 1168 return RISCV_EXCP_NONE; 1169 } 1170 1171 static RISCVException write_htinst(CPURISCVState *env, int csrno, 1172 target_ulong val) 1173 { 1174 return RISCV_EXCP_NONE; 1175 } 1176 1177 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 1178 target_ulong *val) 1179 { 1180 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1181 return RISCV_EXCP_NONE; 1182 } 1183 1184 static RISCVException write_hgeip(CPURISCVState *env, int csrno, 1185 target_ulong val) 1186 { 1187 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1188 return RISCV_EXCP_NONE; 1189 } 1190 1191 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 1192 target_ulong *val) 1193 { 1194 *val = env->hgatp; 1195 return RISCV_EXCP_NONE; 1196 } 1197 1198 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 1199 target_ulong val) 1200 { 1201 env->hgatp = val; 1202 return RISCV_EXCP_NONE; 1203 } 1204 1205 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 1206 target_ulong *val) 1207 { 1208 if (!env->rdtime_fn) { 1209 return RISCV_EXCP_ILLEGAL_INST; 1210 } 1211 1212 *val = env->htimedelta; 1213 return RISCV_EXCP_NONE; 1214 } 1215 1216 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 1217 target_ulong val) 1218 { 1219 if (!env->rdtime_fn) { 1220 return RISCV_EXCP_ILLEGAL_INST; 1221 } 1222 1223 if (riscv_cpu_is_32bit(env)) { 1224 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1225 } else { 1226 env->htimedelta = val; 1227 } 1228 return RISCV_EXCP_NONE; 1229 } 1230 1231 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 1232 target_ulong *val) 1233 { 1234 if (!env->rdtime_fn) { 1235 return RISCV_EXCP_ILLEGAL_INST; 1236 } 1237 1238 *val = env->htimedelta >> 32; 1239 return RISCV_EXCP_NONE; 1240 } 1241 1242 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 1243 target_ulong val) 1244 { 1245 if (!env->rdtime_fn) { 1246 return RISCV_EXCP_ILLEGAL_INST; 1247 } 1248 1249 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1250 return RISCV_EXCP_NONE; 1251 } 1252 1253 /* Virtual CSR Registers */ 1254 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 1255 target_ulong *val) 1256 { 1257 *val = env->vsstatus; 1258 return RISCV_EXCP_NONE; 1259 } 1260 1261 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 1262 target_ulong val) 1263 { 1264 uint64_t mask = (target_ulong)-1; 1265 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1266 return RISCV_EXCP_NONE; 1267 } 1268 1269 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1270 { 1271 *val = env->vstvec; 1272 return RISCV_EXCP_NONE; 1273 } 1274 1275 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 1276 target_ulong val) 1277 { 1278 env->vstvec = val; 1279 return RISCV_EXCP_NONE; 1280 } 1281 1282 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 1283 target_ulong *val) 1284 { 1285 *val = env->vsscratch; 1286 return RISCV_EXCP_NONE; 1287 } 1288 1289 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 1290 target_ulong val) 1291 { 1292 env->vsscratch = val; 1293 return RISCV_EXCP_NONE; 1294 } 1295 1296 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 1297 target_ulong *val) 1298 { 1299 *val = env->vsepc; 1300 return RISCV_EXCP_NONE; 1301 } 1302 1303 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 1304 target_ulong val) 1305 { 1306 env->vsepc = val; 1307 return RISCV_EXCP_NONE; 1308 } 1309 1310 static RISCVException read_vscause(CPURISCVState *env, int csrno, 1311 target_ulong *val) 1312 { 1313 *val = env->vscause; 1314 return RISCV_EXCP_NONE; 1315 } 1316 1317 static RISCVException write_vscause(CPURISCVState *env, int csrno, 1318 target_ulong val) 1319 { 1320 env->vscause = val; 1321 return RISCV_EXCP_NONE; 1322 } 1323 1324 static RISCVException read_vstval(CPURISCVState *env, int csrno, 1325 target_ulong *val) 1326 { 1327 *val = env->vstval; 1328 return RISCV_EXCP_NONE; 1329 } 1330 1331 static RISCVException write_vstval(CPURISCVState *env, int csrno, 1332 target_ulong val) 1333 { 1334 env->vstval = val; 1335 return RISCV_EXCP_NONE; 1336 } 1337 1338 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 1339 target_ulong *val) 1340 { 1341 *val = env->vsatp; 1342 return RISCV_EXCP_NONE; 1343 } 1344 1345 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 1346 target_ulong val) 1347 { 1348 env->vsatp = val; 1349 return RISCV_EXCP_NONE; 1350 } 1351 1352 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 1353 target_ulong *val) 1354 { 1355 *val = env->mtval2; 1356 return RISCV_EXCP_NONE; 1357 } 1358 1359 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 1360 target_ulong val) 1361 { 1362 env->mtval2 = val; 1363 return RISCV_EXCP_NONE; 1364 } 1365 1366 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 1367 target_ulong *val) 1368 { 1369 *val = env->mtinst; 1370 return RISCV_EXCP_NONE; 1371 } 1372 1373 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 1374 target_ulong val) 1375 { 1376 env->mtinst = val; 1377 return RISCV_EXCP_NONE; 1378 } 1379 1380 /* Physical Memory Protection */ 1381 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 1382 target_ulong *val) 1383 { 1384 *val = mseccfg_csr_read(env); 1385 return RISCV_EXCP_NONE; 1386 } 1387 1388 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 1389 target_ulong val) 1390 { 1391 mseccfg_csr_write(env, val); 1392 return RISCV_EXCP_NONE; 1393 } 1394 1395 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 1396 target_ulong *val) 1397 { 1398 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1399 return RISCV_EXCP_NONE; 1400 } 1401 1402 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 1403 target_ulong val) 1404 { 1405 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1406 return RISCV_EXCP_NONE; 1407 } 1408 1409 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 1410 target_ulong *val) 1411 { 1412 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1413 return RISCV_EXCP_NONE; 1414 } 1415 1416 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 1417 target_ulong val) 1418 { 1419 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1420 return RISCV_EXCP_NONE; 1421 } 1422 1423 #endif 1424 1425 /* 1426 * riscv_csrrw - read and/or update control and status register 1427 * 1428 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1429 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1430 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1431 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1432 */ 1433 1434 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 1435 target_ulong *ret_value, 1436 target_ulong new_value, target_ulong write_mask) 1437 { 1438 RISCVException ret; 1439 target_ulong old_value; 1440 RISCVCPU *cpu = env_archcpu(env); 1441 1442 /* check privileges and return -1 if check fails */ 1443 #if !defined(CONFIG_USER_ONLY) 1444 int effective_priv = env->priv; 1445 int read_only = get_field(csrno, 0xC00) == 3; 1446 1447 if (riscv_has_ext(env, RVH) && 1448 env->priv == PRV_S && 1449 !riscv_cpu_virt_enabled(env)) { 1450 /* 1451 * We are in S mode without virtualisation, therefore we are in HS Mode. 1452 * Add 1 to the effective privledge level to allow us to access the 1453 * Hypervisor CSRs. 1454 */ 1455 effective_priv++; 1456 } 1457 1458 if ((write_mask && read_only) || 1459 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1460 return RISCV_EXCP_ILLEGAL_INST; 1461 } 1462 #endif 1463 1464 /* ensure the CSR extension is enabled. */ 1465 if (!cpu->cfg.ext_icsr) { 1466 return RISCV_EXCP_ILLEGAL_INST; 1467 } 1468 1469 /* check predicate */ 1470 if (!csr_ops[csrno].predicate) { 1471 return RISCV_EXCP_ILLEGAL_INST; 1472 } 1473 ret = csr_ops[csrno].predicate(env, csrno); 1474 if (ret != RISCV_EXCP_NONE) { 1475 return ret; 1476 } 1477 1478 /* execute combined read/write operation if it exists */ 1479 if (csr_ops[csrno].op) { 1480 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1481 } 1482 1483 /* if no accessor exists then return failure */ 1484 if (!csr_ops[csrno].read) { 1485 return RISCV_EXCP_ILLEGAL_INST; 1486 } 1487 /* read old value */ 1488 ret = csr_ops[csrno].read(env, csrno, &old_value); 1489 if (ret != RISCV_EXCP_NONE) { 1490 return ret; 1491 } 1492 1493 /* write value if writable and write mask set, otherwise drop writes */ 1494 if (write_mask) { 1495 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1496 if (csr_ops[csrno].write) { 1497 ret = csr_ops[csrno].write(env, csrno, new_value); 1498 if (ret != RISCV_EXCP_NONE) { 1499 return ret; 1500 } 1501 } 1502 } 1503 1504 /* return old value */ 1505 if (ret_value) { 1506 *ret_value = old_value; 1507 } 1508 1509 return RISCV_EXCP_NONE; 1510 } 1511 1512 /* 1513 * Debugger support. If not in user mode, set env->debugger before the 1514 * riscv_csrrw call and clear it after the call. 1515 */ 1516 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 1517 target_ulong *ret_value, 1518 target_ulong new_value, 1519 target_ulong write_mask) 1520 { 1521 RISCVException ret; 1522 #if !defined(CONFIG_USER_ONLY) 1523 env->debugger = true; 1524 #endif 1525 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1526 #if !defined(CONFIG_USER_ONLY) 1527 env->debugger = false; 1528 #endif 1529 return ret; 1530 } 1531 1532 /* Control and Status Register function table */ 1533 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1534 /* User Floating-Point CSRs */ 1535 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1536 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1537 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1538 /* Vector CSRs */ 1539 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1540 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1541 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1542 [CSR_VL] = { "vl", vs, read_vl }, 1543 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1544 /* User Timers and Counters */ 1545 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1546 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1547 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1548 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1549 1550 /* 1551 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1552 * rdtime callback is not provided by machine/platform emulation. 1553 */ 1554 [CSR_TIME] = { "time", ctr, read_time }, 1555 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1556 1557 #if !defined(CONFIG_USER_ONLY) 1558 /* Machine Timers and Counters */ 1559 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1560 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1561 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1562 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1563 1564 /* Machine Information Registers */ 1565 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1566 [CSR_MARCHID] = { "marchid", any, read_zero }, 1567 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1568 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1569 1570 /* Machine Trap Setup */ 1571 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1572 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1573 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1574 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1575 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1576 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1577 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1578 1579 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1580 1581 /* Machine Trap Handling */ 1582 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1583 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1584 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1585 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1586 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1587 1588 /* Supervisor Trap Setup */ 1589 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1590 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1591 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1592 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1593 1594 /* Supervisor Trap Handling */ 1595 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1596 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1597 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1598 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1599 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1600 1601 /* Supervisor Protection and Translation */ 1602 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1603 1604 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1605 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1606 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1607 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1608 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1609 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1610 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1611 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, 1612 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1613 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1614 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, 1615 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1616 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1617 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1618 1619 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1620 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1621 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1622 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1623 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1624 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1625 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1626 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1627 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1628 1629 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1630 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1631 1632 /* Physical Memory Protection */ 1633 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, 1634 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1635 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1636 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1637 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1638 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1639 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1640 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1641 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1642 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1643 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1644 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1645 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1646 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1647 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1648 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1649 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1650 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1651 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1652 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1653 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1654 1655 /* Performance Counters */ 1656 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1657 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1658 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1659 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1660 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1661 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1662 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1663 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1664 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1665 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1666 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1667 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1668 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1669 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1670 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1671 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1672 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1673 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1674 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1675 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1676 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1677 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1678 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1679 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1680 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1681 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1682 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1683 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1684 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1685 1686 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1687 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1688 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1689 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1690 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1691 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1692 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1693 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1694 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1695 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1696 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1697 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 1698 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 1699 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 1700 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 1701 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 1702 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 1703 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 1704 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 1705 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 1706 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 1707 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 1708 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 1709 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 1710 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 1711 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 1712 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 1713 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 1714 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 1715 1716 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 1717 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 1718 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 1719 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 1720 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 1721 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 1722 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 1723 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 1724 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 1725 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 1726 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 1727 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 1728 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 1729 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 1730 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 1731 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 1732 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 1733 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 1734 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 1735 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 1736 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 1737 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 1738 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 1739 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 1740 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 1741 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 1742 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 1743 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 1744 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 1745 1746 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 1747 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 1748 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 1749 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 1750 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 1751 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 1752 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 1753 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 1754 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 1755 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 1756 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 1757 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 1758 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 1759 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 1760 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 1761 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 1762 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 1763 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 1764 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 1765 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 1766 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 1767 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 1768 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 1769 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 1770 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 1771 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 1772 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 1773 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 1774 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 1775 1776 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 1777 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 1778 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 1779 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 1780 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 1781 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 1782 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 1783 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 1784 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 1785 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 1786 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 1787 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 1788 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 1789 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 1790 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 1791 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 1792 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 1793 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 1794 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 1795 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 1796 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 1797 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 1798 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 1799 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 1800 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 1801 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 1802 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 1803 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 1804 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 1805 #endif /* !CONFIG_USER_ONLY */ 1806 }; 1807