xref: /openbmc/qemu/target/riscv/csr.c (revision 40bfa5f6) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     CPUState *cs = env_cpu(env);
51     RISCVCPU *cpu = RISCV_CPU(cs);
52 
53     if (env->misa_ext & RVV ||
54         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
55 #if !defined(CONFIG_USER_ONLY)
56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
57             return RISCV_EXCP_ILLEGAL_INST;
58         }
59 #endif
60         return RISCV_EXCP_NONE;
61     }
62     return RISCV_EXCP_ILLEGAL_INST;
63 }
64 
65 static RISCVException ctr(CPURISCVState *env, int csrno)
66 {
67 #if !defined(CONFIG_USER_ONLY)
68     CPUState *cs = env_cpu(env);
69     RISCVCPU *cpu = RISCV_CPU(cs);
70 
71     if (!cpu->cfg.ext_counters) {
72         /* The Counters extensions is not enabled */
73         return RISCV_EXCP_ILLEGAL_INST;
74     }
75 
76     if (riscv_cpu_virt_enabled(env)) {
77         switch (csrno) {
78         case CSR_CYCLE:
79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
80                 get_field(env->mcounteren, COUNTEREN_CY)) {
81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
82             }
83             break;
84         case CSR_TIME:
85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
86                 get_field(env->mcounteren, COUNTEREN_TM)) {
87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
88             }
89             break;
90         case CSR_INSTRET:
91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
92                 get_field(env->mcounteren, COUNTEREN_IR)) {
93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
94             }
95             break;
96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
100             }
101             break;
102         }
103         if (riscv_cpu_mxl(env) == MXL_RV32) {
104             switch (csrno) {
105             case CSR_CYCLEH:
106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
107                     get_field(env->mcounteren, COUNTEREN_CY)) {
108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109                 }
110                 break;
111             case CSR_TIMEH:
112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
113                     get_field(env->mcounteren, COUNTEREN_TM)) {
114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
115                 }
116                 break;
117             case CSR_INSTRETH:
118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
119                     get_field(env->mcounteren, COUNTEREN_IR)) {
120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
121                 }
122                 break;
123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
127                 }
128                 break;
129             }
130         }
131     }
132 #endif
133     return RISCV_EXCP_NONE;
134 }
135 
136 static RISCVException ctr32(CPURISCVState *env, int csrno)
137 {
138     if (riscv_cpu_mxl(env) != MXL_RV32) {
139         return RISCV_EXCP_ILLEGAL_INST;
140     }
141 
142     return ctr(env, csrno);
143 }
144 
145 #if !defined(CONFIG_USER_ONLY)
146 static RISCVException any(CPURISCVState *env, int csrno)
147 {
148     return RISCV_EXCP_NONE;
149 }
150 
151 static RISCVException any32(CPURISCVState *env, int csrno)
152 {
153     if (riscv_cpu_mxl(env) != MXL_RV32) {
154         return RISCV_EXCP_ILLEGAL_INST;
155     }
156 
157     return any(env, csrno);
158 
159 }
160 
161 static RISCVException smode(CPURISCVState *env, int csrno)
162 {
163     if (riscv_has_ext(env, RVS)) {
164         return RISCV_EXCP_NONE;
165     }
166 
167     return RISCV_EXCP_ILLEGAL_INST;
168 }
169 
170 static RISCVException hmode(CPURISCVState *env, int csrno)
171 {
172     if (riscv_has_ext(env, RVS) &&
173         riscv_has_ext(env, RVH)) {
174         /* Hypervisor extension is supported */
175         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
176             env->priv == PRV_M) {
177             return RISCV_EXCP_NONE;
178         } else {
179             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
180         }
181     }
182 
183     return RISCV_EXCP_ILLEGAL_INST;
184 }
185 
186 static RISCVException hmode32(CPURISCVState *env, int csrno)
187 {
188     if (riscv_cpu_mxl(env) != MXL_RV32) {
189         if (riscv_cpu_virt_enabled(env)) {
190             return RISCV_EXCP_ILLEGAL_INST;
191         } else {
192             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
193         }
194     }
195 
196     return hmode(env, csrno);
197 
198 }
199 
200 /* Checks if PointerMasking registers could be accessed */
201 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
202 {
203     /* Check if j-ext is present */
204     if (riscv_has_ext(env, RVJ)) {
205         return RISCV_EXCP_NONE;
206     }
207     return RISCV_EXCP_ILLEGAL_INST;
208 }
209 
210 static RISCVException pmp(CPURISCVState *env, int csrno)
211 {
212     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
213         return RISCV_EXCP_NONE;
214     }
215 
216     return RISCV_EXCP_ILLEGAL_INST;
217 }
218 
219 static RISCVException epmp(CPURISCVState *env, int csrno)
220 {
221     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
222         return RISCV_EXCP_NONE;
223     }
224 
225     return RISCV_EXCP_ILLEGAL_INST;
226 }
227 #endif
228 
229 /* User Floating-Point CSRs */
230 static RISCVException read_fflags(CPURISCVState *env, int csrno,
231                                   target_ulong *val)
232 {
233     *val = riscv_cpu_get_fflags(env);
234     return RISCV_EXCP_NONE;
235 }
236 
237 static RISCVException write_fflags(CPURISCVState *env, int csrno,
238                                    target_ulong val)
239 {
240 #if !defined(CONFIG_USER_ONLY)
241     env->mstatus |= MSTATUS_FS;
242 #endif
243     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
244     return RISCV_EXCP_NONE;
245 }
246 
247 static RISCVException read_frm(CPURISCVState *env, int csrno,
248                                target_ulong *val)
249 {
250     *val = env->frm;
251     return RISCV_EXCP_NONE;
252 }
253 
254 static RISCVException write_frm(CPURISCVState *env, int csrno,
255                                 target_ulong val)
256 {
257 #if !defined(CONFIG_USER_ONLY)
258     env->mstatus |= MSTATUS_FS;
259 #endif
260     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
261     return RISCV_EXCP_NONE;
262 }
263 
264 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
265                                 target_ulong *val)
266 {
267     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
268         | (env->frm << FSR_RD_SHIFT);
269     return RISCV_EXCP_NONE;
270 }
271 
272 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
273                                  target_ulong val)
274 {
275 #if !defined(CONFIG_USER_ONLY)
276     env->mstatus |= MSTATUS_FS;
277 #endif
278     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
279     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
280     return RISCV_EXCP_NONE;
281 }
282 
283 static RISCVException read_vtype(CPURISCVState *env, int csrno,
284                                  target_ulong *val)
285 {
286     *val = env->vtype;
287     return RISCV_EXCP_NONE;
288 }
289 
290 static RISCVException read_vl(CPURISCVState *env, int csrno,
291                               target_ulong *val)
292 {
293     *val = env->vl;
294     return RISCV_EXCP_NONE;
295 }
296 
297 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
298 {
299     *val = env_archcpu(env)->cfg.vlen >> 3;
300     return RISCV_EXCP_NONE;
301 }
302 
303 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
304                                 target_ulong *val)
305 {
306     *val = env->vxrm;
307     return RISCV_EXCP_NONE;
308 }
309 
310 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
311                                  target_ulong val)
312 {
313 #if !defined(CONFIG_USER_ONLY)
314     env->mstatus |= MSTATUS_VS;
315 #endif
316     env->vxrm = val;
317     return RISCV_EXCP_NONE;
318 }
319 
320 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
321                                  target_ulong *val)
322 {
323     *val = env->vxsat;
324     return RISCV_EXCP_NONE;
325 }
326 
327 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
328                                   target_ulong val)
329 {
330 #if !defined(CONFIG_USER_ONLY)
331     env->mstatus |= MSTATUS_VS;
332 #endif
333     env->vxsat = val;
334     return RISCV_EXCP_NONE;
335 }
336 
337 static RISCVException read_vstart(CPURISCVState *env, int csrno,
338                                   target_ulong *val)
339 {
340     *val = env->vstart;
341     return RISCV_EXCP_NONE;
342 }
343 
344 static RISCVException write_vstart(CPURISCVState *env, int csrno,
345                                    target_ulong val)
346 {
347 #if !defined(CONFIG_USER_ONLY)
348     env->mstatus |= MSTATUS_VS;
349 #endif
350     /*
351      * The vstart CSR is defined to have only enough writable bits
352      * to hold the largest element index, i.e. lg2(VLEN) bits.
353      */
354     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
355     return RISCV_EXCP_NONE;
356 }
357 
358 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
359 {
360     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
361     return RISCV_EXCP_NONE;
362 }
363 
364 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
365 {
366 #if !defined(CONFIG_USER_ONLY)
367     env->mstatus |= MSTATUS_VS;
368 #endif
369     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
370     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
371     return RISCV_EXCP_NONE;
372 }
373 
374 /* User Timers and Counters */
375 static RISCVException read_instret(CPURISCVState *env, int csrno,
376                                    target_ulong *val)
377 {
378 #if !defined(CONFIG_USER_ONLY)
379     if (icount_enabled()) {
380         *val = icount_get();
381     } else {
382         *val = cpu_get_host_ticks();
383     }
384 #else
385     *val = cpu_get_host_ticks();
386 #endif
387     return RISCV_EXCP_NONE;
388 }
389 
390 static RISCVException read_instreth(CPURISCVState *env, int csrno,
391                                     target_ulong *val)
392 {
393 #if !defined(CONFIG_USER_ONLY)
394     if (icount_enabled()) {
395         *val = icount_get() >> 32;
396     } else {
397         *val = cpu_get_host_ticks() >> 32;
398     }
399 #else
400     *val = cpu_get_host_ticks() >> 32;
401 #endif
402     return RISCV_EXCP_NONE;
403 }
404 
405 #if defined(CONFIG_USER_ONLY)
406 static RISCVException read_time(CPURISCVState *env, int csrno,
407                                 target_ulong *val)
408 {
409     *val = cpu_get_host_ticks();
410     return RISCV_EXCP_NONE;
411 }
412 
413 static RISCVException read_timeh(CPURISCVState *env, int csrno,
414                                  target_ulong *val)
415 {
416     *val = cpu_get_host_ticks() >> 32;
417     return RISCV_EXCP_NONE;
418 }
419 
420 #else /* CONFIG_USER_ONLY */
421 
422 static RISCVException read_time(CPURISCVState *env, int csrno,
423                                 target_ulong *val)
424 {
425     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
426 
427     if (!env->rdtime_fn) {
428         return RISCV_EXCP_ILLEGAL_INST;
429     }
430 
431     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
432     return RISCV_EXCP_NONE;
433 }
434 
435 static RISCVException read_timeh(CPURISCVState *env, int csrno,
436                                  target_ulong *val)
437 {
438     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
439 
440     if (!env->rdtime_fn) {
441         return RISCV_EXCP_ILLEGAL_INST;
442     }
443 
444     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
445     return RISCV_EXCP_NONE;
446 }
447 
448 /* Machine constants */
449 
450 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
451 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
452 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
453 
454 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
455                                            VS_MODE_INTERRUPTS;
456 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
457 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
458                                      VS_MODE_INTERRUPTS;
459 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
460                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
461                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
462                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
463                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
464                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
465                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
466                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
467                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
468                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
469                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
470                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
471                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
472                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
473                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
474                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
475                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
476                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
477                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
478 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
479     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
480       (1ULL << (RISCV_EXCP_VS_ECALL)) |
481       (1ULL << (RISCV_EXCP_M_ECALL)) |
482       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
483       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
484       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
485       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
486 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
487     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
488     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
489 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
490 static const target_ulong hip_writable_mask = MIP_VSSIP;
491 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
492 static const target_ulong vsip_writable_mask = MIP_VSSIP;
493 
494 static const char valid_vm_1_10_32[16] = {
495     [VM_1_10_MBARE] = 1,
496     [VM_1_10_SV32] = 1
497 };
498 
499 static const char valid_vm_1_10_64[16] = {
500     [VM_1_10_MBARE] = 1,
501     [VM_1_10_SV39] = 1,
502     [VM_1_10_SV48] = 1,
503     [VM_1_10_SV57] = 1
504 };
505 
506 /* Machine Information Registers */
507 static RISCVException read_zero(CPURISCVState *env, int csrno,
508                                 target_ulong *val)
509 {
510     *val = 0;
511     return RISCV_EXCP_NONE;
512 }
513 
514 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
515                                    target_ulong *val)
516 {
517     *val = env->mhartid;
518     return RISCV_EXCP_NONE;
519 }
520 
521 /* Machine Trap Setup */
522 
523 /* We do not store SD explicitly, only compute it on demand. */
524 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
525 {
526     if ((status & MSTATUS_FS) == MSTATUS_FS ||
527         (status & MSTATUS_VS) == MSTATUS_VS ||
528         (status & MSTATUS_XS) == MSTATUS_XS) {
529         switch (xl) {
530         case MXL_RV32:
531             return status | MSTATUS32_SD;
532         case MXL_RV64:
533             return status | MSTATUS64_SD;
534         case MXL_RV128:
535             return MSTATUSH128_SD;
536         default:
537             g_assert_not_reached();
538         }
539     }
540     return status;
541 }
542 
543 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
544                                    target_ulong *val)
545 {
546     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
547     return RISCV_EXCP_NONE;
548 }
549 
550 static int validate_vm(CPURISCVState *env, target_ulong vm)
551 {
552     if (riscv_cpu_mxl(env) == MXL_RV32) {
553         return valid_vm_1_10_32[vm & 0xf];
554     } else {
555         return valid_vm_1_10_64[vm & 0xf];
556     }
557 }
558 
559 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
560                                     target_ulong val)
561 {
562     uint64_t mstatus = env->mstatus;
563     uint64_t mask = 0;
564 
565     /* flush tlb on mstatus fields that affect VM */
566     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
567             MSTATUS_MPRV | MSTATUS_SUM)) {
568         tlb_flush(env_cpu(env));
569     }
570     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
571         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
572         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
573         MSTATUS_TW | MSTATUS_VS;
574 
575     if (riscv_cpu_mxl(env) != MXL_RV32) {
576         /*
577          * RV32: MPV and GVA are not in mstatus. The current plan is to
578          * add them to mstatush. For now, we just don't support it.
579          */
580         mask |= MSTATUS_MPV | MSTATUS_GVA;
581     }
582 
583     mstatus = (mstatus & ~mask) | (val & mask);
584 
585     RISCVMXL xl = riscv_cpu_mxl(env);
586     if (xl > MXL_RV32) {
587         /* SXL and UXL fields are for now read only */
588         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
589         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
590     }
591     env->mstatus = mstatus;
592     env->xl = cpu_recompute_xl(env);
593 
594     return RISCV_EXCP_NONE;
595 }
596 
597 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
598                                     target_ulong *val)
599 {
600     *val = env->mstatus >> 32;
601     return RISCV_EXCP_NONE;
602 }
603 
604 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
605                                      target_ulong val)
606 {
607     uint64_t valh = (uint64_t)val << 32;
608     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
609 
610     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
611         tlb_flush(env_cpu(env));
612     }
613 
614     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
615 
616     return RISCV_EXCP_NONE;
617 }
618 
619 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
620                                         Int128 *val)
621 {
622     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
623     return RISCV_EXCP_NONE;
624 }
625 
626 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
627                                      Int128 *val)
628 {
629     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
630     return RISCV_EXCP_NONE;
631 }
632 
633 static RISCVException read_misa(CPURISCVState *env, int csrno,
634                                 target_ulong *val)
635 {
636     target_ulong misa;
637 
638     switch (env->misa_mxl) {
639     case MXL_RV32:
640         misa = (target_ulong)MXL_RV32 << 30;
641         break;
642 #ifdef TARGET_RISCV64
643     case MXL_RV64:
644         misa = (target_ulong)MXL_RV64 << 62;
645         break;
646 #endif
647     default:
648         g_assert_not_reached();
649     }
650 
651     *val = misa | env->misa_ext;
652     return RISCV_EXCP_NONE;
653 }
654 
655 static RISCVException write_misa(CPURISCVState *env, int csrno,
656                                  target_ulong val)
657 {
658     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
659         /* drop write to misa */
660         return RISCV_EXCP_NONE;
661     }
662 
663     /* 'I' or 'E' must be present */
664     if (!(val & (RVI | RVE))) {
665         /* It is not, drop write to misa */
666         return RISCV_EXCP_NONE;
667     }
668 
669     /* 'E' excludes all other extensions */
670     if (val & RVE) {
671         /* when we support 'E' we can do "val = RVE;" however
672          * for now we just drop writes if 'E' is present.
673          */
674         return RISCV_EXCP_NONE;
675     }
676 
677     /*
678      * misa.MXL writes are not supported by QEMU.
679      * Drop writes to those bits.
680      */
681 
682     /* Mask extensions that are not supported by this hart */
683     val &= env->misa_ext_mask;
684 
685     /* Mask extensions that are not supported by QEMU */
686     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
687 
688     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
689     if ((val & RVD) && !(val & RVF)) {
690         val &= ~RVD;
691     }
692 
693     /* Suppress 'C' if next instruction is not aligned
694      * TODO: this should check next_pc
695      */
696     if ((val & RVC) && (GETPC() & ~3) != 0) {
697         val &= ~RVC;
698     }
699 
700     /* If nothing changed, do nothing. */
701     if (val == env->misa_ext) {
702         return RISCV_EXCP_NONE;
703     }
704 
705     /* flush translation cache */
706     tb_flush(env_cpu(env));
707     env->misa_ext = val;
708     env->xl = riscv_cpu_mxl(env);
709     return RISCV_EXCP_NONE;
710 }
711 
712 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
713                                    target_ulong *val)
714 {
715     *val = env->medeleg;
716     return RISCV_EXCP_NONE;
717 }
718 
719 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
720                                     target_ulong val)
721 {
722     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
723     return RISCV_EXCP_NONE;
724 }
725 
726 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
727                                    target_ulong *val)
728 {
729     *val = env->mideleg;
730     return RISCV_EXCP_NONE;
731 }
732 
733 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
734                                     target_ulong val)
735 {
736     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
737     if (riscv_has_ext(env, RVH)) {
738         env->mideleg |= VS_MODE_INTERRUPTS;
739     }
740     return RISCV_EXCP_NONE;
741 }
742 
743 static RISCVException read_mie(CPURISCVState *env, int csrno,
744                                target_ulong *val)
745 {
746     *val = env->mie;
747     return RISCV_EXCP_NONE;
748 }
749 
750 static RISCVException write_mie(CPURISCVState *env, int csrno,
751                                 target_ulong val)
752 {
753     env->mie = (env->mie & ~all_ints) | (val & all_ints);
754     return RISCV_EXCP_NONE;
755 }
756 
757 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
758                                  target_ulong *val)
759 {
760     *val = env->mtvec;
761     return RISCV_EXCP_NONE;
762 }
763 
764 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
765                                   target_ulong val)
766 {
767     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
768     if ((val & 3) < 2) {
769         env->mtvec = val;
770     } else {
771         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
772     }
773     return RISCV_EXCP_NONE;
774 }
775 
776 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
777                                       target_ulong *val)
778 {
779     *val = env->mcounteren;
780     return RISCV_EXCP_NONE;
781 }
782 
783 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
784                                        target_ulong val)
785 {
786     env->mcounteren = val;
787     return RISCV_EXCP_NONE;
788 }
789 
790 /* Machine Trap Handling */
791 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
792                                          Int128 *val)
793 {
794     *val = int128_make128(env->mscratch, env->mscratchh);
795     return RISCV_EXCP_NONE;
796 }
797 
798 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
799                                           Int128 val)
800 {
801     env->mscratch = int128_getlo(val);
802     env->mscratchh = int128_gethi(val);
803     return RISCV_EXCP_NONE;
804 }
805 
806 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
807                                     target_ulong *val)
808 {
809     *val = env->mscratch;
810     return RISCV_EXCP_NONE;
811 }
812 
813 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
814                                      target_ulong val)
815 {
816     env->mscratch = val;
817     return RISCV_EXCP_NONE;
818 }
819 
820 static RISCVException read_mepc(CPURISCVState *env, int csrno,
821                                      target_ulong *val)
822 {
823     *val = env->mepc;
824     return RISCV_EXCP_NONE;
825 }
826 
827 static RISCVException write_mepc(CPURISCVState *env, int csrno,
828                                      target_ulong val)
829 {
830     env->mepc = val;
831     return RISCV_EXCP_NONE;
832 }
833 
834 static RISCVException read_mcause(CPURISCVState *env, int csrno,
835                                      target_ulong *val)
836 {
837     *val = env->mcause;
838     return RISCV_EXCP_NONE;
839 }
840 
841 static RISCVException write_mcause(CPURISCVState *env, int csrno,
842                                      target_ulong val)
843 {
844     env->mcause = val;
845     return RISCV_EXCP_NONE;
846 }
847 
848 static RISCVException read_mtval(CPURISCVState *env, int csrno,
849                                  target_ulong *val)
850 {
851     *val = env->mtval;
852     return RISCV_EXCP_NONE;
853 }
854 
855 static RISCVException write_mtval(CPURISCVState *env, int csrno,
856                                   target_ulong val)
857 {
858     env->mtval = val;
859     return RISCV_EXCP_NONE;
860 }
861 
862 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
863                               target_ulong *ret_value,
864                               target_ulong new_value, target_ulong write_mask)
865 {
866     RISCVCPU *cpu = env_archcpu(env);
867     /* Allow software control of delegable interrupts not claimed by hardware */
868     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
869     uint32_t old_mip;
870 
871     if (mask) {
872         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
873     } else {
874         old_mip = env->mip;
875     }
876 
877     if (ret_value) {
878         *ret_value = old_mip;
879     }
880 
881     return RISCV_EXCP_NONE;
882 }
883 
884 /* Supervisor Trap Setup */
885 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
886                                         Int128 *val)
887 {
888     uint64_t mask = sstatus_v1_10_mask;
889     uint64_t sstatus = env->mstatus & mask;
890 
891     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
892     return RISCV_EXCP_NONE;
893 }
894 
895 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
896                                    target_ulong *val)
897 {
898     target_ulong mask = (sstatus_v1_10_mask);
899 
900     /* TODO: Use SXL not MXL. */
901     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
902     return RISCV_EXCP_NONE;
903 }
904 
905 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
906                                     target_ulong val)
907 {
908     target_ulong mask = (sstatus_v1_10_mask);
909     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
910     return write_mstatus(env, CSR_MSTATUS, newval);
911 }
912 
913 static RISCVException read_vsie(CPURISCVState *env, int csrno,
914                                 target_ulong *val)
915 {
916     /* Shift the VS bits to their S bit location in vsie */
917     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
918     return RISCV_EXCP_NONE;
919 }
920 
921 static RISCVException read_sie(CPURISCVState *env, int csrno,
922                                target_ulong *val)
923 {
924     if (riscv_cpu_virt_enabled(env)) {
925         read_vsie(env, CSR_VSIE, val);
926     } else {
927         *val = env->mie & env->mideleg;
928     }
929     return RISCV_EXCP_NONE;
930 }
931 
932 static RISCVException write_vsie(CPURISCVState *env, int csrno,
933                                  target_ulong val)
934 {
935     /* Shift the S bits to their VS bit location in mie */
936     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
937                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
938     return write_mie(env, CSR_MIE, newval);
939 }
940 
941 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
942 {
943     if (riscv_cpu_virt_enabled(env)) {
944         write_vsie(env, CSR_VSIE, val);
945     } else {
946         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
947                               (val & S_MODE_INTERRUPTS);
948         write_mie(env, CSR_MIE, newval);
949     }
950 
951     return RISCV_EXCP_NONE;
952 }
953 
954 static RISCVException read_stvec(CPURISCVState *env, int csrno,
955                                  target_ulong *val)
956 {
957     *val = env->stvec;
958     return RISCV_EXCP_NONE;
959 }
960 
961 static RISCVException write_stvec(CPURISCVState *env, int csrno,
962                                   target_ulong val)
963 {
964     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
965     if ((val & 3) < 2) {
966         env->stvec = val;
967     } else {
968         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
969     }
970     return RISCV_EXCP_NONE;
971 }
972 
973 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
974                                       target_ulong *val)
975 {
976     *val = env->scounteren;
977     return RISCV_EXCP_NONE;
978 }
979 
980 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
981                                        target_ulong val)
982 {
983     env->scounteren = val;
984     return RISCV_EXCP_NONE;
985 }
986 
987 /* Supervisor Trap Handling */
988 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
989                                          Int128 *val)
990 {
991     *val = int128_make128(env->sscratch, env->sscratchh);
992     return RISCV_EXCP_NONE;
993 }
994 
995 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
996                                           Int128 val)
997 {
998     env->sscratch = int128_getlo(val);
999     env->sscratchh = int128_gethi(val);
1000     return RISCV_EXCP_NONE;
1001 }
1002 
1003 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1004                                     target_ulong *val)
1005 {
1006     *val = env->sscratch;
1007     return RISCV_EXCP_NONE;
1008 }
1009 
1010 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1011                                      target_ulong val)
1012 {
1013     env->sscratch = val;
1014     return RISCV_EXCP_NONE;
1015 }
1016 
1017 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1018                                 target_ulong *val)
1019 {
1020     *val = env->sepc;
1021     return RISCV_EXCP_NONE;
1022 }
1023 
1024 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1025                                  target_ulong val)
1026 {
1027     env->sepc = val;
1028     return RISCV_EXCP_NONE;
1029 }
1030 
1031 static RISCVException read_scause(CPURISCVState *env, int csrno,
1032                                   target_ulong *val)
1033 {
1034     *val = env->scause;
1035     return RISCV_EXCP_NONE;
1036 }
1037 
1038 static RISCVException write_scause(CPURISCVState *env, int csrno,
1039                                    target_ulong val)
1040 {
1041     env->scause = val;
1042     return RISCV_EXCP_NONE;
1043 }
1044 
1045 static RISCVException read_stval(CPURISCVState *env, int csrno,
1046                                  target_ulong *val)
1047 {
1048     *val = env->stval;
1049     return RISCV_EXCP_NONE;
1050 }
1051 
1052 static RISCVException write_stval(CPURISCVState *env, int csrno,
1053                                   target_ulong val)
1054 {
1055     env->stval = val;
1056     return RISCV_EXCP_NONE;
1057 }
1058 
1059 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1060                                target_ulong *ret_value,
1061                                target_ulong new_value, target_ulong write_mask)
1062 {
1063     /* Shift the S bits to their VS bit location in mip */
1064     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
1065                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1066 
1067     if (ret_value) {
1068         *ret_value &= VS_MODE_INTERRUPTS;
1069         /* Shift the VS bits to their S bit location in vsip */
1070         *ret_value >>= 1;
1071     }
1072     return ret;
1073 }
1074 
1075 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1076                               target_ulong *ret_value,
1077                               target_ulong new_value, target_ulong write_mask)
1078 {
1079     int ret;
1080 
1081     if (riscv_cpu_virt_enabled(env)) {
1082         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1083     } else {
1084         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
1085                       write_mask & env->mideleg & sip_writable_mask);
1086     }
1087 
1088     if (ret_value) {
1089         *ret_value &= env->mideleg;
1090     }
1091     return ret;
1092 }
1093 
1094 /* Supervisor Protection and Translation */
1095 static RISCVException read_satp(CPURISCVState *env, int csrno,
1096                                 target_ulong *val)
1097 {
1098     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1099         *val = 0;
1100         return RISCV_EXCP_NONE;
1101     }
1102 
1103     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1104         return RISCV_EXCP_ILLEGAL_INST;
1105     } else {
1106         *val = env->satp;
1107     }
1108 
1109     return RISCV_EXCP_NONE;
1110 }
1111 
1112 static RISCVException write_satp(CPURISCVState *env, int csrno,
1113                                  target_ulong val)
1114 {
1115     target_ulong vm, mask, asid;
1116 
1117     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1118         return RISCV_EXCP_NONE;
1119     }
1120 
1121     if (riscv_cpu_mxl(env) == MXL_RV32) {
1122         vm = validate_vm(env, get_field(val, SATP32_MODE));
1123         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1124         asid = (val ^ env->satp) & SATP32_ASID;
1125     } else {
1126         vm = validate_vm(env, get_field(val, SATP64_MODE));
1127         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1128         asid = (val ^ env->satp) & SATP64_ASID;
1129     }
1130 
1131     if (vm && mask) {
1132         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1133             return RISCV_EXCP_ILLEGAL_INST;
1134         } else {
1135             if (asid) {
1136                 tlb_flush(env_cpu(env));
1137             }
1138             env->satp = val;
1139         }
1140     }
1141     return RISCV_EXCP_NONE;
1142 }
1143 
1144 /* Hypervisor Extensions */
1145 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1146                                    target_ulong *val)
1147 {
1148     *val = env->hstatus;
1149     if (riscv_cpu_mxl(env) != MXL_RV32) {
1150         /* We only support 64-bit VSXL */
1151         *val = set_field(*val, HSTATUS_VSXL, 2);
1152     }
1153     /* We only support little endian */
1154     *val = set_field(*val, HSTATUS_VSBE, 0);
1155     return RISCV_EXCP_NONE;
1156 }
1157 
1158 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1159                                     target_ulong val)
1160 {
1161     env->hstatus = val;
1162     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1163         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1164     }
1165     if (get_field(val, HSTATUS_VSBE) != 0) {
1166         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1167     }
1168     return RISCV_EXCP_NONE;
1169 }
1170 
1171 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1172                                    target_ulong *val)
1173 {
1174     *val = env->hedeleg;
1175     return RISCV_EXCP_NONE;
1176 }
1177 
1178 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1179                                     target_ulong val)
1180 {
1181     env->hedeleg = val & vs_delegable_excps;
1182     return RISCV_EXCP_NONE;
1183 }
1184 
1185 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1186                                    target_ulong *val)
1187 {
1188     *val = env->hideleg;
1189     return RISCV_EXCP_NONE;
1190 }
1191 
1192 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1193                                     target_ulong val)
1194 {
1195     env->hideleg = val & vs_delegable_ints;
1196     return RISCV_EXCP_NONE;
1197 }
1198 
1199 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1200                                target_ulong *ret_value,
1201                                target_ulong new_value, target_ulong write_mask)
1202 {
1203     int ret = rmw_mip(env, 0, ret_value, new_value,
1204                       write_mask & hvip_writable_mask);
1205 
1206     if (ret_value) {
1207         *ret_value &= hvip_writable_mask;
1208     }
1209     return ret;
1210 }
1211 
1212 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1213                               target_ulong *ret_value,
1214                               target_ulong new_value, target_ulong write_mask)
1215 {
1216     int ret = rmw_mip(env, 0, ret_value, new_value,
1217                       write_mask & hip_writable_mask);
1218 
1219     if (ret_value) {
1220         *ret_value &= hip_writable_mask;
1221     }
1222     return ret;
1223 }
1224 
1225 static RISCVException read_hie(CPURISCVState *env, int csrno,
1226                                target_ulong *val)
1227 {
1228     *val = env->mie & VS_MODE_INTERRUPTS;
1229     return RISCV_EXCP_NONE;
1230 }
1231 
1232 static RISCVException write_hie(CPURISCVState *env, int csrno,
1233                                 target_ulong val)
1234 {
1235     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1236     return write_mie(env, CSR_MIE, newval);
1237 }
1238 
1239 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1240                                       target_ulong *val)
1241 {
1242     *val = env->hcounteren;
1243     return RISCV_EXCP_NONE;
1244 }
1245 
1246 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1247                                        target_ulong val)
1248 {
1249     env->hcounteren = val;
1250     return RISCV_EXCP_NONE;
1251 }
1252 
1253 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1254                                   target_ulong val)
1255 {
1256     if (val) {
1257         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1258     }
1259     return RISCV_EXCP_NONE;
1260 }
1261 
1262 static RISCVException read_htval(CPURISCVState *env, int csrno,
1263                                  target_ulong *val)
1264 {
1265     *val = env->htval;
1266     return RISCV_EXCP_NONE;
1267 }
1268 
1269 static RISCVException write_htval(CPURISCVState *env, int csrno,
1270                                   target_ulong val)
1271 {
1272     env->htval = val;
1273     return RISCV_EXCP_NONE;
1274 }
1275 
1276 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1277                                   target_ulong *val)
1278 {
1279     *val = env->htinst;
1280     return RISCV_EXCP_NONE;
1281 }
1282 
1283 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1284                                    target_ulong val)
1285 {
1286     return RISCV_EXCP_NONE;
1287 }
1288 
1289 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1290                                   target_ulong val)
1291 {
1292     if (val) {
1293         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1294     }
1295     return RISCV_EXCP_NONE;
1296 }
1297 
1298 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1299                                  target_ulong *val)
1300 {
1301     *val = env->hgatp;
1302     return RISCV_EXCP_NONE;
1303 }
1304 
1305 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1306                                   target_ulong val)
1307 {
1308     env->hgatp = val;
1309     return RISCV_EXCP_NONE;
1310 }
1311 
1312 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1313                                       target_ulong *val)
1314 {
1315     if (!env->rdtime_fn) {
1316         return RISCV_EXCP_ILLEGAL_INST;
1317     }
1318 
1319     *val = env->htimedelta;
1320     return RISCV_EXCP_NONE;
1321 }
1322 
1323 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1324                                        target_ulong val)
1325 {
1326     if (!env->rdtime_fn) {
1327         return RISCV_EXCP_ILLEGAL_INST;
1328     }
1329 
1330     if (riscv_cpu_mxl(env) == MXL_RV32) {
1331         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1332     } else {
1333         env->htimedelta = val;
1334     }
1335     return RISCV_EXCP_NONE;
1336 }
1337 
1338 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1339                                        target_ulong *val)
1340 {
1341     if (!env->rdtime_fn) {
1342         return RISCV_EXCP_ILLEGAL_INST;
1343     }
1344 
1345     *val = env->htimedelta >> 32;
1346     return RISCV_EXCP_NONE;
1347 }
1348 
1349 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1350                                         target_ulong val)
1351 {
1352     if (!env->rdtime_fn) {
1353         return RISCV_EXCP_ILLEGAL_INST;
1354     }
1355 
1356     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1357     return RISCV_EXCP_NONE;
1358 }
1359 
1360 /* Virtual CSR Registers */
1361 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1362                                     target_ulong *val)
1363 {
1364     *val = env->vsstatus;
1365     return RISCV_EXCP_NONE;
1366 }
1367 
1368 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1369                                      target_ulong val)
1370 {
1371     uint64_t mask = (target_ulong)-1;
1372     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1373     return RISCV_EXCP_NONE;
1374 }
1375 
1376 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1377 {
1378     *val = env->vstvec;
1379     return RISCV_EXCP_NONE;
1380 }
1381 
1382 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1383                                    target_ulong val)
1384 {
1385     env->vstvec = val;
1386     return RISCV_EXCP_NONE;
1387 }
1388 
1389 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1390                                      target_ulong *val)
1391 {
1392     *val = env->vsscratch;
1393     return RISCV_EXCP_NONE;
1394 }
1395 
1396 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1397                                       target_ulong val)
1398 {
1399     env->vsscratch = val;
1400     return RISCV_EXCP_NONE;
1401 }
1402 
1403 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1404                                  target_ulong *val)
1405 {
1406     *val = env->vsepc;
1407     return RISCV_EXCP_NONE;
1408 }
1409 
1410 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1411                                   target_ulong val)
1412 {
1413     env->vsepc = val;
1414     return RISCV_EXCP_NONE;
1415 }
1416 
1417 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1418                                    target_ulong *val)
1419 {
1420     *val = env->vscause;
1421     return RISCV_EXCP_NONE;
1422 }
1423 
1424 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1425                                     target_ulong val)
1426 {
1427     env->vscause = val;
1428     return RISCV_EXCP_NONE;
1429 }
1430 
1431 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1432                                   target_ulong *val)
1433 {
1434     *val = env->vstval;
1435     return RISCV_EXCP_NONE;
1436 }
1437 
1438 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1439                                    target_ulong val)
1440 {
1441     env->vstval = val;
1442     return RISCV_EXCP_NONE;
1443 }
1444 
1445 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1446                                  target_ulong *val)
1447 {
1448     *val = env->vsatp;
1449     return RISCV_EXCP_NONE;
1450 }
1451 
1452 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1453                                   target_ulong val)
1454 {
1455     env->vsatp = val;
1456     return RISCV_EXCP_NONE;
1457 }
1458 
1459 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1460                                   target_ulong *val)
1461 {
1462     *val = env->mtval2;
1463     return RISCV_EXCP_NONE;
1464 }
1465 
1466 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1467                                    target_ulong val)
1468 {
1469     env->mtval2 = val;
1470     return RISCV_EXCP_NONE;
1471 }
1472 
1473 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1474                                   target_ulong *val)
1475 {
1476     *val = env->mtinst;
1477     return RISCV_EXCP_NONE;
1478 }
1479 
1480 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1481                                    target_ulong val)
1482 {
1483     env->mtinst = val;
1484     return RISCV_EXCP_NONE;
1485 }
1486 
1487 /* Physical Memory Protection */
1488 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1489                                    target_ulong *val)
1490 {
1491     *val = mseccfg_csr_read(env);
1492     return RISCV_EXCP_NONE;
1493 }
1494 
1495 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1496                          target_ulong val)
1497 {
1498     mseccfg_csr_write(env, val);
1499     return RISCV_EXCP_NONE;
1500 }
1501 
1502 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
1503 {
1504     /* TODO: RV128 restriction check */
1505     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
1506         return false;
1507     }
1508     return true;
1509 }
1510 
1511 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1512                                   target_ulong *val)
1513 {
1514     uint32_t reg_index = csrno - CSR_PMPCFG0;
1515 
1516     if (!check_pmp_reg_index(env, reg_index)) {
1517         return RISCV_EXCP_ILLEGAL_INST;
1518     }
1519     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1520     return RISCV_EXCP_NONE;
1521 }
1522 
1523 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1524                                    target_ulong val)
1525 {
1526     uint32_t reg_index = csrno - CSR_PMPCFG0;
1527 
1528     if (!check_pmp_reg_index(env, reg_index)) {
1529         return RISCV_EXCP_ILLEGAL_INST;
1530     }
1531     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1532     return RISCV_EXCP_NONE;
1533 }
1534 
1535 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1536                                    target_ulong *val)
1537 {
1538     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1539     return RISCV_EXCP_NONE;
1540 }
1541 
1542 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1543                                     target_ulong val)
1544 {
1545     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1546     return RISCV_EXCP_NONE;
1547 }
1548 
1549 /*
1550  * Functions to access Pointer Masking feature registers
1551  * We have to check if current priv lvl could modify
1552  * csr in given mode
1553  */
1554 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1555 {
1556     int csr_priv = get_field(csrno, 0x300);
1557     int pm_current;
1558 
1559     if (env->debugger) {
1560         return false;
1561     }
1562     /*
1563      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1564      * so allow the access
1565      */
1566     if (env->priv != csr_priv) {
1567         return false;
1568     }
1569     switch (env->priv) {
1570     case PRV_M:
1571         pm_current = get_field(env->mmte, M_PM_CURRENT);
1572         break;
1573     case PRV_S:
1574         pm_current = get_field(env->mmte, S_PM_CURRENT);
1575         break;
1576     case PRV_U:
1577         pm_current = get_field(env->mmte, U_PM_CURRENT);
1578         break;
1579     default:
1580         g_assert_not_reached();
1581     }
1582     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1583     return !pm_current;
1584 }
1585 
1586 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1587                                 target_ulong *val)
1588 {
1589     *val = env->mmte & MMTE_MASK;
1590     return RISCV_EXCP_NONE;
1591 }
1592 
1593 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1594                                  target_ulong val)
1595 {
1596     uint64_t mstatus;
1597     target_ulong wpri_val = val & MMTE_MASK;
1598 
1599     if (val != wpri_val) {
1600         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1601                       "MMTE: WPRI violation written 0x", val,
1602                       "vs expected 0x", wpri_val);
1603     }
1604     /* for machine mode pm.current is hardwired to 1 */
1605     wpri_val |= MMTE_M_PM_CURRENT;
1606 
1607     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1608     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1609     env->mmte = wpri_val | PM_EXT_DIRTY;
1610     riscv_cpu_update_mask(env);
1611 
1612     /* Set XS and SD bits, since PM CSRs are dirty */
1613     mstatus = env->mstatus | MSTATUS_XS;
1614     write_mstatus(env, csrno, mstatus);
1615     return RISCV_EXCP_NONE;
1616 }
1617 
1618 static RISCVException read_smte(CPURISCVState *env, int csrno,
1619                                 target_ulong *val)
1620 {
1621     *val = env->mmte & SMTE_MASK;
1622     return RISCV_EXCP_NONE;
1623 }
1624 
1625 static RISCVException write_smte(CPURISCVState *env, int csrno,
1626                                  target_ulong val)
1627 {
1628     target_ulong wpri_val = val & SMTE_MASK;
1629 
1630     if (val != wpri_val) {
1631         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1632                       "SMTE: WPRI violation written 0x", val,
1633                       "vs expected 0x", wpri_val);
1634     }
1635 
1636     /* if pm.current==0 we can't modify current PM CSRs */
1637     if (check_pm_current_disabled(env, csrno)) {
1638         return RISCV_EXCP_NONE;
1639     }
1640 
1641     wpri_val |= (env->mmte & ~SMTE_MASK);
1642     write_mmte(env, csrno, wpri_val);
1643     return RISCV_EXCP_NONE;
1644 }
1645 
1646 static RISCVException read_umte(CPURISCVState *env, int csrno,
1647                                 target_ulong *val)
1648 {
1649     *val = env->mmte & UMTE_MASK;
1650     return RISCV_EXCP_NONE;
1651 }
1652 
1653 static RISCVException write_umte(CPURISCVState *env, int csrno,
1654                                  target_ulong val)
1655 {
1656     target_ulong wpri_val = val & UMTE_MASK;
1657 
1658     if (val != wpri_val) {
1659         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1660                       "UMTE: WPRI violation written 0x", val,
1661                       "vs expected 0x", wpri_val);
1662     }
1663 
1664     if (check_pm_current_disabled(env, csrno)) {
1665         return RISCV_EXCP_NONE;
1666     }
1667 
1668     wpri_val |= (env->mmte & ~UMTE_MASK);
1669     write_mmte(env, csrno, wpri_val);
1670     return RISCV_EXCP_NONE;
1671 }
1672 
1673 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1674                                    target_ulong *val)
1675 {
1676     *val = env->mpmmask;
1677     return RISCV_EXCP_NONE;
1678 }
1679 
1680 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1681                                     target_ulong val)
1682 {
1683     uint64_t mstatus;
1684 
1685     env->mpmmask = val;
1686     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1687         env->cur_pmmask = val;
1688     }
1689     env->mmte |= PM_EXT_DIRTY;
1690 
1691     /* Set XS and SD bits, since PM CSRs are dirty */
1692     mstatus = env->mstatus | MSTATUS_XS;
1693     write_mstatus(env, csrno, mstatus);
1694     return RISCV_EXCP_NONE;
1695 }
1696 
1697 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1698                                    target_ulong *val)
1699 {
1700     *val = env->spmmask;
1701     return RISCV_EXCP_NONE;
1702 }
1703 
1704 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1705                                     target_ulong val)
1706 {
1707     uint64_t mstatus;
1708 
1709     /* if pm.current==0 we can't modify current PM CSRs */
1710     if (check_pm_current_disabled(env, csrno)) {
1711         return RISCV_EXCP_NONE;
1712     }
1713     env->spmmask = val;
1714     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1715         env->cur_pmmask = val;
1716     }
1717     env->mmte |= PM_EXT_DIRTY;
1718 
1719     /* Set XS and SD bits, since PM CSRs are dirty */
1720     mstatus = env->mstatus | MSTATUS_XS;
1721     write_mstatus(env, csrno, mstatus);
1722     return RISCV_EXCP_NONE;
1723 }
1724 
1725 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1726                                    target_ulong *val)
1727 {
1728     *val = env->upmmask;
1729     return RISCV_EXCP_NONE;
1730 }
1731 
1732 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1733                                     target_ulong val)
1734 {
1735     uint64_t mstatus;
1736 
1737     /* if pm.current==0 we can't modify current PM CSRs */
1738     if (check_pm_current_disabled(env, csrno)) {
1739         return RISCV_EXCP_NONE;
1740     }
1741     env->upmmask = val;
1742     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1743         env->cur_pmmask = val;
1744     }
1745     env->mmte |= PM_EXT_DIRTY;
1746 
1747     /* Set XS and SD bits, since PM CSRs are dirty */
1748     mstatus = env->mstatus | MSTATUS_XS;
1749     write_mstatus(env, csrno, mstatus);
1750     return RISCV_EXCP_NONE;
1751 }
1752 
1753 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1754                                    target_ulong *val)
1755 {
1756     *val = env->mpmbase;
1757     return RISCV_EXCP_NONE;
1758 }
1759 
1760 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1761                                     target_ulong val)
1762 {
1763     uint64_t mstatus;
1764 
1765     env->mpmbase = val;
1766     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1767         env->cur_pmbase = val;
1768     }
1769     env->mmte |= PM_EXT_DIRTY;
1770 
1771     /* Set XS and SD bits, since PM CSRs are dirty */
1772     mstatus = env->mstatus | MSTATUS_XS;
1773     write_mstatus(env, csrno, mstatus);
1774     return RISCV_EXCP_NONE;
1775 }
1776 
1777 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1778                                    target_ulong *val)
1779 {
1780     *val = env->spmbase;
1781     return RISCV_EXCP_NONE;
1782 }
1783 
1784 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1785                                     target_ulong val)
1786 {
1787     uint64_t mstatus;
1788 
1789     /* if pm.current==0 we can't modify current PM CSRs */
1790     if (check_pm_current_disabled(env, csrno)) {
1791         return RISCV_EXCP_NONE;
1792     }
1793     env->spmbase = val;
1794     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1795         env->cur_pmbase = val;
1796     }
1797     env->mmte |= PM_EXT_DIRTY;
1798 
1799     /* Set XS and SD bits, since PM CSRs are dirty */
1800     mstatus = env->mstatus | MSTATUS_XS;
1801     write_mstatus(env, csrno, mstatus);
1802     return RISCV_EXCP_NONE;
1803 }
1804 
1805 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1806                                    target_ulong *val)
1807 {
1808     *val = env->upmbase;
1809     return RISCV_EXCP_NONE;
1810 }
1811 
1812 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1813                                     target_ulong val)
1814 {
1815     uint64_t mstatus;
1816 
1817     /* if pm.current==0 we can't modify current PM CSRs */
1818     if (check_pm_current_disabled(env, csrno)) {
1819         return RISCV_EXCP_NONE;
1820     }
1821     env->upmbase = val;
1822     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1823         env->cur_pmbase = val;
1824     }
1825     env->mmte |= PM_EXT_DIRTY;
1826 
1827     /* Set XS and SD bits, since PM CSRs are dirty */
1828     mstatus = env->mstatus | MSTATUS_XS;
1829     write_mstatus(env, csrno, mstatus);
1830     return RISCV_EXCP_NONE;
1831 }
1832 
1833 #endif
1834 
1835 /*
1836  * riscv_csrrw - read and/or update control and status register
1837  *
1838  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1839  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1840  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1841  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1842  */
1843 
1844 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
1845                                                int csrno,
1846                                                bool write_mask,
1847                                                RISCVCPU *cpu)
1848 {
1849     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1850     int read_only = get_field(csrno, 0xC00) == 3;
1851 #if !defined(CONFIG_USER_ONLY)
1852     int effective_priv = env->priv;
1853 
1854     if (riscv_has_ext(env, RVH) &&
1855         env->priv == PRV_S &&
1856         !riscv_cpu_virt_enabled(env)) {
1857         /*
1858          * We are in S mode without virtualisation, therefore we are in HS Mode.
1859          * Add 1 to the effective privledge level to allow us to access the
1860          * Hypervisor CSRs.
1861          */
1862         effective_priv++;
1863     }
1864 
1865     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1866         return RISCV_EXCP_ILLEGAL_INST;
1867     }
1868 #endif
1869     if (write_mask && read_only) {
1870         return RISCV_EXCP_ILLEGAL_INST;
1871     }
1872 
1873     /* ensure the CSR extension is enabled. */
1874     if (!cpu->cfg.ext_icsr) {
1875         return RISCV_EXCP_ILLEGAL_INST;
1876     }
1877 
1878     /* check predicate */
1879     if (!csr_ops[csrno].predicate) {
1880         return RISCV_EXCP_ILLEGAL_INST;
1881     }
1882 
1883     return csr_ops[csrno].predicate(env, csrno);
1884 }
1885 
1886 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
1887                                        target_ulong *ret_value,
1888                                        target_ulong new_value,
1889                                        target_ulong write_mask)
1890 {
1891     RISCVException ret;
1892     target_ulong old_value;
1893 
1894     /* execute combined read/write operation if it exists */
1895     if (csr_ops[csrno].op) {
1896         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1897     }
1898 
1899     /* if no accessor exists then return failure */
1900     if (!csr_ops[csrno].read) {
1901         return RISCV_EXCP_ILLEGAL_INST;
1902     }
1903     /* read old value */
1904     ret = csr_ops[csrno].read(env, csrno, &old_value);
1905     if (ret != RISCV_EXCP_NONE) {
1906         return ret;
1907     }
1908 
1909     /* write value if writable and write mask set, otherwise drop writes */
1910     if (write_mask) {
1911         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1912         if (csr_ops[csrno].write) {
1913             ret = csr_ops[csrno].write(env, csrno, new_value);
1914             if (ret != RISCV_EXCP_NONE) {
1915                 return ret;
1916             }
1917         }
1918     }
1919 
1920     /* return old value */
1921     if (ret_value) {
1922         *ret_value = old_value;
1923     }
1924 
1925     return RISCV_EXCP_NONE;
1926 }
1927 
1928 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1929                            target_ulong *ret_value,
1930                            target_ulong new_value, target_ulong write_mask)
1931 {
1932     RISCVCPU *cpu = env_archcpu(env);
1933 
1934     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
1935     if (ret != RISCV_EXCP_NONE) {
1936         return ret;
1937     }
1938 
1939     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
1940 }
1941 
1942 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
1943                                         Int128 *ret_value,
1944                                         Int128 new_value,
1945                                         Int128 write_mask)
1946 {
1947     RISCVException ret;
1948     Int128 old_value;
1949 
1950     /* read old value */
1951     ret = csr_ops[csrno].read128(env, csrno, &old_value);
1952     if (ret != RISCV_EXCP_NONE) {
1953         return ret;
1954     }
1955 
1956     /* write value if writable and write mask set, otherwise drop writes */
1957     if (int128_nz(write_mask)) {
1958         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
1959                               int128_and(new_value, write_mask));
1960         if (csr_ops[csrno].write128) {
1961             ret = csr_ops[csrno].write128(env, csrno, new_value);
1962             if (ret != RISCV_EXCP_NONE) {
1963                 return ret;
1964             }
1965         } else if (csr_ops[csrno].write) {
1966             /* avoids having to write wrappers for all registers */
1967             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
1968             if (ret != RISCV_EXCP_NONE) {
1969                 return ret;
1970             }
1971         }
1972     }
1973 
1974     /* return old value */
1975     if (ret_value) {
1976         *ret_value = old_value;
1977     }
1978 
1979     return RISCV_EXCP_NONE;
1980 }
1981 
1982 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
1983                                 Int128 *ret_value,
1984                                 Int128 new_value, Int128 write_mask)
1985 {
1986     RISCVException ret;
1987     RISCVCPU *cpu = env_archcpu(env);
1988 
1989     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
1990     if (ret != RISCV_EXCP_NONE) {
1991         return ret;
1992     }
1993 
1994     if (csr_ops[csrno].read128) {
1995         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
1996     }
1997 
1998     /*
1999      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
2000      * at all defined.
2001      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
2002      * significant), for those, this fallback is correctly handling the accesses
2003      */
2004     target_ulong old_value;
2005     ret = riscv_csrrw_do64(env, csrno, &old_value,
2006                            int128_getlo(new_value),
2007                            int128_getlo(write_mask));
2008     if (ret == RISCV_EXCP_NONE && ret_value) {
2009         *ret_value = int128_make64(old_value);
2010     }
2011     return ret;
2012 }
2013 
2014 /*
2015  * Debugger support.  If not in user mode, set env->debugger before the
2016  * riscv_csrrw call and clear it after the call.
2017  */
2018 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
2019                                  target_ulong *ret_value,
2020                                  target_ulong new_value,
2021                                  target_ulong write_mask)
2022 {
2023     RISCVException ret;
2024 #if !defined(CONFIG_USER_ONLY)
2025     env->debugger = true;
2026 #endif
2027     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
2028 #if !defined(CONFIG_USER_ONLY)
2029     env->debugger = false;
2030 #endif
2031     return ret;
2032 }
2033 
2034 /* Control and Status Register function table */
2035 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
2036     /* User Floating-Point CSRs */
2037     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
2038     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
2039     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
2040     /* Vector CSRs */
2041     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
2042     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2043     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2044     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2045     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2046     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2047     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2048     /* User Timers and Counters */
2049     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2050     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2051     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2052     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2053 
2054     /*
2055      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2056      * rdtime callback is not provided by machine/platform emulation.
2057      */
2058     [CSR_TIME]  = { "time",  ctr,   read_time  },
2059     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2060 
2061 #if !defined(CONFIG_USER_ONLY)
2062     /* Machine Timers and Counters */
2063     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2064     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2065     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2066     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2067 
2068     /* Machine Information Registers */
2069     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2070     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2071     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2072     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2073 
2074     /* Machine Trap Setup */
2075     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2076                                                read_mstatus_i128                   },
2077     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2078                                                read_misa_i128                      },
2079     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
2080     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2081     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
2082     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2083     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2084 
2085     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2086 
2087     /* Machine Trap Handling */
2088     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2089                                          read_mscratch_i128, write_mscratch_i128   },
2090     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2091     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2092     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2093     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2094 
2095     /* Supervisor Trap Setup */
2096     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2097                                               read_sstatus_i128                 },
2098     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
2099     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2100     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2101 
2102     /* Supervisor Trap Handling */
2103     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2104                                           read_sscratch_i128, write_sscratch_i128  },
2105     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2106     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2107     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2108     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2109 
2110     /* Supervisor Protection and Translation */
2111     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2112 
2113     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2114     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2115     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
2116     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2117     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2118     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
2119     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2120     [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
2121     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2122     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2123     [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
2124     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2125     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2126     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2127 
2128     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2129     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2130     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
2131     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2132     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2133     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2134     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2135     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2136     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2137 
2138     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2139     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2140 
2141     /* Physical Memory Protection */
2142     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2143     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2144     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2145     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2146     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2147     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2148     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2149     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2150     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2151     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2152     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2153     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2154     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2155     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2156     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2157     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2158     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2159     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2160     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2161     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2162     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2163 
2164     /* User Pointer Masking */
2165     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2166     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2167     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2168     /* Machine Pointer Masking */
2169     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2170     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2171     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2172     /* Supervisor Pointer Masking */
2173     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2174     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2175     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2176 
2177     /* Performance Counters */
2178     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2179     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2180     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2181     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2182     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2183     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2184     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2185     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2186     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2187     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2188     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2189     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2190     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2191     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2192     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2193     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2194     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2195     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2196     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2197     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2198     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2199     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2200     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2201     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2202     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2203     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2204     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2205     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2206     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2207 
2208     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2209     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2210     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2211     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2212     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2213     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2214     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2215     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2216     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2217     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2218     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2219     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2220     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2221     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2222     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2223     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2224     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2225     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2226     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2227     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2228     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2229     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2230     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2231     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2232     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2233     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2234     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2235     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2236     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2237 
2238     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2239     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2240     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2241     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2242     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2243     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2244     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2245     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2246     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2247     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2248     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2249     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2250     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2251     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2252     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2253     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2254     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2255     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2256     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2257     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2258     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2259     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2260     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2261     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2262     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2263     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2264     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2265     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2266     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2267 
2268     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2269     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2270     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2271     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2272     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2273     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2274     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2275     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2276     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2277     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2278     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2279     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2280     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2281     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2282     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2283     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2284     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2285     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2286     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2287     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2288     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2289     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2290     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2291     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2292     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2293     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2294     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2295     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2296     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2297 
2298     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2299     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2300     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2301     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2302     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2303     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2304     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2305     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2306     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2307     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2308     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2309     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2310     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2311     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2312     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2313     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2314     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2315     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2316     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2317     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2318     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2319     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2320     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2321     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2322     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2323     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2324     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2325     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2326     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2327 #endif /* !CONFIG_USER_ONLY */
2328 };
2329