xref: /openbmc/qemu/target/riscv/csr.c (revision 3f4a5a53) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/timer.h"
23 #include "cpu.h"
24 #include "pmu.h"
25 #include "time_helper.h"
26 #include "qemu/main-loop.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/cpu-timers.h"
29 #include "qemu/guest-random.h"
30 #include "qapi/error.h"
31 
32 /* CSR function table public API */
33 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
34 {
35     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
36 }
37 
38 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
39 {
40     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
41 }
42 
43 /* Predicates */
44 #if !defined(CONFIG_USER_ONLY)
45 static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
46                                        uint64_t bit)
47 {
48     bool virt = riscv_cpu_virt_enabled(env);
49     CPUState *cs = env_cpu(env);
50     RISCVCPU *cpu = RISCV_CPU(cs);
51 
52     if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
53         return RISCV_EXCP_NONE;
54     }
55 
56     if (!(env->mstateen[index] & bit)) {
57         return RISCV_EXCP_ILLEGAL_INST;
58     }
59 
60     if (virt) {
61         if (!(env->hstateen[index] & bit)) {
62             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
63         }
64 
65         if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
66             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
67         }
68     }
69 
70     if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
71         if (!(env->sstateen[index] & bit)) {
72             return RISCV_EXCP_ILLEGAL_INST;
73         }
74     }
75 
76     return RISCV_EXCP_NONE;
77 }
78 #endif
79 
80 static RISCVException fs(CPURISCVState *env, int csrno)
81 {
82 #if !defined(CONFIG_USER_ONLY)
83     if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
84         !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
85         return RISCV_EXCP_ILLEGAL_INST;
86     }
87 #endif
88     return RISCV_EXCP_NONE;
89 }
90 
91 static RISCVException vs(CPURISCVState *env, int csrno)
92 {
93     CPUState *cs = env_cpu(env);
94     RISCVCPU *cpu = RISCV_CPU(cs);
95 
96     if (cpu->cfg.ext_zve32f) {
97 #if !defined(CONFIG_USER_ONLY)
98         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
99             return RISCV_EXCP_ILLEGAL_INST;
100         }
101 #endif
102         return RISCV_EXCP_NONE;
103     }
104     return RISCV_EXCP_ILLEGAL_INST;
105 }
106 
107 static RISCVException ctr(CPURISCVState *env, int csrno)
108 {
109 #if !defined(CONFIG_USER_ONLY)
110     CPUState *cs = env_cpu(env);
111     RISCVCPU *cpu = RISCV_CPU(cs);
112     int ctr_index;
113     target_ulong ctr_mask;
114     int base_csrno = CSR_CYCLE;
115     bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
116 
117     if (rv32 && csrno >= CSR_CYCLEH) {
118         /* Offset for RV32 hpmcounternh counters */
119         base_csrno += 0x80;
120     }
121     ctr_index = csrno - base_csrno;
122     ctr_mask = BIT(ctr_index);
123 
124     if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
125         (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
126         goto skip_ext_pmu_check;
127     }
128 
129     if (!(cpu->pmu_avail_ctrs & ctr_mask)) {
130         /* No counter is enabled in PMU or the counter is out of range */
131         return RISCV_EXCP_ILLEGAL_INST;
132     }
133 
134 skip_ext_pmu_check:
135 
136     if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
137         return RISCV_EXCP_ILLEGAL_INST;
138     }
139 
140     if (riscv_cpu_virt_enabled(env)) {
141         if (!get_field(env->hcounteren, ctr_mask) ||
142             (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
143             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
144         }
145     }
146 
147     if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&
148         !get_field(env->scounteren, ctr_mask)) {
149         return RISCV_EXCP_ILLEGAL_INST;
150     }
151 
152 #endif
153     return RISCV_EXCP_NONE;
154 }
155 
156 static RISCVException ctr32(CPURISCVState *env, int csrno)
157 {
158     if (riscv_cpu_mxl(env) != MXL_RV32) {
159         return RISCV_EXCP_ILLEGAL_INST;
160     }
161 
162     return ctr(env, csrno);
163 }
164 
165 #if !defined(CONFIG_USER_ONLY)
166 static RISCVException mctr(CPURISCVState *env, int csrno)
167 {
168     CPUState *cs = env_cpu(env);
169     RISCVCPU *cpu = RISCV_CPU(cs);
170     int ctr_index;
171     int base_csrno = CSR_MHPMCOUNTER3;
172 
173     if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) {
174         /* Offset for RV32 mhpmcounternh counters */
175         base_csrno += 0x80;
176     }
177     ctr_index = csrno - base_csrno;
178     if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
179         /* The PMU is not enabled or counter is out of range*/
180         return RISCV_EXCP_ILLEGAL_INST;
181     }
182 
183     return RISCV_EXCP_NONE;
184 }
185 
186 static RISCVException mctr32(CPURISCVState *env, int csrno)
187 {
188     if (riscv_cpu_mxl(env) != MXL_RV32) {
189         return RISCV_EXCP_ILLEGAL_INST;
190     }
191 
192     return mctr(env, csrno);
193 }
194 
195 static RISCVException sscofpmf(CPURISCVState *env, int csrno)
196 {
197     CPUState *cs = env_cpu(env);
198     RISCVCPU *cpu = RISCV_CPU(cs);
199 
200     if (!cpu->cfg.ext_sscofpmf) {
201         return RISCV_EXCP_ILLEGAL_INST;
202     }
203 
204     return RISCV_EXCP_NONE;
205 }
206 
207 static RISCVException any(CPURISCVState *env, int csrno)
208 {
209     return RISCV_EXCP_NONE;
210 }
211 
212 static RISCVException any32(CPURISCVState *env, int csrno)
213 {
214     if (riscv_cpu_mxl(env) != MXL_RV32) {
215         return RISCV_EXCP_ILLEGAL_INST;
216     }
217 
218     return any(env, csrno);
219 
220 }
221 
222 static int aia_any(CPURISCVState *env, int csrno)
223 {
224     RISCVCPU *cpu = env_archcpu(env);
225 
226     if (!cpu->cfg.ext_smaia) {
227         return RISCV_EXCP_ILLEGAL_INST;
228     }
229 
230     return any(env, csrno);
231 }
232 
233 static int aia_any32(CPURISCVState *env, int csrno)
234 {
235     RISCVCPU *cpu = env_archcpu(env);
236 
237     if (!cpu->cfg.ext_smaia) {
238         return RISCV_EXCP_ILLEGAL_INST;
239     }
240 
241     return any32(env, csrno);
242 }
243 
244 static RISCVException smode(CPURISCVState *env, int csrno)
245 {
246     if (riscv_has_ext(env, RVS)) {
247         return RISCV_EXCP_NONE;
248     }
249 
250     return RISCV_EXCP_ILLEGAL_INST;
251 }
252 
253 static int smode32(CPURISCVState *env, int csrno)
254 {
255     if (riscv_cpu_mxl(env) != MXL_RV32) {
256         return RISCV_EXCP_ILLEGAL_INST;
257     }
258 
259     return smode(env, csrno);
260 }
261 
262 static int aia_smode(CPURISCVState *env, int csrno)
263 {
264     RISCVCPU *cpu = env_archcpu(env);
265 
266     if (!cpu->cfg.ext_ssaia) {
267         return RISCV_EXCP_ILLEGAL_INST;
268     }
269 
270     return smode(env, csrno);
271 }
272 
273 static int aia_smode32(CPURISCVState *env, int csrno)
274 {
275     RISCVCPU *cpu = env_archcpu(env);
276 
277     if (!cpu->cfg.ext_ssaia) {
278         return RISCV_EXCP_ILLEGAL_INST;
279     }
280 
281     return smode32(env, csrno);
282 }
283 
284 static RISCVException hmode(CPURISCVState *env, int csrno)
285 {
286     if (riscv_has_ext(env, RVH)) {
287         return RISCV_EXCP_NONE;
288     }
289 
290     return RISCV_EXCP_ILLEGAL_INST;
291 }
292 
293 static RISCVException hmode32(CPURISCVState *env, int csrno)
294 {
295     if (riscv_cpu_mxl(env) != MXL_RV32) {
296         return RISCV_EXCP_ILLEGAL_INST;
297     }
298 
299     return hmode(env, csrno);
300 
301 }
302 
303 static RISCVException umode(CPURISCVState *env, int csrno)
304 {
305     if (riscv_has_ext(env, RVU)) {
306         return RISCV_EXCP_NONE;
307     }
308 
309     return RISCV_EXCP_ILLEGAL_INST;
310 }
311 
312 static RISCVException umode32(CPURISCVState *env, int csrno)
313 {
314     if (riscv_cpu_mxl(env) != MXL_RV32) {
315         return RISCV_EXCP_ILLEGAL_INST;
316     }
317 
318     return umode(env, csrno);
319 }
320 
321 static RISCVException mstateen(CPURISCVState *env, int csrno)
322 {
323     CPUState *cs = env_cpu(env);
324     RISCVCPU *cpu = RISCV_CPU(cs);
325 
326     if (!cpu->cfg.ext_smstateen) {
327         return RISCV_EXCP_ILLEGAL_INST;
328     }
329 
330     return any(env, csrno);
331 }
332 
333 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
334 {
335     CPUState *cs = env_cpu(env);
336     RISCVCPU *cpu = RISCV_CPU(cs);
337 
338     if (!cpu->cfg.ext_smstateen) {
339         return RISCV_EXCP_ILLEGAL_INST;
340     }
341 
342     if (env->priv < PRV_M) {
343         if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
344             return RISCV_EXCP_ILLEGAL_INST;
345         }
346     }
347 
348     return hmode(env, csrno);
349 }
350 
351 static RISCVException hstateen(CPURISCVState *env, int csrno)
352 {
353     return hstateen_pred(env, csrno, CSR_HSTATEEN0);
354 }
355 
356 static RISCVException hstateenh(CPURISCVState *env, int csrno)
357 {
358     return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
359 }
360 
361 static RISCVException sstateen(CPURISCVState *env, int csrno)
362 {
363     bool virt = riscv_cpu_virt_enabled(env);
364     int index = csrno - CSR_SSTATEEN0;
365     CPUState *cs = env_cpu(env);
366     RISCVCPU *cpu = RISCV_CPU(cs);
367 
368     if (!cpu->cfg.ext_smstateen) {
369         return RISCV_EXCP_ILLEGAL_INST;
370     }
371 
372     if (env->priv < PRV_M) {
373         if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
374             return RISCV_EXCP_ILLEGAL_INST;
375         }
376 
377         if (virt) {
378             if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
379                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
380             }
381         }
382     }
383 
384     return smode(env, csrno);
385 }
386 
387 /* Checks if PointerMasking registers could be accessed */
388 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
389 {
390     /* Check if j-ext is present */
391     if (riscv_has_ext(env, RVJ)) {
392         return RISCV_EXCP_NONE;
393     }
394     return RISCV_EXCP_ILLEGAL_INST;
395 }
396 
397 static int aia_hmode(CPURISCVState *env, int csrno)
398 {
399     RISCVCPU *cpu = env_archcpu(env);
400 
401     if (!cpu->cfg.ext_ssaia) {
402         return RISCV_EXCP_ILLEGAL_INST;
403      }
404 
405      return hmode(env, csrno);
406 }
407 
408 static int aia_hmode32(CPURISCVState *env, int csrno)
409 {
410     RISCVCPU *cpu = env_archcpu(env);
411 
412     if (!cpu->cfg.ext_ssaia) {
413         return RISCV_EXCP_ILLEGAL_INST;
414     }
415 
416     return hmode32(env, csrno);
417 }
418 
419 static RISCVException pmp(CPURISCVState *env, int csrno)
420 {
421     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
422         return RISCV_EXCP_NONE;
423     }
424 
425     return RISCV_EXCP_ILLEGAL_INST;
426 }
427 
428 static RISCVException epmp(CPURISCVState *env, int csrno)
429 {
430     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
431         return RISCV_EXCP_NONE;
432     }
433 
434     return RISCV_EXCP_ILLEGAL_INST;
435 }
436 
437 static RISCVException debug(CPURISCVState *env, int csrno)
438 {
439     if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
440         return RISCV_EXCP_NONE;
441     }
442 
443     return RISCV_EXCP_ILLEGAL_INST;
444 }
445 #endif
446 
447 static RISCVException seed(CPURISCVState *env, int csrno)
448 {
449     RISCVCPU *cpu = env_archcpu(env);
450 
451     if (!cpu->cfg.ext_zkr) {
452         return RISCV_EXCP_ILLEGAL_INST;
453     }
454 
455 #if !defined(CONFIG_USER_ONLY)
456     /*
457      * With a CSR read-write instruction:
458      * 1) The seed CSR is always available in machine mode as normal.
459      * 2) Attempted access to seed from virtual modes VS and VU always raises
460      * an exception(virtual instruction exception only if mseccfg.sseed=1).
461      * 3) Without the corresponding access control bit set to 1, any attempted
462      * access to seed from U, S or HS modes will raise an illegal instruction
463      * exception.
464      */
465     if (env->priv == PRV_M) {
466         return RISCV_EXCP_NONE;
467     } else if (riscv_cpu_virt_enabled(env)) {
468         if (env->mseccfg & MSECCFG_SSEED) {
469             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
470         } else {
471             return RISCV_EXCP_ILLEGAL_INST;
472         }
473     } else {
474         if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
475             return RISCV_EXCP_NONE;
476         } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
477             return RISCV_EXCP_NONE;
478         } else {
479             return RISCV_EXCP_ILLEGAL_INST;
480         }
481     }
482 #else
483     return RISCV_EXCP_NONE;
484 #endif
485 }
486 
487 /* User Floating-Point CSRs */
488 static RISCVException read_fflags(CPURISCVState *env, int csrno,
489                                   target_ulong *val)
490 {
491     *val = riscv_cpu_get_fflags(env);
492     return RISCV_EXCP_NONE;
493 }
494 
495 static RISCVException write_fflags(CPURISCVState *env, int csrno,
496                                    target_ulong val)
497 {
498 #if !defined(CONFIG_USER_ONLY)
499     if (riscv_has_ext(env, RVF)) {
500         env->mstatus |= MSTATUS_FS;
501     }
502 #endif
503     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
504     return RISCV_EXCP_NONE;
505 }
506 
507 static RISCVException read_frm(CPURISCVState *env, int csrno,
508                                target_ulong *val)
509 {
510     *val = env->frm;
511     return RISCV_EXCP_NONE;
512 }
513 
514 static RISCVException write_frm(CPURISCVState *env, int csrno,
515                                 target_ulong val)
516 {
517 #if !defined(CONFIG_USER_ONLY)
518     if (riscv_has_ext(env, RVF)) {
519         env->mstatus |= MSTATUS_FS;
520     }
521 #endif
522     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
523     return RISCV_EXCP_NONE;
524 }
525 
526 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
527                                 target_ulong *val)
528 {
529     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
530         | (env->frm << FSR_RD_SHIFT);
531     return RISCV_EXCP_NONE;
532 }
533 
534 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
535                                  target_ulong val)
536 {
537 #if !defined(CONFIG_USER_ONLY)
538     if (riscv_has_ext(env, RVF)) {
539         env->mstatus |= MSTATUS_FS;
540     }
541 #endif
542     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
543     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
544     return RISCV_EXCP_NONE;
545 }
546 
547 static RISCVException read_vtype(CPURISCVState *env, int csrno,
548                                  target_ulong *val)
549 {
550     uint64_t vill;
551     switch (env->xl) {
552     case MXL_RV32:
553         vill = (uint32_t)env->vill << 31;
554         break;
555     case MXL_RV64:
556         vill = (uint64_t)env->vill << 63;
557         break;
558     default:
559         g_assert_not_reached();
560     }
561     *val = (target_ulong)vill | env->vtype;
562     return RISCV_EXCP_NONE;
563 }
564 
565 static RISCVException read_vl(CPURISCVState *env, int csrno,
566                               target_ulong *val)
567 {
568     *val = env->vl;
569     return RISCV_EXCP_NONE;
570 }
571 
572 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
573 {
574     *val = env_archcpu(env)->cfg.vlen >> 3;
575     return RISCV_EXCP_NONE;
576 }
577 
578 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
579                                 target_ulong *val)
580 {
581     *val = env->vxrm;
582     return RISCV_EXCP_NONE;
583 }
584 
585 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
586                                  target_ulong val)
587 {
588 #if !defined(CONFIG_USER_ONLY)
589     env->mstatus |= MSTATUS_VS;
590 #endif
591     env->vxrm = val;
592     return RISCV_EXCP_NONE;
593 }
594 
595 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
596                                  target_ulong *val)
597 {
598     *val = env->vxsat;
599     return RISCV_EXCP_NONE;
600 }
601 
602 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
603                                   target_ulong val)
604 {
605 #if !defined(CONFIG_USER_ONLY)
606     env->mstatus |= MSTATUS_VS;
607 #endif
608     env->vxsat = val;
609     return RISCV_EXCP_NONE;
610 }
611 
612 static RISCVException read_vstart(CPURISCVState *env, int csrno,
613                                   target_ulong *val)
614 {
615     *val = env->vstart;
616     return RISCV_EXCP_NONE;
617 }
618 
619 static RISCVException write_vstart(CPURISCVState *env, int csrno,
620                                    target_ulong val)
621 {
622 #if !defined(CONFIG_USER_ONLY)
623     env->mstatus |= MSTATUS_VS;
624 #endif
625     /*
626      * The vstart CSR is defined to have only enough writable bits
627      * to hold the largest element index, i.e. lg2(VLEN) bits.
628      */
629     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
630     return RISCV_EXCP_NONE;
631 }
632 
633 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
634 {
635     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
636     return RISCV_EXCP_NONE;
637 }
638 
639 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
640 {
641 #if !defined(CONFIG_USER_ONLY)
642     env->mstatus |= MSTATUS_VS;
643 #endif
644     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
645     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
646     return RISCV_EXCP_NONE;
647 }
648 
649 /* User Timers and Counters */
650 static target_ulong get_ticks(bool shift)
651 {
652     int64_t val;
653     target_ulong result;
654 
655 #if !defined(CONFIG_USER_ONLY)
656     if (icount_enabled()) {
657         val = icount_get();
658     } else {
659         val = cpu_get_host_ticks();
660     }
661 #else
662     val = cpu_get_host_ticks();
663 #endif
664 
665     if (shift) {
666         result = val >> 32;
667     } else {
668         result = val;
669     }
670 
671     return result;
672 }
673 
674 #if defined(CONFIG_USER_ONLY)
675 static RISCVException read_time(CPURISCVState *env, int csrno,
676                                 target_ulong *val)
677 {
678     *val = cpu_get_host_ticks();
679     return RISCV_EXCP_NONE;
680 }
681 
682 static RISCVException read_timeh(CPURISCVState *env, int csrno,
683                                  target_ulong *val)
684 {
685     *val = cpu_get_host_ticks() >> 32;
686     return RISCV_EXCP_NONE;
687 }
688 
689 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
690 {
691     *val = get_ticks(false);
692     return RISCV_EXCP_NONE;
693 }
694 
695 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
696 {
697     *val = get_ticks(true);
698     return RISCV_EXCP_NONE;
699 }
700 
701 #else /* CONFIG_USER_ONLY */
702 
703 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
704 {
705     int evt_index = csrno - CSR_MCOUNTINHIBIT;
706 
707     *val = env->mhpmevent_val[evt_index];
708 
709     return RISCV_EXCP_NONE;
710 }
711 
712 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
713 {
714     int evt_index = csrno - CSR_MCOUNTINHIBIT;
715     uint64_t mhpmevt_val = val;
716 
717     env->mhpmevent_val[evt_index] = val;
718 
719     if (riscv_cpu_mxl(env) == MXL_RV32) {
720         mhpmevt_val = mhpmevt_val |
721                       ((uint64_t)env->mhpmeventh_val[evt_index] << 32);
722     }
723     riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
724 
725     return RISCV_EXCP_NONE;
726 }
727 
728 static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val)
729 {
730     int evt_index = csrno - CSR_MHPMEVENT3H + 3;
731 
732     *val = env->mhpmeventh_val[evt_index];
733 
734     return RISCV_EXCP_NONE;
735 }
736 
737 static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val)
738 {
739     int evt_index = csrno - CSR_MHPMEVENT3H + 3;
740     uint64_t mhpmevth_val = val;
741     uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
742 
743     mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
744     env->mhpmeventh_val[evt_index] = val;
745 
746     riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
747 
748     return RISCV_EXCP_NONE;
749 }
750 
751 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
752 {
753     int ctr_idx = csrno - CSR_MCYCLE;
754     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
755     uint64_t mhpmctr_val = val;
756 
757     counter->mhpmcounter_val = val;
758     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
759         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
760         counter->mhpmcounter_prev = get_ticks(false);
761         if (ctr_idx > 2) {
762             if (riscv_cpu_mxl(env) == MXL_RV32) {
763                 mhpmctr_val = mhpmctr_val |
764                               ((uint64_t)counter->mhpmcounterh_val << 32);
765             }
766             riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
767         }
768      } else {
769         /* Other counters can keep incrementing from the given value */
770         counter->mhpmcounter_prev = val;
771     }
772 
773     return RISCV_EXCP_NONE;
774 }
775 
776 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
777 {
778     int ctr_idx = csrno - CSR_MCYCLEH;
779     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
780     uint64_t mhpmctr_val = counter->mhpmcounter_val;
781     uint64_t mhpmctrh_val = val;
782 
783     counter->mhpmcounterh_val = val;
784     mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);
785     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
786         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
787         counter->mhpmcounterh_prev = get_ticks(true);
788         if (ctr_idx > 2) {
789             riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
790         }
791     } else {
792         counter->mhpmcounterh_prev = val;
793     }
794 
795     return RISCV_EXCP_NONE;
796 }
797 
798 static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
799                                          bool upper_half, uint32_t ctr_idx)
800 {
801     PMUCTRState counter = env->pmu_ctrs[ctr_idx];
802     target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev :
803                                          counter.mhpmcounter_prev;
804     target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val :
805                                         counter.mhpmcounter_val;
806 
807     if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
808         /**
809          * Counter should not increment if inhibit bit is set. We can't really
810          * stop the icount counting. Just return the counter value written by
811          * the supervisor to indicate that counter was not incremented.
812          */
813         if (!counter.started) {
814             *val = ctr_val;
815             return RISCV_EXCP_NONE;
816         } else {
817             /* Mark that the counter has been stopped */
818             counter.started = false;
819         }
820     }
821 
822     /**
823      * The kernel computes the perf delta by subtracting the current value from
824      * the value it initialized previously (ctr_val).
825      */
826     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
827         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
828         *val = get_ticks(upper_half) - ctr_prev + ctr_val;
829     } else {
830         *val = ctr_val;
831     }
832 
833     return RISCV_EXCP_NONE;
834 }
835 
836 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
837 {
838     uint16_t ctr_index;
839 
840     if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
841         ctr_index = csrno - CSR_MCYCLE;
842     } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
843         ctr_index = csrno - CSR_CYCLE;
844     } else {
845         return RISCV_EXCP_ILLEGAL_INST;
846     }
847 
848     return riscv_pmu_read_ctr(env, val, false, ctr_index);
849 }
850 
851 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
852 {
853     uint16_t ctr_index;
854 
855     if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
856         ctr_index = csrno - CSR_MCYCLEH;
857     } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
858         ctr_index = csrno - CSR_CYCLEH;
859     } else {
860         return RISCV_EXCP_ILLEGAL_INST;
861     }
862 
863     return riscv_pmu_read_ctr(env, val, true, ctr_index);
864 }
865 
866 static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
867 {
868     int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
869     int i;
870     *val = 0;
871     target_ulong *mhpm_evt_val;
872     uint64_t of_bit_mask;
873 
874     if (riscv_cpu_mxl(env) == MXL_RV32) {
875         mhpm_evt_val = env->mhpmeventh_val;
876         of_bit_mask = MHPMEVENTH_BIT_OF;
877     } else {
878         mhpm_evt_val = env->mhpmevent_val;
879         of_bit_mask = MHPMEVENT_BIT_OF;
880     }
881 
882     for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
883         if ((get_field(env->mcounteren, BIT(i))) &&
884             (mhpm_evt_val[i] & of_bit_mask)) {
885                     *val |= BIT(i);
886             }
887     }
888 
889     return RISCV_EXCP_NONE;
890 }
891 
892 static RISCVException read_time(CPURISCVState *env, int csrno,
893                                 target_ulong *val)
894 {
895     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
896 
897     if (!env->rdtime_fn) {
898         return RISCV_EXCP_ILLEGAL_INST;
899     }
900 
901     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
902     return RISCV_EXCP_NONE;
903 }
904 
905 static RISCVException read_timeh(CPURISCVState *env, int csrno,
906                                  target_ulong *val)
907 {
908     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
909 
910     if (!env->rdtime_fn) {
911         return RISCV_EXCP_ILLEGAL_INST;
912     }
913 
914     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
915     return RISCV_EXCP_NONE;
916 }
917 
918 static RISCVException sstc(CPURISCVState *env, int csrno)
919 {
920     CPUState *cs = env_cpu(env);
921     RISCVCPU *cpu = RISCV_CPU(cs);
922     bool hmode_check = false;
923 
924     if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
925         return RISCV_EXCP_ILLEGAL_INST;
926     }
927 
928     if (env->priv == PRV_M) {
929         return RISCV_EXCP_NONE;
930     }
931 
932     /*
933      * No need of separate function for rv32 as menvcfg stores both menvcfg
934      * menvcfgh for RV32.
935      */
936     if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
937           get_field(env->menvcfg, MENVCFG_STCE))) {
938         return RISCV_EXCP_ILLEGAL_INST;
939     }
940 
941     if (riscv_cpu_virt_enabled(env)) {
942         if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
943               get_field(env->henvcfg, HENVCFG_STCE))) {
944             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
945         }
946     }
947 
948     if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
949         hmode_check = true;
950     }
951 
952     return hmode_check ? hmode(env, csrno) : smode(env, csrno);
953 }
954 
955 static RISCVException sstc_32(CPURISCVState *env, int csrno)
956 {
957     if (riscv_cpu_mxl(env) != MXL_RV32) {
958         return RISCV_EXCP_ILLEGAL_INST;
959     }
960 
961     return sstc(env, csrno);
962 }
963 
964 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
965                                     target_ulong *val)
966 {
967     *val = env->vstimecmp;
968 
969     return RISCV_EXCP_NONE;
970 }
971 
972 static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
973                                     target_ulong *val)
974 {
975     *val = env->vstimecmp >> 32;
976 
977     return RISCV_EXCP_NONE;
978 }
979 
980 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
981                                     target_ulong val)
982 {
983     RISCVCPU *cpu = env_archcpu(env);
984 
985     if (riscv_cpu_mxl(env) == MXL_RV32) {
986         env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
987     } else {
988         env->vstimecmp = val;
989     }
990 
991     riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
992                               env->htimedelta, MIP_VSTIP);
993 
994     return RISCV_EXCP_NONE;
995 }
996 
997 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
998                                     target_ulong val)
999 {
1000     RISCVCPU *cpu = env_archcpu(env);
1001 
1002     env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
1003     riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
1004                               env->htimedelta, MIP_VSTIP);
1005 
1006     return RISCV_EXCP_NONE;
1007 }
1008 
1009 static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
1010                                     target_ulong *val)
1011 {
1012     if (riscv_cpu_virt_enabled(env)) {
1013         *val = env->vstimecmp;
1014     } else {
1015         *val = env->stimecmp;
1016     }
1017 
1018     return RISCV_EXCP_NONE;
1019 }
1020 
1021 static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
1022                                     target_ulong *val)
1023 {
1024     if (riscv_cpu_virt_enabled(env)) {
1025         *val = env->vstimecmp >> 32;
1026     } else {
1027         *val = env->stimecmp >> 32;
1028     }
1029 
1030     return RISCV_EXCP_NONE;
1031 }
1032 
1033 static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
1034                                     target_ulong val)
1035 {
1036     RISCVCPU *cpu = env_archcpu(env);
1037 
1038     if (riscv_cpu_virt_enabled(env)) {
1039         if (env->hvictl & HVICTL_VTI) {
1040             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1041         }
1042         return write_vstimecmp(env, csrno, val);
1043     }
1044 
1045     if (riscv_cpu_mxl(env) == MXL_RV32) {
1046         env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val);
1047     } else {
1048         env->stimecmp = val;
1049     }
1050 
1051     riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
1052 
1053     return RISCV_EXCP_NONE;
1054 }
1055 
1056 static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
1057                                     target_ulong val)
1058 {
1059     RISCVCPU *cpu = env_archcpu(env);
1060 
1061     if (riscv_cpu_virt_enabled(env)) {
1062         if (env->hvictl & HVICTL_VTI) {
1063             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1064         }
1065         return write_vstimecmph(env, csrno, val);
1066     }
1067 
1068     env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
1069     riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
1070 
1071     return RISCV_EXCP_NONE;
1072 }
1073 
1074 /* Machine constants */
1075 
1076 #define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
1077 #define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \
1078                                       MIP_LCOFIP))
1079 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
1080 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
1081 
1082 #define VSTOPI_NUM_SRCS 5
1083 
1084 static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
1085                                            VS_MODE_INTERRUPTS;
1086 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
1087 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
1088                                      HS_MODE_INTERRUPTS;
1089 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1090                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1091                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1092                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1093                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1094                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1095                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1096                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1097                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
1098                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
1099                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1100                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
1101                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1102                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1103                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1104                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1105                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1106                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1107                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1108 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
1109     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
1110       (1ULL << (RISCV_EXCP_VS_ECALL)) |
1111       (1ULL << (RISCV_EXCP_M_ECALL)) |
1112       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
1113       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
1114       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
1115       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
1116 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
1117     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
1118     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
1119 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
1120                                               SIP_LCOFIP;
1121 static const target_ulong hip_writable_mask = MIP_VSSIP;
1122 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
1123 static const target_ulong vsip_writable_mask = MIP_VSSIP;
1124 
1125 static const char valid_vm_1_10_32[16] = {
1126     [VM_1_10_MBARE] = 1,
1127     [VM_1_10_SV32] = 1
1128 };
1129 
1130 static const char valid_vm_1_10_64[16] = {
1131     [VM_1_10_MBARE] = 1,
1132     [VM_1_10_SV39] = 1,
1133     [VM_1_10_SV48] = 1,
1134     [VM_1_10_SV57] = 1
1135 };
1136 
1137 /* Machine Information Registers */
1138 static RISCVException read_zero(CPURISCVState *env, int csrno,
1139                                 target_ulong *val)
1140 {
1141     *val = 0;
1142     return RISCV_EXCP_NONE;
1143 }
1144 
1145 static RISCVException write_ignore(CPURISCVState *env, int csrno,
1146                                    target_ulong val)
1147 {
1148     return RISCV_EXCP_NONE;
1149 }
1150 
1151 static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
1152                                      target_ulong *val)
1153 {
1154     CPUState *cs = env_cpu(env);
1155     RISCVCPU *cpu = RISCV_CPU(cs);
1156 
1157     *val = cpu->cfg.mvendorid;
1158     return RISCV_EXCP_NONE;
1159 }
1160 
1161 static RISCVException read_marchid(CPURISCVState *env, int csrno,
1162                                    target_ulong *val)
1163 {
1164     CPUState *cs = env_cpu(env);
1165     RISCVCPU *cpu = RISCV_CPU(cs);
1166 
1167     *val = cpu->cfg.marchid;
1168     return RISCV_EXCP_NONE;
1169 }
1170 
1171 static RISCVException read_mimpid(CPURISCVState *env, int csrno,
1172                                   target_ulong *val)
1173 {
1174     CPUState *cs = env_cpu(env);
1175     RISCVCPU *cpu = RISCV_CPU(cs);
1176 
1177     *val = cpu->cfg.mimpid;
1178     return RISCV_EXCP_NONE;
1179 }
1180 
1181 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
1182                                    target_ulong *val)
1183 {
1184     *val = env->mhartid;
1185     return RISCV_EXCP_NONE;
1186 }
1187 
1188 /* Machine Trap Setup */
1189 
1190 /* We do not store SD explicitly, only compute it on demand. */
1191 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
1192 {
1193     if ((status & MSTATUS_FS) == MSTATUS_FS ||
1194         (status & MSTATUS_VS) == MSTATUS_VS ||
1195         (status & MSTATUS_XS) == MSTATUS_XS) {
1196         switch (xl) {
1197         case MXL_RV32:
1198             return status | MSTATUS32_SD;
1199         case MXL_RV64:
1200             return status | MSTATUS64_SD;
1201         case MXL_RV128:
1202             return MSTATUSH128_SD;
1203         default:
1204             g_assert_not_reached();
1205         }
1206     }
1207     return status;
1208 }
1209 
1210 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
1211                                    target_ulong *val)
1212 {
1213     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
1214     return RISCV_EXCP_NONE;
1215 }
1216 
1217 static int validate_vm(CPURISCVState *env, target_ulong vm)
1218 {
1219     if (riscv_cpu_mxl(env) == MXL_RV32) {
1220         return valid_vm_1_10_32[vm & 0xf];
1221     } else {
1222         return valid_vm_1_10_64[vm & 0xf];
1223     }
1224 }
1225 
1226 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
1227                                     target_ulong val)
1228 {
1229     uint64_t mstatus = env->mstatus;
1230     uint64_t mask = 0;
1231     RISCVMXL xl = riscv_cpu_mxl(env);
1232 
1233     /* flush tlb on mstatus fields that affect VM */
1234     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
1235             MSTATUS_MPRV | MSTATUS_SUM)) {
1236         tlb_flush(env_cpu(env));
1237     }
1238     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
1239         MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
1240         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
1241         MSTATUS_TW | MSTATUS_VS;
1242 
1243     if (riscv_has_ext(env, RVF)) {
1244         mask |= MSTATUS_FS;
1245     }
1246 
1247     if (xl != MXL_RV32 || env->debugger) {
1248         /*
1249          * RV32: MPV and GVA are not in mstatus. The current plan is to
1250          * add them to mstatush. For now, we just don't support it.
1251          */
1252         mask |= MSTATUS_MPV | MSTATUS_GVA;
1253         if ((val & MSTATUS64_UXL) != 0) {
1254             mask |= MSTATUS64_UXL;
1255         }
1256     }
1257 
1258     mstatus = (mstatus & ~mask) | (val & mask);
1259 
1260     if (xl > MXL_RV32) {
1261         /* SXL field is for now read only */
1262         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
1263     }
1264     env->mstatus = mstatus;
1265     env->xl = cpu_recompute_xl(env);
1266 
1267     return RISCV_EXCP_NONE;
1268 }
1269 
1270 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
1271                                     target_ulong *val)
1272 {
1273     *val = env->mstatus >> 32;
1274     return RISCV_EXCP_NONE;
1275 }
1276 
1277 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
1278                                      target_ulong val)
1279 {
1280     uint64_t valh = (uint64_t)val << 32;
1281     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
1282 
1283     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
1284         tlb_flush(env_cpu(env));
1285     }
1286 
1287     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
1288 
1289     return RISCV_EXCP_NONE;
1290 }
1291 
1292 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
1293                                         Int128 *val)
1294 {
1295     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
1296     return RISCV_EXCP_NONE;
1297 }
1298 
1299 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
1300                                      Int128 *val)
1301 {
1302     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
1303     return RISCV_EXCP_NONE;
1304 }
1305 
1306 static RISCVException read_misa(CPURISCVState *env, int csrno,
1307                                 target_ulong *val)
1308 {
1309     target_ulong misa;
1310 
1311     switch (env->misa_mxl) {
1312     case MXL_RV32:
1313         misa = (target_ulong)MXL_RV32 << 30;
1314         break;
1315 #ifdef TARGET_RISCV64
1316     case MXL_RV64:
1317         misa = (target_ulong)MXL_RV64 << 62;
1318         break;
1319 #endif
1320     default:
1321         g_assert_not_reached();
1322     }
1323 
1324     *val = misa | env->misa_ext;
1325     return RISCV_EXCP_NONE;
1326 }
1327 
1328 static RISCVException write_misa(CPURISCVState *env, int csrno,
1329                                  target_ulong val)
1330 {
1331     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
1332         /* drop write to misa */
1333         return RISCV_EXCP_NONE;
1334     }
1335 
1336     /* 'I' or 'E' must be present */
1337     if (!(val & (RVI | RVE))) {
1338         /* It is not, drop write to misa */
1339         return RISCV_EXCP_NONE;
1340     }
1341 
1342     /* 'E' excludes all other extensions */
1343     if (val & RVE) {
1344         /* when we support 'E' we can do "val = RVE;" however
1345          * for now we just drop writes if 'E' is present.
1346          */
1347         return RISCV_EXCP_NONE;
1348     }
1349 
1350     /*
1351      * misa.MXL writes are not supported by QEMU.
1352      * Drop writes to those bits.
1353      */
1354 
1355     /* Mask extensions that are not supported by this hart */
1356     val &= env->misa_ext_mask;
1357 
1358     /* Mask extensions that are not supported by QEMU */
1359     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
1360 
1361     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
1362     if ((val & RVD) && !(val & RVF)) {
1363         val &= ~RVD;
1364     }
1365 
1366     /* Suppress 'C' if next instruction is not aligned
1367      * TODO: this should check next_pc
1368      */
1369     if ((val & RVC) && (GETPC() & ~3) != 0) {
1370         val &= ~RVC;
1371     }
1372 
1373     /* If nothing changed, do nothing. */
1374     if (val == env->misa_ext) {
1375         return RISCV_EXCP_NONE;
1376     }
1377 
1378     if (!(val & RVF)) {
1379         env->mstatus &= ~MSTATUS_FS;
1380     }
1381 
1382     /* flush translation cache */
1383     tb_flush(env_cpu(env));
1384     env->misa_ext = val;
1385     env->xl = riscv_cpu_mxl(env);
1386     return RISCV_EXCP_NONE;
1387 }
1388 
1389 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
1390                                    target_ulong *val)
1391 {
1392     *val = env->medeleg;
1393     return RISCV_EXCP_NONE;
1394 }
1395 
1396 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
1397                                     target_ulong val)
1398 {
1399     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
1400     return RISCV_EXCP_NONE;
1401 }
1402 
1403 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
1404                                     uint64_t *ret_val,
1405                                     uint64_t new_val, uint64_t wr_mask)
1406 {
1407     uint64_t mask = wr_mask & delegable_ints;
1408 
1409     if (ret_val) {
1410         *ret_val = env->mideleg;
1411     }
1412 
1413     env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
1414 
1415     if (riscv_has_ext(env, RVH)) {
1416         env->mideleg |= HS_MODE_INTERRUPTS;
1417     }
1418 
1419     return RISCV_EXCP_NONE;
1420 }
1421 
1422 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
1423                                   target_ulong *ret_val,
1424                                   target_ulong new_val, target_ulong wr_mask)
1425 {
1426     uint64_t rval;
1427     RISCVException ret;
1428 
1429     ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
1430     if (ret_val) {
1431         *ret_val = rval;
1432     }
1433 
1434     return ret;
1435 }
1436 
1437 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
1438                                    target_ulong *ret_val,
1439                                    target_ulong new_val,
1440                                    target_ulong wr_mask)
1441 {
1442     uint64_t rval;
1443     RISCVException ret;
1444 
1445     ret = rmw_mideleg64(env, csrno, &rval,
1446         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1447     if (ret_val) {
1448         *ret_val = rval >> 32;
1449     }
1450 
1451     return ret;
1452 }
1453 
1454 static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
1455                                 uint64_t *ret_val,
1456                                 uint64_t new_val, uint64_t wr_mask)
1457 {
1458     uint64_t mask = wr_mask & all_ints;
1459 
1460     if (ret_val) {
1461         *ret_val = env->mie;
1462     }
1463 
1464     env->mie = (env->mie & ~mask) | (new_val & mask);
1465 
1466     if (!riscv_has_ext(env, RVH)) {
1467         env->mie &= ~((uint64_t)MIP_SGEIP);
1468     }
1469 
1470     return RISCV_EXCP_NONE;
1471 }
1472 
1473 static RISCVException rmw_mie(CPURISCVState *env, int csrno,
1474                               target_ulong *ret_val,
1475                               target_ulong new_val, target_ulong wr_mask)
1476 {
1477     uint64_t rval;
1478     RISCVException ret;
1479 
1480     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
1481     if (ret_val) {
1482         *ret_val = rval;
1483     }
1484 
1485     return ret;
1486 }
1487 
1488 static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
1489                                target_ulong *ret_val,
1490                                target_ulong new_val, target_ulong wr_mask)
1491 {
1492     uint64_t rval;
1493     RISCVException ret;
1494 
1495     ret = rmw_mie64(env, csrno, &rval,
1496         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1497     if (ret_val) {
1498         *ret_val = rval >> 32;
1499     }
1500 
1501     return ret;
1502 }
1503 
1504 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
1505 {
1506     int irq;
1507     uint8_t iprio;
1508 
1509     irq = riscv_cpu_mirq_pending(env);
1510     if (irq <= 0 || irq > 63) {
1511         *val = 0;
1512     } else {
1513         iprio = env->miprio[irq];
1514         if (!iprio) {
1515             if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
1516                 iprio = IPRIO_MMAXIPRIO;
1517             }
1518         }
1519         *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
1520         *val |= iprio;
1521     }
1522 
1523     return RISCV_EXCP_NONE;
1524 }
1525 
1526 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
1527 {
1528     if (!riscv_cpu_virt_enabled(env)) {
1529         return csrno;
1530     }
1531 
1532     switch (csrno) {
1533     case CSR_SISELECT:
1534         return CSR_VSISELECT;
1535     case CSR_SIREG:
1536         return CSR_VSIREG;
1537     case CSR_STOPEI:
1538         return CSR_VSTOPEI;
1539     default:
1540         return csrno;
1541     };
1542 }
1543 
1544 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
1545                         target_ulong new_val, target_ulong wr_mask)
1546 {
1547     target_ulong *iselect;
1548 
1549     /* Translate CSR number for VS-mode */
1550     csrno = aia_xlate_vs_csrno(env, csrno);
1551 
1552     /* Find the iselect CSR based on CSR number */
1553     switch (csrno) {
1554     case CSR_MISELECT:
1555         iselect = &env->miselect;
1556         break;
1557     case CSR_SISELECT:
1558         iselect = &env->siselect;
1559         break;
1560     case CSR_VSISELECT:
1561         iselect = &env->vsiselect;
1562         break;
1563     default:
1564          return RISCV_EXCP_ILLEGAL_INST;
1565     };
1566 
1567     if (val) {
1568         *val = *iselect;
1569     }
1570 
1571     wr_mask &= ISELECT_MASK;
1572     if (wr_mask) {
1573         *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
1574     }
1575 
1576     return RISCV_EXCP_NONE;
1577 }
1578 
1579 static int rmw_iprio(target_ulong xlen,
1580                      target_ulong iselect, uint8_t *iprio,
1581                      target_ulong *val, target_ulong new_val,
1582                      target_ulong wr_mask, int ext_irq_no)
1583 {
1584     int i, firq, nirqs;
1585     target_ulong old_val;
1586 
1587     if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
1588         return -EINVAL;
1589     }
1590     if (xlen != 32 && iselect & 0x1) {
1591         return -EINVAL;
1592     }
1593 
1594     nirqs = 4 * (xlen / 32);
1595     firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
1596 
1597     old_val = 0;
1598     for (i = 0; i < nirqs; i++) {
1599         old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
1600     }
1601 
1602     if (val) {
1603         *val = old_val;
1604     }
1605 
1606     if (wr_mask) {
1607         new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
1608         for (i = 0; i < nirqs; i++) {
1609             /*
1610              * M-level and S-level external IRQ priority always read-only
1611              * zero. This means default priority order is always preferred
1612              * for M-level and S-level external IRQs.
1613              */
1614             if ((firq + i) == ext_irq_no) {
1615                 continue;
1616             }
1617             iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
1618         }
1619     }
1620 
1621     return 0;
1622 }
1623 
1624 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
1625                      target_ulong new_val, target_ulong wr_mask)
1626 {
1627     bool virt;
1628     uint8_t *iprio;
1629     int ret = -EINVAL;
1630     target_ulong priv, isel, vgein;
1631 
1632     /* Translate CSR number for VS-mode */
1633     csrno = aia_xlate_vs_csrno(env, csrno);
1634 
1635     /* Decode register details from CSR number */
1636     virt = false;
1637     switch (csrno) {
1638     case CSR_MIREG:
1639         iprio = env->miprio;
1640         isel = env->miselect;
1641         priv = PRV_M;
1642         break;
1643     case CSR_SIREG:
1644         iprio = env->siprio;
1645         isel = env->siselect;
1646         priv = PRV_S;
1647         break;
1648     case CSR_VSIREG:
1649         iprio = env->hviprio;
1650         isel = env->vsiselect;
1651         priv = PRV_S;
1652         virt = true;
1653         break;
1654     default:
1655          goto done;
1656     };
1657 
1658     /* Find the selected guest interrupt file */
1659     vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
1660 
1661     if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
1662         /* Local interrupt priority registers not available for VS-mode */
1663         if (!virt) {
1664             ret = rmw_iprio(riscv_cpu_mxl_bits(env),
1665                             isel, iprio, val, new_val, wr_mask,
1666                             (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
1667         }
1668     } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
1669         /* IMSIC registers only available when machine implements it. */
1670         if (env->aia_ireg_rmw_fn[priv]) {
1671             /* Selected guest interrupt file should not be zero */
1672             if (virt && (!vgein || env->geilen < vgein)) {
1673                 goto done;
1674             }
1675             /* Call machine specific IMSIC register emulation */
1676             ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
1677                                     AIA_MAKE_IREG(isel, priv, virt, vgein,
1678                                                   riscv_cpu_mxl_bits(env)),
1679                                     val, new_val, wr_mask);
1680         }
1681     }
1682 
1683 done:
1684     if (ret) {
1685         return (riscv_cpu_virt_enabled(env) && virt) ?
1686                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1687     }
1688     return RISCV_EXCP_NONE;
1689 }
1690 
1691 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
1692                       target_ulong new_val, target_ulong wr_mask)
1693 {
1694     bool virt;
1695     int ret = -EINVAL;
1696     target_ulong priv, vgein;
1697 
1698     /* Translate CSR number for VS-mode */
1699     csrno = aia_xlate_vs_csrno(env, csrno);
1700 
1701     /* Decode register details from CSR number */
1702     virt = false;
1703     switch (csrno) {
1704     case CSR_MTOPEI:
1705         priv = PRV_M;
1706         break;
1707     case CSR_STOPEI:
1708         priv = PRV_S;
1709         break;
1710     case CSR_VSTOPEI:
1711         priv = PRV_S;
1712         virt = true;
1713         break;
1714     default:
1715         goto done;
1716     };
1717 
1718     /* IMSIC CSRs only available when machine implements IMSIC. */
1719     if (!env->aia_ireg_rmw_fn[priv]) {
1720         goto done;
1721     }
1722 
1723     /* Find the selected guest interrupt file */
1724     vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
1725 
1726     /* Selected guest interrupt file should be valid */
1727     if (virt && (!vgein || env->geilen < vgein)) {
1728         goto done;
1729     }
1730 
1731     /* Call machine specific IMSIC register emulation for TOPEI */
1732     ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
1733                     AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
1734                                   riscv_cpu_mxl_bits(env)),
1735                     val, new_val, wr_mask);
1736 
1737 done:
1738     if (ret) {
1739         return (riscv_cpu_virt_enabled(env) && virt) ?
1740                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1741     }
1742     return RISCV_EXCP_NONE;
1743 }
1744 
1745 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
1746                                  target_ulong *val)
1747 {
1748     *val = env->mtvec;
1749     return RISCV_EXCP_NONE;
1750 }
1751 
1752 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
1753                                   target_ulong val)
1754 {
1755     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1756     if ((val & 3) < 2) {
1757         env->mtvec = val;
1758     } else {
1759         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
1760     }
1761     return RISCV_EXCP_NONE;
1762 }
1763 
1764 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
1765                                          target_ulong *val)
1766 {
1767     *val = env->mcountinhibit;
1768     return RISCV_EXCP_NONE;
1769 }
1770 
1771 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
1772                                           target_ulong val)
1773 {
1774     int cidx;
1775     PMUCTRState *counter;
1776 
1777     env->mcountinhibit = val;
1778 
1779     /* Check if any other counter is also monitoring cycles/instructions */
1780     for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
1781         if (!get_field(env->mcountinhibit, BIT(cidx))) {
1782             counter = &env->pmu_ctrs[cidx];
1783             counter->started = true;
1784         }
1785     }
1786 
1787     return RISCV_EXCP_NONE;
1788 }
1789 
1790 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
1791                                       target_ulong *val)
1792 {
1793     *val = env->mcounteren;
1794     return RISCV_EXCP_NONE;
1795 }
1796 
1797 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
1798                                        target_ulong val)
1799 {
1800     env->mcounteren = val;
1801     return RISCV_EXCP_NONE;
1802 }
1803 
1804 /* Machine Trap Handling */
1805 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
1806                                          Int128 *val)
1807 {
1808     *val = int128_make128(env->mscratch, env->mscratchh);
1809     return RISCV_EXCP_NONE;
1810 }
1811 
1812 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
1813                                           Int128 val)
1814 {
1815     env->mscratch = int128_getlo(val);
1816     env->mscratchh = int128_gethi(val);
1817     return RISCV_EXCP_NONE;
1818 }
1819 
1820 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
1821                                     target_ulong *val)
1822 {
1823     *val = env->mscratch;
1824     return RISCV_EXCP_NONE;
1825 }
1826 
1827 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
1828                                      target_ulong val)
1829 {
1830     env->mscratch = val;
1831     return RISCV_EXCP_NONE;
1832 }
1833 
1834 static RISCVException read_mepc(CPURISCVState *env, int csrno,
1835                                      target_ulong *val)
1836 {
1837     *val = env->mepc;
1838     return RISCV_EXCP_NONE;
1839 }
1840 
1841 static RISCVException write_mepc(CPURISCVState *env, int csrno,
1842                                      target_ulong val)
1843 {
1844     env->mepc = val;
1845     return RISCV_EXCP_NONE;
1846 }
1847 
1848 static RISCVException read_mcause(CPURISCVState *env, int csrno,
1849                                      target_ulong *val)
1850 {
1851     *val = env->mcause;
1852     return RISCV_EXCP_NONE;
1853 }
1854 
1855 static RISCVException write_mcause(CPURISCVState *env, int csrno,
1856                                      target_ulong val)
1857 {
1858     env->mcause = val;
1859     return RISCV_EXCP_NONE;
1860 }
1861 
1862 static RISCVException read_mtval(CPURISCVState *env, int csrno,
1863                                  target_ulong *val)
1864 {
1865     *val = env->mtval;
1866     return RISCV_EXCP_NONE;
1867 }
1868 
1869 static RISCVException write_mtval(CPURISCVState *env, int csrno,
1870                                   target_ulong val)
1871 {
1872     env->mtval = val;
1873     return RISCV_EXCP_NONE;
1874 }
1875 
1876 /* Execution environment configuration setup */
1877 static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
1878                                  target_ulong *val)
1879 {
1880     *val = env->menvcfg;
1881     return RISCV_EXCP_NONE;
1882 }
1883 
1884 static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
1885                                   target_ulong val)
1886 {
1887     uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
1888 
1889     if (riscv_cpu_mxl(env) == MXL_RV64) {
1890         mask |= MENVCFG_PBMTE | MENVCFG_STCE;
1891     }
1892     env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
1893 
1894     return RISCV_EXCP_NONE;
1895 }
1896 
1897 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
1898                                  target_ulong *val)
1899 {
1900     *val = env->menvcfg >> 32;
1901     return RISCV_EXCP_NONE;
1902 }
1903 
1904 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
1905                                   target_ulong val)
1906 {
1907     uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
1908     uint64_t valh = (uint64_t)val << 32;
1909 
1910     env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
1911 
1912     return RISCV_EXCP_NONE;
1913 }
1914 
1915 static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
1916                                  target_ulong *val)
1917 {
1918     RISCVException ret;
1919 
1920     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1921     if (ret != RISCV_EXCP_NONE) {
1922         return ret;
1923     }
1924 
1925     *val = env->senvcfg;
1926     return RISCV_EXCP_NONE;
1927 }
1928 
1929 static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
1930                                   target_ulong val)
1931 {
1932     uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
1933     RISCVException ret;
1934 
1935     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1936     if (ret != RISCV_EXCP_NONE) {
1937         return ret;
1938     }
1939 
1940     env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
1941     return RISCV_EXCP_NONE;
1942 }
1943 
1944 static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
1945                                  target_ulong *val)
1946 {
1947     RISCVException ret;
1948 
1949     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1950     if (ret != RISCV_EXCP_NONE) {
1951         return ret;
1952     }
1953 
1954     *val = env->henvcfg;
1955     return RISCV_EXCP_NONE;
1956 }
1957 
1958 static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
1959                                   target_ulong val)
1960 {
1961     uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
1962     RISCVException ret;
1963 
1964     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1965     if (ret != RISCV_EXCP_NONE) {
1966         return ret;
1967     }
1968 
1969     if (riscv_cpu_mxl(env) == MXL_RV64) {
1970         mask |= HENVCFG_PBMTE | HENVCFG_STCE;
1971     }
1972 
1973     env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
1974 
1975     return RISCV_EXCP_NONE;
1976 }
1977 
1978 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
1979                                  target_ulong *val)
1980 {
1981     RISCVException ret;
1982 
1983     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1984     if (ret != RISCV_EXCP_NONE) {
1985         return ret;
1986     }
1987 
1988     *val = env->henvcfg >> 32;
1989     return RISCV_EXCP_NONE;
1990 }
1991 
1992 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
1993                                   target_ulong val)
1994 {
1995     uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
1996     uint64_t valh = (uint64_t)val << 32;
1997     RISCVException ret;
1998 
1999     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
2000     if (ret != RISCV_EXCP_NONE) {
2001         return ret;
2002     }
2003 
2004     env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
2005     return RISCV_EXCP_NONE;
2006 }
2007 
2008 static RISCVException read_mstateen(CPURISCVState *env, int csrno,
2009                                     target_ulong *val)
2010 {
2011     *val = env->mstateen[csrno - CSR_MSTATEEN0];
2012 
2013     return RISCV_EXCP_NONE;
2014 }
2015 
2016 static RISCVException write_mstateen(CPURISCVState *env, int csrno,
2017                                      uint64_t wr_mask, target_ulong new_val)
2018 {
2019     uint64_t *reg;
2020 
2021     reg = &env->mstateen[csrno - CSR_MSTATEEN0];
2022     *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
2023 
2024     return RISCV_EXCP_NONE;
2025 }
2026 
2027 static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
2028                                       target_ulong new_val)
2029 {
2030     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2031 
2032     return write_mstateen(env, csrno, wr_mask, new_val);
2033 }
2034 
2035 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
2036                                       target_ulong new_val)
2037 {
2038     return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
2039 }
2040 
2041 static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
2042                                       target_ulong *val)
2043 {
2044     *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
2045 
2046     return RISCV_EXCP_NONE;
2047 }
2048 
2049 static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
2050                                       uint64_t wr_mask, target_ulong new_val)
2051 {
2052     uint64_t *reg, val;
2053 
2054     reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
2055     val = (uint64_t)new_val << 32;
2056     val |= *reg & 0xFFFFFFFF;
2057     *reg = (*reg & ~wr_mask) | (val & wr_mask);
2058 
2059     return RISCV_EXCP_NONE;
2060 }
2061 
2062 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
2063                                       target_ulong new_val)
2064 {
2065     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2066 
2067     return write_mstateenh(env, csrno, wr_mask, new_val);
2068 }
2069 
2070 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
2071                                       target_ulong new_val)
2072 {
2073     return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
2074 }
2075 
2076 static RISCVException read_hstateen(CPURISCVState *env, int csrno,
2077                                     target_ulong *val)
2078 {
2079     int index = csrno - CSR_HSTATEEN0;
2080 
2081     *val = env->hstateen[index] & env->mstateen[index];
2082 
2083     return RISCV_EXCP_NONE;
2084 }
2085 
2086 static RISCVException write_hstateen(CPURISCVState *env, int csrno,
2087                                      uint64_t mask, target_ulong new_val)
2088 {
2089     int index = csrno - CSR_HSTATEEN0;
2090     uint64_t *reg, wr_mask;
2091 
2092     reg = &env->hstateen[index];
2093     wr_mask = env->mstateen[index] & mask;
2094     *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
2095 
2096     return RISCV_EXCP_NONE;
2097 }
2098 
2099 static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
2100                                       target_ulong new_val)
2101 {
2102     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2103 
2104     return write_hstateen(env, csrno, wr_mask, new_val);
2105 }
2106 
2107 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
2108                                       target_ulong new_val)
2109 {
2110     return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
2111 }
2112 
2113 static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
2114                                      target_ulong *val)
2115 {
2116     int index = csrno - CSR_HSTATEEN0H;
2117 
2118     *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
2119 
2120     return RISCV_EXCP_NONE;
2121 }
2122 
2123 static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
2124                                       uint64_t mask, target_ulong new_val)
2125 {
2126     int index = csrno - CSR_HSTATEEN0H;
2127     uint64_t *reg, wr_mask, val;
2128 
2129     reg = &env->hstateen[index];
2130     val = (uint64_t)new_val << 32;
2131     val |= *reg & 0xFFFFFFFF;
2132     wr_mask = env->mstateen[index] & mask;
2133     *reg = (*reg & ~wr_mask) | (val & wr_mask);
2134 
2135     return RISCV_EXCP_NONE;
2136 }
2137 
2138 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
2139                                        target_ulong new_val)
2140 {
2141     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2142 
2143     return write_hstateenh(env, csrno, wr_mask, new_val);
2144 }
2145 
2146 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
2147                                        target_ulong new_val)
2148 {
2149     return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
2150 }
2151 
2152 static RISCVException read_sstateen(CPURISCVState *env, int csrno,
2153                                     target_ulong *val)
2154 {
2155     bool virt = riscv_cpu_virt_enabled(env);
2156     int index = csrno - CSR_SSTATEEN0;
2157 
2158     *val = env->sstateen[index] & env->mstateen[index];
2159     if (virt) {
2160         *val &= env->hstateen[index];
2161     }
2162 
2163     return RISCV_EXCP_NONE;
2164 }
2165 
2166 static RISCVException write_sstateen(CPURISCVState *env, int csrno,
2167                                      uint64_t mask, target_ulong new_val)
2168 {
2169     bool virt = riscv_cpu_virt_enabled(env);
2170     int index = csrno - CSR_SSTATEEN0;
2171     uint64_t wr_mask;
2172     uint64_t *reg;
2173 
2174     wr_mask = env->mstateen[index] & mask;
2175     if (virt) {
2176         wr_mask &= env->hstateen[index];
2177     }
2178 
2179     reg = &env->sstateen[index];
2180     *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
2181 
2182     return RISCV_EXCP_NONE;
2183 }
2184 
2185 static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
2186                                       target_ulong new_val)
2187 {
2188     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2189 
2190     return write_sstateen(env, csrno, wr_mask, new_val);
2191 }
2192 
2193 static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
2194                                       target_ulong new_val)
2195 {
2196     return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
2197 }
2198 
2199 static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
2200                                 uint64_t *ret_val,
2201                                 uint64_t new_val, uint64_t wr_mask)
2202 {
2203     RISCVCPU *cpu = env_archcpu(env);
2204     uint64_t old_mip, mask = wr_mask & delegable_ints;
2205     uint32_t gin;
2206 
2207     if (mask & MIP_SEIP) {
2208         env->software_seip = new_val & MIP_SEIP;
2209         new_val |= env->external_seip * MIP_SEIP;
2210     }
2211 
2212     if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
2213         get_field(env->menvcfg, MENVCFG_STCE)) {
2214         /* sstc extension forbids STIP & VSTIP to be writeable in mip */
2215         mask = mask & ~(MIP_STIP | MIP_VSTIP);
2216     }
2217 
2218     if (mask) {
2219         old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
2220     } else {
2221         old_mip = env->mip;
2222     }
2223 
2224     if (csrno != CSR_HVIP) {
2225         gin = get_field(env->hstatus, HSTATUS_VGEIN);
2226         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
2227         old_mip |= env->vstime_irq ? MIP_VSTIP : 0;
2228     }
2229 
2230     if (ret_val) {
2231         *ret_val = old_mip;
2232     }
2233 
2234     return RISCV_EXCP_NONE;
2235 }
2236 
2237 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
2238                               target_ulong *ret_val,
2239                               target_ulong new_val, target_ulong wr_mask)
2240 {
2241     uint64_t rval;
2242     RISCVException ret;
2243 
2244     ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
2245     if (ret_val) {
2246         *ret_val = rval;
2247     }
2248 
2249     return ret;
2250 }
2251 
2252 static RISCVException rmw_miph(CPURISCVState *env, int csrno,
2253                                target_ulong *ret_val,
2254                                target_ulong new_val, target_ulong wr_mask)
2255 {
2256     uint64_t rval;
2257     RISCVException ret;
2258 
2259     ret = rmw_mip64(env, csrno, &rval,
2260         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2261     if (ret_val) {
2262         *ret_val = rval >> 32;
2263     }
2264 
2265     return ret;
2266 }
2267 
2268 /* Supervisor Trap Setup */
2269 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
2270                                         Int128 *val)
2271 {
2272     uint64_t mask = sstatus_v1_10_mask;
2273     uint64_t sstatus = env->mstatus & mask;
2274     if (env->xl != MXL_RV32 || env->debugger) {
2275         mask |= SSTATUS64_UXL;
2276     }
2277 
2278     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
2279     return RISCV_EXCP_NONE;
2280 }
2281 
2282 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
2283                                    target_ulong *val)
2284 {
2285     target_ulong mask = (sstatus_v1_10_mask);
2286     if (env->xl != MXL_RV32 || env->debugger) {
2287         mask |= SSTATUS64_UXL;
2288     }
2289     /* TODO: Use SXL not MXL. */
2290     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
2291     return RISCV_EXCP_NONE;
2292 }
2293 
2294 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
2295                                     target_ulong val)
2296 {
2297     target_ulong mask = (sstatus_v1_10_mask);
2298 
2299     if (env->xl != MXL_RV32 || env->debugger) {
2300         if ((val & SSTATUS64_UXL) != 0) {
2301             mask |= SSTATUS64_UXL;
2302         }
2303     }
2304     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
2305     return write_mstatus(env, CSR_MSTATUS, newval);
2306 }
2307 
2308 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
2309                                  uint64_t *ret_val,
2310                                  uint64_t new_val, uint64_t wr_mask)
2311 {
2312     RISCVException ret;
2313     uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
2314 
2315     /* Bring VS-level bits to correct position */
2316     new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
2317     wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
2318 
2319     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
2320     if (ret_val) {
2321         *ret_val = (rval & mask) >> 1;
2322     }
2323 
2324     return ret;
2325 }
2326 
2327 static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
2328                                target_ulong *ret_val,
2329                                target_ulong new_val, target_ulong wr_mask)
2330 {
2331     uint64_t rval;
2332     RISCVException ret;
2333 
2334     ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
2335     if (ret_val) {
2336         *ret_val = rval;
2337     }
2338 
2339     return ret;
2340 }
2341 
2342 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
2343                                 target_ulong *ret_val,
2344                                 target_ulong new_val, target_ulong wr_mask)
2345 {
2346     uint64_t rval;
2347     RISCVException ret;
2348 
2349     ret = rmw_vsie64(env, csrno, &rval,
2350         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2351     if (ret_val) {
2352         *ret_val = rval >> 32;
2353     }
2354 
2355     return ret;
2356 }
2357 
2358 static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
2359                                 uint64_t *ret_val,
2360                                 uint64_t new_val, uint64_t wr_mask)
2361 {
2362     RISCVException ret;
2363     uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
2364 
2365     if (riscv_cpu_virt_enabled(env)) {
2366         if (env->hvictl & HVICTL_VTI) {
2367             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
2368         }
2369         ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
2370     } else {
2371         ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
2372     }
2373 
2374     if (ret_val) {
2375         *ret_val &= mask;
2376     }
2377 
2378     return ret;
2379 }
2380 
2381 static RISCVException rmw_sie(CPURISCVState *env, int csrno,
2382                               target_ulong *ret_val,
2383                               target_ulong new_val, target_ulong wr_mask)
2384 {
2385     uint64_t rval;
2386     RISCVException ret;
2387 
2388     ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
2389     if (ret == RISCV_EXCP_NONE && ret_val) {
2390         *ret_val = rval;
2391     }
2392 
2393     return ret;
2394 }
2395 
2396 static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
2397                                target_ulong *ret_val,
2398                                target_ulong new_val, target_ulong wr_mask)
2399 {
2400     uint64_t rval;
2401     RISCVException ret;
2402 
2403     ret = rmw_sie64(env, csrno, &rval,
2404         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2405     if (ret_val) {
2406         *ret_val = rval >> 32;
2407     }
2408 
2409     return ret;
2410 }
2411 
2412 static RISCVException read_stvec(CPURISCVState *env, int csrno,
2413                                  target_ulong *val)
2414 {
2415     *val = env->stvec;
2416     return RISCV_EXCP_NONE;
2417 }
2418 
2419 static RISCVException write_stvec(CPURISCVState *env, int csrno,
2420                                   target_ulong val)
2421 {
2422     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
2423     if ((val & 3) < 2) {
2424         env->stvec = val;
2425     } else {
2426         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
2427     }
2428     return RISCV_EXCP_NONE;
2429 }
2430 
2431 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
2432                                       target_ulong *val)
2433 {
2434     *val = env->scounteren;
2435     return RISCV_EXCP_NONE;
2436 }
2437 
2438 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
2439                                        target_ulong val)
2440 {
2441     env->scounteren = val;
2442     return RISCV_EXCP_NONE;
2443 }
2444 
2445 /* Supervisor Trap Handling */
2446 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
2447                                          Int128 *val)
2448 {
2449     *val = int128_make128(env->sscratch, env->sscratchh);
2450     return RISCV_EXCP_NONE;
2451 }
2452 
2453 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
2454                                           Int128 val)
2455 {
2456     env->sscratch = int128_getlo(val);
2457     env->sscratchh = int128_gethi(val);
2458     return RISCV_EXCP_NONE;
2459 }
2460 
2461 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
2462                                     target_ulong *val)
2463 {
2464     *val = env->sscratch;
2465     return RISCV_EXCP_NONE;
2466 }
2467 
2468 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
2469                                      target_ulong val)
2470 {
2471     env->sscratch = val;
2472     return RISCV_EXCP_NONE;
2473 }
2474 
2475 static RISCVException read_sepc(CPURISCVState *env, int csrno,
2476                                 target_ulong *val)
2477 {
2478     *val = env->sepc;
2479     return RISCV_EXCP_NONE;
2480 }
2481 
2482 static RISCVException write_sepc(CPURISCVState *env, int csrno,
2483                                  target_ulong val)
2484 {
2485     env->sepc = val;
2486     return RISCV_EXCP_NONE;
2487 }
2488 
2489 static RISCVException read_scause(CPURISCVState *env, int csrno,
2490                                   target_ulong *val)
2491 {
2492     *val = env->scause;
2493     return RISCV_EXCP_NONE;
2494 }
2495 
2496 static RISCVException write_scause(CPURISCVState *env, int csrno,
2497                                    target_ulong val)
2498 {
2499     env->scause = val;
2500     return RISCV_EXCP_NONE;
2501 }
2502 
2503 static RISCVException read_stval(CPURISCVState *env, int csrno,
2504                                  target_ulong *val)
2505 {
2506     *val = env->stval;
2507     return RISCV_EXCP_NONE;
2508 }
2509 
2510 static RISCVException write_stval(CPURISCVState *env, int csrno,
2511                                   target_ulong val)
2512 {
2513     env->stval = val;
2514     return RISCV_EXCP_NONE;
2515 }
2516 
2517 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
2518                                  uint64_t *ret_val,
2519                                  uint64_t new_val, uint64_t wr_mask)
2520 {
2521     RISCVException ret;
2522     uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
2523 
2524     /* Bring VS-level bits to correct position */
2525     new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
2526     wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
2527 
2528     ret = rmw_mip64(env, csrno, &rval, new_val,
2529                     wr_mask & mask & vsip_writable_mask);
2530     if (ret_val) {
2531         *ret_val = (rval & mask) >> 1;
2532     }
2533 
2534     return ret;
2535 }
2536 
2537 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
2538                                target_ulong *ret_val,
2539                                target_ulong new_val, target_ulong wr_mask)
2540 {
2541     uint64_t rval;
2542     RISCVException ret;
2543 
2544     ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
2545     if (ret_val) {
2546         *ret_val = rval;
2547     }
2548 
2549     return ret;
2550 }
2551 
2552 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
2553                                 target_ulong *ret_val,
2554                                 target_ulong new_val, target_ulong wr_mask)
2555 {
2556     uint64_t rval;
2557     RISCVException ret;
2558 
2559     ret = rmw_vsip64(env, csrno, &rval,
2560         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2561     if (ret_val) {
2562         *ret_val = rval >> 32;
2563     }
2564 
2565     return ret;
2566 }
2567 
2568 static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
2569                                 uint64_t *ret_val,
2570                                 uint64_t new_val, uint64_t wr_mask)
2571 {
2572     RISCVException ret;
2573     uint64_t mask = env->mideleg & sip_writable_mask;
2574 
2575     if (riscv_cpu_virt_enabled(env)) {
2576         if (env->hvictl & HVICTL_VTI) {
2577             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
2578         }
2579         ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
2580     } else {
2581         ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
2582     }
2583 
2584     if (ret_val) {
2585         *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
2586     }
2587 
2588     return ret;
2589 }
2590 
2591 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
2592                               target_ulong *ret_val,
2593                               target_ulong new_val, target_ulong wr_mask)
2594 {
2595     uint64_t rval;
2596     RISCVException ret;
2597 
2598     ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
2599     if (ret_val) {
2600         *ret_val = rval;
2601     }
2602 
2603     return ret;
2604 }
2605 
2606 static RISCVException rmw_siph(CPURISCVState *env, int csrno,
2607                                target_ulong *ret_val,
2608                                target_ulong new_val, target_ulong wr_mask)
2609 {
2610     uint64_t rval;
2611     RISCVException ret;
2612 
2613     ret = rmw_sip64(env, csrno, &rval,
2614         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2615     if (ret_val) {
2616         *ret_val = rval >> 32;
2617     }
2618 
2619     return ret;
2620 }
2621 
2622 /* Supervisor Protection and Translation */
2623 static RISCVException read_satp(CPURISCVState *env, int csrno,
2624                                 target_ulong *val)
2625 {
2626     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
2627         *val = 0;
2628         return RISCV_EXCP_NONE;
2629     }
2630 
2631     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
2632         return RISCV_EXCP_ILLEGAL_INST;
2633     } else {
2634         *val = env->satp;
2635     }
2636 
2637     return RISCV_EXCP_NONE;
2638 }
2639 
2640 static RISCVException write_satp(CPURISCVState *env, int csrno,
2641                                  target_ulong val)
2642 {
2643     target_ulong vm, mask;
2644 
2645     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
2646         return RISCV_EXCP_NONE;
2647     }
2648 
2649     if (riscv_cpu_mxl(env) == MXL_RV32) {
2650         vm = validate_vm(env, get_field(val, SATP32_MODE));
2651         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
2652     } else {
2653         vm = validate_vm(env, get_field(val, SATP64_MODE));
2654         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
2655     }
2656 
2657     if (vm && mask) {
2658         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
2659             return RISCV_EXCP_ILLEGAL_INST;
2660         } else {
2661             /*
2662              * The ISA defines SATP.MODE=Bare as "no translation", but we still
2663              * pass these through QEMU's TLB emulation as it improves
2664              * performance.  Flushing the TLB on SATP writes with paging
2665              * enabled avoids leaking those invalid cached mappings.
2666              */
2667             tlb_flush(env_cpu(env));
2668             env->satp = val;
2669         }
2670     }
2671     return RISCV_EXCP_NONE;
2672 }
2673 
2674 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
2675 {
2676     int irq, ret;
2677     target_ulong topei;
2678     uint64_t vseip, vsgein;
2679     uint32_t iid, iprio, hviid, hviprio, gein;
2680     uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
2681 
2682     gein = get_field(env->hstatus, HSTATUS_VGEIN);
2683     hviid = get_field(env->hvictl, HVICTL_IID);
2684     hviprio = get_field(env->hvictl, HVICTL_IPRIO);
2685 
2686     if (gein) {
2687         vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
2688         vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP;
2689         if (gein <= env->geilen && vseip) {
2690             siid[scount] = IRQ_S_EXT;
2691             siprio[scount] = IPRIO_MMAXIPRIO + 1;
2692             if (env->aia_ireg_rmw_fn[PRV_S]) {
2693                 /*
2694                  * Call machine specific IMSIC register emulation for
2695                  * reading TOPEI.
2696                  */
2697                 ret = env->aia_ireg_rmw_fn[PRV_S](
2698                         env->aia_ireg_rmw_fn_arg[PRV_S],
2699                         AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein,
2700                                       riscv_cpu_mxl_bits(env)),
2701                         &topei, 0, 0);
2702                 if (!ret && topei) {
2703                     siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK;
2704                 }
2705             }
2706             scount++;
2707         }
2708     } else {
2709         if (hviid == IRQ_S_EXT && hviprio) {
2710             siid[scount] = IRQ_S_EXT;
2711             siprio[scount] = hviprio;
2712             scount++;
2713         }
2714     }
2715 
2716     if (env->hvictl & HVICTL_VTI) {
2717         if (hviid != IRQ_S_EXT) {
2718             siid[scount] = hviid;
2719             siprio[scount] = hviprio;
2720             scount++;
2721         }
2722     } else {
2723         irq = riscv_cpu_vsirq_pending(env);
2724         if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) {
2725             siid[scount] = irq;
2726             siprio[scount] = env->hviprio[irq];
2727             scount++;
2728         }
2729     }
2730 
2731     iid = 0;
2732     iprio = UINT_MAX;
2733     for (s = 0; s < scount; s++) {
2734         if (siprio[s] < iprio) {
2735             iid = siid[s];
2736             iprio = siprio[s];
2737         }
2738     }
2739 
2740     if (iid) {
2741         if (env->hvictl & HVICTL_IPRIOM) {
2742             if (iprio > IPRIO_MMAXIPRIO) {
2743                 iprio = IPRIO_MMAXIPRIO;
2744             }
2745             if (!iprio) {
2746                 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) {
2747                     iprio = IPRIO_MMAXIPRIO;
2748                 }
2749             }
2750         } else {
2751             iprio = 1;
2752         }
2753     } else {
2754         iprio = 0;
2755     }
2756 
2757     *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT;
2758     *val |= iprio;
2759     return RISCV_EXCP_NONE;
2760 }
2761 
2762 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
2763 {
2764     int irq;
2765     uint8_t iprio;
2766 
2767     if (riscv_cpu_virt_enabled(env)) {
2768         return read_vstopi(env, CSR_VSTOPI, val);
2769     }
2770 
2771     irq = riscv_cpu_sirq_pending(env);
2772     if (irq <= 0 || irq > 63) {
2773         *val = 0;
2774     } else {
2775         iprio = env->siprio[irq];
2776         if (!iprio) {
2777             if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) {
2778                 iprio = IPRIO_MMAXIPRIO;
2779            }
2780         }
2781         *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
2782         *val |= iprio;
2783     }
2784 
2785     return RISCV_EXCP_NONE;
2786 }
2787 
2788 /* Hypervisor Extensions */
2789 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
2790                                    target_ulong *val)
2791 {
2792     *val = env->hstatus;
2793     if (riscv_cpu_mxl(env) != MXL_RV32) {
2794         /* We only support 64-bit VSXL */
2795         *val = set_field(*val, HSTATUS_VSXL, 2);
2796     }
2797     /* We only support little endian */
2798     *val = set_field(*val, HSTATUS_VSBE, 0);
2799     return RISCV_EXCP_NONE;
2800 }
2801 
2802 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
2803                                     target_ulong val)
2804 {
2805     env->hstatus = val;
2806     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
2807         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
2808     }
2809     if (get_field(val, HSTATUS_VSBE) != 0) {
2810         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
2811     }
2812     return RISCV_EXCP_NONE;
2813 }
2814 
2815 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
2816                                    target_ulong *val)
2817 {
2818     *val = env->hedeleg;
2819     return RISCV_EXCP_NONE;
2820 }
2821 
2822 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
2823                                     target_ulong val)
2824 {
2825     env->hedeleg = val & vs_delegable_excps;
2826     return RISCV_EXCP_NONE;
2827 }
2828 
2829 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
2830                                     uint64_t *ret_val,
2831                                     uint64_t new_val, uint64_t wr_mask)
2832 {
2833     uint64_t mask = wr_mask & vs_delegable_ints;
2834 
2835     if (ret_val) {
2836         *ret_val = env->hideleg & vs_delegable_ints;
2837     }
2838 
2839     env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
2840     return RISCV_EXCP_NONE;
2841 }
2842 
2843 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
2844                                   target_ulong *ret_val,
2845                                   target_ulong new_val, target_ulong wr_mask)
2846 {
2847     uint64_t rval;
2848     RISCVException ret;
2849 
2850     ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
2851     if (ret_val) {
2852         *ret_val = rval;
2853     }
2854 
2855     return ret;
2856 }
2857 
2858 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
2859                                    target_ulong *ret_val,
2860                                    target_ulong new_val, target_ulong wr_mask)
2861 {
2862     uint64_t rval;
2863     RISCVException ret;
2864 
2865     ret = rmw_hideleg64(env, csrno, &rval,
2866         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2867     if (ret_val) {
2868         *ret_val = rval >> 32;
2869     }
2870 
2871     return ret;
2872 }
2873 
2874 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
2875                                  uint64_t *ret_val,
2876                                  uint64_t new_val, uint64_t wr_mask)
2877 {
2878     RISCVException ret;
2879 
2880     ret = rmw_mip64(env, csrno, ret_val, new_val,
2881                     wr_mask & hvip_writable_mask);
2882     if (ret_val) {
2883         *ret_val &= VS_MODE_INTERRUPTS;
2884     }
2885 
2886     return ret;
2887 }
2888 
2889 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
2890                                target_ulong *ret_val,
2891                                target_ulong new_val, target_ulong wr_mask)
2892 {
2893     uint64_t rval;
2894     RISCVException ret;
2895 
2896     ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
2897     if (ret_val) {
2898         *ret_val = rval;
2899     }
2900 
2901     return ret;
2902 }
2903 
2904 static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
2905                                 target_ulong *ret_val,
2906                                 target_ulong new_val, target_ulong wr_mask)
2907 {
2908     uint64_t rval;
2909     RISCVException ret;
2910 
2911     ret = rmw_hvip64(env, csrno, &rval,
2912         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2913     if (ret_val) {
2914         *ret_val = rval >> 32;
2915     }
2916 
2917     return ret;
2918 }
2919 
2920 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
2921                               target_ulong *ret_value,
2922                               target_ulong new_value, target_ulong write_mask)
2923 {
2924     int ret = rmw_mip(env, csrno, ret_value, new_value,
2925                       write_mask & hip_writable_mask);
2926 
2927     if (ret_value) {
2928         *ret_value &= HS_MODE_INTERRUPTS;
2929     }
2930     return ret;
2931 }
2932 
2933 static RISCVException rmw_hie(CPURISCVState *env, int csrno,
2934                               target_ulong *ret_val,
2935                               target_ulong new_val, target_ulong wr_mask)
2936 {
2937     uint64_t rval;
2938     RISCVException ret;
2939 
2940     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
2941     if (ret_val) {
2942         *ret_val = rval & HS_MODE_INTERRUPTS;
2943     }
2944 
2945     return ret;
2946 }
2947 
2948 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
2949                                       target_ulong *val)
2950 {
2951     *val = env->hcounteren;
2952     return RISCV_EXCP_NONE;
2953 }
2954 
2955 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
2956                                        target_ulong val)
2957 {
2958     env->hcounteren = val;
2959     return RISCV_EXCP_NONE;
2960 }
2961 
2962 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
2963                                  target_ulong *val)
2964 {
2965     if (val) {
2966         *val = env->hgeie;
2967     }
2968     return RISCV_EXCP_NONE;
2969 }
2970 
2971 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
2972                                   target_ulong val)
2973 {
2974     /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
2975     val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
2976     env->hgeie = val;
2977     /* Update mip.SGEIP bit */
2978     riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
2979                          BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
2980     return RISCV_EXCP_NONE;
2981 }
2982 
2983 static RISCVException read_htval(CPURISCVState *env, int csrno,
2984                                  target_ulong *val)
2985 {
2986     *val = env->htval;
2987     return RISCV_EXCP_NONE;
2988 }
2989 
2990 static RISCVException write_htval(CPURISCVState *env, int csrno,
2991                                   target_ulong val)
2992 {
2993     env->htval = val;
2994     return RISCV_EXCP_NONE;
2995 }
2996 
2997 static RISCVException read_htinst(CPURISCVState *env, int csrno,
2998                                   target_ulong *val)
2999 {
3000     *val = env->htinst;
3001     return RISCV_EXCP_NONE;
3002 }
3003 
3004 static RISCVException write_htinst(CPURISCVState *env, int csrno,
3005                                    target_ulong val)
3006 {
3007     return RISCV_EXCP_NONE;
3008 }
3009 
3010 static RISCVException read_hgeip(CPURISCVState *env, int csrno,
3011                                  target_ulong *val)
3012 {
3013     if (val) {
3014         *val = env->hgeip;
3015     }
3016     return RISCV_EXCP_NONE;
3017 }
3018 
3019 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
3020                                  target_ulong *val)
3021 {
3022     *val = env->hgatp;
3023     return RISCV_EXCP_NONE;
3024 }
3025 
3026 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
3027                                   target_ulong val)
3028 {
3029     env->hgatp = val;
3030     return RISCV_EXCP_NONE;
3031 }
3032 
3033 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
3034                                       target_ulong *val)
3035 {
3036     if (!env->rdtime_fn) {
3037         return RISCV_EXCP_ILLEGAL_INST;
3038     }
3039 
3040     *val = env->htimedelta;
3041     return RISCV_EXCP_NONE;
3042 }
3043 
3044 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
3045                                        target_ulong val)
3046 {
3047     RISCVCPU *cpu = env_archcpu(env);
3048 
3049     if (!env->rdtime_fn) {
3050         return RISCV_EXCP_ILLEGAL_INST;
3051     }
3052 
3053     if (riscv_cpu_mxl(env) == MXL_RV32) {
3054         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
3055     } else {
3056         env->htimedelta = val;
3057     }
3058 
3059     if (cpu->cfg.ext_sstc && env->rdtime_fn) {
3060         riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
3061                                   env->htimedelta, MIP_VSTIP);
3062     }
3063 
3064     return RISCV_EXCP_NONE;
3065 }
3066 
3067 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
3068                                        target_ulong *val)
3069 {
3070     if (!env->rdtime_fn) {
3071         return RISCV_EXCP_ILLEGAL_INST;
3072     }
3073 
3074     *val = env->htimedelta >> 32;
3075     return RISCV_EXCP_NONE;
3076 }
3077 
3078 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
3079                                         target_ulong val)
3080 {
3081     RISCVCPU *cpu = env_archcpu(env);
3082 
3083     if (!env->rdtime_fn) {
3084         return RISCV_EXCP_ILLEGAL_INST;
3085     }
3086 
3087     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
3088 
3089     if (cpu->cfg.ext_sstc && env->rdtime_fn) {
3090         riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
3091                                   env->htimedelta, MIP_VSTIP);
3092     }
3093 
3094     return RISCV_EXCP_NONE;
3095 }
3096 
3097 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
3098 {
3099     *val = env->hvictl;
3100     return RISCV_EXCP_NONE;
3101 }
3102 
3103 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
3104 {
3105     env->hvictl = val & HVICTL_VALID_MASK;
3106     return RISCV_EXCP_NONE;
3107 }
3108 
3109 static int read_hvipriox(CPURISCVState *env, int first_index,
3110                          uint8_t *iprio, target_ulong *val)
3111 {
3112     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
3113 
3114     /* First index has to be a multiple of number of irqs per register */
3115     if (first_index % num_irqs) {
3116         return (riscv_cpu_virt_enabled(env)) ?
3117                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
3118     }
3119 
3120     /* Fill-up return value */
3121     *val = 0;
3122     for (i = 0; i < num_irqs; i++) {
3123         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
3124             continue;
3125         }
3126         if (rdzero) {
3127             continue;
3128         }
3129         *val |= ((target_ulong)iprio[irq]) << (i * 8);
3130     }
3131 
3132     return RISCV_EXCP_NONE;
3133 }
3134 
3135 static int write_hvipriox(CPURISCVState *env, int first_index,
3136                           uint8_t *iprio, target_ulong val)
3137 {
3138     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
3139 
3140     /* First index has to be a multiple of number of irqs per register */
3141     if (first_index % num_irqs) {
3142         return (riscv_cpu_virt_enabled(env)) ?
3143                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
3144     }
3145 
3146     /* Fill-up priority arrary */
3147     for (i = 0; i < num_irqs; i++) {
3148         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
3149             continue;
3150         }
3151         if (rdzero) {
3152             iprio[irq] = 0;
3153         } else {
3154             iprio[irq] = (val >> (i * 8)) & 0xff;
3155         }
3156     }
3157 
3158     return RISCV_EXCP_NONE;
3159 }
3160 
3161 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
3162 {
3163     return read_hvipriox(env, 0, env->hviprio, val);
3164 }
3165 
3166 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
3167 {
3168     return write_hvipriox(env, 0, env->hviprio, val);
3169 }
3170 
3171 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
3172 {
3173     return read_hvipriox(env, 4, env->hviprio, val);
3174 }
3175 
3176 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
3177 {
3178     return write_hvipriox(env, 4, env->hviprio, val);
3179 }
3180 
3181 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
3182 {
3183     return read_hvipriox(env, 8, env->hviprio, val);
3184 }
3185 
3186 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
3187 {
3188     return write_hvipriox(env, 8, env->hviprio, val);
3189 }
3190 
3191 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
3192 {
3193     return read_hvipriox(env, 12, env->hviprio, val);
3194 }
3195 
3196 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
3197 {
3198     return write_hvipriox(env, 12, env->hviprio, val);
3199 }
3200 
3201 /* Virtual CSR Registers */
3202 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
3203                                     target_ulong *val)
3204 {
3205     *val = env->vsstatus;
3206     return RISCV_EXCP_NONE;
3207 }
3208 
3209 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
3210                                      target_ulong val)
3211 {
3212     uint64_t mask = (target_ulong)-1;
3213     if ((val & VSSTATUS64_UXL) == 0) {
3214         mask &= ~VSSTATUS64_UXL;
3215     }
3216     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
3217     return RISCV_EXCP_NONE;
3218 }
3219 
3220 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
3221 {
3222     *val = env->vstvec;
3223     return RISCV_EXCP_NONE;
3224 }
3225 
3226 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
3227                                    target_ulong val)
3228 {
3229     env->vstvec = val;
3230     return RISCV_EXCP_NONE;
3231 }
3232 
3233 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
3234                                      target_ulong *val)
3235 {
3236     *val = env->vsscratch;
3237     return RISCV_EXCP_NONE;
3238 }
3239 
3240 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
3241                                       target_ulong val)
3242 {
3243     env->vsscratch = val;
3244     return RISCV_EXCP_NONE;
3245 }
3246 
3247 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
3248                                  target_ulong *val)
3249 {
3250     *val = env->vsepc;
3251     return RISCV_EXCP_NONE;
3252 }
3253 
3254 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
3255                                   target_ulong val)
3256 {
3257     env->vsepc = val;
3258     return RISCV_EXCP_NONE;
3259 }
3260 
3261 static RISCVException read_vscause(CPURISCVState *env, int csrno,
3262                                    target_ulong *val)
3263 {
3264     *val = env->vscause;
3265     return RISCV_EXCP_NONE;
3266 }
3267 
3268 static RISCVException write_vscause(CPURISCVState *env, int csrno,
3269                                     target_ulong val)
3270 {
3271     env->vscause = val;
3272     return RISCV_EXCP_NONE;
3273 }
3274 
3275 static RISCVException read_vstval(CPURISCVState *env, int csrno,
3276                                   target_ulong *val)
3277 {
3278     *val = env->vstval;
3279     return RISCV_EXCP_NONE;
3280 }
3281 
3282 static RISCVException write_vstval(CPURISCVState *env, int csrno,
3283                                    target_ulong val)
3284 {
3285     env->vstval = val;
3286     return RISCV_EXCP_NONE;
3287 }
3288 
3289 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
3290                                  target_ulong *val)
3291 {
3292     *val = env->vsatp;
3293     return RISCV_EXCP_NONE;
3294 }
3295 
3296 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
3297                                   target_ulong val)
3298 {
3299     env->vsatp = val;
3300     return RISCV_EXCP_NONE;
3301 }
3302 
3303 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
3304                                   target_ulong *val)
3305 {
3306     *val = env->mtval2;
3307     return RISCV_EXCP_NONE;
3308 }
3309 
3310 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
3311                                    target_ulong val)
3312 {
3313     env->mtval2 = val;
3314     return RISCV_EXCP_NONE;
3315 }
3316 
3317 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
3318                                   target_ulong *val)
3319 {
3320     *val = env->mtinst;
3321     return RISCV_EXCP_NONE;
3322 }
3323 
3324 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
3325                                    target_ulong val)
3326 {
3327     env->mtinst = val;
3328     return RISCV_EXCP_NONE;
3329 }
3330 
3331 /* Physical Memory Protection */
3332 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
3333                                    target_ulong *val)
3334 {
3335     *val = mseccfg_csr_read(env);
3336     return RISCV_EXCP_NONE;
3337 }
3338 
3339 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
3340                          target_ulong val)
3341 {
3342     mseccfg_csr_write(env, val);
3343     return RISCV_EXCP_NONE;
3344 }
3345 
3346 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
3347 {
3348     /* TODO: RV128 restriction check */
3349     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
3350         return false;
3351     }
3352     return true;
3353 }
3354 
3355 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
3356                                   target_ulong *val)
3357 {
3358     uint32_t reg_index = csrno - CSR_PMPCFG0;
3359 
3360     if (!check_pmp_reg_index(env, reg_index)) {
3361         return RISCV_EXCP_ILLEGAL_INST;
3362     }
3363     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
3364     return RISCV_EXCP_NONE;
3365 }
3366 
3367 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
3368                                    target_ulong val)
3369 {
3370     uint32_t reg_index = csrno - CSR_PMPCFG0;
3371 
3372     if (!check_pmp_reg_index(env, reg_index)) {
3373         return RISCV_EXCP_ILLEGAL_INST;
3374     }
3375     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
3376     return RISCV_EXCP_NONE;
3377 }
3378 
3379 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
3380                                    target_ulong *val)
3381 {
3382     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
3383     return RISCV_EXCP_NONE;
3384 }
3385 
3386 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
3387                                     target_ulong val)
3388 {
3389     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
3390     return RISCV_EXCP_NONE;
3391 }
3392 
3393 static RISCVException read_tselect(CPURISCVState *env, int csrno,
3394                                    target_ulong *val)
3395 {
3396     *val = tselect_csr_read(env);
3397     return RISCV_EXCP_NONE;
3398 }
3399 
3400 static RISCVException write_tselect(CPURISCVState *env, int csrno,
3401                                     target_ulong val)
3402 {
3403     tselect_csr_write(env, val);
3404     return RISCV_EXCP_NONE;
3405 }
3406 
3407 static RISCVException read_tdata(CPURISCVState *env, int csrno,
3408                                  target_ulong *val)
3409 {
3410     /* return 0 in tdata1 to end the trigger enumeration */
3411     if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) {
3412         *val = 0;
3413         return RISCV_EXCP_NONE;
3414     }
3415 
3416     if (!tdata_available(env, csrno - CSR_TDATA1)) {
3417         return RISCV_EXCP_ILLEGAL_INST;
3418     }
3419 
3420     *val = tdata_csr_read(env, csrno - CSR_TDATA1);
3421     return RISCV_EXCP_NONE;
3422 }
3423 
3424 static RISCVException write_tdata(CPURISCVState *env, int csrno,
3425                                   target_ulong val)
3426 {
3427     if (!tdata_available(env, csrno - CSR_TDATA1)) {
3428         return RISCV_EXCP_ILLEGAL_INST;
3429     }
3430 
3431     tdata_csr_write(env, csrno - CSR_TDATA1, val);
3432     return RISCV_EXCP_NONE;
3433 }
3434 
3435 static RISCVException read_tinfo(CPURISCVState *env, int csrno,
3436                                  target_ulong *val)
3437 {
3438     *val = tinfo_csr_read(env);
3439     return RISCV_EXCP_NONE;
3440 }
3441 
3442 /*
3443  * Functions to access Pointer Masking feature registers
3444  * We have to check if current priv lvl could modify
3445  * csr in given mode
3446  */
3447 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
3448 {
3449     int csr_priv = get_field(csrno, 0x300);
3450     int pm_current;
3451 
3452     if (env->debugger) {
3453         return false;
3454     }
3455     /*
3456      * If priv lvls differ that means we're accessing csr from higher priv lvl,
3457      * so allow the access
3458      */
3459     if (env->priv != csr_priv) {
3460         return false;
3461     }
3462     switch (env->priv) {
3463     case PRV_M:
3464         pm_current = get_field(env->mmte, M_PM_CURRENT);
3465         break;
3466     case PRV_S:
3467         pm_current = get_field(env->mmte, S_PM_CURRENT);
3468         break;
3469     case PRV_U:
3470         pm_current = get_field(env->mmte, U_PM_CURRENT);
3471         break;
3472     default:
3473         g_assert_not_reached();
3474     }
3475     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
3476     return !pm_current;
3477 }
3478 
3479 static RISCVException read_mmte(CPURISCVState *env, int csrno,
3480                                 target_ulong *val)
3481 {
3482     *val = env->mmte & MMTE_MASK;
3483     return RISCV_EXCP_NONE;
3484 }
3485 
3486 static RISCVException write_mmte(CPURISCVState *env, int csrno,
3487                                  target_ulong val)
3488 {
3489     uint64_t mstatus;
3490     target_ulong wpri_val = val & MMTE_MASK;
3491 
3492     if (val != wpri_val) {
3493         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
3494                       "MMTE: WPRI violation written 0x", val,
3495                       "vs expected 0x", wpri_val);
3496     }
3497     /* for machine mode pm.current is hardwired to 1 */
3498     wpri_val |= MMTE_M_PM_CURRENT;
3499 
3500     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
3501     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
3502     env->mmte = wpri_val | PM_EXT_DIRTY;
3503     riscv_cpu_update_mask(env);
3504 
3505     /* Set XS and SD bits, since PM CSRs are dirty */
3506     mstatus = env->mstatus | MSTATUS_XS;
3507     write_mstatus(env, csrno, mstatus);
3508     return RISCV_EXCP_NONE;
3509 }
3510 
3511 static RISCVException read_smte(CPURISCVState *env, int csrno,
3512                                 target_ulong *val)
3513 {
3514     *val = env->mmte & SMTE_MASK;
3515     return RISCV_EXCP_NONE;
3516 }
3517 
3518 static RISCVException write_smte(CPURISCVState *env, int csrno,
3519                                  target_ulong val)
3520 {
3521     target_ulong wpri_val = val & SMTE_MASK;
3522 
3523     if (val != wpri_val) {
3524         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
3525                       "SMTE: WPRI violation written 0x", val,
3526                       "vs expected 0x", wpri_val);
3527     }
3528 
3529     /* if pm.current==0 we can't modify current PM CSRs */
3530     if (check_pm_current_disabled(env, csrno)) {
3531         return RISCV_EXCP_NONE;
3532     }
3533 
3534     wpri_val |= (env->mmte & ~SMTE_MASK);
3535     write_mmte(env, csrno, wpri_val);
3536     return RISCV_EXCP_NONE;
3537 }
3538 
3539 static RISCVException read_umte(CPURISCVState *env, int csrno,
3540                                 target_ulong *val)
3541 {
3542     *val = env->mmte & UMTE_MASK;
3543     return RISCV_EXCP_NONE;
3544 }
3545 
3546 static RISCVException write_umte(CPURISCVState *env, int csrno,
3547                                  target_ulong val)
3548 {
3549     target_ulong wpri_val = val & UMTE_MASK;
3550 
3551     if (val != wpri_val) {
3552         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
3553                       "UMTE: WPRI violation written 0x", val,
3554                       "vs expected 0x", wpri_val);
3555     }
3556 
3557     if (check_pm_current_disabled(env, csrno)) {
3558         return RISCV_EXCP_NONE;
3559     }
3560 
3561     wpri_val |= (env->mmte & ~UMTE_MASK);
3562     write_mmte(env, csrno, wpri_val);
3563     return RISCV_EXCP_NONE;
3564 }
3565 
3566 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
3567                                    target_ulong *val)
3568 {
3569     *val = env->mpmmask;
3570     return RISCV_EXCP_NONE;
3571 }
3572 
3573 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
3574                                     target_ulong val)
3575 {
3576     uint64_t mstatus;
3577 
3578     env->mpmmask = val;
3579     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
3580         env->cur_pmmask = val;
3581     }
3582     env->mmte |= PM_EXT_DIRTY;
3583 
3584     /* Set XS and SD bits, since PM CSRs are dirty */
3585     mstatus = env->mstatus | MSTATUS_XS;
3586     write_mstatus(env, csrno, mstatus);
3587     return RISCV_EXCP_NONE;
3588 }
3589 
3590 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
3591                                    target_ulong *val)
3592 {
3593     *val = env->spmmask;
3594     return RISCV_EXCP_NONE;
3595 }
3596 
3597 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
3598                                     target_ulong val)
3599 {
3600     uint64_t mstatus;
3601 
3602     /* if pm.current==0 we can't modify current PM CSRs */
3603     if (check_pm_current_disabled(env, csrno)) {
3604         return RISCV_EXCP_NONE;
3605     }
3606     env->spmmask = val;
3607     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
3608         env->cur_pmmask = val;
3609     }
3610     env->mmte |= PM_EXT_DIRTY;
3611 
3612     /* Set XS and SD bits, since PM CSRs are dirty */
3613     mstatus = env->mstatus | MSTATUS_XS;
3614     write_mstatus(env, csrno, mstatus);
3615     return RISCV_EXCP_NONE;
3616 }
3617 
3618 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
3619                                    target_ulong *val)
3620 {
3621     *val = env->upmmask;
3622     return RISCV_EXCP_NONE;
3623 }
3624 
3625 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
3626                                     target_ulong val)
3627 {
3628     uint64_t mstatus;
3629 
3630     /* if pm.current==0 we can't modify current PM CSRs */
3631     if (check_pm_current_disabled(env, csrno)) {
3632         return RISCV_EXCP_NONE;
3633     }
3634     env->upmmask = val;
3635     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
3636         env->cur_pmmask = val;
3637     }
3638     env->mmte |= PM_EXT_DIRTY;
3639 
3640     /* Set XS and SD bits, since PM CSRs are dirty */
3641     mstatus = env->mstatus | MSTATUS_XS;
3642     write_mstatus(env, csrno, mstatus);
3643     return RISCV_EXCP_NONE;
3644 }
3645 
3646 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
3647                                    target_ulong *val)
3648 {
3649     *val = env->mpmbase;
3650     return RISCV_EXCP_NONE;
3651 }
3652 
3653 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
3654                                     target_ulong val)
3655 {
3656     uint64_t mstatus;
3657 
3658     env->mpmbase = val;
3659     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
3660         env->cur_pmbase = val;
3661     }
3662     env->mmte |= PM_EXT_DIRTY;
3663 
3664     /* Set XS and SD bits, since PM CSRs are dirty */
3665     mstatus = env->mstatus | MSTATUS_XS;
3666     write_mstatus(env, csrno, mstatus);
3667     return RISCV_EXCP_NONE;
3668 }
3669 
3670 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
3671                                    target_ulong *val)
3672 {
3673     *val = env->spmbase;
3674     return RISCV_EXCP_NONE;
3675 }
3676 
3677 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
3678                                     target_ulong val)
3679 {
3680     uint64_t mstatus;
3681 
3682     /* if pm.current==0 we can't modify current PM CSRs */
3683     if (check_pm_current_disabled(env, csrno)) {
3684         return RISCV_EXCP_NONE;
3685     }
3686     env->spmbase = val;
3687     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
3688         env->cur_pmbase = val;
3689     }
3690     env->mmte |= PM_EXT_DIRTY;
3691 
3692     /* Set XS and SD bits, since PM CSRs are dirty */
3693     mstatus = env->mstatus | MSTATUS_XS;
3694     write_mstatus(env, csrno, mstatus);
3695     return RISCV_EXCP_NONE;
3696 }
3697 
3698 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
3699                                    target_ulong *val)
3700 {
3701     *val = env->upmbase;
3702     return RISCV_EXCP_NONE;
3703 }
3704 
3705 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
3706                                     target_ulong val)
3707 {
3708     uint64_t mstatus;
3709 
3710     /* if pm.current==0 we can't modify current PM CSRs */
3711     if (check_pm_current_disabled(env, csrno)) {
3712         return RISCV_EXCP_NONE;
3713     }
3714     env->upmbase = val;
3715     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
3716         env->cur_pmbase = val;
3717     }
3718     env->mmte |= PM_EXT_DIRTY;
3719 
3720     /* Set XS and SD bits, since PM CSRs are dirty */
3721     mstatus = env->mstatus | MSTATUS_XS;
3722     write_mstatus(env, csrno, mstatus);
3723     return RISCV_EXCP_NONE;
3724 }
3725 
3726 #endif
3727 
3728 /* Crypto Extension */
3729 static RISCVException rmw_seed(CPURISCVState *env, int csrno,
3730                                target_ulong *ret_value,
3731                                target_ulong new_value,
3732                                target_ulong write_mask)
3733 {
3734     uint16_t random_v;
3735     Error *random_e = NULL;
3736     int random_r;
3737     target_ulong rval;
3738 
3739     random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
3740     if (unlikely(random_r < 0)) {
3741         /*
3742          * Failed, for unknown reasons in the crypto subsystem.
3743          * The best we can do is log the reason and return a
3744          * failure indication to the guest.  There is no reason
3745          * we know to expect the failure to be transitory, so
3746          * indicate DEAD to avoid having the guest spin on WAIT.
3747          */
3748         qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
3749                       __func__, error_get_pretty(random_e));
3750         error_free(random_e);
3751         rval = SEED_OPST_DEAD;
3752     } else {
3753         rval = random_v | SEED_OPST_ES16;
3754     }
3755 
3756     if (ret_value) {
3757         *ret_value = rval;
3758     }
3759 
3760     return RISCV_EXCP_NONE;
3761 }
3762 
3763 /*
3764  * riscv_csrrw - read and/or update control and status register
3765  *
3766  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
3767  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
3768  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
3769  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
3770  */
3771 
3772 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
3773                                                int csrno,
3774                                                bool write_mask,
3775                                                RISCVCPU *cpu)
3776 {
3777     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
3778     int read_only = get_field(csrno, 0xC00) == 3;
3779     int csr_min_priv = csr_ops[csrno].min_priv_ver;
3780 
3781     /* ensure the CSR extension is enabled. */
3782     if (!cpu->cfg.ext_icsr) {
3783         return RISCV_EXCP_ILLEGAL_INST;
3784     }
3785 
3786     if (env->priv_ver < csr_min_priv) {
3787         return RISCV_EXCP_ILLEGAL_INST;
3788     }
3789 
3790     /* check predicate */
3791     if (!csr_ops[csrno].predicate) {
3792         return RISCV_EXCP_ILLEGAL_INST;
3793     }
3794 
3795     if (write_mask && read_only) {
3796         return RISCV_EXCP_ILLEGAL_INST;
3797     }
3798 
3799     RISCVException ret = csr_ops[csrno].predicate(env, csrno);
3800     if (ret != RISCV_EXCP_NONE) {
3801         return ret;
3802     }
3803 
3804 #if !defined(CONFIG_USER_ONLY)
3805     int csr_priv, effective_priv = env->priv;
3806 
3807     if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
3808         !riscv_cpu_virt_enabled(env)) {
3809         /*
3810          * We are in HS mode. Add 1 to the effective privledge level to
3811          * allow us to access the Hypervisor CSRs.
3812          */
3813         effective_priv++;
3814     }
3815 
3816     csr_priv = get_field(csrno, 0x300);
3817     if (!env->debugger && (effective_priv < csr_priv)) {
3818         if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
3819             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
3820         }
3821         return RISCV_EXCP_ILLEGAL_INST;
3822     }
3823 #endif
3824     return RISCV_EXCP_NONE;
3825 }
3826 
3827 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
3828                                        target_ulong *ret_value,
3829                                        target_ulong new_value,
3830                                        target_ulong write_mask)
3831 {
3832     RISCVException ret;
3833     target_ulong old_value;
3834 
3835     /* execute combined read/write operation if it exists */
3836     if (csr_ops[csrno].op) {
3837         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
3838     }
3839 
3840     /* if no accessor exists then return failure */
3841     if (!csr_ops[csrno].read) {
3842         return RISCV_EXCP_ILLEGAL_INST;
3843     }
3844     /* read old value */
3845     ret = csr_ops[csrno].read(env, csrno, &old_value);
3846     if (ret != RISCV_EXCP_NONE) {
3847         return ret;
3848     }
3849 
3850     /* write value if writable and write mask set, otherwise drop writes */
3851     if (write_mask) {
3852         new_value = (old_value & ~write_mask) | (new_value & write_mask);
3853         if (csr_ops[csrno].write) {
3854             ret = csr_ops[csrno].write(env, csrno, new_value);
3855             if (ret != RISCV_EXCP_NONE) {
3856                 return ret;
3857             }
3858         }
3859     }
3860 
3861     /* return old value */
3862     if (ret_value) {
3863         *ret_value = old_value;
3864     }
3865 
3866     return RISCV_EXCP_NONE;
3867 }
3868 
3869 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
3870                            target_ulong *ret_value,
3871                            target_ulong new_value, target_ulong write_mask)
3872 {
3873     RISCVCPU *cpu = env_archcpu(env);
3874 
3875     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
3876     if (ret != RISCV_EXCP_NONE) {
3877         return ret;
3878     }
3879 
3880     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
3881 }
3882 
3883 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
3884                                         Int128 *ret_value,
3885                                         Int128 new_value,
3886                                         Int128 write_mask)
3887 {
3888     RISCVException ret;
3889     Int128 old_value;
3890 
3891     /* read old value */
3892     ret = csr_ops[csrno].read128(env, csrno, &old_value);
3893     if (ret != RISCV_EXCP_NONE) {
3894         return ret;
3895     }
3896 
3897     /* write value if writable and write mask set, otherwise drop writes */
3898     if (int128_nz(write_mask)) {
3899         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
3900                               int128_and(new_value, write_mask));
3901         if (csr_ops[csrno].write128) {
3902             ret = csr_ops[csrno].write128(env, csrno, new_value);
3903             if (ret != RISCV_EXCP_NONE) {
3904                 return ret;
3905             }
3906         } else if (csr_ops[csrno].write) {
3907             /* avoids having to write wrappers for all registers */
3908             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
3909             if (ret != RISCV_EXCP_NONE) {
3910                 return ret;
3911             }
3912         }
3913     }
3914 
3915     /* return old value */
3916     if (ret_value) {
3917         *ret_value = old_value;
3918     }
3919 
3920     return RISCV_EXCP_NONE;
3921 }
3922 
3923 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
3924                                 Int128 *ret_value,
3925                                 Int128 new_value, Int128 write_mask)
3926 {
3927     RISCVException ret;
3928     RISCVCPU *cpu = env_archcpu(env);
3929 
3930     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
3931     if (ret != RISCV_EXCP_NONE) {
3932         return ret;
3933     }
3934 
3935     if (csr_ops[csrno].read128) {
3936         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
3937     }
3938 
3939     /*
3940      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
3941      * at all defined.
3942      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
3943      * significant), for those, this fallback is correctly handling the accesses
3944      */
3945     target_ulong old_value;
3946     ret = riscv_csrrw_do64(env, csrno, &old_value,
3947                            int128_getlo(new_value),
3948                            int128_getlo(write_mask));
3949     if (ret == RISCV_EXCP_NONE && ret_value) {
3950         *ret_value = int128_make64(old_value);
3951     }
3952     return ret;
3953 }
3954 
3955 /*
3956  * Debugger support.  If not in user mode, set env->debugger before the
3957  * riscv_csrrw call and clear it after the call.
3958  */
3959 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
3960                                  target_ulong *ret_value,
3961                                  target_ulong new_value,
3962                                  target_ulong write_mask)
3963 {
3964     RISCVException ret;
3965 #if !defined(CONFIG_USER_ONLY)
3966     env->debugger = true;
3967 #endif
3968     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
3969 #if !defined(CONFIG_USER_ONLY)
3970     env->debugger = false;
3971 #endif
3972     return ret;
3973 }
3974 
3975 /* Control and Status Register function table */
3976 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
3977     /* User Floating-Point CSRs */
3978     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
3979     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
3980     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
3981     /* Vector CSRs */
3982     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
3983     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
3984     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
3985     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
3986     [CSR_VL]       = { "vl",       vs,     read_vl                    },
3987     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
3988     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
3989     /* User Timers and Counters */
3990     [CSR_CYCLE]    = { "cycle",    ctr,    read_hpmcounter  },
3991     [CSR_INSTRET]  = { "instret",  ctr,    read_hpmcounter  },
3992     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_hpmcounterh },
3993     [CSR_INSTRETH] = { "instreth", ctr32,  read_hpmcounterh },
3994 
3995     /*
3996      * In privileged mode, the monitor will have to emulate TIME CSRs only if
3997      * rdtime callback is not provided by machine/platform emulation.
3998      */
3999     [CSR_TIME]  = { "time",  ctr,   read_time  },
4000     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
4001 
4002     /* Crypto Extension */
4003     [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
4004 
4005 #if !defined(CONFIG_USER_ONLY)
4006     /* Machine Timers and Counters */
4007     [CSR_MCYCLE]    = { "mcycle",    any,   read_hpmcounter,
4008                         write_mhpmcounter                    },
4009     [CSR_MINSTRET]  = { "minstret",  any,   read_hpmcounter,
4010                         write_mhpmcounter                    },
4011     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_hpmcounterh,
4012                         write_mhpmcounterh                   },
4013     [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh,
4014                         write_mhpmcounterh                   },
4015 
4016     /* Machine Information Registers */
4017     [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
4018     [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
4019     [CSR_MIMPID]    = { "mimpid",    any,   read_mimpid    },
4020     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
4021 
4022     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
4023                           .min_priv_ver = PRIV_VERSION_1_12_0 },
4024     /* Machine Trap Setup */
4025     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus, write_mstatus,
4026                           NULL,                read_mstatus_i128           },
4027     [CSR_MISA]        = { "misa",       any,   read_misa,    write_misa,
4028                           NULL,                read_misa_i128              },
4029     [CSR_MIDELEG]     = { "mideleg",    any,   NULL, NULL,   rmw_mideleg   },
4030     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg, write_medeleg },
4031     [CSR_MIE]         = { "mie",        any,   NULL, NULL,   rmw_mie       },
4032     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,   write_mtvec   },
4033     [CSR_MCOUNTEREN]  = { "mcounteren", umode, read_mcounteren,
4034                           write_mcounteren                                 },
4035 
4036     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,
4037                           write_mstatush                                   },
4038 
4039     /* Machine Trap Handling */
4040     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch,
4041                        NULL, read_mscratch_i128, write_mscratch_i128   },
4042     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
4043     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
4044     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
4045     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
4046 
4047     /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
4048     [CSR_MISELECT] = { "miselect", aia_any,   NULL, NULL,    rmw_xiselect },
4049     [CSR_MIREG]    = { "mireg",    aia_any,   NULL, NULL,    rmw_xireg },
4050 
4051     /* Machine-Level Interrupts (AIA) */
4052     [CSR_MTOPEI]   = { "mtopei",   aia_any, NULL, NULL, rmw_xtopei },
4053     [CSR_MTOPI]    = { "mtopi",    aia_any, read_mtopi },
4054 
4055     /* Virtual Interrupts for Supervisor Level (AIA) */
4056     [CSR_MVIEN]    = { "mvien",    aia_any, read_zero, write_ignore },
4057     [CSR_MVIP]     = { "mvip",     aia_any, read_zero, write_ignore },
4058 
4059     /* Machine-Level High-Half CSRs (AIA) */
4060     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
4061     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
4062     [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
4063     [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
4064     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
4065 
4066     /* Execution environment configuration */
4067     [CSR_MENVCFG]  = { "menvcfg",  umode, read_menvcfg,  write_menvcfg,
4068                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4069     [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh,
4070                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4071     [CSR_SENVCFG]  = { "senvcfg",  smode, read_senvcfg,  write_senvcfg,
4072                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4073     [CSR_HENVCFG]  = { "henvcfg",  hmode, read_henvcfg, write_henvcfg,
4074                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4075     [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
4076                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4077 
4078     /* Smstateen extension CSRs */
4079     [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,
4080                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4081     [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,
4082                           write_mstateen0h,
4083                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4084     [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,
4085                         write_mstateen_1_3,
4086                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4087     [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh,
4088                          write_mstateenh_1_3,
4089                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4090     [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,
4091                         write_mstateen_1_3,
4092                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4093     [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh,
4094                          write_mstateenh_1_3,
4095                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4096     [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,
4097                         write_mstateen_1_3,
4098                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4099     [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh,
4100                          write_mstateenh_1_3,
4101                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4102     [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
4103                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4104     [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh,
4105                          write_hstateen0h,
4106                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4107     [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen,
4108                         write_hstateen_1_3,
4109                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4110     [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh,
4111                          write_hstateenh_1_3,
4112                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4113     [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen,
4114                         write_hstateen_1_3,
4115                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4116     [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh,
4117                          write_hstateenh_1_3,
4118                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4119     [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen,
4120                         write_hstateen_1_3,
4121                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4122     [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh,
4123                          write_hstateenh_1_3,
4124                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4125     [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,
4126                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4127     [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen,
4128                         write_sstateen_1_3,
4129                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4130     [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen,
4131                         write_sstateen_1_3,
4132                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4133     [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen,
4134                         write_sstateen_1_3,
4135                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4136 
4137     /* Supervisor Trap Setup */
4138     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus,
4139                          NULL,                read_sstatus_i128               },
4140     [CSR_SIE]        = { "sie",        smode, NULL,   NULL,    rmw_sie        },
4141     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec    },
4142     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
4143                          write_scounteren                                     },
4144 
4145     /* Supervisor Trap Handling */
4146     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
4147                        NULL, read_sscratch_i128, write_sscratch_i128    },
4148     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
4149     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
4150     [CSR_STVAL]    = { "stval",    smode, read_stval,    write_stval    },
4151     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
4152     [CSR_STIMECMP] = { "stimecmp", sstc, read_stimecmp, write_stimecmp,
4153                        .min_priv_ver = PRIV_VERSION_1_12_0 },
4154     [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph,
4155                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4156     [CSR_VSTIMECMP] = { "vstimecmp", sstc, read_vstimecmp,
4157                         write_vstimecmp,
4158                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4159     [CSR_VSTIMECMPH] = { "vstimecmph", sstc_32, read_vstimecmph,
4160                          write_vstimecmph,
4161                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4162 
4163     /* Supervisor Protection and Translation */
4164     [CSR_SATP]     = { "satp",     smode, read_satp,     write_satp     },
4165 
4166     /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
4167     [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
4168     [CSR_SIREG]      = { "sireg",      aia_smode, NULL, NULL, rmw_xireg },
4169 
4170     /* Supervisor-Level Interrupts (AIA) */
4171     [CSR_STOPEI]     = { "stopei",     aia_smode, NULL, NULL, rmw_xtopei },
4172     [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
4173 
4174     /* Supervisor-Level High-Half CSRs (AIA) */
4175     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
4176     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
4177 
4178     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus, write_hstatus,
4179                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4180     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg, write_hedeleg,
4181                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4182     [CSR_HIDELEG]     = { "hideleg",     hmode,   NULL,   NULL, rmw_hideleg,
4183                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4184     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL, rmw_hvip,
4185                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4186     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL, rmw_hip,
4187                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4188     [CSR_HIE]         = { "hie",         hmode,   NULL,   NULL, rmw_hie,
4189                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4190     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,
4191                           write_hcounteren,
4192                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4193     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,   write_hgeie,
4194                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4195     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,   write_htval,
4196                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4197     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,  write_htinst,
4198                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4199     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,
4200                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4201     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,   write_hgatp,
4202                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4203     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,
4204                           write_htimedelta,
4205                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4206     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
4207                           write_htimedeltah,
4208                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4209 
4210     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,
4211                           write_vsstatus,
4212                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4213     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL, rmw_vsip,
4214                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4215     [CSR_VSIE]        = { "vsie",        hmode,   NULL,    NULL, rmw_vsie ,
4216                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4217     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,   write_vstvec,
4218                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4219     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,
4220                           write_vsscratch,
4221                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4222     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,    write_vsepc,
4223                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4224     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,  write_vscause,
4225                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4226     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,   write_vstval,
4227                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4228     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,    write_vsatp,
4229                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4230 
4231     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,   write_mtval2,
4232                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4233     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,   write_mtinst,
4234                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4235 
4236     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
4237     [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero, write_ignore },
4238     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl,
4239                           write_hvictl                                      },
4240     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,
4241                           write_hviprio1                                    },
4242     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,
4243                           write_hviprio2                                    },
4244 
4245     /*
4246      * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
4247      */
4248     [CSR_VSISELECT]   = { "vsiselect",   aia_hmode, NULL, NULL,
4249                           rmw_xiselect                                     },
4250     [CSR_VSIREG]      = { "vsireg",      aia_hmode, NULL, NULL, rmw_xireg  },
4251 
4252     /* VS-Level Interrupts (H-extension with AIA) */
4253     [CSR_VSTOPEI]     = { "vstopei",     aia_hmode, NULL, NULL, rmw_xtopei },
4254     [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
4255 
4256     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
4257     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL,
4258                           rmw_hidelegh                                      },
4259     [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero,
4260                           write_ignore                                      },
4261     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
4262     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h,
4263                           write_hviprio1h                                   },
4264     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h,
4265                           write_hviprio2h                                   },
4266     [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
4267     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
4268 
4269     /* Physical Memory Protection */
4270     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
4271                          .min_priv_ver = PRIV_VERSION_1_11_0           },
4272     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
4273     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
4274     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
4275     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
4276     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
4277     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
4278     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
4279     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
4280     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
4281     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
4282     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
4283     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
4284     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
4285     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
4286     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
4287     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
4288     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
4289     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
4290     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
4291     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
4292 
4293     /* Debug CSRs */
4294     [CSR_TSELECT]   =  { "tselect", debug, read_tselect, write_tselect },
4295     [CSR_TDATA1]    =  { "tdata1",  debug, read_tdata,   write_tdata   },
4296     [CSR_TDATA2]    =  { "tdata2",  debug, read_tdata,   write_tdata   },
4297     [CSR_TDATA3]    =  { "tdata3",  debug, read_tdata,   write_tdata   },
4298     [CSR_TINFO]     =  { "tinfo",   debug, read_tinfo,   write_ignore  },
4299 
4300     /* User Pointer Masking */
4301     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,  write_umte },
4302     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask,
4303                          write_upmmask                                      },
4304     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase,
4305                          write_upmbase                                      },
4306     /* Machine Pointer Masking */
4307     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,  write_mmte },
4308     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask,
4309                          write_mpmmask                                      },
4310     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase,
4311                          write_mpmbase                                      },
4312     /* Supervisor Pointer Masking */
4313     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,  write_smte },
4314     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask,
4315                          write_spmmask                                      },
4316     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase,
4317                          write_spmbase                                      },
4318 
4319     /* Performance Counters */
4320     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_hpmcounter },
4321     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_hpmcounter },
4322     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_hpmcounter },
4323     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_hpmcounter },
4324     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_hpmcounter },
4325     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_hpmcounter },
4326     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_hpmcounter },
4327     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_hpmcounter },
4328     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_hpmcounter },
4329     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_hpmcounter },
4330     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_hpmcounter },
4331     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_hpmcounter },
4332     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_hpmcounter },
4333     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_hpmcounter },
4334     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_hpmcounter },
4335     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_hpmcounter },
4336     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_hpmcounter },
4337     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_hpmcounter },
4338     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_hpmcounter },
4339     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_hpmcounter },
4340     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_hpmcounter },
4341     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_hpmcounter },
4342     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_hpmcounter },
4343     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_hpmcounter },
4344     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_hpmcounter },
4345     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_hpmcounter },
4346     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_hpmcounter },
4347     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_hpmcounter },
4348     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_hpmcounter },
4349 
4350     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   mctr,    read_hpmcounter,
4351                              write_mhpmcounter                         },
4352     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   mctr,    read_hpmcounter,
4353                              write_mhpmcounter                         },
4354     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   mctr,    read_hpmcounter,
4355                              write_mhpmcounter                         },
4356     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   mctr,    read_hpmcounter,
4357                              write_mhpmcounter                         },
4358     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   mctr,    read_hpmcounter,
4359                              write_mhpmcounter                         },
4360     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   mctr,    read_hpmcounter,
4361                              write_mhpmcounter                         },
4362     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   mctr,    read_hpmcounter,
4363                              write_mhpmcounter                         },
4364     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  mctr,    read_hpmcounter,
4365                              write_mhpmcounter                         },
4366     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  mctr,    read_hpmcounter,
4367                              write_mhpmcounter                         },
4368     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  mctr,    read_hpmcounter,
4369                              write_mhpmcounter                         },
4370     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  mctr,    read_hpmcounter,
4371                              write_mhpmcounter                         },
4372     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  mctr,    read_hpmcounter,
4373                              write_mhpmcounter                         },
4374     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  mctr,    read_hpmcounter,
4375                              write_mhpmcounter                         },
4376     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  mctr,    read_hpmcounter,
4377                              write_mhpmcounter                         },
4378     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  mctr,    read_hpmcounter,
4379                              write_mhpmcounter                         },
4380     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  mctr,    read_hpmcounter,
4381                              write_mhpmcounter                         },
4382     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  mctr,    read_hpmcounter,
4383                              write_mhpmcounter                         },
4384     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  mctr,    read_hpmcounter,
4385                              write_mhpmcounter                         },
4386     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  mctr,    read_hpmcounter,
4387                              write_mhpmcounter                         },
4388     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  mctr,    read_hpmcounter,
4389                              write_mhpmcounter                         },
4390     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  mctr,    read_hpmcounter,
4391                              write_mhpmcounter                         },
4392     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  mctr,    read_hpmcounter,
4393                              write_mhpmcounter                         },
4394     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  mctr,    read_hpmcounter,
4395                              write_mhpmcounter                         },
4396     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  mctr,    read_hpmcounter,
4397                              write_mhpmcounter                         },
4398     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  mctr,    read_hpmcounter,
4399                              write_mhpmcounter                         },
4400     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  mctr,    read_hpmcounter,
4401                              write_mhpmcounter                         },
4402     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  mctr,    read_hpmcounter,
4403                              write_mhpmcounter                         },
4404     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  mctr,    read_hpmcounter,
4405                              write_mhpmcounter                         },
4406     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  mctr,    read_hpmcounter,
4407                              write_mhpmcounter                         },
4408 
4409     [CSR_MCOUNTINHIBIT]  = { "mcountinhibit",  any, read_mcountinhibit,
4410                              write_mcountinhibit,
4411                              .min_priv_ver = PRIV_VERSION_1_11_0       },
4412 
4413     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_mhpmevent,
4414                              write_mhpmevent                           },
4415     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_mhpmevent,
4416                              write_mhpmevent                           },
4417     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_mhpmevent,
4418                              write_mhpmevent                           },
4419     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_mhpmevent,
4420                              write_mhpmevent                           },
4421     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_mhpmevent,
4422                              write_mhpmevent                           },
4423     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_mhpmevent,
4424                              write_mhpmevent                           },
4425     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_mhpmevent,
4426                              write_mhpmevent                           },
4427     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_mhpmevent,
4428                              write_mhpmevent                           },
4429     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_mhpmevent,
4430                              write_mhpmevent                           },
4431     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_mhpmevent,
4432                              write_mhpmevent                           },
4433     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_mhpmevent,
4434                              write_mhpmevent                           },
4435     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_mhpmevent,
4436                              write_mhpmevent                           },
4437     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_mhpmevent,
4438                              write_mhpmevent                           },
4439     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_mhpmevent,
4440                              write_mhpmevent                           },
4441     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_mhpmevent,
4442                              write_mhpmevent                           },
4443     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_mhpmevent,
4444                              write_mhpmevent                           },
4445     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_mhpmevent,
4446                              write_mhpmevent                           },
4447     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_mhpmevent,
4448                              write_mhpmevent                           },
4449     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_mhpmevent,
4450                              write_mhpmevent                           },
4451     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_mhpmevent,
4452                              write_mhpmevent                           },
4453     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_mhpmevent,
4454                              write_mhpmevent                           },
4455     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_mhpmevent,
4456                              write_mhpmevent                           },
4457     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_mhpmevent,
4458                              write_mhpmevent                           },
4459     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_mhpmevent,
4460                              write_mhpmevent                           },
4461     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_mhpmevent,
4462                              write_mhpmevent                           },
4463     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_mhpmevent,
4464                              write_mhpmevent                           },
4465     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_mhpmevent,
4466                              write_mhpmevent                           },
4467     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_mhpmevent,
4468                              write_mhpmevent                           },
4469     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_mhpmevent,
4470                              write_mhpmevent                           },
4471 
4472     [CSR_MHPMEVENT3H]    = { "mhpmevent3h",    sscofpmf,  read_mhpmeventh,
4473                              write_mhpmeventh,
4474                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4475     [CSR_MHPMEVENT4H]    = { "mhpmevent4h",    sscofpmf,  read_mhpmeventh,
4476                              write_mhpmeventh,
4477                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4478     [CSR_MHPMEVENT5H]    = { "mhpmevent5h",    sscofpmf,  read_mhpmeventh,
4479                              write_mhpmeventh,
4480                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4481     [CSR_MHPMEVENT6H]    = { "mhpmevent6h",    sscofpmf,  read_mhpmeventh,
4482                              write_mhpmeventh,
4483                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4484     [CSR_MHPMEVENT7H]    = { "mhpmevent7h",    sscofpmf,  read_mhpmeventh,
4485                              write_mhpmeventh,
4486                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4487     [CSR_MHPMEVENT8H]    = { "mhpmevent8h",    sscofpmf,  read_mhpmeventh,
4488                              write_mhpmeventh,
4489                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4490     [CSR_MHPMEVENT9H]    = { "mhpmevent9h",    sscofpmf,  read_mhpmeventh,
4491                              write_mhpmeventh,
4492                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4493     [CSR_MHPMEVENT10H]   = { "mhpmevent10h",    sscofpmf,  read_mhpmeventh,
4494                              write_mhpmeventh,
4495                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4496     [CSR_MHPMEVENT11H]   = { "mhpmevent11h",    sscofpmf,  read_mhpmeventh,
4497                              write_mhpmeventh,
4498                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4499     [CSR_MHPMEVENT12H]   = { "mhpmevent12h",    sscofpmf,  read_mhpmeventh,
4500                              write_mhpmeventh,
4501                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4502     [CSR_MHPMEVENT13H]   = { "mhpmevent13h",    sscofpmf,  read_mhpmeventh,
4503                              write_mhpmeventh,
4504                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4505     [CSR_MHPMEVENT14H]   = { "mhpmevent14h",    sscofpmf,  read_mhpmeventh,
4506                              write_mhpmeventh,
4507                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4508     [CSR_MHPMEVENT15H]   = { "mhpmevent15h",    sscofpmf,  read_mhpmeventh,
4509                              write_mhpmeventh,
4510                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4511     [CSR_MHPMEVENT16H]   = { "mhpmevent16h",    sscofpmf,  read_mhpmeventh,
4512                              write_mhpmeventh,
4513                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4514     [CSR_MHPMEVENT17H]   = { "mhpmevent17h",    sscofpmf,  read_mhpmeventh,
4515                              write_mhpmeventh,
4516                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4517     [CSR_MHPMEVENT18H]   = { "mhpmevent18h",    sscofpmf,  read_mhpmeventh,
4518                              write_mhpmeventh,
4519                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4520     [CSR_MHPMEVENT19H]   = { "mhpmevent19h",    sscofpmf,  read_mhpmeventh,
4521                              write_mhpmeventh,
4522                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4523     [CSR_MHPMEVENT20H]   = { "mhpmevent20h",    sscofpmf,  read_mhpmeventh,
4524                              write_mhpmeventh,
4525                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4526     [CSR_MHPMEVENT21H]   = { "mhpmevent21h",    sscofpmf,  read_mhpmeventh,
4527                              write_mhpmeventh,
4528                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4529     [CSR_MHPMEVENT22H]   = { "mhpmevent22h",    sscofpmf,  read_mhpmeventh,
4530                              write_mhpmeventh,
4531                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4532     [CSR_MHPMEVENT23H]   = { "mhpmevent23h",    sscofpmf,  read_mhpmeventh,
4533                              write_mhpmeventh,
4534                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4535     [CSR_MHPMEVENT24H]   = { "mhpmevent24h",    sscofpmf,  read_mhpmeventh,
4536                              write_mhpmeventh,
4537                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4538     [CSR_MHPMEVENT25H]   = { "mhpmevent25h",    sscofpmf,  read_mhpmeventh,
4539                              write_mhpmeventh,
4540                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4541     [CSR_MHPMEVENT26H]   = { "mhpmevent26h",    sscofpmf,  read_mhpmeventh,
4542                              write_mhpmeventh,
4543                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4544     [CSR_MHPMEVENT27H]   = { "mhpmevent27h",    sscofpmf,  read_mhpmeventh,
4545                              write_mhpmeventh,
4546                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4547     [CSR_MHPMEVENT28H]   = { "mhpmevent28h",    sscofpmf,  read_mhpmeventh,
4548                              write_mhpmeventh,
4549                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4550     [CSR_MHPMEVENT29H]   = { "mhpmevent29h",    sscofpmf,  read_mhpmeventh,
4551                              write_mhpmeventh,
4552                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4553     [CSR_MHPMEVENT30H]   = { "mhpmevent30h",    sscofpmf,  read_mhpmeventh,
4554                              write_mhpmeventh,
4555                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4556     [CSR_MHPMEVENT31H]   = { "mhpmevent31h",    sscofpmf,  read_mhpmeventh,
4557                              write_mhpmeventh,
4558                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4559 
4560     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_hpmcounterh },
4561     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_hpmcounterh },
4562     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_hpmcounterh },
4563     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_hpmcounterh },
4564     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_hpmcounterh },
4565     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_hpmcounterh },
4566     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_hpmcounterh },
4567     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_hpmcounterh },
4568     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_hpmcounterh },
4569     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_hpmcounterh },
4570     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_hpmcounterh },
4571     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_hpmcounterh },
4572     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_hpmcounterh },
4573     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_hpmcounterh },
4574     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_hpmcounterh },
4575     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_hpmcounterh },
4576     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_hpmcounterh },
4577     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_hpmcounterh },
4578     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_hpmcounterh },
4579     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_hpmcounterh },
4580     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_hpmcounterh },
4581     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_hpmcounterh },
4582     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_hpmcounterh },
4583     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_hpmcounterh },
4584     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_hpmcounterh },
4585     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_hpmcounterh },
4586     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_hpmcounterh },
4587     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_hpmcounterh },
4588     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_hpmcounterh },
4589 
4590     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  mctr32,  read_hpmcounterh,
4591                              write_mhpmcounterh                         },
4592     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  mctr32,  read_hpmcounterh,
4593                              write_mhpmcounterh                         },
4594     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  mctr32,  read_hpmcounterh,
4595                              write_mhpmcounterh                         },
4596     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  mctr32,  read_hpmcounterh,
4597                              write_mhpmcounterh                         },
4598     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  mctr32,  read_hpmcounterh,
4599                              write_mhpmcounterh                         },
4600     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  mctr32,  read_hpmcounterh,
4601                              write_mhpmcounterh                         },
4602     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  mctr32,  read_hpmcounterh,
4603                              write_mhpmcounterh                         },
4604     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32,  read_hpmcounterh,
4605                              write_mhpmcounterh                         },
4606     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32,  read_hpmcounterh,
4607                              write_mhpmcounterh                         },
4608     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32,  read_hpmcounterh,
4609                              write_mhpmcounterh                         },
4610     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32,  read_hpmcounterh,
4611                              write_mhpmcounterh                         },
4612     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32,  read_hpmcounterh,
4613                              write_mhpmcounterh                         },
4614     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32,  read_hpmcounterh,
4615                              write_mhpmcounterh                         },
4616     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32,  read_hpmcounterh,
4617                              write_mhpmcounterh                         },
4618     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32,  read_hpmcounterh,
4619                              write_mhpmcounterh                         },
4620     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32,  read_hpmcounterh,
4621                              write_mhpmcounterh                         },
4622     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32,  read_hpmcounterh,
4623                              write_mhpmcounterh                         },
4624     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32,  read_hpmcounterh,
4625                              write_mhpmcounterh                         },
4626     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32,  read_hpmcounterh,
4627                              write_mhpmcounterh                         },
4628     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32,  read_hpmcounterh,
4629                              write_mhpmcounterh                         },
4630     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32,  read_hpmcounterh,
4631                              write_mhpmcounterh                         },
4632     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32,  read_hpmcounterh,
4633                              write_mhpmcounterh                         },
4634     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32,  read_hpmcounterh,
4635                              write_mhpmcounterh                         },
4636     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32,  read_hpmcounterh,
4637                              write_mhpmcounterh                         },
4638     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32,  read_hpmcounterh,
4639                              write_mhpmcounterh                         },
4640     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32,  read_hpmcounterh,
4641                              write_mhpmcounterh                         },
4642     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32,  read_hpmcounterh,
4643                              write_mhpmcounterh                         },
4644     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32,  read_hpmcounterh,
4645                              write_mhpmcounterh                         },
4646     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32,  read_hpmcounterh,
4647                              write_mhpmcounterh                         },
4648     [CSR_SCOUNTOVF]      = { "scountovf", sscofpmf,  read_scountovf,
4649                              .min_priv_ver = PRIV_VERSION_1_12_0 },
4650 
4651 #endif /* !CONFIG_USER_ONLY */
4652 };
4653