xref: /openbmc/qemu/target/riscv/csr.c (revision 38256529) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/timer.h"
23 #include "cpu.h"
24 #include "pmu.h"
25 #include "time_helper.h"
26 #include "qemu/main-loop.h"
27 #include "exec/exec-all.h"
28 #include "exec/tb-flush.h"
29 #include "sysemu/cpu-timers.h"
30 #include "qemu/guest-random.h"
31 #include "qapi/error.h"
32 
33 /* CSR function table public API */
34 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
35 {
36     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
37 }
38 
39 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
40 {
41     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
42 }
43 
44 /* Predicates */
45 #if !defined(CONFIG_USER_ONLY)
46 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
47 {
48     bool virt = env->virt_enabled;
49 
50     if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
51         return RISCV_EXCP_NONE;
52     }
53 
54     if (!(env->mstateen[index] & bit)) {
55         return RISCV_EXCP_ILLEGAL_INST;
56     }
57 
58     if (virt) {
59         if (!(env->hstateen[index] & bit)) {
60             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
61         }
62 
63         if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
64             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
65         }
66     }
67 
68     if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
69         if (!(env->sstateen[index] & bit)) {
70             return RISCV_EXCP_ILLEGAL_INST;
71         }
72     }
73 
74     return RISCV_EXCP_NONE;
75 }
76 #endif
77 
78 static RISCVException fs(CPURISCVState *env, int csrno)
79 {
80 #if !defined(CONFIG_USER_ONLY)
81     if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
82         !riscv_cpu_cfg(env)->ext_zfinx) {
83         return RISCV_EXCP_ILLEGAL_INST;
84     }
85 #endif
86     return RISCV_EXCP_NONE;
87 }
88 
89 static RISCVException vs(CPURISCVState *env, int csrno)
90 {
91     if (riscv_cpu_cfg(env)->ext_zve32f) {
92 #if !defined(CONFIG_USER_ONLY)
93         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
94             return RISCV_EXCP_ILLEGAL_INST;
95         }
96 #endif
97         return RISCV_EXCP_NONE;
98     }
99     return RISCV_EXCP_ILLEGAL_INST;
100 }
101 
102 static RISCVException ctr(CPURISCVState *env, int csrno)
103 {
104 #if !defined(CONFIG_USER_ONLY)
105     RISCVCPU *cpu = env_archcpu(env);
106     int ctr_index;
107     target_ulong ctr_mask;
108     int base_csrno = CSR_CYCLE;
109     bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
110 
111     if (rv32 && csrno >= CSR_CYCLEH) {
112         /* Offset for RV32 hpmcounternh counters */
113         base_csrno += 0x80;
114     }
115     ctr_index = csrno - base_csrno;
116     ctr_mask = BIT(ctr_index);
117 
118     if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
119         (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
120         goto skip_ext_pmu_check;
121     }
122 
123     if (!(cpu->pmu_avail_ctrs & ctr_mask)) {
124         /* No counter is enabled in PMU or the counter is out of range */
125         return RISCV_EXCP_ILLEGAL_INST;
126     }
127 
128 skip_ext_pmu_check:
129 
130     if (env->debugger) {
131         return RISCV_EXCP_NONE;
132     }
133 
134     if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
135         return RISCV_EXCP_ILLEGAL_INST;
136     }
137 
138     if (env->virt_enabled) {
139         if (!get_field(env->hcounteren, ctr_mask) ||
140             (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
141             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
142         }
143     }
144 
145     if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&
146         !get_field(env->scounteren, ctr_mask)) {
147         return RISCV_EXCP_ILLEGAL_INST;
148     }
149 
150 #endif
151     return RISCV_EXCP_NONE;
152 }
153 
154 static RISCVException ctr32(CPURISCVState *env, int csrno)
155 {
156     if (riscv_cpu_mxl(env) != MXL_RV32) {
157         return RISCV_EXCP_ILLEGAL_INST;
158     }
159 
160     return ctr(env, csrno);
161 }
162 
163 static RISCVException zcmt(CPURISCVState *env, int csrno)
164 {
165     if (!riscv_cpu_cfg(env)->ext_zcmt) {
166         return RISCV_EXCP_ILLEGAL_INST;
167     }
168 
169 #if !defined(CONFIG_USER_ONLY)
170     RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
171     if (ret != RISCV_EXCP_NONE) {
172         return ret;
173     }
174 #endif
175 
176     return RISCV_EXCP_NONE;
177 }
178 
179 #if !defined(CONFIG_USER_ONLY)
180 static RISCVException mctr(CPURISCVState *env, int csrno)
181 {
182     int pmu_num = riscv_cpu_cfg(env)->pmu_num;
183     int ctr_index;
184     int base_csrno = CSR_MHPMCOUNTER3;
185 
186     if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) {
187         /* Offset for RV32 mhpmcounternh counters */
188         base_csrno += 0x80;
189     }
190     ctr_index = csrno - base_csrno;
191     if (!pmu_num || ctr_index >= pmu_num) {
192         /* The PMU is not enabled or counter is out of range*/
193         return RISCV_EXCP_ILLEGAL_INST;
194     }
195 
196     return RISCV_EXCP_NONE;
197 }
198 
199 static RISCVException mctr32(CPURISCVState *env, int csrno)
200 {
201     if (riscv_cpu_mxl(env) != MXL_RV32) {
202         return RISCV_EXCP_ILLEGAL_INST;
203     }
204 
205     return mctr(env, csrno);
206 }
207 
208 static RISCVException sscofpmf(CPURISCVState *env, int csrno)
209 {
210     if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
211         return RISCV_EXCP_ILLEGAL_INST;
212     }
213 
214     return RISCV_EXCP_NONE;
215 }
216 
217 static RISCVException any(CPURISCVState *env, int csrno)
218 {
219     return RISCV_EXCP_NONE;
220 }
221 
222 static RISCVException any32(CPURISCVState *env, int csrno)
223 {
224     if (riscv_cpu_mxl(env) != MXL_RV32) {
225         return RISCV_EXCP_ILLEGAL_INST;
226     }
227 
228     return any(env, csrno);
229 
230 }
231 
232 static int aia_any(CPURISCVState *env, int csrno)
233 {
234     if (!riscv_cpu_cfg(env)->ext_smaia) {
235         return RISCV_EXCP_ILLEGAL_INST;
236     }
237 
238     return any(env, csrno);
239 }
240 
241 static int aia_any32(CPURISCVState *env, int csrno)
242 {
243     if (!riscv_cpu_cfg(env)->ext_smaia) {
244         return RISCV_EXCP_ILLEGAL_INST;
245     }
246 
247     return any32(env, csrno);
248 }
249 
250 static RISCVException smode(CPURISCVState *env, int csrno)
251 {
252     if (riscv_has_ext(env, RVS)) {
253         return RISCV_EXCP_NONE;
254     }
255 
256     return RISCV_EXCP_ILLEGAL_INST;
257 }
258 
259 static int smode32(CPURISCVState *env, int csrno)
260 {
261     if (riscv_cpu_mxl(env) != MXL_RV32) {
262         return RISCV_EXCP_ILLEGAL_INST;
263     }
264 
265     return smode(env, csrno);
266 }
267 
268 static int aia_smode(CPURISCVState *env, int csrno)
269 {
270     if (!riscv_cpu_cfg(env)->ext_ssaia) {
271         return RISCV_EXCP_ILLEGAL_INST;
272     }
273 
274     return smode(env, csrno);
275 }
276 
277 static int aia_smode32(CPURISCVState *env, int csrno)
278 {
279     if (!riscv_cpu_cfg(env)->ext_ssaia) {
280         return RISCV_EXCP_ILLEGAL_INST;
281     }
282 
283     return smode32(env, csrno);
284 }
285 
286 static RISCVException hmode(CPURISCVState *env, int csrno)
287 {
288     if (riscv_has_ext(env, RVH)) {
289         return RISCV_EXCP_NONE;
290     }
291 
292     return RISCV_EXCP_ILLEGAL_INST;
293 }
294 
295 static RISCVException hmode32(CPURISCVState *env, int csrno)
296 {
297     if (riscv_cpu_mxl(env) != MXL_RV32) {
298         return RISCV_EXCP_ILLEGAL_INST;
299     }
300 
301     return hmode(env, csrno);
302 
303 }
304 
305 static RISCVException umode(CPURISCVState *env, int csrno)
306 {
307     if (riscv_has_ext(env, RVU)) {
308         return RISCV_EXCP_NONE;
309     }
310 
311     return RISCV_EXCP_ILLEGAL_INST;
312 }
313 
314 static RISCVException umode32(CPURISCVState *env, int csrno)
315 {
316     if (riscv_cpu_mxl(env) != MXL_RV32) {
317         return RISCV_EXCP_ILLEGAL_INST;
318     }
319 
320     return umode(env, csrno);
321 }
322 
323 static RISCVException mstateen(CPURISCVState *env, int csrno)
324 {
325     if (!riscv_cpu_cfg(env)->ext_smstateen) {
326         return RISCV_EXCP_ILLEGAL_INST;
327     }
328 
329     return any(env, csrno);
330 }
331 
332 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
333 {
334     if (!riscv_cpu_cfg(env)->ext_smstateen) {
335         return RISCV_EXCP_ILLEGAL_INST;
336     }
337 
338     RISCVException ret = hmode(env, csrno);
339     if (ret != RISCV_EXCP_NONE) {
340         return ret;
341     }
342 
343     if (env->debugger) {
344         return RISCV_EXCP_NONE;
345     }
346 
347     if (env->priv < PRV_M) {
348         if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
349             return RISCV_EXCP_ILLEGAL_INST;
350         }
351     }
352 
353     return RISCV_EXCP_NONE;
354 }
355 
356 static RISCVException hstateen(CPURISCVState *env, int csrno)
357 {
358     return hstateen_pred(env, csrno, CSR_HSTATEEN0);
359 }
360 
361 static RISCVException hstateenh(CPURISCVState *env, int csrno)
362 {
363     return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
364 }
365 
366 static RISCVException sstateen(CPURISCVState *env, int csrno)
367 {
368     bool virt = env->virt_enabled;
369     int index = csrno - CSR_SSTATEEN0;
370 
371     if (!riscv_cpu_cfg(env)->ext_smstateen) {
372         return RISCV_EXCP_ILLEGAL_INST;
373     }
374 
375     RISCVException ret = smode(env, csrno);
376     if (ret != RISCV_EXCP_NONE) {
377         return ret;
378     }
379 
380     if (env->debugger) {
381         return RISCV_EXCP_NONE;
382     }
383 
384     if (env->priv < PRV_M) {
385         if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
386             return RISCV_EXCP_ILLEGAL_INST;
387         }
388 
389         if (virt) {
390             if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
391                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
392             }
393         }
394     }
395 
396     return RISCV_EXCP_NONE;
397 }
398 
399 static RISCVException sstc(CPURISCVState *env, int csrno)
400 {
401     bool hmode_check = false;
402 
403     if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
404         return RISCV_EXCP_ILLEGAL_INST;
405     }
406 
407     if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
408         hmode_check = true;
409     }
410 
411     RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
412     if (ret != RISCV_EXCP_NONE) {
413         return ret;
414     }
415 
416     if (env->debugger) {
417         return RISCV_EXCP_NONE;
418     }
419 
420     if (env->priv == PRV_M) {
421         return RISCV_EXCP_NONE;
422     }
423 
424     /*
425      * No need of separate function for rv32 as menvcfg stores both menvcfg
426      * menvcfgh for RV32.
427      */
428     if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
429           get_field(env->menvcfg, MENVCFG_STCE))) {
430         return RISCV_EXCP_ILLEGAL_INST;
431     }
432 
433     if (env->virt_enabled) {
434         if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
435               get_field(env->henvcfg, HENVCFG_STCE))) {
436             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
437         }
438     }
439 
440     return RISCV_EXCP_NONE;
441 }
442 
443 static RISCVException sstc_32(CPURISCVState *env, int csrno)
444 {
445     if (riscv_cpu_mxl(env) != MXL_RV32) {
446         return RISCV_EXCP_ILLEGAL_INST;
447     }
448 
449     return sstc(env, csrno);
450 }
451 
452 /* Checks if PointerMasking registers could be accessed */
453 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
454 {
455     /* Check if j-ext is present */
456     if (riscv_has_ext(env, RVJ)) {
457         return RISCV_EXCP_NONE;
458     }
459     return RISCV_EXCP_ILLEGAL_INST;
460 }
461 
462 static int aia_hmode(CPURISCVState *env, int csrno)
463 {
464     if (!riscv_cpu_cfg(env)->ext_ssaia) {
465         return RISCV_EXCP_ILLEGAL_INST;
466      }
467 
468      return hmode(env, csrno);
469 }
470 
471 static int aia_hmode32(CPURISCVState *env, int csrno)
472 {
473     if (!riscv_cpu_cfg(env)->ext_ssaia) {
474         return RISCV_EXCP_ILLEGAL_INST;
475     }
476 
477     return hmode32(env, csrno);
478 }
479 
480 static RISCVException pmp(CPURISCVState *env, int csrno)
481 {
482     if (riscv_cpu_cfg(env)->pmp) {
483         if (csrno <= CSR_PMPCFG3) {
484             uint32_t reg_index = csrno - CSR_PMPCFG0;
485 
486             /* TODO: RV128 restriction check */
487             if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
488                 return RISCV_EXCP_ILLEGAL_INST;
489             }
490         }
491 
492         return RISCV_EXCP_NONE;
493     }
494 
495     return RISCV_EXCP_ILLEGAL_INST;
496 }
497 
498 static RISCVException epmp(CPURISCVState *env, int csrno)
499 {
500     if (riscv_cpu_cfg(env)->epmp) {
501         return RISCV_EXCP_NONE;
502     }
503 
504     return RISCV_EXCP_ILLEGAL_INST;
505 }
506 
507 static RISCVException debug(CPURISCVState *env, int csrno)
508 {
509     if (riscv_cpu_cfg(env)->debug) {
510         return RISCV_EXCP_NONE;
511     }
512 
513     return RISCV_EXCP_ILLEGAL_INST;
514 }
515 #endif
516 
517 static RISCVException seed(CPURISCVState *env, int csrno)
518 {
519     if (!riscv_cpu_cfg(env)->ext_zkr) {
520         return RISCV_EXCP_ILLEGAL_INST;
521     }
522 
523 #if !defined(CONFIG_USER_ONLY)
524     if (env->debugger) {
525         return RISCV_EXCP_NONE;
526     }
527 
528     /*
529      * With a CSR read-write instruction:
530      * 1) The seed CSR is always available in machine mode as normal.
531      * 2) Attempted access to seed from virtual modes VS and VU always raises
532      * an exception(virtual instruction exception only if mseccfg.sseed=1).
533      * 3) Without the corresponding access control bit set to 1, any attempted
534      * access to seed from U, S or HS modes will raise an illegal instruction
535      * exception.
536      */
537     if (env->priv == PRV_M) {
538         return RISCV_EXCP_NONE;
539     } else if (env->virt_enabled) {
540         if (env->mseccfg & MSECCFG_SSEED) {
541             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
542         } else {
543             return RISCV_EXCP_ILLEGAL_INST;
544         }
545     } else {
546         if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
547             return RISCV_EXCP_NONE;
548         } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
549             return RISCV_EXCP_NONE;
550         } else {
551             return RISCV_EXCP_ILLEGAL_INST;
552         }
553     }
554 #else
555     return RISCV_EXCP_NONE;
556 #endif
557 }
558 
559 /* User Floating-Point CSRs */
560 static RISCVException read_fflags(CPURISCVState *env, int csrno,
561                                   target_ulong *val)
562 {
563     *val = riscv_cpu_get_fflags(env);
564     return RISCV_EXCP_NONE;
565 }
566 
567 static RISCVException write_fflags(CPURISCVState *env, int csrno,
568                                    target_ulong val)
569 {
570 #if !defined(CONFIG_USER_ONLY)
571     if (riscv_has_ext(env, RVF)) {
572         env->mstatus |= MSTATUS_FS;
573     }
574 #endif
575     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
576     return RISCV_EXCP_NONE;
577 }
578 
579 static RISCVException read_frm(CPURISCVState *env, int csrno,
580                                target_ulong *val)
581 {
582     *val = env->frm;
583     return RISCV_EXCP_NONE;
584 }
585 
586 static RISCVException write_frm(CPURISCVState *env, int csrno,
587                                 target_ulong val)
588 {
589 #if !defined(CONFIG_USER_ONLY)
590     if (riscv_has_ext(env, RVF)) {
591         env->mstatus |= MSTATUS_FS;
592     }
593 #endif
594     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
595     return RISCV_EXCP_NONE;
596 }
597 
598 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
599                                 target_ulong *val)
600 {
601     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
602         | (env->frm << FSR_RD_SHIFT);
603     return RISCV_EXCP_NONE;
604 }
605 
606 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
607                                  target_ulong val)
608 {
609 #if !defined(CONFIG_USER_ONLY)
610     if (riscv_has_ext(env, RVF)) {
611         env->mstatus |= MSTATUS_FS;
612     }
613 #endif
614     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
615     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
616     return RISCV_EXCP_NONE;
617 }
618 
619 static RISCVException read_vtype(CPURISCVState *env, int csrno,
620                                  target_ulong *val)
621 {
622     uint64_t vill;
623     switch (env->xl) {
624     case MXL_RV32:
625         vill = (uint32_t)env->vill << 31;
626         break;
627     case MXL_RV64:
628         vill = (uint64_t)env->vill << 63;
629         break;
630     default:
631         g_assert_not_reached();
632     }
633     *val = (target_ulong)vill | env->vtype;
634     return RISCV_EXCP_NONE;
635 }
636 
637 static RISCVException read_vl(CPURISCVState *env, int csrno,
638                               target_ulong *val)
639 {
640     *val = env->vl;
641     return RISCV_EXCP_NONE;
642 }
643 
644 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
645 {
646     *val = riscv_cpu_cfg(env)->vlen >> 3;
647     return RISCV_EXCP_NONE;
648 }
649 
650 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
651                                 target_ulong *val)
652 {
653     *val = env->vxrm;
654     return RISCV_EXCP_NONE;
655 }
656 
657 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
658                                  target_ulong val)
659 {
660 #if !defined(CONFIG_USER_ONLY)
661     env->mstatus |= MSTATUS_VS;
662 #endif
663     env->vxrm = val;
664     return RISCV_EXCP_NONE;
665 }
666 
667 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
668                                  target_ulong *val)
669 {
670     *val = env->vxsat;
671     return RISCV_EXCP_NONE;
672 }
673 
674 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
675                                   target_ulong val)
676 {
677 #if !defined(CONFIG_USER_ONLY)
678     env->mstatus |= MSTATUS_VS;
679 #endif
680     env->vxsat = val;
681     return RISCV_EXCP_NONE;
682 }
683 
684 static RISCVException read_vstart(CPURISCVState *env, int csrno,
685                                   target_ulong *val)
686 {
687     *val = env->vstart;
688     return RISCV_EXCP_NONE;
689 }
690 
691 static RISCVException write_vstart(CPURISCVState *env, int csrno,
692                                    target_ulong val)
693 {
694 #if !defined(CONFIG_USER_ONLY)
695     env->mstatus |= MSTATUS_VS;
696 #endif
697     /*
698      * The vstart CSR is defined to have only enough writable bits
699      * to hold the largest element index, i.e. lg2(VLEN) bits.
700      */
701     env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
702     return RISCV_EXCP_NONE;
703 }
704 
705 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
706 {
707     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
708     return RISCV_EXCP_NONE;
709 }
710 
711 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
712 {
713 #if !defined(CONFIG_USER_ONLY)
714     env->mstatus |= MSTATUS_VS;
715 #endif
716     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
717     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
718     return RISCV_EXCP_NONE;
719 }
720 
721 /* User Timers and Counters */
722 static target_ulong get_ticks(bool shift)
723 {
724     int64_t val;
725     target_ulong result;
726 
727 #if !defined(CONFIG_USER_ONLY)
728     if (icount_enabled()) {
729         val = icount_get();
730     } else {
731         val = cpu_get_host_ticks();
732     }
733 #else
734     val = cpu_get_host_ticks();
735 #endif
736 
737     if (shift) {
738         result = val >> 32;
739     } else {
740         result = val;
741     }
742 
743     return result;
744 }
745 
746 #if defined(CONFIG_USER_ONLY)
747 static RISCVException read_time(CPURISCVState *env, int csrno,
748                                 target_ulong *val)
749 {
750     *val = cpu_get_host_ticks();
751     return RISCV_EXCP_NONE;
752 }
753 
754 static RISCVException read_timeh(CPURISCVState *env, int csrno,
755                                  target_ulong *val)
756 {
757     *val = cpu_get_host_ticks() >> 32;
758     return RISCV_EXCP_NONE;
759 }
760 
761 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
762 {
763     *val = get_ticks(false);
764     return RISCV_EXCP_NONE;
765 }
766 
767 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
768 {
769     *val = get_ticks(true);
770     return RISCV_EXCP_NONE;
771 }
772 
773 #else /* CONFIG_USER_ONLY */
774 
775 static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
776 {
777     int evt_index = csrno - CSR_MCOUNTINHIBIT;
778 
779     *val = env->mhpmevent_val[evt_index];
780 
781     return RISCV_EXCP_NONE;
782 }
783 
784 static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
785 {
786     int evt_index = csrno - CSR_MCOUNTINHIBIT;
787     uint64_t mhpmevt_val = val;
788 
789     env->mhpmevent_val[evt_index] = val;
790 
791     if (riscv_cpu_mxl(env) == MXL_RV32) {
792         mhpmevt_val = mhpmevt_val |
793                       ((uint64_t)env->mhpmeventh_val[evt_index] << 32);
794     }
795     riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
796 
797     return RISCV_EXCP_NONE;
798 }
799 
800 static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val)
801 {
802     int evt_index = csrno - CSR_MHPMEVENT3H + 3;
803 
804     *val = env->mhpmeventh_val[evt_index];
805 
806     return RISCV_EXCP_NONE;
807 }
808 
809 static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val)
810 {
811     int evt_index = csrno - CSR_MHPMEVENT3H + 3;
812     uint64_t mhpmevth_val = val;
813     uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
814 
815     mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
816     env->mhpmeventh_val[evt_index] = val;
817 
818     riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
819 
820     return RISCV_EXCP_NONE;
821 }
822 
823 static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
824 {
825     int ctr_idx = csrno - CSR_MCYCLE;
826     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
827     uint64_t mhpmctr_val = val;
828 
829     counter->mhpmcounter_val = val;
830     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
831         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
832         counter->mhpmcounter_prev = get_ticks(false);
833         if (ctr_idx > 2) {
834             if (riscv_cpu_mxl(env) == MXL_RV32) {
835                 mhpmctr_val = mhpmctr_val |
836                               ((uint64_t)counter->mhpmcounterh_val << 32);
837             }
838             riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
839         }
840      } else {
841         /* Other counters can keep incrementing from the given value */
842         counter->mhpmcounter_prev = val;
843     }
844 
845     return RISCV_EXCP_NONE;
846 }
847 
848 static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
849 {
850     int ctr_idx = csrno - CSR_MCYCLEH;
851     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
852     uint64_t mhpmctr_val = counter->mhpmcounter_val;
853     uint64_t mhpmctrh_val = val;
854 
855     counter->mhpmcounterh_val = val;
856     mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);
857     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
858         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
859         counter->mhpmcounterh_prev = get_ticks(true);
860         if (ctr_idx > 2) {
861             riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx);
862         }
863     } else {
864         counter->mhpmcounterh_prev = val;
865     }
866 
867     return RISCV_EXCP_NONE;
868 }
869 
870 static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
871                                          bool upper_half, uint32_t ctr_idx)
872 {
873     PMUCTRState counter = env->pmu_ctrs[ctr_idx];
874     target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev :
875                                          counter.mhpmcounter_prev;
876     target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val :
877                                         counter.mhpmcounter_val;
878 
879     if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
880         /**
881          * Counter should not increment if inhibit bit is set. We can't really
882          * stop the icount counting. Just return the counter value written by
883          * the supervisor to indicate that counter was not incremented.
884          */
885         if (!counter.started) {
886             *val = ctr_val;
887             return RISCV_EXCP_NONE;
888         } else {
889             /* Mark that the counter has been stopped */
890             counter.started = false;
891         }
892     }
893 
894     /**
895      * The kernel computes the perf delta by subtracting the current value from
896      * the value it initialized previously (ctr_val).
897      */
898     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
899         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
900         *val = get_ticks(upper_half) - ctr_prev + ctr_val;
901     } else {
902         *val = ctr_val;
903     }
904 
905     return RISCV_EXCP_NONE;
906 }
907 
908 static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
909 {
910     uint16_t ctr_index;
911 
912     if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
913         ctr_index = csrno - CSR_MCYCLE;
914     } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
915         ctr_index = csrno - CSR_CYCLE;
916     } else {
917         return RISCV_EXCP_ILLEGAL_INST;
918     }
919 
920     return riscv_pmu_read_ctr(env, val, false, ctr_index);
921 }
922 
923 static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
924 {
925     uint16_t ctr_index;
926 
927     if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
928         ctr_index = csrno - CSR_MCYCLEH;
929     } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
930         ctr_index = csrno - CSR_CYCLEH;
931     } else {
932         return RISCV_EXCP_ILLEGAL_INST;
933     }
934 
935     return riscv_pmu_read_ctr(env, val, true, ctr_index);
936 }
937 
938 static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
939 {
940     int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
941     int i;
942     *val = 0;
943     target_ulong *mhpm_evt_val;
944     uint64_t of_bit_mask;
945 
946     if (riscv_cpu_mxl(env) == MXL_RV32) {
947         mhpm_evt_val = env->mhpmeventh_val;
948         of_bit_mask = MHPMEVENTH_BIT_OF;
949     } else {
950         mhpm_evt_val = env->mhpmevent_val;
951         of_bit_mask = MHPMEVENT_BIT_OF;
952     }
953 
954     for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
955         if ((get_field(env->mcounteren, BIT(i))) &&
956             (mhpm_evt_val[i] & of_bit_mask)) {
957                     *val |= BIT(i);
958             }
959     }
960 
961     return RISCV_EXCP_NONE;
962 }
963 
964 static RISCVException read_time(CPURISCVState *env, int csrno,
965                                 target_ulong *val)
966 {
967     uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
968 
969     if (!env->rdtime_fn) {
970         return RISCV_EXCP_ILLEGAL_INST;
971     }
972 
973     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
974     return RISCV_EXCP_NONE;
975 }
976 
977 static RISCVException read_timeh(CPURISCVState *env, int csrno,
978                                  target_ulong *val)
979 {
980     uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
981 
982     if (!env->rdtime_fn) {
983         return RISCV_EXCP_ILLEGAL_INST;
984     }
985 
986     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
987     return RISCV_EXCP_NONE;
988 }
989 
990 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
991                                      target_ulong *val)
992 {
993     *val = env->vstimecmp;
994 
995     return RISCV_EXCP_NONE;
996 }
997 
998 static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
999                                       target_ulong *val)
1000 {
1001     *val = env->vstimecmp >> 32;
1002 
1003     return RISCV_EXCP_NONE;
1004 }
1005 
1006 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
1007                                       target_ulong val)
1008 {
1009     if (riscv_cpu_mxl(env) == MXL_RV32) {
1010         env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
1011     } else {
1012         env->vstimecmp = val;
1013     }
1014 
1015     riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
1016                               env->htimedelta, MIP_VSTIP);
1017 
1018     return RISCV_EXCP_NONE;
1019 }
1020 
1021 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
1022                                        target_ulong val)
1023 {
1024     env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
1025     riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
1026                               env->htimedelta, MIP_VSTIP);
1027 
1028     return RISCV_EXCP_NONE;
1029 }
1030 
1031 static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
1032                                     target_ulong *val)
1033 {
1034     if (env->virt_enabled) {
1035         *val = env->vstimecmp;
1036     } else {
1037         *val = env->stimecmp;
1038     }
1039 
1040     return RISCV_EXCP_NONE;
1041 }
1042 
1043 static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
1044                                      target_ulong *val)
1045 {
1046     if (env->virt_enabled) {
1047         *val = env->vstimecmp >> 32;
1048     } else {
1049         *val = env->stimecmp >> 32;
1050     }
1051 
1052     return RISCV_EXCP_NONE;
1053 }
1054 
1055 static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
1056                                      target_ulong val)
1057 {
1058     if (env->virt_enabled) {
1059         if (env->hvictl & HVICTL_VTI) {
1060             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1061         }
1062         return write_vstimecmp(env, csrno, val);
1063     }
1064 
1065     if (riscv_cpu_mxl(env) == MXL_RV32) {
1066         env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val);
1067     } else {
1068         env->stimecmp = val;
1069     }
1070 
1071     riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
1072 
1073     return RISCV_EXCP_NONE;
1074 }
1075 
1076 static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
1077                                       target_ulong val)
1078 {
1079     if (env->virt_enabled) {
1080         if (env->hvictl & HVICTL_VTI) {
1081             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1082         }
1083         return write_vstimecmph(env, csrno, val);
1084     }
1085 
1086     env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
1087     riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
1088 
1089     return RISCV_EXCP_NONE;
1090 }
1091 
1092 /* Machine constants */
1093 
1094 #define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
1095 #define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \
1096                                       MIP_LCOFIP))
1097 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
1098 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
1099 
1100 #define VSTOPI_NUM_SRCS 5
1101 
1102 static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
1103                                            VS_MODE_INTERRUPTS;
1104 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
1105 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
1106                                      HS_MODE_INTERRUPTS;
1107 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1108                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1109                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1110                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1111                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1112                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1113                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1114                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1115                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
1116                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
1117                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1118                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
1119                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1120                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1121                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1122                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1123                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1124                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1125                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1126 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
1127     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
1128       (1ULL << (RISCV_EXCP_VS_ECALL)) |
1129       (1ULL << (RISCV_EXCP_M_ECALL)) |
1130       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
1131       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
1132       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
1133       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
1134 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
1135     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
1136     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
1137 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
1138                                               SIP_LCOFIP;
1139 static const target_ulong hip_writable_mask = MIP_VSSIP;
1140 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
1141 static const target_ulong vsip_writable_mask = MIP_VSSIP;
1142 
1143 const bool valid_vm_1_10_32[16] = {
1144     [VM_1_10_MBARE] = true,
1145     [VM_1_10_SV32] = true
1146 };
1147 
1148 const bool valid_vm_1_10_64[16] = {
1149     [VM_1_10_MBARE] = true,
1150     [VM_1_10_SV39] = true,
1151     [VM_1_10_SV48] = true,
1152     [VM_1_10_SV57] = true
1153 };
1154 
1155 /* Machine Information Registers */
1156 static RISCVException read_zero(CPURISCVState *env, int csrno,
1157                                 target_ulong *val)
1158 {
1159     *val = 0;
1160     return RISCV_EXCP_NONE;
1161 }
1162 
1163 static RISCVException write_ignore(CPURISCVState *env, int csrno,
1164                                    target_ulong val)
1165 {
1166     return RISCV_EXCP_NONE;
1167 }
1168 
1169 static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
1170                                      target_ulong *val)
1171 {
1172     *val = riscv_cpu_cfg(env)->mvendorid;
1173     return RISCV_EXCP_NONE;
1174 }
1175 
1176 static RISCVException read_marchid(CPURISCVState *env, int csrno,
1177                                    target_ulong *val)
1178 {
1179     *val = riscv_cpu_cfg(env)->marchid;
1180     return RISCV_EXCP_NONE;
1181 }
1182 
1183 static RISCVException read_mimpid(CPURISCVState *env, int csrno,
1184                                   target_ulong *val)
1185 {
1186     *val = riscv_cpu_cfg(env)->mimpid;
1187     return RISCV_EXCP_NONE;
1188 }
1189 
1190 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
1191                                    target_ulong *val)
1192 {
1193     *val = env->mhartid;
1194     return RISCV_EXCP_NONE;
1195 }
1196 
1197 /* Machine Trap Setup */
1198 
1199 /* We do not store SD explicitly, only compute it on demand. */
1200 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
1201 {
1202     if ((status & MSTATUS_FS) == MSTATUS_FS ||
1203         (status & MSTATUS_VS) == MSTATUS_VS ||
1204         (status & MSTATUS_XS) == MSTATUS_XS) {
1205         switch (xl) {
1206         case MXL_RV32:
1207             return status | MSTATUS32_SD;
1208         case MXL_RV64:
1209             return status | MSTATUS64_SD;
1210         case MXL_RV128:
1211             return MSTATUSH128_SD;
1212         default:
1213             g_assert_not_reached();
1214         }
1215     }
1216     return status;
1217 }
1218 
1219 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
1220                                    target_ulong *val)
1221 {
1222     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
1223     return RISCV_EXCP_NONE;
1224 }
1225 
1226 static bool validate_vm(CPURISCVState *env, target_ulong vm)
1227 {
1228     return (vm & 0xf) <=
1229            satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
1230 }
1231 
1232 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
1233                                     target_ulong val)
1234 {
1235     uint64_t mstatus = env->mstatus;
1236     uint64_t mask = 0;
1237     RISCVMXL xl = riscv_cpu_mxl(env);
1238 
1239     /* flush tlb on mstatus fields that affect VM */
1240     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
1241             MSTATUS_MPRV | MSTATUS_SUM)) {
1242         tlb_flush(env_cpu(env));
1243     }
1244     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
1245         MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
1246         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
1247         MSTATUS_TW | MSTATUS_VS;
1248 
1249     if (riscv_has_ext(env, RVF)) {
1250         mask |= MSTATUS_FS;
1251     }
1252 
1253     if (xl != MXL_RV32 || env->debugger) {
1254         /*
1255          * RV32: MPV and GVA are not in mstatus. The current plan is to
1256          * add them to mstatush. For now, we just don't support it.
1257          */
1258         mask |= MSTATUS_MPV | MSTATUS_GVA;
1259         if ((val & MSTATUS64_UXL) != 0) {
1260             mask |= MSTATUS64_UXL;
1261         }
1262     }
1263 
1264     mstatus = (mstatus & ~mask) | (val & mask);
1265 
1266     if (xl > MXL_RV32) {
1267         /* SXL field is for now read only */
1268         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
1269     }
1270     env->mstatus = mstatus;
1271     env->xl = cpu_recompute_xl(env);
1272 
1273     return RISCV_EXCP_NONE;
1274 }
1275 
1276 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
1277                                     target_ulong *val)
1278 {
1279     *val = env->mstatus >> 32;
1280     return RISCV_EXCP_NONE;
1281 }
1282 
1283 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
1284                                      target_ulong val)
1285 {
1286     uint64_t valh = (uint64_t)val << 32;
1287     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
1288 
1289     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
1290         tlb_flush(env_cpu(env));
1291     }
1292 
1293     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
1294 
1295     return RISCV_EXCP_NONE;
1296 }
1297 
1298 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
1299                                         Int128 *val)
1300 {
1301     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
1302     return RISCV_EXCP_NONE;
1303 }
1304 
1305 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
1306                                      Int128 *val)
1307 {
1308     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
1309     return RISCV_EXCP_NONE;
1310 }
1311 
1312 static RISCVException read_misa(CPURISCVState *env, int csrno,
1313                                 target_ulong *val)
1314 {
1315     target_ulong misa;
1316 
1317     switch (env->misa_mxl) {
1318     case MXL_RV32:
1319         misa = (target_ulong)MXL_RV32 << 30;
1320         break;
1321 #ifdef TARGET_RISCV64
1322     case MXL_RV64:
1323         misa = (target_ulong)MXL_RV64 << 62;
1324         break;
1325 #endif
1326     default:
1327         g_assert_not_reached();
1328     }
1329 
1330     *val = misa | env->misa_ext;
1331     return RISCV_EXCP_NONE;
1332 }
1333 
1334 static RISCVException write_misa(CPURISCVState *env, int csrno,
1335                                  target_ulong val)
1336 {
1337     if (!riscv_cpu_cfg(env)->misa_w) {
1338         /* drop write to misa */
1339         return RISCV_EXCP_NONE;
1340     }
1341 
1342     /* 'I' or 'E' must be present */
1343     if (!(val & (RVI | RVE))) {
1344         /* It is not, drop write to misa */
1345         return RISCV_EXCP_NONE;
1346     }
1347 
1348     /* 'E' excludes all other extensions */
1349     if (val & RVE) {
1350         /*
1351          * when we support 'E' we can do "val = RVE;" however
1352          * for now we just drop writes if 'E' is present.
1353          */
1354         return RISCV_EXCP_NONE;
1355     }
1356 
1357     /*
1358      * misa.MXL writes are not supported by QEMU.
1359      * Drop writes to those bits.
1360      */
1361 
1362     /* Mask extensions that are not supported by this hart */
1363     val &= env->misa_ext_mask;
1364 
1365     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
1366     if ((val & RVD) && !(val & RVF)) {
1367         val &= ~RVD;
1368     }
1369 
1370     /*
1371      * Suppress 'C' if next instruction is not aligned
1372      * TODO: this should check next_pc
1373      */
1374     if ((val & RVC) && (GETPC() & ~3) != 0) {
1375         val &= ~RVC;
1376     }
1377 
1378     /* If nothing changed, do nothing. */
1379     if (val == env->misa_ext) {
1380         return RISCV_EXCP_NONE;
1381     }
1382 
1383     if (!(val & RVF)) {
1384         env->mstatus &= ~MSTATUS_FS;
1385     }
1386 
1387     /* flush translation cache */
1388     tb_flush(env_cpu(env));
1389     env->misa_ext = val;
1390     env->xl = riscv_cpu_mxl(env);
1391     return RISCV_EXCP_NONE;
1392 }
1393 
1394 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
1395                                    target_ulong *val)
1396 {
1397     *val = env->medeleg;
1398     return RISCV_EXCP_NONE;
1399 }
1400 
1401 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
1402                                     target_ulong val)
1403 {
1404     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
1405     return RISCV_EXCP_NONE;
1406 }
1407 
1408 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
1409                                     uint64_t *ret_val,
1410                                     uint64_t new_val, uint64_t wr_mask)
1411 {
1412     uint64_t mask = wr_mask & delegable_ints;
1413 
1414     if (ret_val) {
1415         *ret_val = env->mideleg;
1416     }
1417 
1418     env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
1419 
1420     if (riscv_has_ext(env, RVH)) {
1421         env->mideleg |= HS_MODE_INTERRUPTS;
1422     }
1423 
1424     return RISCV_EXCP_NONE;
1425 }
1426 
1427 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
1428                                   target_ulong *ret_val,
1429                                   target_ulong new_val, target_ulong wr_mask)
1430 {
1431     uint64_t rval;
1432     RISCVException ret;
1433 
1434     ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
1435     if (ret_val) {
1436         *ret_val = rval;
1437     }
1438 
1439     return ret;
1440 }
1441 
1442 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
1443                                    target_ulong *ret_val,
1444                                    target_ulong new_val,
1445                                    target_ulong wr_mask)
1446 {
1447     uint64_t rval;
1448     RISCVException ret;
1449 
1450     ret = rmw_mideleg64(env, csrno, &rval,
1451         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1452     if (ret_val) {
1453         *ret_val = rval >> 32;
1454     }
1455 
1456     return ret;
1457 }
1458 
1459 static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
1460                                 uint64_t *ret_val,
1461                                 uint64_t new_val, uint64_t wr_mask)
1462 {
1463     uint64_t mask = wr_mask & all_ints;
1464 
1465     if (ret_val) {
1466         *ret_val = env->mie;
1467     }
1468 
1469     env->mie = (env->mie & ~mask) | (new_val & mask);
1470 
1471     if (!riscv_has_ext(env, RVH)) {
1472         env->mie &= ~((uint64_t)MIP_SGEIP);
1473     }
1474 
1475     return RISCV_EXCP_NONE;
1476 }
1477 
1478 static RISCVException rmw_mie(CPURISCVState *env, int csrno,
1479                               target_ulong *ret_val,
1480                               target_ulong new_val, target_ulong wr_mask)
1481 {
1482     uint64_t rval;
1483     RISCVException ret;
1484 
1485     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
1486     if (ret_val) {
1487         *ret_val = rval;
1488     }
1489 
1490     return ret;
1491 }
1492 
1493 static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
1494                                target_ulong *ret_val,
1495                                target_ulong new_val, target_ulong wr_mask)
1496 {
1497     uint64_t rval;
1498     RISCVException ret;
1499 
1500     ret = rmw_mie64(env, csrno, &rval,
1501         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1502     if (ret_val) {
1503         *ret_val = rval >> 32;
1504     }
1505 
1506     return ret;
1507 }
1508 
1509 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
1510 {
1511     int irq;
1512     uint8_t iprio;
1513 
1514     irq = riscv_cpu_mirq_pending(env);
1515     if (irq <= 0 || irq > 63) {
1516         *val = 0;
1517     } else {
1518         iprio = env->miprio[irq];
1519         if (!iprio) {
1520             if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
1521                 iprio = IPRIO_MMAXIPRIO;
1522             }
1523         }
1524         *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
1525         *val |= iprio;
1526     }
1527 
1528     return RISCV_EXCP_NONE;
1529 }
1530 
1531 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
1532 {
1533     if (!env->virt_enabled) {
1534         return csrno;
1535     }
1536 
1537     switch (csrno) {
1538     case CSR_SISELECT:
1539         return CSR_VSISELECT;
1540     case CSR_SIREG:
1541         return CSR_VSIREG;
1542     case CSR_STOPEI:
1543         return CSR_VSTOPEI;
1544     default:
1545         return csrno;
1546     };
1547 }
1548 
1549 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
1550                         target_ulong new_val, target_ulong wr_mask)
1551 {
1552     target_ulong *iselect;
1553 
1554     /* Translate CSR number for VS-mode */
1555     csrno = aia_xlate_vs_csrno(env, csrno);
1556 
1557     /* Find the iselect CSR based on CSR number */
1558     switch (csrno) {
1559     case CSR_MISELECT:
1560         iselect = &env->miselect;
1561         break;
1562     case CSR_SISELECT:
1563         iselect = &env->siselect;
1564         break;
1565     case CSR_VSISELECT:
1566         iselect = &env->vsiselect;
1567         break;
1568     default:
1569          return RISCV_EXCP_ILLEGAL_INST;
1570     };
1571 
1572     if (val) {
1573         *val = *iselect;
1574     }
1575 
1576     wr_mask &= ISELECT_MASK;
1577     if (wr_mask) {
1578         *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
1579     }
1580 
1581     return RISCV_EXCP_NONE;
1582 }
1583 
1584 static int rmw_iprio(target_ulong xlen,
1585                      target_ulong iselect, uint8_t *iprio,
1586                      target_ulong *val, target_ulong new_val,
1587                      target_ulong wr_mask, int ext_irq_no)
1588 {
1589     int i, firq, nirqs;
1590     target_ulong old_val;
1591 
1592     if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
1593         return -EINVAL;
1594     }
1595     if (xlen != 32 && iselect & 0x1) {
1596         return -EINVAL;
1597     }
1598 
1599     nirqs = 4 * (xlen / 32);
1600     firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
1601 
1602     old_val = 0;
1603     for (i = 0; i < nirqs; i++) {
1604         old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
1605     }
1606 
1607     if (val) {
1608         *val = old_val;
1609     }
1610 
1611     if (wr_mask) {
1612         new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
1613         for (i = 0; i < nirqs; i++) {
1614             /*
1615              * M-level and S-level external IRQ priority always read-only
1616              * zero. This means default priority order is always preferred
1617              * for M-level and S-level external IRQs.
1618              */
1619             if ((firq + i) == ext_irq_no) {
1620                 continue;
1621             }
1622             iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
1623         }
1624     }
1625 
1626     return 0;
1627 }
1628 
1629 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
1630                      target_ulong new_val, target_ulong wr_mask)
1631 {
1632     bool virt;
1633     uint8_t *iprio;
1634     int ret = -EINVAL;
1635     target_ulong priv, isel, vgein;
1636 
1637     /* Translate CSR number for VS-mode */
1638     csrno = aia_xlate_vs_csrno(env, csrno);
1639 
1640     /* Decode register details from CSR number */
1641     virt = false;
1642     switch (csrno) {
1643     case CSR_MIREG:
1644         iprio = env->miprio;
1645         isel = env->miselect;
1646         priv = PRV_M;
1647         break;
1648     case CSR_SIREG:
1649         iprio = env->siprio;
1650         isel = env->siselect;
1651         priv = PRV_S;
1652         break;
1653     case CSR_VSIREG:
1654         iprio = env->hviprio;
1655         isel = env->vsiselect;
1656         priv = PRV_S;
1657         virt = true;
1658         break;
1659     default:
1660          goto done;
1661     };
1662 
1663     /* Find the selected guest interrupt file */
1664     vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
1665 
1666     if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
1667         /* Local interrupt priority registers not available for VS-mode */
1668         if (!virt) {
1669             ret = rmw_iprio(riscv_cpu_mxl_bits(env),
1670                             isel, iprio, val, new_val, wr_mask,
1671                             (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
1672         }
1673     } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
1674         /* IMSIC registers only available when machine implements it. */
1675         if (env->aia_ireg_rmw_fn[priv]) {
1676             /* Selected guest interrupt file should not be zero */
1677             if (virt && (!vgein || env->geilen < vgein)) {
1678                 goto done;
1679             }
1680             /* Call machine specific IMSIC register emulation */
1681             ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
1682                                     AIA_MAKE_IREG(isel, priv, virt, vgein,
1683                                                   riscv_cpu_mxl_bits(env)),
1684                                     val, new_val, wr_mask);
1685         }
1686     }
1687 
1688 done:
1689     if (ret) {
1690         return (env->virt_enabled && virt) ?
1691                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1692     }
1693     return RISCV_EXCP_NONE;
1694 }
1695 
1696 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
1697                       target_ulong new_val, target_ulong wr_mask)
1698 {
1699     bool virt;
1700     int ret = -EINVAL;
1701     target_ulong priv, vgein;
1702 
1703     /* Translate CSR number for VS-mode */
1704     csrno = aia_xlate_vs_csrno(env, csrno);
1705 
1706     /* Decode register details from CSR number */
1707     virt = false;
1708     switch (csrno) {
1709     case CSR_MTOPEI:
1710         priv = PRV_M;
1711         break;
1712     case CSR_STOPEI:
1713         priv = PRV_S;
1714         break;
1715     case CSR_VSTOPEI:
1716         priv = PRV_S;
1717         virt = true;
1718         break;
1719     default:
1720         goto done;
1721     };
1722 
1723     /* IMSIC CSRs only available when machine implements IMSIC. */
1724     if (!env->aia_ireg_rmw_fn[priv]) {
1725         goto done;
1726     }
1727 
1728     /* Find the selected guest interrupt file */
1729     vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
1730 
1731     /* Selected guest interrupt file should be valid */
1732     if (virt && (!vgein || env->geilen < vgein)) {
1733         goto done;
1734     }
1735 
1736     /* Call machine specific IMSIC register emulation for TOPEI */
1737     ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
1738                     AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
1739                                   riscv_cpu_mxl_bits(env)),
1740                     val, new_val, wr_mask);
1741 
1742 done:
1743     if (ret) {
1744         return (env->virt_enabled && virt) ?
1745                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1746     }
1747     return RISCV_EXCP_NONE;
1748 }
1749 
1750 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
1751                                  target_ulong *val)
1752 {
1753     *val = env->mtvec;
1754     return RISCV_EXCP_NONE;
1755 }
1756 
1757 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
1758                                   target_ulong val)
1759 {
1760     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1761     if ((val & 3) < 2) {
1762         env->mtvec = val;
1763     } else {
1764         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
1765     }
1766     return RISCV_EXCP_NONE;
1767 }
1768 
1769 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
1770                                          target_ulong *val)
1771 {
1772     *val = env->mcountinhibit;
1773     return RISCV_EXCP_NONE;
1774 }
1775 
1776 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
1777                                           target_ulong val)
1778 {
1779     int cidx;
1780     PMUCTRState *counter;
1781 
1782     env->mcountinhibit = val;
1783 
1784     /* Check if any other counter is also monitoring cycles/instructions */
1785     for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
1786         if (!get_field(env->mcountinhibit, BIT(cidx))) {
1787             counter = &env->pmu_ctrs[cidx];
1788             counter->started = true;
1789         }
1790     }
1791 
1792     return RISCV_EXCP_NONE;
1793 }
1794 
1795 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
1796                                       target_ulong *val)
1797 {
1798     *val = env->mcounteren;
1799     return RISCV_EXCP_NONE;
1800 }
1801 
1802 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
1803                                        target_ulong val)
1804 {
1805     env->mcounteren = val;
1806     return RISCV_EXCP_NONE;
1807 }
1808 
1809 /* Machine Trap Handling */
1810 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
1811                                          Int128 *val)
1812 {
1813     *val = int128_make128(env->mscratch, env->mscratchh);
1814     return RISCV_EXCP_NONE;
1815 }
1816 
1817 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
1818                                           Int128 val)
1819 {
1820     env->mscratch = int128_getlo(val);
1821     env->mscratchh = int128_gethi(val);
1822     return RISCV_EXCP_NONE;
1823 }
1824 
1825 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
1826                                     target_ulong *val)
1827 {
1828     *val = env->mscratch;
1829     return RISCV_EXCP_NONE;
1830 }
1831 
1832 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
1833                                      target_ulong val)
1834 {
1835     env->mscratch = val;
1836     return RISCV_EXCP_NONE;
1837 }
1838 
1839 static RISCVException read_mepc(CPURISCVState *env, int csrno,
1840                                 target_ulong *val)
1841 {
1842     *val = env->mepc;
1843     return RISCV_EXCP_NONE;
1844 }
1845 
1846 static RISCVException write_mepc(CPURISCVState *env, int csrno,
1847                                  target_ulong val)
1848 {
1849     env->mepc = val;
1850     return RISCV_EXCP_NONE;
1851 }
1852 
1853 static RISCVException read_mcause(CPURISCVState *env, int csrno,
1854                                   target_ulong *val)
1855 {
1856     *val = env->mcause;
1857     return RISCV_EXCP_NONE;
1858 }
1859 
1860 static RISCVException write_mcause(CPURISCVState *env, int csrno,
1861                                    target_ulong val)
1862 {
1863     env->mcause = val;
1864     return RISCV_EXCP_NONE;
1865 }
1866 
1867 static RISCVException read_mtval(CPURISCVState *env, int csrno,
1868                                  target_ulong *val)
1869 {
1870     *val = env->mtval;
1871     return RISCV_EXCP_NONE;
1872 }
1873 
1874 static RISCVException write_mtval(CPURISCVState *env, int csrno,
1875                                   target_ulong val)
1876 {
1877     env->mtval = val;
1878     return RISCV_EXCP_NONE;
1879 }
1880 
1881 /* Execution environment configuration setup */
1882 static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
1883                                    target_ulong *val)
1884 {
1885     *val = env->menvcfg;
1886     return RISCV_EXCP_NONE;
1887 }
1888 
1889 static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
1890                                     target_ulong val)
1891 {
1892     const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
1893     uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
1894 
1895     if (riscv_cpu_mxl(env) == MXL_RV64) {
1896         mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
1897                 (cfg->ext_sstc ? MENVCFG_STCE : 0) |
1898                 (cfg->ext_svadu ? MENVCFG_HADE : 0);
1899     }
1900     env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
1901 
1902     return RISCV_EXCP_NONE;
1903 }
1904 
1905 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
1906                                     target_ulong *val)
1907 {
1908     *val = env->menvcfg >> 32;
1909     return RISCV_EXCP_NONE;
1910 }
1911 
1912 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
1913                                      target_ulong val)
1914 {
1915     const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
1916     uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
1917                     (cfg->ext_sstc ? MENVCFG_STCE : 0) |
1918                     (cfg->ext_svadu ? MENVCFG_HADE : 0);
1919     uint64_t valh = (uint64_t)val << 32;
1920 
1921     env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
1922 
1923     return RISCV_EXCP_NONE;
1924 }
1925 
1926 static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
1927                                    target_ulong *val)
1928 {
1929     RISCVException ret;
1930 
1931     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1932     if (ret != RISCV_EXCP_NONE) {
1933         return ret;
1934     }
1935 
1936     *val = env->senvcfg;
1937     return RISCV_EXCP_NONE;
1938 }
1939 
1940 static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
1941                                     target_ulong val)
1942 {
1943     uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
1944     RISCVException ret;
1945 
1946     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1947     if (ret != RISCV_EXCP_NONE) {
1948         return ret;
1949     }
1950 
1951     env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
1952     return RISCV_EXCP_NONE;
1953 }
1954 
1955 static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
1956                                    target_ulong *val)
1957 {
1958     RISCVException ret;
1959 
1960     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1961     if (ret != RISCV_EXCP_NONE) {
1962         return ret;
1963     }
1964 
1965     /*
1966      * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
1967      * henvcfg.stce is read_only 0 when menvcfg.stce = 0
1968      * henvcfg.hade is read_only 0 when menvcfg.hade = 0
1969      */
1970     *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
1971                            env->menvcfg);
1972     return RISCV_EXCP_NONE;
1973 }
1974 
1975 static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
1976                                     target_ulong val)
1977 {
1978     uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
1979     RISCVException ret;
1980 
1981     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
1982     if (ret != RISCV_EXCP_NONE) {
1983         return ret;
1984     }
1985 
1986     if (riscv_cpu_mxl(env) == MXL_RV64) {
1987         mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
1988     }
1989 
1990     env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
1991 
1992     return RISCV_EXCP_NONE;
1993 }
1994 
1995 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
1996                                     target_ulong *val)
1997 {
1998     RISCVException ret;
1999 
2000     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
2001     if (ret != RISCV_EXCP_NONE) {
2002         return ret;
2003     }
2004 
2005     *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
2006                             env->menvcfg)) >> 32;
2007     return RISCV_EXCP_NONE;
2008 }
2009 
2010 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
2011                                      target_ulong val)
2012 {
2013     uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
2014                                     HENVCFG_HADE);
2015     uint64_t valh = (uint64_t)val << 32;
2016     RISCVException ret;
2017 
2018     ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
2019     if (ret != RISCV_EXCP_NONE) {
2020         return ret;
2021     }
2022 
2023     env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
2024     return RISCV_EXCP_NONE;
2025 }
2026 
2027 static RISCVException read_mstateen(CPURISCVState *env, int csrno,
2028                                     target_ulong *val)
2029 {
2030     *val = env->mstateen[csrno - CSR_MSTATEEN0];
2031 
2032     return RISCV_EXCP_NONE;
2033 }
2034 
2035 static RISCVException write_mstateen(CPURISCVState *env, int csrno,
2036                                      uint64_t wr_mask, target_ulong new_val)
2037 {
2038     uint64_t *reg;
2039 
2040     reg = &env->mstateen[csrno - CSR_MSTATEEN0];
2041     *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
2042 
2043     return RISCV_EXCP_NONE;
2044 }
2045 
2046 static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
2047                                       target_ulong new_val)
2048 {
2049     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2050 
2051     return write_mstateen(env, csrno, wr_mask, new_val);
2052 }
2053 
2054 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
2055                                          target_ulong new_val)
2056 {
2057     return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
2058 }
2059 
2060 static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
2061                                      target_ulong *val)
2062 {
2063     *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
2064 
2065     return RISCV_EXCP_NONE;
2066 }
2067 
2068 static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
2069                                       uint64_t wr_mask, target_ulong new_val)
2070 {
2071     uint64_t *reg, val;
2072 
2073     reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
2074     val = (uint64_t)new_val << 32;
2075     val |= *reg & 0xFFFFFFFF;
2076     *reg = (*reg & ~wr_mask) | (val & wr_mask);
2077 
2078     return RISCV_EXCP_NONE;
2079 }
2080 
2081 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
2082                                        target_ulong new_val)
2083 {
2084     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2085 
2086     return write_mstateenh(env, csrno, wr_mask, new_val);
2087 }
2088 
2089 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
2090                                           target_ulong new_val)
2091 {
2092     return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
2093 }
2094 
2095 static RISCVException read_hstateen(CPURISCVState *env, int csrno,
2096                                     target_ulong *val)
2097 {
2098     int index = csrno - CSR_HSTATEEN0;
2099 
2100     *val = env->hstateen[index] & env->mstateen[index];
2101 
2102     return RISCV_EXCP_NONE;
2103 }
2104 
2105 static RISCVException write_hstateen(CPURISCVState *env, int csrno,
2106                                      uint64_t mask, target_ulong new_val)
2107 {
2108     int index = csrno - CSR_HSTATEEN0;
2109     uint64_t *reg, wr_mask;
2110 
2111     reg = &env->hstateen[index];
2112     wr_mask = env->mstateen[index] & mask;
2113     *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
2114 
2115     return RISCV_EXCP_NONE;
2116 }
2117 
2118 static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
2119                                       target_ulong new_val)
2120 {
2121     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2122 
2123     return write_hstateen(env, csrno, wr_mask, new_val);
2124 }
2125 
2126 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
2127                                          target_ulong new_val)
2128 {
2129     return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
2130 }
2131 
2132 static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
2133                                      target_ulong *val)
2134 {
2135     int index = csrno - CSR_HSTATEEN0H;
2136 
2137     *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
2138 
2139     return RISCV_EXCP_NONE;
2140 }
2141 
2142 static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
2143                                       uint64_t mask, target_ulong new_val)
2144 {
2145     int index = csrno - CSR_HSTATEEN0H;
2146     uint64_t *reg, wr_mask, val;
2147 
2148     reg = &env->hstateen[index];
2149     val = (uint64_t)new_val << 32;
2150     val |= *reg & 0xFFFFFFFF;
2151     wr_mask = env->mstateen[index] & mask;
2152     *reg = (*reg & ~wr_mask) | (val & wr_mask);
2153 
2154     return RISCV_EXCP_NONE;
2155 }
2156 
2157 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
2158                                        target_ulong new_val)
2159 {
2160     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2161 
2162     return write_hstateenh(env, csrno, wr_mask, new_val);
2163 }
2164 
2165 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
2166                                           target_ulong new_val)
2167 {
2168     return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
2169 }
2170 
2171 static RISCVException read_sstateen(CPURISCVState *env, int csrno,
2172                                     target_ulong *val)
2173 {
2174     bool virt = env->virt_enabled;
2175     int index = csrno - CSR_SSTATEEN0;
2176 
2177     *val = env->sstateen[index] & env->mstateen[index];
2178     if (virt) {
2179         *val &= env->hstateen[index];
2180     }
2181 
2182     return RISCV_EXCP_NONE;
2183 }
2184 
2185 static RISCVException write_sstateen(CPURISCVState *env, int csrno,
2186                                      uint64_t mask, target_ulong new_val)
2187 {
2188     bool virt = env->virt_enabled;
2189     int index = csrno - CSR_SSTATEEN0;
2190     uint64_t wr_mask;
2191     uint64_t *reg;
2192 
2193     wr_mask = env->mstateen[index] & mask;
2194     if (virt) {
2195         wr_mask &= env->hstateen[index];
2196     }
2197 
2198     reg = &env->sstateen[index];
2199     *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
2200 
2201     return RISCV_EXCP_NONE;
2202 }
2203 
2204 static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
2205                                       target_ulong new_val)
2206 {
2207     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
2208 
2209     return write_sstateen(env, csrno, wr_mask, new_val);
2210 }
2211 
2212 static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
2213                                       target_ulong new_val)
2214 {
2215     return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
2216 }
2217 
2218 static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
2219                                 uint64_t *ret_val,
2220                                 uint64_t new_val, uint64_t wr_mask)
2221 {
2222     uint64_t old_mip, mask = wr_mask & delegable_ints;
2223     uint32_t gin;
2224 
2225     if (mask & MIP_SEIP) {
2226         env->software_seip = new_val & MIP_SEIP;
2227         new_val |= env->external_seip * MIP_SEIP;
2228     }
2229 
2230     if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
2231         get_field(env->menvcfg, MENVCFG_STCE)) {
2232         /* sstc extension forbids STIP & VSTIP to be writeable in mip */
2233         mask = mask & ~(MIP_STIP | MIP_VSTIP);
2234     }
2235 
2236     if (mask) {
2237         old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
2238     } else {
2239         old_mip = env->mip;
2240     }
2241 
2242     if (csrno != CSR_HVIP) {
2243         gin = get_field(env->hstatus, HSTATUS_VGEIN);
2244         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
2245         old_mip |= env->vstime_irq ? MIP_VSTIP : 0;
2246     }
2247 
2248     if (ret_val) {
2249         *ret_val = old_mip;
2250     }
2251 
2252     return RISCV_EXCP_NONE;
2253 }
2254 
2255 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
2256                               target_ulong *ret_val,
2257                               target_ulong new_val, target_ulong wr_mask)
2258 {
2259     uint64_t rval;
2260     RISCVException ret;
2261 
2262     ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
2263     if (ret_val) {
2264         *ret_val = rval;
2265     }
2266 
2267     return ret;
2268 }
2269 
2270 static RISCVException rmw_miph(CPURISCVState *env, int csrno,
2271                                target_ulong *ret_val,
2272                                target_ulong new_val, target_ulong wr_mask)
2273 {
2274     uint64_t rval;
2275     RISCVException ret;
2276 
2277     ret = rmw_mip64(env, csrno, &rval,
2278         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2279     if (ret_val) {
2280         *ret_val = rval >> 32;
2281     }
2282 
2283     return ret;
2284 }
2285 
2286 /* Supervisor Trap Setup */
2287 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
2288                                         Int128 *val)
2289 {
2290     uint64_t mask = sstatus_v1_10_mask;
2291     uint64_t sstatus = env->mstatus & mask;
2292     if (env->xl != MXL_RV32 || env->debugger) {
2293         mask |= SSTATUS64_UXL;
2294     }
2295 
2296     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
2297     return RISCV_EXCP_NONE;
2298 }
2299 
2300 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
2301                                    target_ulong *val)
2302 {
2303     target_ulong mask = (sstatus_v1_10_mask);
2304     if (env->xl != MXL_RV32 || env->debugger) {
2305         mask |= SSTATUS64_UXL;
2306     }
2307     /* TODO: Use SXL not MXL. */
2308     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
2309     return RISCV_EXCP_NONE;
2310 }
2311 
2312 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
2313                                     target_ulong val)
2314 {
2315     target_ulong mask = (sstatus_v1_10_mask);
2316 
2317     if (env->xl != MXL_RV32 || env->debugger) {
2318         if ((val & SSTATUS64_UXL) != 0) {
2319             mask |= SSTATUS64_UXL;
2320         }
2321     }
2322     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
2323     return write_mstatus(env, CSR_MSTATUS, newval);
2324 }
2325 
2326 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
2327                                  uint64_t *ret_val,
2328                                  uint64_t new_val, uint64_t wr_mask)
2329 {
2330     RISCVException ret;
2331     uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
2332 
2333     /* Bring VS-level bits to correct position */
2334     new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
2335     wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
2336 
2337     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
2338     if (ret_val) {
2339         *ret_val = (rval & mask) >> 1;
2340     }
2341 
2342     return ret;
2343 }
2344 
2345 static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
2346                                target_ulong *ret_val,
2347                                target_ulong new_val, target_ulong wr_mask)
2348 {
2349     uint64_t rval;
2350     RISCVException ret;
2351 
2352     ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
2353     if (ret_val) {
2354         *ret_val = rval;
2355     }
2356 
2357     return ret;
2358 }
2359 
2360 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
2361                                 target_ulong *ret_val,
2362                                 target_ulong new_val, target_ulong wr_mask)
2363 {
2364     uint64_t rval;
2365     RISCVException ret;
2366 
2367     ret = rmw_vsie64(env, csrno, &rval,
2368         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2369     if (ret_val) {
2370         *ret_val = rval >> 32;
2371     }
2372 
2373     return ret;
2374 }
2375 
2376 static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
2377                                 uint64_t *ret_val,
2378                                 uint64_t new_val, uint64_t wr_mask)
2379 {
2380     RISCVException ret;
2381     uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
2382 
2383     if (env->virt_enabled) {
2384         if (env->hvictl & HVICTL_VTI) {
2385             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
2386         }
2387         ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
2388     } else {
2389         ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
2390     }
2391 
2392     if (ret_val) {
2393         *ret_val &= mask;
2394     }
2395 
2396     return ret;
2397 }
2398 
2399 static RISCVException rmw_sie(CPURISCVState *env, int csrno,
2400                               target_ulong *ret_val,
2401                               target_ulong new_val, target_ulong wr_mask)
2402 {
2403     uint64_t rval;
2404     RISCVException ret;
2405 
2406     ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
2407     if (ret == RISCV_EXCP_NONE && ret_val) {
2408         *ret_val = rval;
2409     }
2410 
2411     return ret;
2412 }
2413 
2414 static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
2415                                target_ulong *ret_val,
2416                                target_ulong new_val, target_ulong wr_mask)
2417 {
2418     uint64_t rval;
2419     RISCVException ret;
2420 
2421     ret = rmw_sie64(env, csrno, &rval,
2422         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2423     if (ret_val) {
2424         *ret_val = rval >> 32;
2425     }
2426 
2427     return ret;
2428 }
2429 
2430 static RISCVException read_stvec(CPURISCVState *env, int csrno,
2431                                  target_ulong *val)
2432 {
2433     *val = env->stvec;
2434     return RISCV_EXCP_NONE;
2435 }
2436 
2437 static RISCVException write_stvec(CPURISCVState *env, int csrno,
2438                                   target_ulong val)
2439 {
2440     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
2441     if ((val & 3) < 2) {
2442         env->stvec = val;
2443     } else {
2444         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
2445     }
2446     return RISCV_EXCP_NONE;
2447 }
2448 
2449 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
2450                                       target_ulong *val)
2451 {
2452     *val = env->scounteren;
2453     return RISCV_EXCP_NONE;
2454 }
2455 
2456 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
2457                                        target_ulong val)
2458 {
2459     env->scounteren = val;
2460     return RISCV_EXCP_NONE;
2461 }
2462 
2463 /* Supervisor Trap Handling */
2464 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
2465                                          Int128 *val)
2466 {
2467     *val = int128_make128(env->sscratch, env->sscratchh);
2468     return RISCV_EXCP_NONE;
2469 }
2470 
2471 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
2472                                           Int128 val)
2473 {
2474     env->sscratch = int128_getlo(val);
2475     env->sscratchh = int128_gethi(val);
2476     return RISCV_EXCP_NONE;
2477 }
2478 
2479 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
2480                                     target_ulong *val)
2481 {
2482     *val = env->sscratch;
2483     return RISCV_EXCP_NONE;
2484 }
2485 
2486 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
2487                                      target_ulong val)
2488 {
2489     env->sscratch = val;
2490     return RISCV_EXCP_NONE;
2491 }
2492 
2493 static RISCVException read_sepc(CPURISCVState *env, int csrno,
2494                                 target_ulong *val)
2495 {
2496     *val = env->sepc;
2497     return RISCV_EXCP_NONE;
2498 }
2499 
2500 static RISCVException write_sepc(CPURISCVState *env, int csrno,
2501                                  target_ulong val)
2502 {
2503     env->sepc = val;
2504     return RISCV_EXCP_NONE;
2505 }
2506 
2507 static RISCVException read_scause(CPURISCVState *env, int csrno,
2508                                   target_ulong *val)
2509 {
2510     *val = env->scause;
2511     return RISCV_EXCP_NONE;
2512 }
2513 
2514 static RISCVException write_scause(CPURISCVState *env, int csrno,
2515                                    target_ulong val)
2516 {
2517     env->scause = val;
2518     return RISCV_EXCP_NONE;
2519 }
2520 
2521 static RISCVException read_stval(CPURISCVState *env, int csrno,
2522                                  target_ulong *val)
2523 {
2524     *val = env->stval;
2525     return RISCV_EXCP_NONE;
2526 }
2527 
2528 static RISCVException write_stval(CPURISCVState *env, int csrno,
2529                                   target_ulong val)
2530 {
2531     env->stval = val;
2532     return RISCV_EXCP_NONE;
2533 }
2534 
2535 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
2536                                  uint64_t *ret_val,
2537                                  uint64_t new_val, uint64_t wr_mask)
2538 {
2539     RISCVException ret;
2540     uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
2541 
2542     /* Bring VS-level bits to correct position */
2543     new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
2544     wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
2545 
2546     ret = rmw_mip64(env, csrno, &rval, new_val,
2547                     wr_mask & mask & vsip_writable_mask);
2548     if (ret_val) {
2549         *ret_val = (rval & mask) >> 1;
2550     }
2551 
2552     return ret;
2553 }
2554 
2555 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
2556                                target_ulong *ret_val,
2557                                target_ulong new_val, target_ulong wr_mask)
2558 {
2559     uint64_t rval;
2560     RISCVException ret;
2561 
2562     ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
2563     if (ret_val) {
2564         *ret_val = rval;
2565     }
2566 
2567     return ret;
2568 }
2569 
2570 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
2571                                 target_ulong *ret_val,
2572                                 target_ulong new_val, target_ulong wr_mask)
2573 {
2574     uint64_t rval;
2575     RISCVException ret;
2576 
2577     ret = rmw_vsip64(env, csrno, &rval,
2578         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2579     if (ret_val) {
2580         *ret_val = rval >> 32;
2581     }
2582 
2583     return ret;
2584 }
2585 
2586 static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
2587                                 uint64_t *ret_val,
2588                                 uint64_t new_val, uint64_t wr_mask)
2589 {
2590     RISCVException ret;
2591     uint64_t mask = env->mideleg & sip_writable_mask;
2592 
2593     if (env->virt_enabled) {
2594         if (env->hvictl & HVICTL_VTI) {
2595             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
2596         }
2597         ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
2598     } else {
2599         ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
2600     }
2601 
2602     if (ret_val) {
2603         *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
2604     }
2605 
2606     return ret;
2607 }
2608 
2609 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
2610                               target_ulong *ret_val,
2611                               target_ulong new_val, target_ulong wr_mask)
2612 {
2613     uint64_t rval;
2614     RISCVException ret;
2615 
2616     ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
2617     if (ret_val) {
2618         *ret_val = rval;
2619     }
2620 
2621     return ret;
2622 }
2623 
2624 static RISCVException rmw_siph(CPURISCVState *env, int csrno,
2625                                target_ulong *ret_val,
2626                                target_ulong new_val, target_ulong wr_mask)
2627 {
2628     uint64_t rval;
2629     RISCVException ret;
2630 
2631     ret = rmw_sip64(env, csrno, &rval,
2632         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2633     if (ret_val) {
2634         *ret_val = rval >> 32;
2635     }
2636 
2637     return ret;
2638 }
2639 
2640 /* Supervisor Protection and Translation */
2641 static RISCVException read_satp(CPURISCVState *env, int csrno,
2642                                 target_ulong *val)
2643 {
2644     if (!riscv_cpu_cfg(env)->mmu) {
2645         *val = 0;
2646         return RISCV_EXCP_NONE;
2647     }
2648 
2649     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
2650         return RISCV_EXCP_ILLEGAL_INST;
2651     } else {
2652         *val = env->satp;
2653     }
2654 
2655     return RISCV_EXCP_NONE;
2656 }
2657 
2658 static RISCVException write_satp(CPURISCVState *env, int csrno,
2659                                  target_ulong val)
2660 {
2661     target_ulong mask;
2662     bool vm;
2663 
2664     if (!riscv_cpu_cfg(env)->mmu) {
2665         return RISCV_EXCP_NONE;
2666     }
2667 
2668     if (riscv_cpu_mxl(env) == MXL_RV32) {
2669         vm = validate_vm(env, get_field(val, SATP32_MODE));
2670         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
2671     } else {
2672         vm = validate_vm(env, get_field(val, SATP64_MODE));
2673         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
2674     }
2675 
2676     if (vm && mask) {
2677         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
2678             return RISCV_EXCP_ILLEGAL_INST;
2679         } else {
2680             /*
2681              * The ISA defines SATP.MODE=Bare as "no translation", but we still
2682              * pass these through QEMU's TLB emulation as it improves
2683              * performance.  Flushing the TLB on SATP writes with paging
2684              * enabled avoids leaking those invalid cached mappings.
2685              */
2686             tlb_flush(env_cpu(env));
2687             env->satp = val;
2688         }
2689     }
2690     return RISCV_EXCP_NONE;
2691 }
2692 
2693 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
2694 {
2695     int irq, ret;
2696     target_ulong topei;
2697     uint64_t vseip, vsgein;
2698     uint32_t iid, iprio, hviid, hviprio, gein;
2699     uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
2700 
2701     gein = get_field(env->hstatus, HSTATUS_VGEIN);
2702     hviid = get_field(env->hvictl, HVICTL_IID);
2703     hviprio = get_field(env->hvictl, HVICTL_IPRIO);
2704 
2705     if (gein) {
2706         vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
2707         vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP;
2708         if (gein <= env->geilen && vseip) {
2709             siid[scount] = IRQ_S_EXT;
2710             siprio[scount] = IPRIO_MMAXIPRIO + 1;
2711             if (env->aia_ireg_rmw_fn[PRV_S]) {
2712                 /*
2713                  * Call machine specific IMSIC register emulation for
2714                  * reading TOPEI.
2715                  */
2716                 ret = env->aia_ireg_rmw_fn[PRV_S](
2717                         env->aia_ireg_rmw_fn_arg[PRV_S],
2718                         AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein,
2719                                       riscv_cpu_mxl_bits(env)),
2720                         &topei, 0, 0);
2721                 if (!ret && topei) {
2722                     siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK;
2723                 }
2724             }
2725             scount++;
2726         }
2727     } else {
2728         if (hviid == IRQ_S_EXT && hviprio) {
2729             siid[scount] = IRQ_S_EXT;
2730             siprio[scount] = hviprio;
2731             scount++;
2732         }
2733     }
2734 
2735     if (env->hvictl & HVICTL_VTI) {
2736         if (hviid != IRQ_S_EXT) {
2737             siid[scount] = hviid;
2738             siprio[scount] = hviprio;
2739             scount++;
2740         }
2741     } else {
2742         irq = riscv_cpu_vsirq_pending(env);
2743         if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) {
2744             siid[scount] = irq;
2745             siprio[scount] = env->hviprio[irq];
2746             scount++;
2747         }
2748     }
2749 
2750     iid = 0;
2751     iprio = UINT_MAX;
2752     for (s = 0; s < scount; s++) {
2753         if (siprio[s] < iprio) {
2754             iid = siid[s];
2755             iprio = siprio[s];
2756         }
2757     }
2758 
2759     if (iid) {
2760         if (env->hvictl & HVICTL_IPRIOM) {
2761             if (iprio > IPRIO_MMAXIPRIO) {
2762                 iprio = IPRIO_MMAXIPRIO;
2763             }
2764             if (!iprio) {
2765                 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) {
2766                     iprio = IPRIO_MMAXIPRIO;
2767                 }
2768             }
2769         } else {
2770             iprio = 1;
2771         }
2772     } else {
2773         iprio = 0;
2774     }
2775 
2776     *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT;
2777     *val |= iprio;
2778     return RISCV_EXCP_NONE;
2779 }
2780 
2781 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
2782 {
2783     int irq;
2784     uint8_t iprio;
2785 
2786     if (env->virt_enabled) {
2787         return read_vstopi(env, CSR_VSTOPI, val);
2788     }
2789 
2790     irq = riscv_cpu_sirq_pending(env);
2791     if (irq <= 0 || irq > 63) {
2792         *val = 0;
2793     } else {
2794         iprio = env->siprio[irq];
2795         if (!iprio) {
2796             if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) {
2797                 iprio = IPRIO_MMAXIPRIO;
2798            }
2799         }
2800         *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
2801         *val |= iprio;
2802     }
2803 
2804     return RISCV_EXCP_NONE;
2805 }
2806 
2807 /* Hypervisor Extensions */
2808 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
2809                                    target_ulong *val)
2810 {
2811     *val = env->hstatus;
2812     if (riscv_cpu_mxl(env) != MXL_RV32) {
2813         /* We only support 64-bit VSXL */
2814         *val = set_field(*val, HSTATUS_VSXL, 2);
2815     }
2816     /* We only support little endian */
2817     *val = set_field(*val, HSTATUS_VSBE, 0);
2818     return RISCV_EXCP_NONE;
2819 }
2820 
2821 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
2822                                     target_ulong val)
2823 {
2824     env->hstatus = val;
2825     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
2826         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
2827     }
2828     if (get_field(val, HSTATUS_VSBE) != 0) {
2829         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
2830     }
2831     return RISCV_EXCP_NONE;
2832 }
2833 
2834 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
2835                                    target_ulong *val)
2836 {
2837     *val = env->hedeleg;
2838     return RISCV_EXCP_NONE;
2839 }
2840 
2841 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
2842                                     target_ulong val)
2843 {
2844     env->hedeleg = val & vs_delegable_excps;
2845     return RISCV_EXCP_NONE;
2846 }
2847 
2848 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
2849                                     uint64_t *ret_val,
2850                                     uint64_t new_val, uint64_t wr_mask)
2851 {
2852     uint64_t mask = wr_mask & vs_delegable_ints;
2853 
2854     if (ret_val) {
2855         *ret_val = env->hideleg & vs_delegable_ints;
2856     }
2857 
2858     env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
2859     return RISCV_EXCP_NONE;
2860 }
2861 
2862 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
2863                                   target_ulong *ret_val,
2864                                   target_ulong new_val, target_ulong wr_mask)
2865 {
2866     uint64_t rval;
2867     RISCVException ret;
2868 
2869     ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
2870     if (ret_val) {
2871         *ret_val = rval;
2872     }
2873 
2874     return ret;
2875 }
2876 
2877 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
2878                                    target_ulong *ret_val,
2879                                    target_ulong new_val, target_ulong wr_mask)
2880 {
2881     uint64_t rval;
2882     RISCVException ret;
2883 
2884     ret = rmw_hideleg64(env, csrno, &rval,
2885         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2886     if (ret_val) {
2887         *ret_val = rval >> 32;
2888     }
2889 
2890     return ret;
2891 }
2892 
2893 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
2894                                  uint64_t *ret_val,
2895                                  uint64_t new_val, uint64_t wr_mask)
2896 {
2897     RISCVException ret;
2898 
2899     ret = rmw_mip64(env, csrno, ret_val, new_val,
2900                     wr_mask & hvip_writable_mask);
2901     if (ret_val) {
2902         *ret_val &= VS_MODE_INTERRUPTS;
2903     }
2904 
2905     return ret;
2906 }
2907 
2908 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
2909                                target_ulong *ret_val,
2910                                target_ulong new_val, target_ulong wr_mask)
2911 {
2912     uint64_t rval;
2913     RISCVException ret;
2914 
2915     ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
2916     if (ret_val) {
2917         *ret_val = rval;
2918     }
2919 
2920     return ret;
2921 }
2922 
2923 static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
2924                                 target_ulong *ret_val,
2925                                 target_ulong new_val, target_ulong wr_mask)
2926 {
2927     uint64_t rval;
2928     RISCVException ret;
2929 
2930     ret = rmw_hvip64(env, csrno, &rval,
2931         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2932     if (ret_val) {
2933         *ret_val = rval >> 32;
2934     }
2935 
2936     return ret;
2937 }
2938 
2939 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
2940                               target_ulong *ret_value,
2941                               target_ulong new_value, target_ulong write_mask)
2942 {
2943     int ret = rmw_mip(env, csrno, ret_value, new_value,
2944                       write_mask & hip_writable_mask);
2945 
2946     if (ret_value) {
2947         *ret_value &= HS_MODE_INTERRUPTS;
2948     }
2949     return ret;
2950 }
2951 
2952 static RISCVException rmw_hie(CPURISCVState *env, int csrno,
2953                               target_ulong *ret_val,
2954                               target_ulong new_val, target_ulong wr_mask)
2955 {
2956     uint64_t rval;
2957     RISCVException ret;
2958 
2959     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
2960     if (ret_val) {
2961         *ret_val = rval & HS_MODE_INTERRUPTS;
2962     }
2963 
2964     return ret;
2965 }
2966 
2967 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
2968                                       target_ulong *val)
2969 {
2970     *val = env->hcounteren;
2971     return RISCV_EXCP_NONE;
2972 }
2973 
2974 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
2975                                        target_ulong val)
2976 {
2977     env->hcounteren = val;
2978     return RISCV_EXCP_NONE;
2979 }
2980 
2981 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
2982                                  target_ulong *val)
2983 {
2984     if (val) {
2985         *val = env->hgeie;
2986     }
2987     return RISCV_EXCP_NONE;
2988 }
2989 
2990 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
2991                                   target_ulong val)
2992 {
2993     /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
2994     val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
2995     env->hgeie = val;
2996     /* Update mip.SGEIP bit */
2997     riscv_cpu_update_mip(env, MIP_SGEIP,
2998                          BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
2999     return RISCV_EXCP_NONE;
3000 }
3001 
3002 static RISCVException read_htval(CPURISCVState *env, int csrno,
3003                                  target_ulong *val)
3004 {
3005     *val = env->htval;
3006     return RISCV_EXCP_NONE;
3007 }
3008 
3009 static RISCVException write_htval(CPURISCVState *env, int csrno,
3010                                   target_ulong val)
3011 {
3012     env->htval = val;
3013     return RISCV_EXCP_NONE;
3014 }
3015 
3016 static RISCVException read_htinst(CPURISCVState *env, int csrno,
3017                                   target_ulong *val)
3018 {
3019     *val = env->htinst;
3020     return RISCV_EXCP_NONE;
3021 }
3022 
3023 static RISCVException write_htinst(CPURISCVState *env, int csrno,
3024                                    target_ulong val)
3025 {
3026     return RISCV_EXCP_NONE;
3027 }
3028 
3029 static RISCVException read_hgeip(CPURISCVState *env, int csrno,
3030                                  target_ulong *val)
3031 {
3032     if (val) {
3033         *val = env->hgeip;
3034     }
3035     return RISCV_EXCP_NONE;
3036 }
3037 
3038 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
3039                                  target_ulong *val)
3040 {
3041     *val = env->hgatp;
3042     return RISCV_EXCP_NONE;
3043 }
3044 
3045 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
3046                                   target_ulong val)
3047 {
3048     env->hgatp = val;
3049     return RISCV_EXCP_NONE;
3050 }
3051 
3052 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
3053                                       target_ulong *val)
3054 {
3055     if (!env->rdtime_fn) {
3056         return RISCV_EXCP_ILLEGAL_INST;
3057     }
3058 
3059     *val = env->htimedelta;
3060     return RISCV_EXCP_NONE;
3061 }
3062 
3063 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
3064                                        target_ulong val)
3065 {
3066     if (!env->rdtime_fn) {
3067         return RISCV_EXCP_ILLEGAL_INST;
3068     }
3069 
3070     if (riscv_cpu_mxl(env) == MXL_RV32) {
3071         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
3072     } else {
3073         env->htimedelta = val;
3074     }
3075 
3076     if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
3077         riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
3078                                   env->htimedelta, MIP_VSTIP);
3079     }
3080 
3081     return RISCV_EXCP_NONE;
3082 }
3083 
3084 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
3085                                        target_ulong *val)
3086 {
3087     if (!env->rdtime_fn) {
3088         return RISCV_EXCP_ILLEGAL_INST;
3089     }
3090 
3091     *val = env->htimedelta >> 32;
3092     return RISCV_EXCP_NONE;
3093 }
3094 
3095 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
3096                                         target_ulong val)
3097 {
3098     if (!env->rdtime_fn) {
3099         return RISCV_EXCP_ILLEGAL_INST;
3100     }
3101 
3102     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
3103 
3104     if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
3105         riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
3106                                   env->htimedelta, MIP_VSTIP);
3107     }
3108 
3109     return RISCV_EXCP_NONE;
3110 }
3111 
3112 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
3113 {
3114     *val = env->hvictl;
3115     return RISCV_EXCP_NONE;
3116 }
3117 
3118 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
3119 {
3120     env->hvictl = val & HVICTL_VALID_MASK;
3121     return RISCV_EXCP_NONE;
3122 }
3123 
3124 static int read_hvipriox(CPURISCVState *env, int first_index,
3125                          uint8_t *iprio, target_ulong *val)
3126 {
3127     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
3128 
3129     /* First index has to be a multiple of number of irqs per register */
3130     if (first_index % num_irqs) {
3131         return (env->virt_enabled) ?
3132                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
3133     }
3134 
3135     /* Fill-up return value */
3136     *val = 0;
3137     for (i = 0; i < num_irqs; i++) {
3138         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
3139             continue;
3140         }
3141         if (rdzero) {
3142             continue;
3143         }
3144         *val |= ((target_ulong)iprio[irq]) << (i * 8);
3145     }
3146 
3147     return RISCV_EXCP_NONE;
3148 }
3149 
3150 static int write_hvipriox(CPURISCVState *env, int first_index,
3151                           uint8_t *iprio, target_ulong val)
3152 {
3153     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
3154 
3155     /* First index has to be a multiple of number of irqs per register */
3156     if (first_index % num_irqs) {
3157         return (env->virt_enabled) ?
3158                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
3159     }
3160 
3161     /* Fill-up priority arrary */
3162     for (i = 0; i < num_irqs; i++) {
3163         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
3164             continue;
3165         }
3166         if (rdzero) {
3167             iprio[irq] = 0;
3168         } else {
3169             iprio[irq] = (val >> (i * 8)) & 0xff;
3170         }
3171     }
3172 
3173     return RISCV_EXCP_NONE;
3174 }
3175 
3176 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
3177 {
3178     return read_hvipriox(env, 0, env->hviprio, val);
3179 }
3180 
3181 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
3182 {
3183     return write_hvipriox(env, 0, env->hviprio, val);
3184 }
3185 
3186 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
3187 {
3188     return read_hvipriox(env, 4, env->hviprio, val);
3189 }
3190 
3191 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
3192 {
3193     return write_hvipriox(env, 4, env->hviprio, val);
3194 }
3195 
3196 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
3197 {
3198     return read_hvipriox(env, 8, env->hviprio, val);
3199 }
3200 
3201 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
3202 {
3203     return write_hvipriox(env, 8, env->hviprio, val);
3204 }
3205 
3206 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
3207 {
3208     return read_hvipriox(env, 12, env->hviprio, val);
3209 }
3210 
3211 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
3212 {
3213     return write_hvipriox(env, 12, env->hviprio, val);
3214 }
3215 
3216 /* Virtual CSR Registers */
3217 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
3218                                     target_ulong *val)
3219 {
3220     *val = env->vsstatus;
3221     return RISCV_EXCP_NONE;
3222 }
3223 
3224 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
3225                                      target_ulong val)
3226 {
3227     uint64_t mask = (target_ulong)-1;
3228     if ((val & VSSTATUS64_UXL) == 0) {
3229         mask &= ~VSSTATUS64_UXL;
3230     }
3231     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
3232     return RISCV_EXCP_NONE;
3233 }
3234 
3235 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
3236 {
3237     *val = env->vstvec;
3238     return RISCV_EXCP_NONE;
3239 }
3240 
3241 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
3242                                    target_ulong val)
3243 {
3244     env->vstvec = val;
3245     return RISCV_EXCP_NONE;
3246 }
3247 
3248 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
3249                                      target_ulong *val)
3250 {
3251     *val = env->vsscratch;
3252     return RISCV_EXCP_NONE;
3253 }
3254 
3255 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
3256                                       target_ulong val)
3257 {
3258     env->vsscratch = val;
3259     return RISCV_EXCP_NONE;
3260 }
3261 
3262 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
3263                                  target_ulong *val)
3264 {
3265     *val = env->vsepc;
3266     return RISCV_EXCP_NONE;
3267 }
3268 
3269 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
3270                                   target_ulong val)
3271 {
3272     env->vsepc = val;
3273     return RISCV_EXCP_NONE;
3274 }
3275 
3276 static RISCVException read_vscause(CPURISCVState *env, int csrno,
3277                                    target_ulong *val)
3278 {
3279     *val = env->vscause;
3280     return RISCV_EXCP_NONE;
3281 }
3282 
3283 static RISCVException write_vscause(CPURISCVState *env, int csrno,
3284                                     target_ulong val)
3285 {
3286     env->vscause = val;
3287     return RISCV_EXCP_NONE;
3288 }
3289 
3290 static RISCVException read_vstval(CPURISCVState *env, int csrno,
3291                                   target_ulong *val)
3292 {
3293     *val = env->vstval;
3294     return RISCV_EXCP_NONE;
3295 }
3296 
3297 static RISCVException write_vstval(CPURISCVState *env, int csrno,
3298                                    target_ulong val)
3299 {
3300     env->vstval = val;
3301     return RISCV_EXCP_NONE;
3302 }
3303 
3304 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
3305                                  target_ulong *val)
3306 {
3307     *val = env->vsatp;
3308     return RISCV_EXCP_NONE;
3309 }
3310 
3311 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
3312                                   target_ulong val)
3313 {
3314     env->vsatp = val;
3315     return RISCV_EXCP_NONE;
3316 }
3317 
3318 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
3319                                   target_ulong *val)
3320 {
3321     *val = env->mtval2;
3322     return RISCV_EXCP_NONE;
3323 }
3324 
3325 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
3326                                    target_ulong val)
3327 {
3328     env->mtval2 = val;
3329     return RISCV_EXCP_NONE;
3330 }
3331 
3332 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
3333                                   target_ulong *val)
3334 {
3335     *val = env->mtinst;
3336     return RISCV_EXCP_NONE;
3337 }
3338 
3339 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
3340                                    target_ulong val)
3341 {
3342     env->mtinst = val;
3343     return RISCV_EXCP_NONE;
3344 }
3345 
3346 /* Physical Memory Protection */
3347 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
3348                                    target_ulong *val)
3349 {
3350     *val = mseccfg_csr_read(env);
3351     return RISCV_EXCP_NONE;
3352 }
3353 
3354 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
3355                                     target_ulong val)
3356 {
3357     mseccfg_csr_write(env, val);
3358     return RISCV_EXCP_NONE;
3359 }
3360 
3361 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
3362                                   target_ulong *val)
3363 {
3364     uint32_t reg_index = csrno - CSR_PMPCFG0;
3365 
3366     *val = pmpcfg_csr_read(env, reg_index);
3367     return RISCV_EXCP_NONE;
3368 }
3369 
3370 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
3371                                    target_ulong val)
3372 {
3373     uint32_t reg_index = csrno - CSR_PMPCFG0;
3374 
3375     pmpcfg_csr_write(env, reg_index, val);
3376     return RISCV_EXCP_NONE;
3377 }
3378 
3379 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
3380                                    target_ulong *val)
3381 {
3382     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
3383     return RISCV_EXCP_NONE;
3384 }
3385 
3386 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
3387                                     target_ulong val)
3388 {
3389     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
3390     return RISCV_EXCP_NONE;
3391 }
3392 
3393 static RISCVException read_tselect(CPURISCVState *env, int csrno,
3394                                    target_ulong *val)
3395 {
3396     *val = tselect_csr_read(env);
3397     return RISCV_EXCP_NONE;
3398 }
3399 
3400 static RISCVException write_tselect(CPURISCVState *env, int csrno,
3401                                     target_ulong val)
3402 {
3403     tselect_csr_write(env, val);
3404     return RISCV_EXCP_NONE;
3405 }
3406 
3407 static RISCVException read_tdata(CPURISCVState *env, int csrno,
3408                                  target_ulong *val)
3409 {
3410     /* return 0 in tdata1 to end the trigger enumeration */
3411     if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) {
3412         *val = 0;
3413         return RISCV_EXCP_NONE;
3414     }
3415 
3416     if (!tdata_available(env, csrno - CSR_TDATA1)) {
3417         return RISCV_EXCP_ILLEGAL_INST;
3418     }
3419 
3420     *val = tdata_csr_read(env, csrno - CSR_TDATA1);
3421     return RISCV_EXCP_NONE;
3422 }
3423 
3424 static RISCVException write_tdata(CPURISCVState *env, int csrno,
3425                                   target_ulong val)
3426 {
3427     if (!tdata_available(env, csrno - CSR_TDATA1)) {
3428         return RISCV_EXCP_ILLEGAL_INST;
3429     }
3430 
3431     tdata_csr_write(env, csrno - CSR_TDATA1, val);
3432     return RISCV_EXCP_NONE;
3433 }
3434 
3435 static RISCVException read_tinfo(CPURISCVState *env, int csrno,
3436                                  target_ulong *val)
3437 {
3438     *val = tinfo_csr_read(env);
3439     return RISCV_EXCP_NONE;
3440 }
3441 
3442 /*
3443  * Functions to access Pointer Masking feature registers
3444  * We have to check if current priv lvl could modify
3445  * csr in given mode
3446  */
3447 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
3448 {
3449     int csr_priv = get_field(csrno, 0x300);
3450     int pm_current;
3451 
3452     if (env->debugger) {
3453         return false;
3454     }
3455     /*
3456      * If priv lvls differ that means we're accessing csr from higher priv lvl,
3457      * so allow the access
3458      */
3459     if (env->priv != csr_priv) {
3460         return false;
3461     }
3462     switch (env->priv) {
3463     case PRV_M:
3464         pm_current = get_field(env->mmte, M_PM_CURRENT);
3465         break;
3466     case PRV_S:
3467         pm_current = get_field(env->mmte, S_PM_CURRENT);
3468         break;
3469     case PRV_U:
3470         pm_current = get_field(env->mmte, U_PM_CURRENT);
3471         break;
3472     default:
3473         g_assert_not_reached();
3474     }
3475     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
3476     return !pm_current;
3477 }
3478 
3479 static RISCVException read_mmte(CPURISCVState *env, int csrno,
3480                                 target_ulong *val)
3481 {
3482     *val = env->mmte & MMTE_MASK;
3483     return RISCV_EXCP_NONE;
3484 }
3485 
3486 static RISCVException write_mmte(CPURISCVState *env, int csrno,
3487                                  target_ulong val)
3488 {
3489     uint64_t mstatus;
3490     target_ulong wpri_val = val & MMTE_MASK;
3491 
3492     if (val != wpri_val) {
3493         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
3494                       "MMTE: WPRI violation written 0x", val,
3495                       "vs expected 0x", wpri_val);
3496     }
3497     /* for machine mode pm.current is hardwired to 1 */
3498     wpri_val |= MMTE_M_PM_CURRENT;
3499 
3500     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
3501     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
3502     env->mmte = wpri_val | PM_EXT_DIRTY;
3503     riscv_cpu_update_mask(env);
3504 
3505     /* Set XS and SD bits, since PM CSRs are dirty */
3506     mstatus = env->mstatus | MSTATUS_XS;
3507     write_mstatus(env, csrno, mstatus);
3508     return RISCV_EXCP_NONE;
3509 }
3510 
3511 static RISCVException read_smte(CPURISCVState *env, int csrno,
3512                                 target_ulong *val)
3513 {
3514     *val = env->mmte & SMTE_MASK;
3515     return RISCV_EXCP_NONE;
3516 }
3517 
3518 static RISCVException write_smte(CPURISCVState *env, int csrno,
3519                                  target_ulong val)
3520 {
3521     target_ulong wpri_val = val & SMTE_MASK;
3522 
3523     if (val != wpri_val) {
3524         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
3525                       "SMTE: WPRI violation written 0x", val,
3526                       "vs expected 0x", wpri_val);
3527     }
3528 
3529     /* if pm.current==0 we can't modify current PM CSRs */
3530     if (check_pm_current_disabled(env, csrno)) {
3531         return RISCV_EXCP_NONE;
3532     }
3533 
3534     wpri_val |= (env->mmte & ~SMTE_MASK);
3535     write_mmte(env, csrno, wpri_val);
3536     return RISCV_EXCP_NONE;
3537 }
3538 
3539 static RISCVException read_umte(CPURISCVState *env, int csrno,
3540                                 target_ulong *val)
3541 {
3542     *val = env->mmte & UMTE_MASK;
3543     return RISCV_EXCP_NONE;
3544 }
3545 
3546 static RISCVException write_umte(CPURISCVState *env, int csrno,
3547                                  target_ulong val)
3548 {
3549     target_ulong wpri_val = val & UMTE_MASK;
3550 
3551     if (val != wpri_val) {
3552         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
3553                       "UMTE: WPRI violation written 0x", val,
3554                       "vs expected 0x", wpri_val);
3555     }
3556 
3557     if (check_pm_current_disabled(env, csrno)) {
3558         return RISCV_EXCP_NONE;
3559     }
3560 
3561     wpri_val |= (env->mmte & ~UMTE_MASK);
3562     write_mmte(env, csrno, wpri_val);
3563     return RISCV_EXCP_NONE;
3564 }
3565 
3566 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
3567                                    target_ulong *val)
3568 {
3569     *val = env->mpmmask;
3570     return RISCV_EXCP_NONE;
3571 }
3572 
3573 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
3574                                     target_ulong val)
3575 {
3576     uint64_t mstatus;
3577 
3578     env->mpmmask = val;
3579     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
3580         env->cur_pmmask = val;
3581     }
3582     env->mmte |= PM_EXT_DIRTY;
3583 
3584     /* Set XS and SD bits, since PM CSRs are dirty */
3585     mstatus = env->mstatus | MSTATUS_XS;
3586     write_mstatus(env, csrno, mstatus);
3587     return RISCV_EXCP_NONE;
3588 }
3589 
3590 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
3591                                    target_ulong *val)
3592 {
3593     *val = env->spmmask;
3594     return RISCV_EXCP_NONE;
3595 }
3596 
3597 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
3598                                     target_ulong val)
3599 {
3600     uint64_t mstatus;
3601 
3602     /* if pm.current==0 we can't modify current PM CSRs */
3603     if (check_pm_current_disabled(env, csrno)) {
3604         return RISCV_EXCP_NONE;
3605     }
3606     env->spmmask = val;
3607     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
3608         env->cur_pmmask = val;
3609     }
3610     env->mmte |= PM_EXT_DIRTY;
3611 
3612     /* Set XS and SD bits, since PM CSRs are dirty */
3613     mstatus = env->mstatus | MSTATUS_XS;
3614     write_mstatus(env, csrno, mstatus);
3615     return RISCV_EXCP_NONE;
3616 }
3617 
3618 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
3619                                    target_ulong *val)
3620 {
3621     *val = env->upmmask;
3622     return RISCV_EXCP_NONE;
3623 }
3624 
3625 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
3626                                     target_ulong val)
3627 {
3628     uint64_t mstatus;
3629 
3630     /* if pm.current==0 we can't modify current PM CSRs */
3631     if (check_pm_current_disabled(env, csrno)) {
3632         return RISCV_EXCP_NONE;
3633     }
3634     env->upmmask = val;
3635     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
3636         env->cur_pmmask = val;
3637     }
3638     env->mmte |= PM_EXT_DIRTY;
3639 
3640     /* Set XS and SD bits, since PM CSRs are dirty */
3641     mstatus = env->mstatus | MSTATUS_XS;
3642     write_mstatus(env, csrno, mstatus);
3643     return RISCV_EXCP_NONE;
3644 }
3645 
3646 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
3647                                    target_ulong *val)
3648 {
3649     *val = env->mpmbase;
3650     return RISCV_EXCP_NONE;
3651 }
3652 
3653 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
3654                                     target_ulong val)
3655 {
3656     uint64_t mstatus;
3657 
3658     env->mpmbase = val;
3659     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
3660         env->cur_pmbase = val;
3661     }
3662     env->mmte |= PM_EXT_DIRTY;
3663 
3664     /* Set XS and SD bits, since PM CSRs are dirty */
3665     mstatus = env->mstatus | MSTATUS_XS;
3666     write_mstatus(env, csrno, mstatus);
3667     return RISCV_EXCP_NONE;
3668 }
3669 
3670 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
3671                                    target_ulong *val)
3672 {
3673     *val = env->spmbase;
3674     return RISCV_EXCP_NONE;
3675 }
3676 
3677 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
3678                                     target_ulong val)
3679 {
3680     uint64_t mstatus;
3681 
3682     /* if pm.current==0 we can't modify current PM CSRs */
3683     if (check_pm_current_disabled(env, csrno)) {
3684         return RISCV_EXCP_NONE;
3685     }
3686     env->spmbase = val;
3687     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
3688         env->cur_pmbase = val;
3689     }
3690     env->mmte |= PM_EXT_DIRTY;
3691 
3692     /* Set XS and SD bits, since PM CSRs are dirty */
3693     mstatus = env->mstatus | MSTATUS_XS;
3694     write_mstatus(env, csrno, mstatus);
3695     return RISCV_EXCP_NONE;
3696 }
3697 
3698 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
3699                                    target_ulong *val)
3700 {
3701     *val = env->upmbase;
3702     return RISCV_EXCP_NONE;
3703 }
3704 
3705 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
3706                                     target_ulong val)
3707 {
3708     uint64_t mstatus;
3709 
3710     /* if pm.current==0 we can't modify current PM CSRs */
3711     if (check_pm_current_disabled(env, csrno)) {
3712         return RISCV_EXCP_NONE;
3713     }
3714     env->upmbase = val;
3715     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
3716         env->cur_pmbase = val;
3717     }
3718     env->mmte |= PM_EXT_DIRTY;
3719 
3720     /* Set XS and SD bits, since PM CSRs are dirty */
3721     mstatus = env->mstatus | MSTATUS_XS;
3722     write_mstatus(env, csrno, mstatus);
3723     return RISCV_EXCP_NONE;
3724 }
3725 
3726 #endif
3727 
3728 /* Crypto Extension */
3729 static RISCVException rmw_seed(CPURISCVState *env, int csrno,
3730                                target_ulong *ret_value,
3731                                target_ulong new_value,
3732                                target_ulong write_mask)
3733 {
3734     uint16_t random_v;
3735     Error *random_e = NULL;
3736     int random_r;
3737     target_ulong rval;
3738 
3739     random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
3740     if (unlikely(random_r < 0)) {
3741         /*
3742          * Failed, for unknown reasons in the crypto subsystem.
3743          * The best we can do is log the reason and return a
3744          * failure indication to the guest.  There is no reason
3745          * we know to expect the failure to be transitory, so
3746          * indicate DEAD to avoid having the guest spin on WAIT.
3747          */
3748         qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
3749                       __func__, error_get_pretty(random_e));
3750         error_free(random_e);
3751         rval = SEED_OPST_DEAD;
3752     } else {
3753         rval = random_v | SEED_OPST_ES16;
3754     }
3755 
3756     if (ret_value) {
3757         *ret_value = rval;
3758     }
3759 
3760     return RISCV_EXCP_NONE;
3761 }
3762 
3763 /*
3764  * riscv_csrrw - read and/or update control and status register
3765  *
3766  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
3767  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
3768  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
3769  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
3770  */
3771 
3772 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
3773                                                int csrno,
3774                                                bool write_mask)
3775 {
3776     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
3777     bool read_only = get_field(csrno, 0xC00) == 3;
3778     int csr_min_priv = csr_ops[csrno].min_priv_ver;
3779 
3780     /* ensure the CSR extension is enabled */
3781     if (!riscv_cpu_cfg(env)->ext_icsr) {
3782         return RISCV_EXCP_ILLEGAL_INST;
3783     }
3784 
3785     /* privileged spec version check */
3786     if (env->priv_ver < csr_min_priv) {
3787         return RISCV_EXCP_ILLEGAL_INST;
3788     }
3789 
3790     /* read / write check */
3791     if (write_mask && read_only) {
3792         return RISCV_EXCP_ILLEGAL_INST;
3793     }
3794 
3795     /*
3796      * The predicate() not only does existence check but also does some
3797      * access control check which triggers for example virtual instruction
3798      * exception in some cases. When writing read-only CSRs in those cases
3799      * illegal instruction exception should be triggered instead of virtual
3800      * instruction exception. Hence this comes after the read / write check.
3801      */
3802     g_assert(csr_ops[csrno].predicate != NULL);
3803     RISCVException ret = csr_ops[csrno].predicate(env, csrno);
3804     if (ret != RISCV_EXCP_NONE) {
3805         return ret;
3806     }
3807 
3808 #if !defined(CONFIG_USER_ONLY)
3809     int csr_priv, effective_priv = env->priv;
3810 
3811     if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
3812         !env->virt_enabled) {
3813         /*
3814          * We are in HS mode. Add 1 to the effective privledge level to
3815          * allow us to access the Hypervisor CSRs.
3816          */
3817         effective_priv++;
3818     }
3819 
3820     csr_priv = get_field(csrno, 0x300);
3821     if (!env->debugger && (effective_priv < csr_priv)) {
3822         if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
3823             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
3824         }
3825         return RISCV_EXCP_ILLEGAL_INST;
3826     }
3827 #endif
3828     return RISCV_EXCP_NONE;
3829 }
3830 
3831 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
3832                                        target_ulong *ret_value,
3833                                        target_ulong new_value,
3834                                        target_ulong write_mask)
3835 {
3836     RISCVException ret;
3837     target_ulong old_value;
3838 
3839     /* execute combined read/write operation if it exists */
3840     if (csr_ops[csrno].op) {
3841         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
3842     }
3843 
3844     /* if no accessor exists then return failure */
3845     if (!csr_ops[csrno].read) {
3846         return RISCV_EXCP_ILLEGAL_INST;
3847     }
3848     /* read old value */
3849     ret = csr_ops[csrno].read(env, csrno, &old_value);
3850     if (ret != RISCV_EXCP_NONE) {
3851         return ret;
3852     }
3853 
3854     /* write value if writable and write mask set, otherwise drop writes */
3855     if (write_mask) {
3856         new_value = (old_value & ~write_mask) | (new_value & write_mask);
3857         if (csr_ops[csrno].write) {
3858             ret = csr_ops[csrno].write(env, csrno, new_value);
3859             if (ret != RISCV_EXCP_NONE) {
3860                 return ret;
3861             }
3862         }
3863     }
3864 
3865     /* return old value */
3866     if (ret_value) {
3867         *ret_value = old_value;
3868     }
3869 
3870     return RISCV_EXCP_NONE;
3871 }
3872 
3873 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
3874                            target_ulong *ret_value,
3875                            target_ulong new_value, target_ulong write_mask)
3876 {
3877     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
3878     if (ret != RISCV_EXCP_NONE) {
3879         return ret;
3880     }
3881 
3882     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
3883 }
3884 
3885 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
3886                                         Int128 *ret_value,
3887                                         Int128 new_value,
3888                                         Int128 write_mask)
3889 {
3890     RISCVException ret;
3891     Int128 old_value;
3892 
3893     /* read old value */
3894     ret = csr_ops[csrno].read128(env, csrno, &old_value);
3895     if (ret != RISCV_EXCP_NONE) {
3896         return ret;
3897     }
3898 
3899     /* write value if writable and write mask set, otherwise drop writes */
3900     if (int128_nz(write_mask)) {
3901         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
3902                               int128_and(new_value, write_mask));
3903         if (csr_ops[csrno].write128) {
3904             ret = csr_ops[csrno].write128(env, csrno, new_value);
3905             if (ret != RISCV_EXCP_NONE) {
3906                 return ret;
3907             }
3908         } else if (csr_ops[csrno].write) {
3909             /* avoids having to write wrappers for all registers */
3910             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
3911             if (ret != RISCV_EXCP_NONE) {
3912                 return ret;
3913             }
3914         }
3915     }
3916 
3917     /* return old value */
3918     if (ret_value) {
3919         *ret_value = old_value;
3920     }
3921 
3922     return RISCV_EXCP_NONE;
3923 }
3924 
3925 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
3926                                 Int128 *ret_value,
3927                                 Int128 new_value, Int128 write_mask)
3928 {
3929     RISCVException ret;
3930 
3931     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
3932     if (ret != RISCV_EXCP_NONE) {
3933         return ret;
3934     }
3935 
3936     if (csr_ops[csrno].read128) {
3937         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
3938     }
3939 
3940     /*
3941      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
3942      * at all defined.
3943      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
3944      * significant), for those, this fallback is correctly handling the accesses
3945      */
3946     target_ulong old_value;
3947     ret = riscv_csrrw_do64(env, csrno, &old_value,
3948                            int128_getlo(new_value),
3949                            int128_getlo(write_mask));
3950     if (ret == RISCV_EXCP_NONE && ret_value) {
3951         *ret_value = int128_make64(old_value);
3952     }
3953     return ret;
3954 }
3955 
3956 /*
3957  * Debugger support.  If not in user mode, set env->debugger before the
3958  * riscv_csrrw call and clear it after the call.
3959  */
3960 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
3961                                  target_ulong *ret_value,
3962                                  target_ulong new_value,
3963                                  target_ulong write_mask)
3964 {
3965     RISCVException ret;
3966 #if !defined(CONFIG_USER_ONLY)
3967     env->debugger = true;
3968 #endif
3969     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
3970 #if !defined(CONFIG_USER_ONLY)
3971     env->debugger = false;
3972 #endif
3973     return ret;
3974 }
3975 
3976 static RISCVException read_jvt(CPURISCVState *env, int csrno,
3977                                target_ulong *val)
3978 {
3979     *val = env->jvt;
3980     return RISCV_EXCP_NONE;
3981 }
3982 
3983 static RISCVException write_jvt(CPURISCVState *env, int csrno,
3984                                 target_ulong val)
3985 {
3986     env->jvt = val;
3987     return RISCV_EXCP_NONE;
3988 }
3989 
3990 /* Control and Status Register function table */
3991 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
3992     /* User Floating-Point CSRs */
3993     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
3994     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
3995     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
3996     /* Vector CSRs */
3997     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
3998     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
3999     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
4000     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
4001     [CSR_VL]       = { "vl",       vs,     read_vl                    },
4002     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
4003     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
4004     /* User Timers and Counters */
4005     [CSR_CYCLE]    = { "cycle",    ctr,    read_hpmcounter  },
4006     [CSR_INSTRET]  = { "instret",  ctr,    read_hpmcounter  },
4007     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_hpmcounterh },
4008     [CSR_INSTRETH] = { "instreth", ctr32,  read_hpmcounterh },
4009 
4010     /*
4011      * In privileged mode, the monitor will have to emulate TIME CSRs only if
4012      * rdtime callback is not provided by machine/platform emulation.
4013      */
4014     [CSR_TIME]  = { "time",  ctr,   read_time  },
4015     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
4016 
4017     /* Crypto Extension */
4018     [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
4019 
4020     /* Zcmt Extension */
4021     [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt},
4022 
4023 #if !defined(CONFIG_USER_ONLY)
4024     /* Machine Timers and Counters */
4025     [CSR_MCYCLE]    = { "mcycle",    any,   read_hpmcounter,
4026                         write_mhpmcounter                    },
4027     [CSR_MINSTRET]  = { "minstret",  any,   read_hpmcounter,
4028                         write_mhpmcounter                    },
4029     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_hpmcounterh,
4030                         write_mhpmcounterh                   },
4031     [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh,
4032                         write_mhpmcounterh                   },
4033 
4034     /* Machine Information Registers */
4035     [CSR_MVENDORID] = { "mvendorid", any,   read_mvendorid },
4036     [CSR_MARCHID]   = { "marchid",   any,   read_marchid   },
4037     [CSR_MIMPID]    = { "mimpid",    any,   read_mimpid    },
4038     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid   },
4039 
4040     [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
4041                           .min_priv_ver = PRIV_VERSION_1_12_0 },
4042     /* Machine Trap Setup */
4043     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus, write_mstatus,
4044                           NULL,                read_mstatus_i128           },
4045     [CSR_MISA]        = { "misa",       any,   read_misa,    write_misa,
4046                           NULL,                read_misa_i128              },
4047     [CSR_MIDELEG]     = { "mideleg",    any,   NULL, NULL,   rmw_mideleg   },
4048     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg, write_medeleg },
4049     [CSR_MIE]         = { "mie",        any,   NULL, NULL,   rmw_mie       },
4050     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,   write_mtvec   },
4051     [CSR_MCOUNTEREN]  = { "mcounteren", umode, read_mcounteren,
4052                           write_mcounteren                                 },
4053 
4054     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,
4055                           write_mstatush                                   },
4056 
4057     /* Machine Trap Handling */
4058     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch,
4059                        NULL, read_mscratch_i128, write_mscratch_i128   },
4060     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
4061     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
4062     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
4063     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
4064 
4065     /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
4066     [CSR_MISELECT] = { "miselect", aia_any,   NULL, NULL,    rmw_xiselect },
4067     [CSR_MIREG]    = { "mireg",    aia_any,   NULL, NULL,    rmw_xireg },
4068 
4069     /* Machine-Level Interrupts (AIA) */
4070     [CSR_MTOPEI]   = { "mtopei",   aia_any, NULL, NULL, rmw_xtopei },
4071     [CSR_MTOPI]    = { "mtopi",    aia_any, read_mtopi },
4072 
4073     /* Virtual Interrupts for Supervisor Level (AIA) */
4074     [CSR_MVIEN]    = { "mvien",    aia_any, read_zero, write_ignore },
4075     [CSR_MVIP]     = { "mvip",     aia_any, read_zero, write_ignore },
4076 
4077     /* Machine-Level High-Half CSRs (AIA) */
4078     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
4079     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
4080     [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
4081     [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
4082     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
4083 
4084     /* Execution environment configuration */
4085     [CSR_MENVCFG]  = { "menvcfg",  umode, read_menvcfg,  write_menvcfg,
4086                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4087     [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh,
4088                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4089     [CSR_SENVCFG]  = { "senvcfg",  smode, read_senvcfg,  write_senvcfg,
4090                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4091     [CSR_HENVCFG]  = { "henvcfg",  hmode, read_henvcfg, write_henvcfg,
4092                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4093     [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
4094                        .min_priv_ver = PRIV_VERSION_1_12_0              },
4095 
4096     /* Smstateen extension CSRs */
4097     [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0,
4098                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4099     [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh,
4100                           write_mstateen0h,
4101                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4102     [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen,
4103                         write_mstateen_1_3,
4104                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4105     [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh,
4106                          write_mstateenh_1_3,
4107                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4108     [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,
4109                         write_mstateen_1_3,
4110                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4111     [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh,
4112                          write_mstateenh_1_3,
4113                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4114     [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen,
4115                         write_mstateen_1_3,
4116                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4117     [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh,
4118                          write_mstateenh_1_3,
4119                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4120     [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0,
4121                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4122     [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh,
4123                          write_hstateen0h,
4124                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4125     [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen,
4126                         write_hstateen_1_3,
4127                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4128     [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh,
4129                          write_hstateenh_1_3,
4130                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4131     [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen,
4132                         write_hstateen_1_3,
4133                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4134     [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh,
4135                          write_hstateenh_1_3,
4136                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4137     [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen,
4138                         write_hstateen_1_3,
4139                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4140     [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh,
4141                          write_hstateenh_1_3,
4142                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4143     [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0,
4144                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4145     [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen,
4146                         write_sstateen_1_3,
4147                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4148     [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen,
4149                         write_sstateen_1_3,
4150                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4151     [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen,
4152                         write_sstateen_1_3,
4153                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4154 
4155     /* Supervisor Trap Setup */
4156     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus,
4157                          NULL,                read_sstatus_i128               },
4158     [CSR_SIE]        = { "sie",        smode, NULL,   NULL,    rmw_sie        },
4159     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec    },
4160     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
4161                          write_scounteren                                     },
4162 
4163     /* Supervisor Trap Handling */
4164     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
4165                        NULL, read_sscratch_i128, write_sscratch_i128    },
4166     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
4167     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
4168     [CSR_STVAL]    = { "stval",    smode, read_stval,    write_stval    },
4169     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
4170     [CSR_STIMECMP] = { "stimecmp", sstc, read_stimecmp, write_stimecmp,
4171                        .min_priv_ver = PRIV_VERSION_1_12_0 },
4172     [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph,
4173                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4174     [CSR_VSTIMECMP] = { "vstimecmp", sstc, read_vstimecmp,
4175                         write_vstimecmp,
4176                         .min_priv_ver = PRIV_VERSION_1_12_0 },
4177     [CSR_VSTIMECMPH] = { "vstimecmph", sstc_32, read_vstimecmph,
4178                          write_vstimecmph,
4179                          .min_priv_ver = PRIV_VERSION_1_12_0 },
4180 
4181     /* Supervisor Protection and Translation */
4182     [CSR_SATP]     = { "satp",     smode, read_satp,     write_satp     },
4183 
4184     /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
4185     [CSR_SISELECT]   = { "siselect",   aia_smode, NULL, NULL, rmw_xiselect },
4186     [CSR_SIREG]      = { "sireg",      aia_smode, NULL, NULL, rmw_xireg },
4187 
4188     /* Supervisor-Level Interrupts (AIA) */
4189     [CSR_STOPEI]     = { "stopei",     aia_smode, NULL, NULL, rmw_xtopei },
4190     [CSR_STOPI]      = { "stopi",      aia_smode, read_stopi },
4191 
4192     /* Supervisor-Level High-Half CSRs (AIA) */
4193     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
4194     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
4195 
4196     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus, write_hstatus,
4197                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4198     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg, write_hedeleg,
4199                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4200     [CSR_HIDELEG]     = { "hideleg",     hmode,   NULL,   NULL, rmw_hideleg,
4201                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4202     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL, rmw_hvip,
4203                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4204     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL, rmw_hip,
4205                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4206     [CSR_HIE]         = { "hie",         hmode,   NULL,   NULL, rmw_hie,
4207                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4208     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,
4209                           write_hcounteren,
4210                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4211     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,   write_hgeie,
4212                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4213     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,   write_htval,
4214                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4215     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,  write_htinst,
4216                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4217     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,
4218                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4219     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,   write_hgatp,
4220                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4221     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,
4222                           write_htimedelta,
4223                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4224     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
4225                           write_htimedeltah,
4226                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4227 
4228     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,
4229                           write_vsstatus,
4230                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4231     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL, rmw_vsip,
4232                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4233     [CSR_VSIE]        = { "vsie",        hmode,   NULL,    NULL, rmw_vsie ,
4234                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4235     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,   write_vstvec,
4236                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4237     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,
4238                           write_vsscratch,
4239                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4240     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,    write_vsepc,
4241                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4242     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,  write_vscause,
4243                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4244     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,   write_vstval,
4245                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4246     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,    write_vsatp,
4247                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4248 
4249     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,   write_mtval2,
4250                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4251     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,   write_mtinst,
4252                           .min_priv_ver = PRIV_VERSION_1_12_0                },
4253 
4254     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
4255     [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero, write_ignore },
4256     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl,
4257                           write_hvictl                                      },
4258     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,
4259                           write_hviprio1                                    },
4260     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,
4261                           write_hviprio2                                    },
4262 
4263     /*
4264      * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
4265      */
4266     [CSR_VSISELECT]   = { "vsiselect",   aia_hmode, NULL, NULL,
4267                           rmw_xiselect                                     },
4268     [CSR_VSIREG]      = { "vsireg",      aia_hmode, NULL, NULL, rmw_xireg  },
4269 
4270     /* VS-Level Interrupts (H-extension with AIA) */
4271     [CSR_VSTOPEI]     = { "vstopei",     aia_hmode, NULL, NULL, rmw_xtopei },
4272     [CSR_VSTOPI]      = { "vstopi",      aia_hmode, read_vstopi },
4273 
4274     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
4275     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL,
4276                           rmw_hidelegh                                      },
4277     [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero,
4278                           write_ignore                                      },
4279     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
4280     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h,
4281                           write_hviprio1h                                   },
4282     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h,
4283                           write_hviprio2h                                   },
4284     [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
4285     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
4286 
4287     /* Physical Memory Protection */
4288     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
4289                          .min_priv_ver = PRIV_VERSION_1_11_0           },
4290     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
4291     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
4292     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
4293     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
4294     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
4295     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
4296     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
4297     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
4298     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
4299     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
4300     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
4301     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
4302     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
4303     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
4304     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
4305     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
4306     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
4307     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
4308     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
4309     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
4310 
4311     /* Debug CSRs */
4312     [CSR_TSELECT]   =  { "tselect", debug, read_tselect, write_tselect },
4313     [CSR_TDATA1]    =  { "tdata1",  debug, read_tdata,   write_tdata   },
4314     [CSR_TDATA2]    =  { "tdata2",  debug, read_tdata,   write_tdata   },
4315     [CSR_TDATA3]    =  { "tdata3",  debug, read_tdata,   write_tdata   },
4316     [CSR_TINFO]     =  { "tinfo",   debug, read_tinfo,   write_ignore  },
4317 
4318     /* User Pointer Masking */
4319     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,  write_umte },
4320     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask,
4321                          write_upmmask                                      },
4322     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase,
4323                          write_upmbase                                      },
4324     /* Machine Pointer Masking */
4325     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,  write_mmte },
4326     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask,
4327                          write_mpmmask                                      },
4328     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase,
4329                          write_mpmbase                                      },
4330     /* Supervisor Pointer Masking */
4331     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,  write_smte },
4332     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask,
4333                          write_spmmask                                      },
4334     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase,
4335                          write_spmbase                                      },
4336 
4337     /* Performance Counters */
4338     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_hpmcounter },
4339     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_hpmcounter },
4340     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_hpmcounter },
4341     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_hpmcounter },
4342     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_hpmcounter },
4343     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_hpmcounter },
4344     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_hpmcounter },
4345     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_hpmcounter },
4346     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_hpmcounter },
4347     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_hpmcounter },
4348     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_hpmcounter },
4349     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_hpmcounter },
4350     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_hpmcounter },
4351     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_hpmcounter },
4352     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_hpmcounter },
4353     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_hpmcounter },
4354     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_hpmcounter },
4355     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_hpmcounter },
4356     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_hpmcounter },
4357     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_hpmcounter },
4358     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_hpmcounter },
4359     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_hpmcounter },
4360     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_hpmcounter },
4361     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_hpmcounter },
4362     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_hpmcounter },
4363     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_hpmcounter },
4364     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_hpmcounter },
4365     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_hpmcounter },
4366     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_hpmcounter },
4367 
4368     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   mctr,    read_hpmcounter,
4369                              write_mhpmcounter                         },
4370     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   mctr,    read_hpmcounter,
4371                              write_mhpmcounter                         },
4372     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   mctr,    read_hpmcounter,
4373                              write_mhpmcounter                         },
4374     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   mctr,    read_hpmcounter,
4375                              write_mhpmcounter                         },
4376     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   mctr,    read_hpmcounter,
4377                              write_mhpmcounter                         },
4378     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   mctr,    read_hpmcounter,
4379                              write_mhpmcounter                         },
4380     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   mctr,    read_hpmcounter,
4381                              write_mhpmcounter                         },
4382     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  mctr,    read_hpmcounter,
4383                              write_mhpmcounter                         },
4384     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  mctr,    read_hpmcounter,
4385                              write_mhpmcounter                         },
4386     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  mctr,    read_hpmcounter,
4387                              write_mhpmcounter                         },
4388     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  mctr,    read_hpmcounter,
4389                              write_mhpmcounter                         },
4390     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  mctr,    read_hpmcounter,
4391                              write_mhpmcounter                         },
4392     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  mctr,    read_hpmcounter,
4393                              write_mhpmcounter                         },
4394     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  mctr,    read_hpmcounter,
4395                              write_mhpmcounter                         },
4396     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  mctr,    read_hpmcounter,
4397                              write_mhpmcounter                         },
4398     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  mctr,    read_hpmcounter,
4399                              write_mhpmcounter                         },
4400     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  mctr,    read_hpmcounter,
4401                              write_mhpmcounter                         },
4402     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  mctr,    read_hpmcounter,
4403                              write_mhpmcounter                         },
4404     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  mctr,    read_hpmcounter,
4405                              write_mhpmcounter                         },
4406     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  mctr,    read_hpmcounter,
4407                              write_mhpmcounter                         },
4408     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  mctr,    read_hpmcounter,
4409                              write_mhpmcounter                         },
4410     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  mctr,    read_hpmcounter,
4411                              write_mhpmcounter                         },
4412     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  mctr,    read_hpmcounter,
4413                              write_mhpmcounter                         },
4414     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  mctr,    read_hpmcounter,
4415                              write_mhpmcounter                         },
4416     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  mctr,    read_hpmcounter,
4417                              write_mhpmcounter                         },
4418     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  mctr,    read_hpmcounter,
4419                              write_mhpmcounter                         },
4420     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  mctr,    read_hpmcounter,
4421                              write_mhpmcounter                         },
4422     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  mctr,    read_hpmcounter,
4423                              write_mhpmcounter                         },
4424     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  mctr,    read_hpmcounter,
4425                              write_mhpmcounter                         },
4426 
4427     [CSR_MCOUNTINHIBIT]  = { "mcountinhibit",  any, read_mcountinhibit,
4428                              write_mcountinhibit,
4429                              .min_priv_ver = PRIV_VERSION_1_11_0       },
4430 
4431     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_mhpmevent,
4432                              write_mhpmevent                           },
4433     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_mhpmevent,
4434                              write_mhpmevent                           },
4435     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_mhpmevent,
4436                              write_mhpmevent                           },
4437     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_mhpmevent,
4438                              write_mhpmevent                           },
4439     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_mhpmevent,
4440                              write_mhpmevent                           },
4441     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_mhpmevent,
4442                              write_mhpmevent                           },
4443     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_mhpmevent,
4444                              write_mhpmevent                           },
4445     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_mhpmevent,
4446                              write_mhpmevent                           },
4447     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_mhpmevent,
4448                              write_mhpmevent                           },
4449     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_mhpmevent,
4450                              write_mhpmevent                           },
4451     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_mhpmevent,
4452                              write_mhpmevent                           },
4453     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_mhpmevent,
4454                              write_mhpmevent                           },
4455     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_mhpmevent,
4456                              write_mhpmevent                           },
4457     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_mhpmevent,
4458                              write_mhpmevent                           },
4459     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_mhpmevent,
4460                              write_mhpmevent                           },
4461     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_mhpmevent,
4462                              write_mhpmevent                           },
4463     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_mhpmevent,
4464                              write_mhpmevent                           },
4465     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_mhpmevent,
4466                              write_mhpmevent                           },
4467     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_mhpmevent,
4468                              write_mhpmevent                           },
4469     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_mhpmevent,
4470                              write_mhpmevent                           },
4471     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_mhpmevent,
4472                              write_mhpmevent                           },
4473     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_mhpmevent,
4474                              write_mhpmevent                           },
4475     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_mhpmevent,
4476                              write_mhpmevent                           },
4477     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_mhpmevent,
4478                              write_mhpmevent                           },
4479     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_mhpmevent,
4480                              write_mhpmevent                           },
4481     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_mhpmevent,
4482                              write_mhpmevent                           },
4483     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_mhpmevent,
4484                              write_mhpmevent                           },
4485     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_mhpmevent,
4486                              write_mhpmevent                           },
4487     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_mhpmevent,
4488                              write_mhpmevent                           },
4489 
4490     [CSR_MHPMEVENT3H]    = { "mhpmevent3h",    sscofpmf,  read_mhpmeventh,
4491                              write_mhpmeventh,
4492                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4493     [CSR_MHPMEVENT4H]    = { "mhpmevent4h",    sscofpmf,  read_mhpmeventh,
4494                              write_mhpmeventh,
4495                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4496     [CSR_MHPMEVENT5H]    = { "mhpmevent5h",    sscofpmf,  read_mhpmeventh,
4497                              write_mhpmeventh,
4498                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4499     [CSR_MHPMEVENT6H]    = { "mhpmevent6h",    sscofpmf,  read_mhpmeventh,
4500                              write_mhpmeventh,
4501                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4502     [CSR_MHPMEVENT7H]    = { "mhpmevent7h",    sscofpmf,  read_mhpmeventh,
4503                              write_mhpmeventh,
4504                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4505     [CSR_MHPMEVENT8H]    = { "mhpmevent8h",    sscofpmf,  read_mhpmeventh,
4506                              write_mhpmeventh,
4507                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4508     [CSR_MHPMEVENT9H]    = { "mhpmevent9h",    sscofpmf,  read_mhpmeventh,
4509                              write_mhpmeventh,
4510                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4511     [CSR_MHPMEVENT10H]   = { "mhpmevent10h",    sscofpmf,  read_mhpmeventh,
4512                              write_mhpmeventh,
4513                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4514     [CSR_MHPMEVENT11H]   = { "mhpmevent11h",    sscofpmf,  read_mhpmeventh,
4515                              write_mhpmeventh,
4516                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4517     [CSR_MHPMEVENT12H]   = { "mhpmevent12h",    sscofpmf,  read_mhpmeventh,
4518                              write_mhpmeventh,
4519                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4520     [CSR_MHPMEVENT13H]   = { "mhpmevent13h",    sscofpmf,  read_mhpmeventh,
4521                              write_mhpmeventh,
4522                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4523     [CSR_MHPMEVENT14H]   = { "mhpmevent14h",    sscofpmf,  read_mhpmeventh,
4524                              write_mhpmeventh,
4525                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4526     [CSR_MHPMEVENT15H]   = { "mhpmevent15h",    sscofpmf,  read_mhpmeventh,
4527                              write_mhpmeventh,
4528                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4529     [CSR_MHPMEVENT16H]   = { "mhpmevent16h",    sscofpmf,  read_mhpmeventh,
4530                              write_mhpmeventh,
4531                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4532     [CSR_MHPMEVENT17H]   = { "mhpmevent17h",    sscofpmf,  read_mhpmeventh,
4533                              write_mhpmeventh,
4534                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4535     [CSR_MHPMEVENT18H]   = { "mhpmevent18h",    sscofpmf,  read_mhpmeventh,
4536                              write_mhpmeventh,
4537                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4538     [CSR_MHPMEVENT19H]   = { "mhpmevent19h",    sscofpmf,  read_mhpmeventh,
4539                              write_mhpmeventh,
4540                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4541     [CSR_MHPMEVENT20H]   = { "mhpmevent20h",    sscofpmf,  read_mhpmeventh,
4542                              write_mhpmeventh,
4543                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4544     [CSR_MHPMEVENT21H]   = { "mhpmevent21h",    sscofpmf,  read_mhpmeventh,
4545                              write_mhpmeventh,
4546                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4547     [CSR_MHPMEVENT22H]   = { "mhpmevent22h",    sscofpmf,  read_mhpmeventh,
4548                              write_mhpmeventh,
4549                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4550     [CSR_MHPMEVENT23H]   = { "mhpmevent23h",    sscofpmf,  read_mhpmeventh,
4551                              write_mhpmeventh,
4552                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4553     [CSR_MHPMEVENT24H]   = { "mhpmevent24h",    sscofpmf,  read_mhpmeventh,
4554                              write_mhpmeventh,
4555                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4556     [CSR_MHPMEVENT25H]   = { "mhpmevent25h",    sscofpmf,  read_mhpmeventh,
4557                              write_mhpmeventh,
4558                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4559     [CSR_MHPMEVENT26H]   = { "mhpmevent26h",    sscofpmf,  read_mhpmeventh,
4560                              write_mhpmeventh,
4561                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4562     [CSR_MHPMEVENT27H]   = { "mhpmevent27h",    sscofpmf,  read_mhpmeventh,
4563                              write_mhpmeventh,
4564                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4565     [CSR_MHPMEVENT28H]   = { "mhpmevent28h",    sscofpmf,  read_mhpmeventh,
4566                              write_mhpmeventh,
4567                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4568     [CSR_MHPMEVENT29H]   = { "mhpmevent29h",    sscofpmf,  read_mhpmeventh,
4569                              write_mhpmeventh,
4570                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4571     [CSR_MHPMEVENT30H]   = { "mhpmevent30h",    sscofpmf,  read_mhpmeventh,
4572                              write_mhpmeventh,
4573                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4574     [CSR_MHPMEVENT31H]   = { "mhpmevent31h",    sscofpmf,  read_mhpmeventh,
4575                              write_mhpmeventh,
4576                              .min_priv_ver = PRIV_VERSION_1_12_0        },
4577 
4578     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_hpmcounterh },
4579     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_hpmcounterh },
4580     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_hpmcounterh },
4581     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_hpmcounterh },
4582     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_hpmcounterh },
4583     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_hpmcounterh },
4584     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_hpmcounterh },
4585     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_hpmcounterh },
4586     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_hpmcounterh },
4587     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_hpmcounterh },
4588     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_hpmcounterh },
4589     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_hpmcounterh },
4590     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_hpmcounterh },
4591     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_hpmcounterh },
4592     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_hpmcounterh },
4593     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_hpmcounterh },
4594     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_hpmcounterh },
4595     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_hpmcounterh },
4596     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_hpmcounterh },
4597     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_hpmcounterh },
4598     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_hpmcounterh },
4599     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_hpmcounterh },
4600     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_hpmcounterh },
4601     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_hpmcounterh },
4602     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_hpmcounterh },
4603     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_hpmcounterh },
4604     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_hpmcounterh },
4605     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_hpmcounterh },
4606     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_hpmcounterh },
4607 
4608     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  mctr32,  read_hpmcounterh,
4609                              write_mhpmcounterh                         },
4610     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  mctr32,  read_hpmcounterh,
4611                              write_mhpmcounterh                         },
4612     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  mctr32,  read_hpmcounterh,
4613                              write_mhpmcounterh                         },
4614     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  mctr32,  read_hpmcounterh,
4615                              write_mhpmcounterh                         },
4616     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  mctr32,  read_hpmcounterh,
4617                              write_mhpmcounterh                         },
4618     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  mctr32,  read_hpmcounterh,
4619                              write_mhpmcounterh                         },
4620     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  mctr32,  read_hpmcounterh,
4621                              write_mhpmcounterh                         },
4622     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32,  read_hpmcounterh,
4623                              write_mhpmcounterh                         },
4624     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32,  read_hpmcounterh,
4625                              write_mhpmcounterh                         },
4626     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32,  read_hpmcounterh,
4627                              write_mhpmcounterh                         },
4628     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32,  read_hpmcounterh,
4629                              write_mhpmcounterh                         },
4630     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32,  read_hpmcounterh,
4631                              write_mhpmcounterh                         },
4632     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32,  read_hpmcounterh,
4633                              write_mhpmcounterh                         },
4634     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32,  read_hpmcounterh,
4635                              write_mhpmcounterh                         },
4636     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32,  read_hpmcounterh,
4637                              write_mhpmcounterh                         },
4638     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32,  read_hpmcounterh,
4639                              write_mhpmcounterh                         },
4640     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32,  read_hpmcounterh,
4641                              write_mhpmcounterh                         },
4642     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32,  read_hpmcounterh,
4643                              write_mhpmcounterh                         },
4644     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32,  read_hpmcounterh,
4645                              write_mhpmcounterh                         },
4646     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32,  read_hpmcounterh,
4647                              write_mhpmcounterh                         },
4648     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32,  read_hpmcounterh,
4649                              write_mhpmcounterh                         },
4650     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32,  read_hpmcounterh,
4651                              write_mhpmcounterh                         },
4652     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32,  read_hpmcounterh,
4653                              write_mhpmcounterh                         },
4654     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32,  read_hpmcounterh,
4655                              write_mhpmcounterh                         },
4656     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32,  read_hpmcounterh,
4657                              write_mhpmcounterh                         },
4658     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32,  read_hpmcounterh,
4659                              write_mhpmcounterh                         },
4660     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32,  read_hpmcounterh,
4661                              write_mhpmcounterh                         },
4662     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32,  read_hpmcounterh,
4663                              write_mhpmcounterh                         },
4664     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32,  read_hpmcounterh,
4665                              write_mhpmcounterh                         },
4666     [CSR_SCOUNTOVF]      = { "scountovf", sscofpmf,  read_scountovf,
4667                              .min_priv_ver = PRIV_VERSION_1_12_0 },
4668 
4669 #endif /* !CONFIG_USER_ONLY */
4670 };
4671