1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "qemu/main-loop.h" 25 #include "exec/exec-all.h" 26 #include "sysemu/cpu-timers.h" 27 28 /* CSR function table public API */ 29 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 30 { 31 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 32 } 33 34 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 35 { 36 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 37 } 38 39 /* Predicates */ 40 static RISCVException fs(CPURISCVState *env, int csrno) 41 { 42 #if !defined(CONFIG_USER_ONLY) 43 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 44 !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 45 return RISCV_EXCP_ILLEGAL_INST; 46 } 47 #endif 48 return RISCV_EXCP_NONE; 49 } 50 51 static RISCVException vs(CPURISCVState *env, int csrno) 52 { 53 CPUState *cs = env_cpu(env); 54 RISCVCPU *cpu = RISCV_CPU(cs); 55 56 if (env->misa_ext & RVV || 57 cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 58 #if !defined(CONFIG_USER_ONLY) 59 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 60 return RISCV_EXCP_ILLEGAL_INST; 61 } 62 #endif 63 return RISCV_EXCP_NONE; 64 } 65 return RISCV_EXCP_ILLEGAL_INST; 66 } 67 68 static RISCVException ctr(CPURISCVState *env, int csrno) 69 { 70 #if !defined(CONFIG_USER_ONLY) 71 CPUState *cs = env_cpu(env); 72 RISCVCPU *cpu = RISCV_CPU(cs); 73 74 if (!cpu->cfg.ext_counters) { 75 /* The Counters extensions is not enabled */ 76 return RISCV_EXCP_ILLEGAL_INST; 77 } 78 79 if (riscv_cpu_virt_enabled(env)) { 80 switch (csrno) { 81 case CSR_CYCLE: 82 if (!get_field(env->hcounteren, COUNTEREN_CY) && 83 get_field(env->mcounteren, COUNTEREN_CY)) { 84 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 85 } 86 break; 87 case CSR_TIME: 88 if (!get_field(env->hcounteren, COUNTEREN_TM) && 89 get_field(env->mcounteren, COUNTEREN_TM)) { 90 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 91 } 92 break; 93 case CSR_INSTRET: 94 if (!get_field(env->hcounteren, COUNTEREN_IR) && 95 get_field(env->mcounteren, COUNTEREN_IR)) { 96 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 97 } 98 break; 99 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 100 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 101 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 102 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 103 } 104 break; 105 } 106 if (riscv_cpu_mxl(env) == MXL_RV32) { 107 switch (csrno) { 108 case CSR_CYCLEH: 109 if (!get_field(env->hcounteren, COUNTEREN_CY) && 110 get_field(env->mcounteren, COUNTEREN_CY)) { 111 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 112 } 113 break; 114 case CSR_TIMEH: 115 if (!get_field(env->hcounteren, COUNTEREN_TM) && 116 get_field(env->mcounteren, COUNTEREN_TM)) { 117 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 118 } 119 break; 120 case CSR_INSTRETH: 121 if (!get_field(env->hcounteren, COUNTEREN_IR) && 122 get_field(env->mcounteren, COUNTEREN_IR)) { 123 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 124 } 125 break; 126 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 127 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 128 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 129 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 130 } 131 break; 132 } 133 } 134 } 135 #endif 136 return RISCV_EXCP_NONE; 137 } 138 139 static RISCVException ctr32(CPURISCVState *env, int csrno) 140 { 141 if (riscv_cpu_mxl(env) != MXL_RV32) { 142 return RISCV_EXCP_ILLEGAL_INST; 143 } 144 145 return ctr(env, csrno); 146 } 147 148 #if !defined(CONFIG_USER_ONLY) 149 static RISCVException any(CPURISCVState *env, int csrno) 150 { 151 return RISCV_EXCP_NONE; 152 } 153 154 static RISCVException any32(CPURISCVState *env, int csrno) 155 { 156 if (riscv_cpu_mxl(env) != MXL_RV32) { 157 return RISCV_EXCP_ILLEGAL_INST; 158 } 159 160 return any(env, csrno); 161 162 } 163 164 static int aia_any(CPURISCVState *env, int csrno) 165 { 166 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 167 return RISCV_EXCP_ILLEGAL_INST; 168 } 169 170 return any(env, csrno); 171 } 172 173 static int aia_any32(CPURISCVState *env, int csrno) 174 { 175 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 176 return RISCV_EXCP_ILLEGAL_INST; 177 } 178 179 return any32(env, csrno); 180 } 181 182 static RISCVException smode(CPURISCVState *env, int csrno) 183 { 184 if (riscv_has_ext(env, RVS)) { 185 return RISCV_EXCP_NONE; 186 } 187 188 return RISCV_EXCP_ILLEGAL_INST; 189 } 190 191 static int smode32(CPURISCVState *env, int csrno) 192 { 193 if (riscv_cpu_mxl(env) != MXL_RV32) { 194 return RISCV_EXCP_ILLEGAL_INST; 195 } 196 197 return smode(env, csrno); 198 } 199 200 static int aia_smode(CPURISCVState *env, int csrno) 201 { 202 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 203 return RISCV_EXCP_ILLEGAL_INST; 204 } 205 206 return smode(env, csrno); 207 } 208 209 static int aia_smode32(CPURISCVState *env, int csrno) 210 { 211 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 212 return RISCV_EXCP_ILLEGAL_INST; 213 } 214 215 return smode32(env, csrno); 216 } 217 218 static RISCVException hmode(CPURISCVState *env, int csrno) 219 { 220 if (riscv_has_ext(env, RVS) && 221 riscv_has_ext(env, RVH)) { 222 /* Hypervisor extension is supported */ 223 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 224 env->priv == PRV_M) { 225 return RISCV_EXCP_NONE; 226 } else { 227 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 228 } 229 } 230 231 return RISCV_EXCP_ILLEGAL_INST; 232 } 233 234 static RISCVException hmode32(CPURISCVState *env, int csrno) 235 { 236 if (riscv_cpu_mxl(env) != MXL_RV32) { 237 if (!riscv_cpu_virt_enabled(env)) { 238 return RISCV_EXCP_ILLEGAL_INST; 239 } else { 240 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 241 } 242 } 243 244 return hmode(env, csrno); 245 246 } 247 248 /* Checks if PointerMasking registers could be accessed */ 249 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 250 { 251 /* Check if j-ext is present */ 252 if (riscv_has_ext(env, RVJ)) { 253 return RISCV_EXCP_NONE; 254 } 255 return RISCV_EXCP_ILLEGAL_INST; 256 } 257 258 static int aia_hmode(CPURISCVState *env, int csrno) 259 { 260 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 261 return RISCV_EXCP_ILLEGAL_INST; 262 } 263 264 return hmode(env, csrno); 265 } 266 267 static int aia_hmode32(CPURISCVState *env, int csrno) 268 { 269 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 270 return RISCV_EXCP_ILLEGAL_INST; 271 } 272 273 return hmode32(env, csrno); 274 } 275 276 static RISCVException pmp(CPURISCVState *env, int csrno) 277 { 278 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 279 return RISCV_EXCP_NONE; 280 } 281 282 return RISCV_EXCP_ILLEGAL_INST; 283 } 284 285 static RISCVException epmp(CPURISCVState *env, int csrno) 286 { 287 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 288 return RISCV_EXCP_NONE; 289 } 290 291 return RISCV_EXCP_ILLEGAL_INST; 292 } 293 #endif 294 295 /* User Floating-Point CSRs */ 296 static RISCVException read_fflags(CPURISCVState *env, int csrno, 297 target_ulong *val) 298 { 299 *val = riscv_cpu_get_fflags(env); 300 return RISCV_EXCP_NONE; 301 } 302 303 static RISCVException write_fflags(CPURISCVState *env, int csrno, 304 target_ulong val) 305 { 306 #if !defined(CONFIG_USER_ONLY) 307 if (riscv_has_ext(env, RVF)) { 308 env->mstatus |= MSTATUS_FS; 309 } 310 #endif 311 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 312 return RISCV_EXCP_NONE; 313 } 314 315 static RISCVException read_frm(CPURISCVState *env, int csrno, 316 target_ulong *val) 317 { 318 *val = env->frm; 319 return RISCV_EXCP_NONE; 320 } 321 322 static RISCVException write_frm(CPURISCVState *env, int csrno, 323 target_ulong val) 324 { 325 #if !defined(CONFIG_USER_ONLY) 326 if (riscv_has_ext(env, RVF)) { 327 env->mstatus |= MSTATUS_FS; 328 } 329 #endif 330 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 331 return RISCV_EXCP_NONE; 332 } 333 334 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 335 target_ulong *val) 336 { 337 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 338 | (env->frm << FSR_RD_SHIFT); 339 return RISCV_EXCP_NONE; 340 } 341 342 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 343 target_ulong val) 344 { 345 #if !defined(CONFIG_USER_ONLY) 346 if (riscv_has_ext(env, RVF)) { 347 env->mstatus |= MSTATUS_FS; 348 } 349 #endif 350 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 351 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 352 return RISCV_EXCP_NONE; 353 } 354 355 static RISCVException read_vtype(CPURISCVState *env, int csrno, 356 target_ulong *val) 357 { 358 uint64_t vill; 359 switch (env->xl) { 360 case MXL_RV32: 361 vill = (uint32_t)env->vill << 31; 362 break; 363 case MXL_RV64: 364 vill = (uint64_t)env->vill << 63; 365 break; 366 default: 367 g_assert_not_reached(); 368 } 369 *val = (target_ulong)vill | env->vtype; 370 return RISCV_EXCP_NONE; 371 } 372 373 static RISCVException read_vl(CPURISCVState *env, int csrno, 374 target_ulong *val) 375 { 376 *val = env->vl; 377 return RISCV_EXCP_NONE; 378 } 379 380 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 381 { 382 *val = env_archcpu(env)->cfg.vlen >> 3; 383 return RISCV_EXCP_NONE; 384 } 385 386 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 387 target_ulong *val) 388 { 389 *val = env->vxrm; 390 return RISCV_EXCP_NONE; 391 } 392 393 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 394 target_ulong val) 395 { 396 #if !defined(CONFIG_USER_ONLY) 397 env->mstatus |= MSTATUS_VS; 398 #endif 399 env->vxrm = val; 400 return RISCV_EXCP_NONE; 401 } 402 403 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 404 target_ulong *val) 405 { 406 *val = env->vxsat; 407 return RISCV_EXCP_NONE; 408 } 409 410 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 411 target_ulong val) 412 { 413 #if !defined(CONFIG_USER_ONLY) 414 env->mstatus |= MSTATUS_VS; 415 #endif 416 env->vxsat = val; 417 return RISCV_EXCP_NONE; 418 } 419 420 static RISCVException read_vstart(CPURISCVState *env, int csrno, 421 target_ulong *val) 422 { 423 *val = env->vstart; 424 return RISCV_EXCP_NONE; 425 } 426 427 static RISCVException write_vstart(CPURISCVState *env, int csrno, 428 target_ulong val) 429 { 430 #if !defined(CONFIG_USER_ONLY) 431 env->mstatus |= MSTATUS_VS; 432 #endif 433 /* 434 * The vstart CSR is defined to have only enough writable bits 435 * to hold the largest element index, i.e. lg2(VLEN) bits. 436 */ 437 env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); 438 return RISCV_EXCP_NONE; 439 } 440 441 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 442 { 443 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 444 return RISCV_EXCP_NONE; 445 } 446 447 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 448 { 449 #if !defined(CONFIG_USER_ONLY) 450 env->mstatus |= MSTATUS_VS; 451 #endif 452 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 453 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 454 return RISCV_EXCP_NONE; 455 } 456 457 /* User Timers and Counters */ 458 static RISCVException read_instret(CPURISCVState *env, int csrno, 459 target_ulong *val) 460 { 461 #if !defined(CONFIG_USER_ONLY) 462 if (icount_enabled()) { 463 *val = icount_get(); 464 } else { 465 *val = cpu_get_host_ticks(); 466 } 467 #else 468 *val = cpu_get_host_ticks(); 469 #endif 470 return RISCV_EXCP_NONE; 471 } 472 473 static RISCVException read_instreth(CPURISCVState *env, int csrno, 474 target_ulong *val) 475 { 476 #if !defined(CONFIG_USER_ONLY) 477 if (icount_enabled()) { 478 *val = icount_get() >> 32; 479 } else { 480 *val = cpu_get_host_ticks() >> 32; 481 } 482 #else 483 *val = cpu_get_host_ticks() >> 32; 484 #endif 485 return RISCV_EXCP_NONE; 486 } 487 488 #if defined(CONFIG_USER_ONLY) 489 static RISCVException read_time(CPURISCVState *env, int csrno, 490 target_ulong *val) 491 { 492 *val = cpu_get_host_ticks(); 493 return RISCV_EXCP_NONE; 494 } 495 496 static RISCVException read_timeh(CPURISCVState *env, int csrno, 497 target_ulong *val) 498 { 499 *val = cpu_get_host_ticks() >> 32; 500 return RISCV_EXCP_NONE; 501 } 502 503 #else /* CONFIG_USER_ONLY */ 504 505 static RISCVException read_time(CPURISCVState *env, int csrno, 506 target_ulong *val) 507 { 508 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 509 510 if (!env->rdtime_fn) { 511 return RISCV_EXCP_ILLEGAL_INST; 512 } 513 514 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 515 return RISCV_EXCP_NONE; 516 } 517 518 static RISCVException read_timeh(CPURISCVState *env, int csrno, 519 target_ulong *val) 520 { 521 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 522 523 if (!env->rdtime_fn) { 524 return RISCV_EXCP_ILLEGAL_INST; 525 } 526 527 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 528 return RISCV_EXCP_NONE; 529 } 530 531 /* Machine constants */ 532 533 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 534 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 535 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 536 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 537 538 #define VSTOPI_NUM_SRCS 5 539 540 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | 541 VS_MODE_INTERRUPTS; 542 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; 543 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 544 HS_MODE_INTERRUPTS; 545 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 546 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 547 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 548 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 549 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 550 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 551 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 552 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 553 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 554 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 555 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 556 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 557 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 558 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 559 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 560 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 561 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 562 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 563 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 564 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 565 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 566 (1ULL << (RISCV_EXCP_VS_ECALL)) | 567 (1ULL << (RISCV_EXCP_M_ECALL)) | 568 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 569 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 570 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 571 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 572 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 573 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 574 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 575 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 576 static const target_ulong hip_writable_mask = MIP_VSSIP; 577 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 578 static const target_ulong vsip_writable_mask = MIP_VSSIP; 579 580 static const char valid_vm_1_10_32[16] = { 581 [VM_1_10_MBARE] = 1, 582 [VM_1_10_SV32] = 1 583 }; 584 585 static const char valid_vm_1_10_64[16] = { 586 [VM_1_10_MBARE] = 1, 587 [VM_1_10_SV39] = 1, 588 [VM_1_10_SV48] = 1, 589 [VM_1_10_SV57] = 1 590 }; 591 592 /* Machine Information Registers */ 593 static RISCVException read_zero(CPURISCVState *env, int csrno, 594 target_ulong *val) 595 { 596 *val = 0; 597 return RISCV_EXCP_NONE; 598 } 599 600 static RISCVException write_ignore(CPURISCVState *env, int csrno, 601 target_ulong val) 602 { 603 return RISCV_EXCP_NONE; 604 } 605 606 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 607 target_ulong *val) 608 { 609 *val = env->mhartid; 610 return RISCV_EXCP_NONE; 611 } 612 613 /* Machine Trap Setup */ 614 615 /* We do not store SD explicitly, only compute it on demand. */ 616 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 617 { 618 if ((status & MSTATUS_FS) == MSTATUS_FS || 619 (status & MSTATUS_VS) == MSTATUS_VS || 620 (status & MSTATUS_XS) == MSTATUS_XS) { 621 switch (xl) { 622 case MXL_RV32: 623 return status | MSTATUS32_SD; 624 case MXL_RV64: 625 return status | MSTATUS64_SD; 626 case MXL_RV128: 627 return MSTATUSH128_SD; 628 default: 629 g_assert_not_reached(); 630 } 631 } 632 return status; 633 } 634 635 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 636 target_ulong *val) 637 { 638 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 639 return RISCV_EXCP_NONE; 640 } 641 642 static int validate_vm(CPURISCVState *env, target_ulong vm) 643 { 644 if (riscv_cpu_mxl(env) == MXL_RV32) { 645 return valid_vm_1_10_32[vm & 0xf]; 646 } else { 647 return valid_vm_1_10_64[vm & 0xf]; 648 } 649 } 650 651 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 652 target_ulong val) 653 { 654 uint64_t mstatus = env->mstatus; 655 uint64_t mask = 0; 656 RISCVMXL xl = riscv_cpu_mxl(env); 657 658 /* flush tlb on mstatus fields that affect VM */ 659 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 660 MSTATUS_MPRV | MSTATUS_SUM)) { 661 tlb_flush(env_cpu(env)); 662 } 663 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 664 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 665 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 666 MSTATUS_TW | MSTATUS_VS; 667 668 if (riscv_has_ext(env, RVF)) { 669 mask |= MSTATUS_FS; 670 } 671 672 if (xl != MXL_RV32 || env->debugger) { 673 /* 674 * RV32: MPV and GVA are not in mstatus. The current plan is to 675 * add them to mstatush. For now, we just don't support it. 676 */ 677 mask |= MSTATUS_MPV | MSTATUS_GVA; 678 if ((val & MSTATUS64_UXL) != 0) { 679 mask |= MSTATUS64_UXL; 680 } 681 } 682 683 mstatus = (mstatus & ~mask) | (val & mask); 684 685 if (xl > MXL_RV32) { 686 /* SXL field is for now read only */ 687 mstatus = set_field(mstatus, MSTATUS64_SXL, xl); 688 } 689 env->mstatus = mstatus; 690 env->xl = cpu_recompute_xl(env); 691 692 return RISCV_EXCP_NONE; 693 } 694 695 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 696 target_ulong *val) 697 { 698 *val = env->mstatus >> 32; 699 return RISCV_EXCP_NONE; 700 } 701 702 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 703 target_ulong val) 704 { 705 uint64_t valh = (uint64_t)val << 32; 706 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 707 708 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 709 tlb_flush(env_cpu(env)); 710 } 711 712 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 713 714 return RISCV_EXCP_NONE; 715 } 716 717 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 718 Int128 *val) 719 { 720 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); 721 return RISCV_EXCP_NONE; 722 } 723 724 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 725 Int128 *val) 726 { 727 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 728 return RISCV_EXCP_NONE; 729 } 730 731 static RISCVException read_misa(CPURISCVState *env, int csrno, 732 target_ulong *val) 733 { 734 target_ulong misa; 735 736 switch (env->misa_mxl) { 737 case MXL_RV32: 738 misa = (target_ulong)MXL_RV32 << 30; 739 break; 740 #ifdef TARGET_RISCV64 741 case MXL_RV64: 742 misa = (target_ulong)MXL_RV64 << 62; 743 break; 744 #endif 745 default: 746 g_assert_not_reached(); 747 } 748 749 *val = misa | env->misa_ext; 750 return RISCV_EXCP_NONE; 751 } 752 753 static RISCVException write_misa(CPURISCVState *env, int csrno, 754 target_ulong val) 755 { 756 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 757 /* drop write to misa */ 758 return RISCV_EXCP_NONE; 759 } 760 761 /* 'I' or 'E' must be present */ 762 if (!(val & (RVI | RVE))) { 763 /* It is not, drop write to misa */ 764 return RISCV_EXCP_NONE; 765 } 766 767 /* 'E' excludes all other extensions */ 768 if (val & RVE) { 769 /* when we support 'E' we can do "val = RVE;" however 770 * for now we just drop writes if 'E' is present. 771 */ 772 return RISCV_EXCP_NONE; 773 } 774 775 /* 776 * misa.MXL writes are not supported by QEMU. 777 * Drop writes to those bits. 778 */ 779 780 /* Mask extensions that are not supported by this hart */ 781 val &= env->misa_ext_mask; 782 783 /* Mask extensions that are not supported by QEMU */ 784 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 785 786 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 787 if ((val & RVD) && !(val & RVF)) { 788 val &= ~RVD; 789 } 790 791 /* Suppress 'C' if next instruction is not aligned 792 * TODO: this should check next_pc 793 */ 794 if ((val & RVC) && (GETPC() & ~3) != 0) { 795 val &= ~RVC; 796 } 797 798 /* If nothing changed, do nothing. */ 799 if (val == env->misa_ext) { 800 return RISCV_EXCP_NONE; 801 } 802 803 if (!(val & RVF)) { 804 env->mstatus &= ~MSTATUS_FS; 805 } 806 807 /* flush translation cache */ 808 tb_flush(env_cpu(env)); 809 env->misa_ext = val; 810 env->xl = riscv_cpu_mxl(env); 811 return RISCV_EXCP_NONE; 812 } 813 814 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 815 target_ulong *val) 816 { 817 *val = env->medeleg; 818 return RISCV_EXCP_NONE; 819 } 820 821 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 822 target_ulong val) 823 { 824 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 825 return RISCV_EXCP_NONE; 826 } 827 828 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 829 uint64_t *ret_val, 830 uint64_t new_val, uint64_t wr_mask) 831 { 832 uint64_t mask = wr_mask & delegable_ints; 833 834 if (ret_val) { 835 *ret_val = env->mideleg; 836 } 837 838 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 839 840 if (riscv_has_ext(env, RVH)) { 841 env->mideleg |= HS_MODE_INTERRUPTS; 842 } 843 844 return RISCV_EXCP_NONE; 845 } 846 847 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 848 target_ulong *ret_val, 849 target_ulong new_val, target_ulong wr_mask) 850 { 851 uint64_t rval; 852 RISCVException ret; 853 854 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 855 if (ret_val) { 856 *ret_val = rval; 857 } 858 859 return ret; 860 } 861 862 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 863 target_ulong *ret_val, 864 target_ulong new_val, 865 target_ulong wr_mask) 866 { 867 uint64_t rval; 868 RISCVException ret; 869 870 ret = rmw_mideleg64(env, csrno, &rval, 871 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 872 if (ret_val) { 873 *ret_val = rval >> 32; 874 } 875 876 return ret; 877 } 878 879 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 880 uint64_t *ret_val, 881 uint64_t new_val, uint64_t wr_mask) 882 { 883 uint64_t mask = wr_mask & all_ints; 884 885 if (ret_val) { 886 *ret_val = env->mie; 887 } 888 889 env->mie = (env->mie & ~mask) | (new_val & mask); 890 891 if (!riscv_has_ext(env, RVH)) { 892 env->mie &= ~((uint64_t)MIP_SGEIP); 893 } 894 895 return RISCV_EXCP_NONE; 896 } 897 898 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 899 target_ulong *ret_val, 900 target_ulong new_val, target_ulong wr_mask) 901 { 902 uint64_t rval; 903 RISCVException ret; 904 905 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 906 if (ret_val) { 907 *ret_val = rval; 908 } 909 910 return ret; 911 } 912 913 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 914 target_ulong *ret_val, 915 target_ulong new_val, target_ulong wr_mask) 916 { 917 uint64_t rval; 918 RISCVException ret; 919 920 ret = rmw_mie64(env, csrno, &rval, 921 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 922 if (ret_val) { 923 *ret_val = rval >> 32; 924 } 925 926 return ret; 927 } 928 929 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 930 { 931 int irq; 932 uint8_t iprio; 933 934 irq = riscv_cpu_mirq_pending(env); 935 if (irq <= 0 || irq > 63) { 936 *val = 0; 937 } else { 938 iprio = env->miprio[irq]; 939 if (!iprio) { 940 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 941 iprio = IPRIO_MMAXIPRIO; 942 } 943 } 944 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 945 *val |= iprio; 946 } 947 948 return RISCV_EXCP_NONE; 949 } 950 951 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 952 { 953 if (!riscv_cpu_virt_enabled(env)) { 954 return csrno; 955 } 956 957 switch (csrno) { 958 case CSR_SISELECT: 959 return CSR_VSISELECT; 960 case CSR_SIREG: 961 return CSR_VSIREG; 962 case CSR_SSETEIPNUM: 963 return CSR_VSSETEIPNUM; 964 case CSR_SCLREIPNUM: 965 return CSR_VSCLREIPNUM; 966 case CSR_SSETEIENUM: 967 return CSR_VSSETEIENUM; 968 case CSR_SCLREIENUM: 969 return CSR_VSCLREIENUM; 970 case CSR_STOPEI: 971 return CSR_VSTOPEI; 972 default: 973 return csrno; 974 }; 975 } 976 977 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 978 target_ulong new_val, target_ulong wr_mask) 979 { 980 target_ulong *iselect; 981 982 /* Translate CSR number for VS-mode */ 983 csrno = aia_xlate_vs_csrno(env, csrno); 984 985 /* Find the iselect CSR based on CSR number */ 986 switch (csrno) { 987 case CSR_MISELECT: 988 iselect = &env->miselect; 989 break; 990 case CSR_SISELECT: 991 iselect = &env->siselect; 992 break; 993 case CSR_VSISELECT: 994 iselect = &env->vsiselect; 995 break; 996 default: 997 return RISCV_EXCP_ILLEGAL_INST; 998 }; 999 1000 if (val) { 1001 *val = *iselect; 1002 } 1003 1004 wr_mask &= ISELECT_MASK; 1005 if (wr_mask) { 1006 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1007 } 1008 1009 return RISCV_EXCP_NONE; 1010 } 1011 1012 static int rmw_iprio(target_ulong xlen, 1013 target_ulong iselect, uint8_t *iprio, 1014 target_ulong *val, target_ulong new_val, 1015 target_ulong wr_mask, int ext_irq_no) 1016 { 1017 int i, firq, nirqs; 1018 target_ulong old_val; 1019 1020 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1021 return -EINVAL; 1022 } 1023 if (xlen != 32 && iselect & 0x1) { 1024 return -EINVAL; 1025 } 1026 1027 nirqs = 4 * (xlen / 32); 1028 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1029 1030 old_val = 0; 1031 for (i = 0; i < nirqs; i++) { 1032 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1033 } 1034 1035 if (val) { 1036 *val = old_val; 1037 } 1038 1039 if (wr_mask) { 1040 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1041 for (i = 0; i < nirqs; i++) { 1042 /* 1043 * M-level and S-level external IRQ priority always read-only 1044 * zero. This means default priority order is always preferred 1045 * for M-level and S-level external IRQs. 1046 */ 1047 if ((firq + i) == ext_irq_no) { 1048 continue; 1049 } 1050 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1051 } 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1058 target_ulong new_val, target_ulong wr_mask) 1059 { 1060 bool virt; 1061 uint8_t *iprio; 1062 int ret = -EINVAL; 1063 target_ulong priv, isel, vgein; 1064 1065 /* Translate CSR number for VS-mode */ 1066 csrno = aia_xlate_vs_csrno(env, csrno); 1067 1068 /* Decode register details from CSR number */ 1069 virt = false; 1070 switch (csrno) { 1071 case CSR_MIREG: 1072 iprio = env->miprio; 1073 isel = env->miselect; 1074 priv = PRV_M; 1075 break; 1076 case CSR_SIREG: 1077 iprio = env->siprio; 1078 isel = env->siselect; 1079 priv = PRV_S; 1080 break; 1081 case CSR_VSIREG: 1082 iprio = env->hviprio; 1083 isel = env->vsiselect; 1084 priv = PRV_S; 1085 virt = true; 1086 break; 1087 default: 1088 goto done; 1089 }; 1090 1091 /* Find the selected guest interrupt file */ 1092 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1093 1094 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1095 /* Local interrupt priority registers not available for VS-mode */ 1096 if (!virt) { 1097 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1098 isel, iprio, val, new_val, wr_mask, 1099 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1100 } 1101 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1102 /* IMSIC registers only available when machine implements it. */ 1103 if (env->aia_ireg_rmw_fn[priv]) { 1104 /* Selected guest interrupt file should not be zero */ 1105 if (virt && (!vgein || env->geilen < vgein)) { 1106 goto done; 1107 } 1108 /* Call machine specific IMSIC register emulation */ 1109 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1110 AIA_MAKE_IREG(isel, priv, virt, vgein, 1111 riscv_cpu_mxl_bits(env)), 1112 val, new_val, wr_mask); 1113 } 1114 } 1115 1116 done: 1117 if (ret) { 1118 return (riscv_cpu_virt_enabled(env) && virt) ? 1119 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1120 } 1121 return RISCV_EXCP_NONE; 1122 } 1123 1124 static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val, 1125 target_ulong new_val, target_ulong wr_mask) 1126 { 1127 int ret = -EINVAL; 1128 bool set, pend, virt; 1129 target_ulong priv, isel, vgein, xlen, nval, wmask; 1130 1131 /* Translate CSR number for VS-mode */ 1132 csrno = aia_xlate_vs_csrno(env, csrno); 1133 1134 /* Decode register details from CSR number */ 1135 virt = set = pend = false; 1136 switch (csrno) { 1137 case CSR_MSETEIPNUM: 1138 priv = PRV_M; 1139 set = true; 1140 pend = true; 1141 break; 1142 case CSR_MCLREIPNUM: 1143 priv = PRV_M; 1144 pend = true; 1145 break; 1146 case CSR_MSETEIENUM: 1147 priv = PRV_M; 1148 set = true; 1149 break; 1150 case CSR_MCLREIENUM: 1151 priv = PRV_M; 1152 break; 1153 case CSR_SSETEIPNUM: 1154 priv = PRV_S; 1155 set = true; 1156 pend = true; 1157 break; 1158 case CSR_SCLREIPNUM: 1159 priv = PRV_S; 1160 pend = true; 1161 break; 1162 case CSR_SSETEIENUM: 1163 priv = PRV_S; 1164 set = true; 1165 break; 1166 case CSR_SCLREIENUM: 1167 priv = PRV_S; 1168 break; 1169 case CSR_VSSETEIPNUM: 1170 priv = PRV_S; 1171 virt = true; 1172 set = true; 1173 pend = true; 1174 break; 1175 case CSR_VSCLREIPNUM: 1176 priv = PRV_S; 1177 virt = true; 1178 pend = true; 1179 break; 1180 case CSR_VSSETEIENUM: 1181 priv = PRV_S; 1182 virt = true; 1183 set = true; 1184 break; 1185 case CSR_VSCLREIENUM: 1186 priv = PRV_S; 1187 virt = true; 1188 break; 1189 default: 1190 goto done; 1191 }; 1192 1193 /* IMSIC CSRs only available when machine implements IMSIC. */ 1194 if (!env->aia_ireg_rmw_fn[priv]) { 1195 goto done; 1196 } 1197 1198 /* Find the selected guest interrupt file */ 1199 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1200 1201 /* Selected guest interrupt file should be valid */ 1202 if (virt && (!vgein || env->geilen < vgein)) { 1203 goto done; 1204 } 1205 1206 /* Set/Clear CSRs always read zero */ 1207 if (val) { 1208 *val = 0; 1209 } 1210 1211 if (wr_mask) { 1212 /* Get interrupt number */ 1213 new_val &= wr_mask; 1214 1215 /* Find target interrupt pending/enable register */ 1216 xlen = riscv_cpu_mxl_bits(env); 1217 isel = (new_val / xlen); 1218 isel *= (xlen / IMSIC_EIPx_BITS); 1219 isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; 1220 1221 /* Find the interrupt bit to be set/clear */ 1222 wmask = ((target_ulong)1) << (new_val % xlen); 1223 nval = (set) ? wmask : 0; 1224 1225 /* Call machine specific IMSIC register emulation */ 1226 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1227 AIA_MAKE_IREG(isel, priv, virt, 1228 vgein, xlen), 1229 NULL, nval, wmask); 1230 } else { 1231 ret = 0; 1232 } 1233 1234 done: 1235 if (ret) { 1236 return (riscv_cpu_virt_enabled(env) && virt) ? 1237 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1238 } 1239 return RISCV_EXCP_NONE; 1240 } 1241 1242 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1243 target_ulong new_val, target_ulong wr_mask) 1244 { 1245 bool virt; 1246 int ret = -EINVAL; 1247 target_ulong priv, vgein; 1248 1249 /* Translate CSR number for VS-mode */ 1250 csrno = aia_xlate_vs_csrno(env, csrno); 1251 1252 /* Decode register details from CSR number */ 1253 virt = false; 1254 switch (csrno) { 1255 case CSR_MTOPEI: 1256 priv = PRV_M; 1257 break; 1258 case CSR_STOPEI: 1259 priv = PRV_S; 1260 break; 1261 case CSR_VSTOPEI: 1262 priv = PRV_S; 1263 virt = true; 1264 break; 1265 default: 1266 goto done; 1267 }; 1268 1269 /* IMSIC CSRs only available when machine implements IMSIC. */ 1270 if (!env->aia_ireg_rmw_fn[priv]) { 1271 goto done; 1272 } 1273 1274 /* Find the selected guest interrupt file */ 1275 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1276 1277 /* Selected guest interrupt file should be valid */ 1278 if (virt && (!vgein || env->geilen < vgein)) { 1279 goto done; 1280 } 1281 1282 /* Call machine specific IMSIC register emulation for TOPEI */ 1283 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1284 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1285 riscv_cpu_mxl_bits(env)), 1286 val, new_val, wr_mask); 1287 1288 done: 1289 if (ret) { 1290 return (riscv_cpu_virt_enabled(env) && virt) ? 1291 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1292 } 1293 return RISCV_EXCP_NONE; 1294 } 1295 1296 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1297 target_ulong *val) 1298 { 1299 *val = env->mtvec; 1300 return RISCV_EXCP_NONE; 1301 } 1302 1303 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1304 target_ulong val) 1305 { 1306 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1307 if ((val & 3) < 2) { 1308 env->mtvec = val; 1309 } else { 1310 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1311 } 1312 return RISCV_EXCP_NONE; 1313 } 1314 1315 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1316 target_ulong *val) 1317 { 1318 *val = env->mcounteren; 1319 return RISCV_EXCP_NONE; 1320 } 1321 1322 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1323 target_ulong val) 1324 { 1325 env->mcounteren = val; 1326 return RISCV_EXCP_NONE; 1327 } 1328 1329 /* Machine Trap Handling */ 1330 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1331 Int128 *val) 1332 { 1333 *val = int128_make128(env->mscratch, env->mscratchh); 1334 return RISCV_EXCP_NONE; 1335 } 1336 1337 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1338 Int128 val) 1339 { 1340 env->mscratch = int128_getlo(val); 1341 env->mscratchh = int128_gethi(val); 1342 return RISCV_EXCP_NONE; 1343 } 1344 1345 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1346 target_ulong *val) 1347 { 1348 *val = env->mscratch; 1349 return RISCV_EXCP_NONE; 1350 } 1351 1352 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1353 target_ulong val) 1354 { 1355 env->mscratch = val; 1356 return RISCV_EXCP_NONE; 1357 } 1358 1359 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1360 target_ulong *val) 1361 { 1362 *val = env->mepc; 1363 return RISCV_EXCP_NONE; 1364 } 1365 1366 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1367 target_ulong val) 1368 { 1369 env->mepc = val; 1370 return RISCV_EXCP_NONE; 1371 } 1372 1373 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1374 target_ulong *val) 1375 { 1376 *val = env->mcause; 1377 return RISCV_EXCP_NONE; 1378 } 1379 1380 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1381 target_ulong val) 1382 { 1383 env->mcause = val; 1384 return RISCV_EXCP_NONE; 1385 } 1386 1387 static RISCVException read_mtval(CPURISCVState *env, int csrno, 1388 target_ulong *val) 1389 { 1390 *val = env->mtval; 1391 return RISCV_EXCP_NONE; 1392 } 1393 1394 static RISCVException write_mtval(CPURISCVState *env, int csrno, 1395 target_ulong val) 1396 { 1397 env->mtval = val; 1398 return RISCV_EXCP_NONE; 1399 } 1400 1401 /* Execution environment configuration setup */ 1402 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 1403 target_ulong *val) 1404 { 1405 *val = env->menvcfg; 1406 return RISCV_EXCP_NONE; 1407 } 1408 1409 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 1410 target_ulong val) 1411 { 1412 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 1413 1414 if (riscv_cpu_mxl(env) == MXL_RV64) { 1415 mask |= MENVCFG_PBMTE | MENVCFG_STCE; 1416 } 1417 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 1418 1419 return RISCV_EXCP_NONE; 1420 } 1421 1422 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 1423 target_ulong *val) 1424 { 1425 *val = env->menvcfg >> 32; 1426 return RISCV_EXCP_NONE; 1427 } 1428 1429 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 1430 target_ulong val) 1431 { 1432 uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; 1433 uint64_t valh = (uint64_t)val << 32; 1434 1435 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 1436 1437 return RISCV_EXCP_NONE; 1438 } 1439 1440 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 1441 target_ulong *val) 1442 { 1443 *val = env->senvcfg; 1444 return RISCV_EXCP_NONE; 1445 } 1446 1447 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 1448 target_ulong val) 1449 { 1450 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 1451 1452 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 1453 1454 return RISCV_EXCP_NONE; 1455 } 1456 1457 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 1458 target_ulong *val) 1459 { 1460 *val = env->henvcfg; 1461 return RISCV_EXCP_NONE; 1462 } 1463 1464 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 1465 target_ulong val) 1466 { 1467 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 1468 1469 if (riscv_cpu_mxl(env) == MXL_RV64) { 1470 mask |= HENVCFG_PBMTE | HENVCFG_STCE; 1471 } 1472 1473 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 1474 1475 return RISCV_EXCP_NONE; 1476 } 1477 1478 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 1479 target_ulong *val) 1480 { 1481 *val = env->henvcfg >> 32; 1482 return RISCV_EXCP_NONE; 1483 } 1484 1485 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 1486 target_ulong val) 1487 { 1488 uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; 1489 uint64_t valh = (uint64_t)val << 32; 1490 1491 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 1492 1493 return RISCV_EXCP_NONE; 1494 } 1495 1496 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 1497 uint64_t *ret_val, 1498 uint64_t new_val, uint64_t wr_mask) 1499 { 1500 RISCVCPU *cpu = env_archcpu(env); 1501 /* Allow software control of delegable interrupts not claimed by hardware */ 1502 uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim; 1503 uint32_t gin; 1504 1505 if (mask) { 1506 old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); 1507 } else { 1508 old_mip = env->mip; 1509 } 1510 1511 if (csrno != CSR_HVIP) { 1512 gin = get_field(env->hstatus, HSTATUS_VGEIN); 1513 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 1514 } 1515 1516 if (ret_val) { 1517 *ret_val = old_mip; 1518 } 1519 1520 return RISCV_EXCP_NONE; 1521 } 1522 1523 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 1524 target_ulong *ret_val, 1525 target_ulong new_val, target_ulong wr_mask) 1526 { 1527 uint64_t rval; 1528 RISCVException ret; 1529 1530 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 1531 if (ret_val) { 1532 *ret_val = rval; 1533 } 1534 1535 return ret; 1536 } 1537 1538 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 1539 target_ulong *ret_val, 1540 target_ulong new_val, target_ulong wr_mask) 1541 { 1542 uint64_t rval; 1543 RISCVException ret; 1544 1545 ret = rmw_mip64(env, csrno, &rval, 1546 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1547 if (ret_val) { 1548 *ret_val = rval >> 32; 1549 } 1550 1551 return ret; 1552 } 1553 1554 /* Supervisor Trap Setup */ 1555 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 1556 Int128 *val) 1557 { 1558 uint64_t mask = sstatus_v1_10_mask; 1559 uint64_t sstatus = env->mstatus & mask; 1560 if (env->xl != MXL_RV32 || env->debugger) { 1561 mask |= SSTATUS64_UXL; 1562 } 1563 1564 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 1565 return RISCV_EXCP_NONE; 1566 } 1567 1568 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 1569 target_ulong *val) 1570 { 1571 target_ulong mask = (sstatus_v1_10_mask); 1572 if (env->xl != MXL_RV32 || env->debugger) { 1573 mask |= SSTATUS64_UXL; 1574 } 1575 /* TODO: Use SXL not MXL. */ 1576 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 1577 return RISCV_EXCP_NONE; 1578 } 1579 1580 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 1581 target_ulong val) 1582 { 1583 target_ulong mask = (sstatus_v1_10_mask); 1584 1585 if (env->xl != MXL_RV32 || env->debugger) { 1586 if ((val & SSTATUS64_UXL) != 0) { 1587 mask |= SSTATUS64_UXL; 1588 } 1589 } 1590 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 1591 return write_mstatus(env, CSR_MSTATUS, newval); 1592 } 1593 1594 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 1595 uint64_t *ret_val, 1596 uint64_t new_val, uint64_t wr_mask) 1597 { 1598 RISCVException ret; 1599 uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; 1600 1601 /* Bring VS-level bits to correct position */ 1602 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1603 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1604 new_val |= vsbits << 1; 1605 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1606 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1607 wr_mask |= vsbits << 1; 1608 1609 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); 1610 if (ret_val) { 1611 rval &= mask; 1612 vsbits = rval & VS_MODE_INTERRUPTS; 1613 rval &= ~VS_MODE_INTERRUPTS; 1614 *ret_val = rval | (vsbits >> 1); 1615 } 1616 1617 return ret; 1618 } 1619 1620 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 1621 target_ulong *ret_val, 1622 target_ulong new_val, target_ulong wr_mask) 1623 { 1624 uint64_t rval; 1625 RISCVException ret; 1626 1627 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 1628 if (ret_val) { 1629 *ret_val = rval; 1630 } 1631 1632 return ret; 1633 } 1634 1635 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 1636 target_ulong *ret_val, 1637 target_ulong new_val, target_ulong wr_mask) 1638 { 1639 uint64_t rval; 1640 RISCVException ret; 1641 1642 ret = rmw_vsie64(env, csrno, &rval, 1643 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1644 if (ret_val) { 1645 *ret_val = rval >> 32; 1646 } 1647 1648 return ret; 1649 } 1650 1651 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 1652 uint64_t *ret_val, 1653 uint64_t new_val, uint64_t wr_mask) 1654 { 1655 RISCVException ret; 1656 uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; 1657 1658 if (riscv_cpu_virt_enabled(env)) { 1659 if (env->hvictl & HVICTL_VTI) { 1660 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1661 } 1662 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 1663 } else { 1664 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); 1665 } 1666 1667 if (ret_val) { 1668 *ret_val &= mask; 1669 } 1670 1671 return ret; 1672 } 1673 1674 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 1675 target_ulong *ret_val, 1676 target_ulong new_val, target_ulong wr_mask) 1677 { 1678 uint64_t rval; 1679 RISCVException ret; 1680 1681 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 1682 if (ret == RISCV_EXCP_NONE && ret_val) { 1683 *ret_val = rval; 1684 } 1685 1686 return ret; 1687 } 1688 1689 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 1690 target_ulong *ret_val, 1691 target_ulong new_val, target_ulong wr_mask) 1692 { 1693 uint64_t rval; 1694 RISCVException ret; 1695 1696 ret = rmw_sie64(env, csrno, &rval, 1697 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1698 if (ret_val) { 1699 *ret_val = rval >> 32; 1700 } 1701 1702 return ret; 1703 } 1704 1705 static RISCVException read_stvec(CPURISCVState *env, int csrno, 1706 target_ulong *val) 1707 { 1708 *val = env->stvec; 1709 return RISCV_EXCP_NONE; 1710 } 1711 1712 static RISCVException write_stvec(CPURISCVState *env, int csrno, 1713 target_ulong val) 1714 { 1715 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1716 if ((val & 3) < 2) { 1717 env->stvec = val; 1718 } else { 1719 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 1720 } 1721 return RISCV_EXCP_NONE; 1722 } 1723 1724 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 1725 target_ulong *val) 1726 { 1727 *val = env->scounteren; 1728 return RISCV_EXCP_NONE; 1729 } 1730 1731 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 1732 target_ulong val) 1733 { 1734 env->scounteren = val; 1735 return RISCV_EXCP_NONE; 1736 } 1737 1738 /* Supervisor Trap Handling */ 1739 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 1740 Int128 *val) 1741 { 1742 *val = int128_make128(env->sscratch, env->sscratchh); 1743 return RISCV_EXCP_NONE; 1744 } 1745 1746 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 1747 Int128 val) 1748 { 1749 env->sscratch = int128_getlo(val); 1750 env->sscratchh = int128_gethi(val); 1751 return RISCV_EXCP_NONE; 1752 } 1753 1754 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 1755 target_ulong *val) 1756 { 1757 *val = env->sscratch; 1758 return RISCV_EXCP_NONE; 1759 } 1760 1761 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 1762 target_ulong val) 1763 { 1764 env->sscratch = val; 1765 return RISCV_EXCP_NONE; 1766 } 1767 1768 static RISCVException read_sepc(CPURISCVState *env, int csrno, 1769 target_ulong *val) 1770 { 1771 *val = env->sepc; 1772 return RISCV_EXCP_NONE; 1773 } 1774 1775 static RISCVException write_sepc(CPURISCVState *env, int csrno, 1776 target_ulong val) 1777 { 1778 env->sepc = val; 1779 return RISCV_EXCP_NONE; 1780 } 1781 1782 static RISCVException read_scause(CPURISCVState *env, int csrno, 1783 target_ulong *val) 1784 { 1785 *val = env->scause; 1786 return RISCV_EXCP_NONE; 1787 } 1788 1789 static RISCVException write_scause(CPURISCVState *env, int csrno, 1790 target_ulong val) 1791 { 1792 env->scause = val; 1793 return RISCV_EXCP_NONE; 1794 } 1795 1796 static RISCVException read_stval(CPURISCVState *env, int csrno, 1797 target_ulong *val) 1798 { 1799 *val = env->stval; 1800 return RISCV_EXCP_NONE; 1801 } 1802 1803 static RISCVException write_stval(CPURISCVState *env, int csrno, 1804 target_ulong val) 1805 { 1806 env->stval = val; 1807 return RISCV_EXCP_NONE; 1808 } 1809 1810 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 1811 uint64_t *ret_val, 1812 uint64_t new_val, uint64_t wr_mask) 1813 { 1814 RISCVException ret; 1815 uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; 1816 1817 /* Bring VS-level bits to correct position */ 1818 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1819 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1820 new_val |= vsbits << 1; 1821 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1822 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1823 wr_mask |= vsbits << 1; 1824 1825 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); 1826 if (ret_val) { 1827 rval &= mask; 1828 vsbits = rval & VS_MODE_INTERRUPTS; 1829 rval &= ~VS_MODE_INTERRUPTS; 1830 *ret_val = rval | (vsbits >> 1); 1831 } 1832 1833 return ret; 1834 } 1835 1836 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 1837 target_ulong *ret_val, 1838 target_ulong new_val, target_ulong wr_mask) 1839 { 1840 uint64_t rval; 1841 RISCVException ret; 1842 1843 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 1844 if (ret_val) { 1845 *ret_val = rval; 1846 } 1847 1848 return ret; 1849 } 1850 1851 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 1852 target_ulong *ret_val, 1853 target_ulong new_val, target_ulong wr_mask) 1854 { 1855 uint64_t rval; 1856 RISCVException ret; 1857 1858 ret = rmw_vsip64(env, csrno, &rval, 1859 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1860 if (ret_val) { 1861 *ret_val = rval >> 32; 1862 } 1863 1864 return ret; 1865 } 1866 1867 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 1868 uint64_t *ret_val, 1869 uint64_t new_val, uint64_t wr_mask) 1870 { 1871 RISCVException ret; 1872 uint64_t mask = env->mideleg & sip_writable_mask; 1873 1874 if (riscv_cpu_virt_enabled(env)) { 1875 if (env->hvictl & HVICTL_VTI) { 1876 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1877 } 1878 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 1879 } else { 1880 ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); 1881 } 1882 1883 if (ret_val) { 1884 *ret_val &= env->mideleg & S_MODE_INTERRUPTS; 1885 } 1886 1887 return ret; 1888 } 1889 1890 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 1891 target_ulong *ret_val, 1892 target_ulong new_val, target_ulong wr_mask) 1893 { 1894 uint64_t rval; 1895 RISCVException ret; 1896 1897 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 1898 if (ret_val) { 1899 *ret_val = rval; 1900 } 1901 1902 return ret; 1903 } 1904 1905 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 1906 target_ulong *ret_val, 1907 target_ulong new_val, target_ulong wr_mask) 1908 { 1909 uint64_t rval; 1910 RISCVException ret; 1911 1912 ret = rmw_sip64(env, csrno, &rval, 1913 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1914 if (ret_val) { 1915 *ret_val = rval >> 32; 1916 } 1917 1918 return ret; 1919 } 1920 1921 /* Supervisor Protection and Translation */ 1922 static RISCVException read_satp(CPURISCVState *env, int csrno, 1923 target_ulong *val) 1924 { 1925 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1926 *val = 0; 1927 return RISCV_EXCP_NONE; 1928 } 1929 1930 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1931 return RISCV_EXCP_ILLEGAL_INST; 1932 } else { 1933 *val = env->satp; 1934 } 1935 1936 return RISCV_EXCP_NONE; 1937 } 1938 1939 static RISCVException write_satp(CPURISCVState *env, int csrno, 1940 target_ulong val) 1941 { 1942 target_ulong vm, mask; 1943 1944 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1945 return RISCV_EXCP_NONE; 1946 } 1947 1948 if (riscv_cpu_mxl(env) == MXL_RV32) { 1949 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1950 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1951 } else { 1952 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1953 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1954 } 1955 1956 if (vm && mask) { 1957 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1958 return RISCV_EXCP_ILLEGAL_INST; 1959 } else { 1960 /* 1961 * The ISA defines SATP.MODE=Bare as "no translation", but we still 1962 * pass these through QEMU's TLB emulation as it improves 1963 * performance. Flushing the TLB on SATP writes with paging 1964 * enabled avoids leaking those invalid cached mappings. 1965 */ 1966 tlb_flush(env_cpu(env)); 1967 env->satp = val; 1968 } 1969 } 1970 return RISCV_EXCP_NONE; 1971 } 1972 1973 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 1974 { 1975 int irq, ret; 1976 target_ulong topei; 1977 uint64_t vseip, vsgein; 1978 uint32_t iid, iprio, hviid, hviprio, gein; 1979 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 1980 1981 gein = get_field(env->hstatus, HSTATUS_VGEIN); 1982 hviid = get_field(env->hvictl, HVICTL_IID); 1983 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 1984 1985 if (gein) { 1986 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 1987 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 1988 if (gein <= env->geilen && vseip) { 1989 siid[scount] = IRQ_S_EXT; 1990 siprio[scount] = IPRIO_MMAXIPRIO + 1; 1991 if (env->aia_ireg_rmw_fn[PRV_S]) { 1992 /* 1993 * Call machine specific IMSIC register emulation for 1994 * reading TOPEI. 1995 */ 1996 ret = env->aia_ireg_rmw_fn[PRV_S]( 1997 env->aia_ireg_rmw_fn_arg[PRV_S], 1998 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 1999 riscv_cpu_mxl_bits(env)), 2000 &topei, 0, 0); 2001 if (!ret && topei) { 2002 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 2003 } 2004 } 2005 scount++; 2006 } 2007 } else { 2008 if (hviid == IRQ_S_EXT && hviprio) { 2009 siid[scount] = IRQ_S_EXT; 2010 siprio[scount] = hviprio; 2011 scount++; 2012 } 2013 } 2014 2015 if (env->hvictl & HVICTL_VTI) { 2016 if (hviid != IRQ_S_EXT) { 2017 siid[scount] = hviid; 2018 siprio[scount] = hviprio; 2019 scount++; 2020 } 2021 } else { 2022 irq = riscv_cpu_vsirq_pending(env); 2023 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 2024 siid[scount] = irq; 2025 siprio[scount] = env->hviprio[irq]; 2026 scount++; 2027 } 2028 } 2029 2030 iid = 0; 2031 iprio = UINT_MAX; 2032 for (s = 0; s < scount; s++) { 2033 if (siprio[s] < iprio) { 2034 iid = siid[s]; 2035 iprio = siprio[s]; 2036 } 2037 } 2038 2039 if (iid) { 2040 if (env->hvictl & HVICTL_IPRIOM) { 2041 if (iprio > IPRIO_MMAXIPRIO) { 2042 iprio = IPRIO_MMAXIPRIO; 2043 } 2044 if (!iprio) { 2045 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 2046 iprio = IPRIO_MMAXIPRIO; 2047 } 2048 } 2049 } else { 2050 iprio = 1; 2051 } 2052 } else { 2053 iprio = 0; 2054 } 2055 2056 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2057 *val |= iprio; 2058 return RISCV_EXCP_NONE; 2059 } 2060 2061 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 2062 { 2063 int irq; 2064 uint8_t iprio; 2065 2066 if (riscv_cpu_virt_enabled(env)) { 2067 return read_vstopi(env, CSR_VSTOPI, val); 2068 } 2069 2070 irq = riscv_cpu_sirq_pending(env); 2071 if (irq <= 0 || irq > 63) { 2072 *val = 0; 2073 } else { 2074 iprio = env->siprio[irq]; 2075 if (!iprio) { 2076 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 2077 iprio = IPRIO_MMAXIPRIO; 2078 } 2079 } 2080 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2081 *val |= iprio; 2082 } 2083 2084 return RISCV_EXCP_NONE; 2085 } 2086 2087 /* Hypervisor Extensions */ 2088 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 2089 target_ulong *val) 2090 { 2091 *val = env->hstatus; 2092 if (riscv_cpu_mxl(env) != MXL_RV32) { 2093 /* We only support 64-bit VSXL */ 2094 *val = set_field(*val, HSTATUS_VSXL, 2); 2095 } 2096 /* We only support little endian */ 2097 *val = set_field(*val, HSTATUS_VSBE, 0); 2098 return RISCV_EXCP_NONE; 2099 } 2100 2101 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 2102 target_ulong val) 2103 { 2104 env->hstatus = val; 2105 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 2106 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 2107 } 2108 if (get_field(val, HSTATUS_VSBE) != 0) { 2109 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 2110 } 2111 return RISCV_EXCP_NONE; 2112 } 2113 2114 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 2115 target_ulong *val) 2116 { 2117 *val = env->hedeleg; 2118 return RISCV_EXCP_NONE; 2119 } 2120 2121 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 2122 target_ulong val) 2123 { 2124 env->hedeleg = val & vs_delegable_excps; 2125 return RISCV_EXCP_NONE; 2126 } 2127 2128 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 2129 uint64_t *ret_val, 2130 uint64_t new_val, uint64_t wr_mask) 2131 { 2132 uint64_t mask = wr_mask & vs_delegable_ints; 2133 2134 if (ret_val) { 2135 *ret_val = env->hideleg & vs_delegable_ints; 2136 } 2137 2138 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 2139 return RISCV_EXCP_NONE; 2140 } 2141 2142 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 2143 target_ulong *ret_val, 2144 target_ulong new_val, target_ulong wr_mask) 2145 { 2146 uint64_t rval; 2147 RISCVException ret; 2148 2149 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 2150 if (ret_val) { 2151 *ret_val = rval; 2152 } 2153 2154 return ret; 2155 } 2156 2157 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 2158 target_ulong *ret_val, 2159 target_ulong new_val, target_ulong wr_mask) 2160 { 2161 uint64_t rval; 2162 RISCVException ret; 2163 2164 ret = rmw_hideleg64(env, csrno, &rval, 2165 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2166 if (ret_val) { 2167 *ret_val = rval >> 32; 2168 } 2169 2170 return ret; 2171 } 2172 2173 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2174 uint64_t *ret_val, 2175 uint64_t new_val, uint64_t wr_mask) 2176 { 2177 RISCVException ret; 2178 2179 ret = rmw_mip64(env, csrno, ret_val, new_val, 2180 wr_mask & hvip_writable_mask); 2181 if (ret_val) { 2182 *ret_val &= VS_MODE_INTERRUPTS; 2183 } 2184 2185 return ret; 2186 } 2187 2188 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 2189 target_ulong *ret_val, 2190 target_ulong new_val, target_ulong wr_mask) 2191 { 2192 uint64_t rval; 2193 RISCVException ret; 2194 2195 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 2196 if (ret_val) { 2197 *ret_val = rval; 2198 } 2199 2200 return ret; 2201 } 2202 2203 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 2204 target_ulong *ret_val, 2205 target_ulong new_val, target_ulong wr_mask) 2206 { 2207 uint64_t rval; 2208 RISCVException ret; 2209 2210 ret = rmw_hvip64(env, csrno, &rval, 2211 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2212 if (ret_val) { 2213 *ret_val = rval >> 32; 2214 } 2215 2216 return ret; 2217 } 2218 2219 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 2220 target_ulong *ret_value, 2221 target_ulong new_value, target_ulong write_mask) 2222 { 2223 int ret = rmw_mip(env, csrno, ret_value, new_value, 2224 write_mask & hip_writable_mask); 2225 2226 if (ret_value) { 2227 *ret_value &= HS_MODE_INTERRUPTS; 2228 } 2229 return ret; 2230 } 2231 2232 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 2233 target_ulong *ret_val, 2234 target_ulong new_val, target_ulong wr_mask) 2235 { 2236 uint64_t rval; 2237 RISCVException ret; 2238 2239 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 2240 if (ret_val) { 2241 *ret_val = rval & HS_MODE_INTERRUPTS; 2242 } 2243 2244 return ret; 2245 } 2246 2247 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 2248 target_ulong *val) 2249 { 2250 *val = env->hcounteren; 2251 return RISCV_EXCP_NONE; 2252 } 2253 2254 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 2255 target_ulong val) 2256 { 2257 env->hcounteren = val; 2258 return RISCV_EXCP_NONE; 2259 } 2260 2261 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 2262 target_ulong *val) 2263 { 2264 if (val) { 2265 *val = env->hgeie; 2266 } 2267 return RISCV_EXCP_NONE; 2268 } 2269 2270 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 2271 target_ulong val) 2272 { 2273 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 2274 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 2275 env->hgeie = val; 2276 /* Update mip.SGEIP bit */ 2277 riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, 2278 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 2279 return RISCV_EXCP_NONE; 2280 } 2281 2282 static RISCVException read_htval(CPURISCVState *env, int csrno, 2283 target_ulong *val) 2284 { 2285 *val = env->htval; 2286 return RISCV_EXCP_NONE; 2287 } 2288 2289 static RISCVException write_htval(CPURISCVState *env, int csrno, 2290 target_ulong val) 2291 { 2292 env->htval = val; 2293 return RISCV_EXCP_NONE; 2294 } 2295 2296 static RISCVException read_htinst(CPURISCVState *env, int csrno, 2297 target_ulong *val) 2298 { 2299 *val = env->htinst; 2300 return RISCV_EXCP_NONE; 2301 } 2302 2303 static RISCVException write_htinst(CPURISCVState *env, int csrno, 2304 target_ulong val) 2305 { 2306 return RISCV_EXCP_NONE; 2307 } 2308 2309 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 2310 target_ulong *val) 2311 { 2312 if (val) { 2313 *val = env->hgeip; 2314 } 2315 return RISCV_EXCP_NONE; 2316 } 2317 2318 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 2319 target_ulong *val) 2320 { 2321 *val = env->hgatp; 2322 return RISCV_EXCP_NONE; 2323 } 2324 2325 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 2326 target_ulong val) 2327 { 2328 env->hgatp = val; 2329 return RISCV_EXCP_NONE; 2330 } 2331 2332 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 2333 target_ulong *val) 2334 { 2335 if (!env->rdtime_fn) { 2336 return RISCV_EXCP_ILLEGAL_INST; 2337 } 2338 2339 *val = env->htimedelta; 2340 return RISCV_EXCP_NONE; 2341 } 2342 2343 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 2344 target_ulong val) 2345 { 2346 if (!env->rdtime_fn) { 2347 return RISCV_EXCP_ILLEGAL_INST; 2348 } 2349 2350 if (riscv_cpu_mxl(env) == MXL_RV32) { 2351 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 2352 } else { 2353 env->htimedelta = val; 2354 } 2355 return RISCV_EXCP_NONE; 2356 } 2357 2358 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 2359 target_ulong *val) 2360 { 2361 if (!env->rdtime_fn) { 2362 return RISCV_EXCP_ILLEGAL_INST; 2363 } 2364 2365 *val = env->htimedelta >> 32; 2366 return RISCV_EXCP_NONE; 2367 } 2368 2369 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 2370 target_ulong val) 2371 { 2372 if (!env->rdtime_fn) { 2373 return RISCV_EXCP_ILLEGAL_INST; 2374 } 2375 2376 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 2377 return RISCV_EXCP_NONE; 2378 } 2379 2380 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 2381 { 2382 *val = env->hvictl; 2383 return RISCV_EXCP_NONE; 2384 } 2385 2386 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 2387 { 2388 env->hvictl = val & HVICTL_VALID_MASK; 2389 return RISCV_EXCP_NONE; 2390 } 2391 2392 static int read_hvipriox(CPURISCVState *env, int first_index, 2393 uint8_t *iprio, target_ulong *val) 2394 { 2395 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2396 2397 /* First index has to be a multiple of number of irqs per register */ 2398 if (first_index % num_irqs) { 2399 return (riscv_cpu_virt_enabled(env)) ? 2400 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2401 } 2402 2403 /* Fill-up return value */ 2404 *val = 0; 2405 for (i = 0; i < num_irqs; i++) { 2406 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2407 continue; 2408 } 2409 if (rdzero) { 2410 continue; 2411 } 2412 *val |= ((target_ulong)iprio[irq]) << (i * 8); 2413 } 2414 2415 return RISCV_EXCP_NONE; 2416 } 2417 2418 static int write_hvipriox(CPURISCVState *env, int first_index, 2419 uint8_t *iprio, target_ulong val) 2420 { 2421 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2422 2423 /* First index has to be a multiple of number of irqs per register */ 2424 if (first_index % num_irqs) { 2425 return (riscv_cpu_virt_enabled(env)) ? 2426 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2427 } 2428 2429 /* Fill-up priority arrary */ 2430 for (i = 0; i < num_irqs; i++) { 2431 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2432 continue; 2433 } 2434 if (rdzero) { 2435 iprio[irq] = 0; 2436 } else { 2437 iprio[irq] = (val >> (i * 8)) & 0xff; 2438 } 2439 } 2440 2441 return RISCV_EXCP_NONE; 2442 } 2443 2444 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 2445 { 2446 return read_hvipriox(env, 0, env->hviprio, val); 2447 } 2448 2449 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 2450 { 2451 return write_hvipriox(env, 0, env->hviprio, val); 2452 } 2453 2454 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 2455 { 2456 return read_hvipriox(env, 4, env->hviprio, val); 2457 } 2458 2459 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 2460 { 2461 return write_hvipriox(env, 4, env->hviprio, val); 2462 } 2463 2464 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 2465 { 2466 return read_hvipriox(env, 8, env->hviprio, val); 2467 } 2468 2469 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 2470 { 2471 return write_hvipriox(env, 8, env->hviprio, val); 2472 } 2473 2474 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 2475 { 2476 return read_hvipriox(env, 12, env->hviprio, val); 2477 } 2478 2479 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 2480 { 2481 return write_hvipriox(env, 12, env->hviprio, val); 2482 } 2483 2484 /* Virtual CSR Registers */ 2485 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 2486 target_ulong *val) 2487 { 2488 *val = env->vsstatus; 2489 return RISCV_EXCP_NONE; 2490 } 2491 2492 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 2493 target_ulong val) 2494 { 2495 uint64_t mask = (target_ulong)-1; 2496 if ((val & VSSTATUS64_UXL) == 0) { 2497 mask &= ~VSSTATUS64_UXL; 2498 } 2499 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 2500 return RISCV_EXCP_NONE; 2501 } 2502 2503 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 2504 { 2505 *val = env->vstvec; 2506 return RISCV_EXCP_NONE; 2507 } 2508 2509 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 2510 target_ulong val) 2511 { 2512 env->vstvec = val; 2513 return RISCV_EXCP_NONE; 2514 } 2515 2516 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 2517 target_ulong *val) 2518 { 2519 *val = env->vsscratch; 2520 return RISCV_EXCP_NONE; 2521 } 2522 2523 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 2524 target_ulong val) 2525 { 2526 env->vsscratch = val; 2527 return RISCV_EXCP_NONE; 2528 } 2529 2530 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 2531 target_ulong *val) 2532 { 2533 *val = env->vsepc; 2534 return RISCV_EXCP_NONE; 2535 } 2536 2537 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 2538 target_ulong val) 2539 { 2540 env->vsepc = val; 2541 return RISCV_EXCP_NONE; 2542 } 2543 2544 static RISCVException read_vscause(CPURISCVState *env, int csrno, 2545 target_ulong *val) 2546 { 2547 *val = env->vscause; 2548 return RISCV_EXCP_NONE; 2549 } 2550 2551 static RISCVException write_vscause(CPURISCVState *env, int csrno, 2552 target_ulong val) 2553 { 2554 env->vscause = val; 2555 return RISCV_EXCP_NONE; 2556 } 2557 2558 static RISCVException read_vstval(CPURISCVState *env, int csrno, 2559 target_ulong *val) 2560 { 2561 *val = env->vstval; 2562 return RISCV_EXCP_NONE; 2563 } 2564 2565 static RISCVException write_vstval(CPURISCVState *env, int csrno, 2566 target_ulong val) 2567 { 2568 env->vstval = val; 2569 return RISCV_EXCP_NONE; 2570 } 2571 2572 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 2573 target_ulong *val) 2574 { 2575 *val = env->vsatp; 2576 return RISCV_EXCP_NONE; 2577 } 2578 2579 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 2580 target_ulong val) 2581 { 2582 env->vsatp = val; 2583 return RISCV_EXCP_NONE; 2584 } 2585 2586 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 2587 target_ulong *val) 2588 { 2589 *val = env->mtval2; 2590 return RISCV_EXCP_NONE; 2591 } 2592 2593 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 2594 target_ulong val) 2595 { 2596 env->mtval2 = val; 2597 return RISCV_EXCP_NONE; 2598 } 2599 2600 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 2601 target_ulong *val) 2602 { 2603 *val = env->mtinst; 2604 return RISCV_EXCP_NONE; 2605 } 2606 2607 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 2608 target_ulong val) 2609 { 2610 env->mtinst = val; 2611 return RISCV_EXCP_NONE; 2612 } 2613 2614 /* Physical Memory Protection */ 2615 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 2616 target_ulong *val) 2617 { 2618 *val = mseccfg_csr_read(env); 2619 return RISCV_EXCP_NONE; 2620 } 2621 2622 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 2623 target_ulong val) 2624 { 2625 mseccfg_csr_write(env, val); 2626 return RISCV_EXCP_NONE; 2627 } 2628 2629 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) 2630 { 2631 /* TODO: RV128 restriction check */ 2632 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 2633 return false; 2634 } 2635 return true; 2636 } 2637 2638 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 2639 target_ulong *val) 2640 { 2641 uint32_t reg_index = csrno - CSR_PMPCFG0; 2642 2643 if (!check_pmp_reg_index(env, reg_index)) { 2644 return RISCV_EXCP_ILLEGAL_INST; 2645 } 2646 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 2647 return RISCV_EXCP_NONE; 2648 } 2649 2650 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 2651 target_ulong val) 2652 { 2653 uint32_t reg_index = csrno - CSR_PMPCFG0; 2654 2655 if (!check_pmp_reg_index(env, reg_index)) { 2656 return RISCV_EXCP_ILLEGAL_INST; 2657 } 2658 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 2659 return RISCV_EXCP_NONE; 2660 } 2661 2662 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 2663 target_ulong *val) 2664 { 2665 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 2666 return RISCV_EXCP_NONE; 2667 } 2668 2669 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 2670 target_ulong val) 2671 { 2672 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 2673 return RISCV_EXCP_NONE; 2674 } 2675 2676 /* 2677 * Functions to access Pointer Masking feature registers 2678 * We have to check if current priv lvl could modify 2679 * csr in given mode 2680 */ 2681 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 2682 { 2683 int csr_priv = get_field(csrno, 0x300); 2684 int pm_current; 2685 2686 if (env->debugger) { 2687 return false; 2688 } 2689 /* 2690 * If priv lvls differ that means we're accessing csr from higher priv lvl, 2691 * so allow the access 2692 */ 2693 if (env->priv != csr_priv) { 2694 return false; 2695 } 2696 switch (env->priv) { 2697 case PRV_M: 2698 pm_current = get_field(env->mmte, M_PM_CURRENT); 2699 break; 2700 case PRV_S: 2701 pm_current = get_field(env->mmte, S_PM_CURRENT); 2702 break; 2703 case PRV_U: 2704 pm_current = get_field(env->mmte, U_PM_CURRENT); 2705 break; 2706 default: 2707 g_assert_not_reached(); 2708 } 2709 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 2710 return !pm_current; 2711 } 2712 2713 static RISCVException read_mmte(CPURISCVState *env, int csrno, 2714 target_ulong *val) 2715 { 2716 *val = env->mmte & MMTE_MASK; 2717 return RISCV_EXCP_NONE; 2718 } 2719 2720 static RISCVException write_mmte(CPURISCVState *env, int csrno, 2721 target_ulong val) 2722 { 2723 uint64_t mstatus; 2724 target_ulong wpri_val = val & MMTE_MASK; 2725 2726 if (val != wpri_val) { 2727 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2728 "MMTE: WPRI violation written 0x", val, 2729 "vs expected 0x", wpri_val); 2730 } 2731 /* for machine mode pm.current is hardwired to 1 */ 2732 wpri_val |= MMTE_M_PM_CURRENT; 2733 2734 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 2735 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 2736 env->mmte = wpri_val | PM_EXT_DIRTY; 2737 riscv_cpu_update_mask(env); 2738 2739 /* Set XS and SD bits, since PM CSRs are dirty */ 2740 mstatus = env->mstatus | MSTATUS_XS; 2741 write_mstatus(env, csrno, mstatus); 2742 return RISCV_EXCP_NONE; 2743 } 2744 2745 static RISCVException read_smte(CPURISCVState *env, int csrno, 2746 target_ulong *val) 2747 { 2748 *val = env->mmte & SMTE_MASK; 2749 return RISCV_EXCP_NONE; 2750 } 2751 2752 static RISCVException write_smte(CPURISCVState *env, int csrno, 2753 target_ulong val) 2754 { 2755 target_ulong wpri_val = val & SMTE_MASK; 2756 2757 if (val != wpri_val) { 2758 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2759 "SMTE: WPRI violation written 0x", val, 2760 "vs expected 0x", wpri_val); 2761 } 2762 2763 /* if pm.current==0 we can't modify current PM CSRs */ 2764 if (check_pm_current_disabled(env, csrno)) { 2765 return RISCV_EXCP_NONE; 2766 } 2767 2768 wpri_val |= (env->mmte & ~SMTE_MASK); 2769 write_mmte(env, csrno, wpri_val); 2770 return RISCV_EXCP_NONE; 2771 } 2772 2773 static RISCVException read_umte(CPURISCVState *env, int csrno, 2774 target_ulong *val) 2775 { 2776 *val = env->mmte & UMTE_MASK; 2777 return RISCV_EXCP_NONE; 2778 } 2779 2780 static RISCVException write_umte(CPURISCVState *env, int csrno, 2781 target_ulong val) 2782 { 2783 target_ulong wpri_val = val & UMTE_MASK; 2784 2785 if (val != wpri_val) { 2786 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2787 "UMTE: WPRI violation written 0x", val, 2788 "vs expected 0x", wpri_val); 2789 } 2790 2791 if (check_pm_current_disabled(env, csrno)) { 2792 return RISCV_EXCP_NONE; 2793 } 2794 2795 wpri_val |= (env->mmte & ~UMTE_MASK); 2796 write_mmte(env, csrno, wpri_val); 2797 return RISCV_EXCP_NONE; 2798 } 2799 2800 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 2801 target_ulong *val) 2802 { 2803 *val = env->mpmmask; 2804 return RISCV_EXCP_NONE; 2805 } 2806 2807 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 2808 target_ulong val) 2809 { 2810 uint64_t mstatus; 2811 2812 env->mpmmask = val; 2813 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 2814 env->cur_pmmask = val; 2815 } 2816 env->mmte |= PM_EXT_DIRTY; 2817 2818 /* Set XS and SD bits, since PM CSRs are dirty */ 2819 mstatus = env->mstatus | MSTATUS_XS; 2820 write_mstatus(env, csrno, mstatus); 2821 return RISCV_EXCP_NONE; 2822 } 2823 2824 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 2825 target_ulong *val) 2826 { 2827 *val = env->spmmask; 2828 return RISCV_EXCP_NONE; 2829 } 2830 2831 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 2832 target_ulong val) 2833 { 2834 uint64_t mstatus; 2835 2836 /* if pm.current==0 we can't modify current PM CSRs */ 2837 if (check_pm_current_disabled(env, csrno)) { 2838 return RISCV_EXCP_NONE; 2839 } 2840 env->spmmask = val; 2841 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 2842 env->cur_pmmask = val; 2843 } 2844 env->mmte |= PM_EXT_DIRTY; 2845 2846 /* Set XS and SD bits, since PM CSRs are dirty */ 2847 mstatus = env->mstatus | MSTATUS_XS; 2848 write_mstatus(env, csrno, mstatus); 2849 return RISCV_EXCP_NONE; 2850 } 2851 2852 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 2853 target_ulong *val) 2854 { 2855 *val = env->upmmask; 2856 return RISCV_EXCP_NONE; 2857 } 2858 2859 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 2860 target_ulong val) 2861 { 2862 uint64_t mstatus; 2863 2864 /* if pm.current==0 we can't modify current PM CSRs */ 2865 if (check_pm_current_disabled(env, csrno)) { 2866 return RISCV_EXCP_NONE; 2867 } 2868 env->upmmask = val; 2869 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 2870 env->cur_pmmask = val; 2871 } 2872 env->mmte |= PM_EXT_DIRTY; 2873 2874 /* Set XS and SD bits, since PM CSRs are dirty */ 2875 mstatus = env->mstatus | MSTATUS_XS; 2876 write_mstatus(env, csrno, mstatus); 2877 return RISCV_EXCP_NONE; 2878 } 2879 2880 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 2881 target_ulong *val) 2882 { 2883 *val = env->mpmbase; 2884 return RISCV_EXCP_NONE; 2885 } 2886 2887 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 2888 target_ulong val) 2889 { 2890 uint64_t mstatus; 2891 2892 env->mpmbase = val; 2893 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 2894 env->cur_pmbase = val; 2895 } 2896 env->mmte |= PM_EXT_DIRTY; 2897 2898 /* Set XS and SD bits, since PM CSRs are dirty */ 2899 mstatus = env->mstatus | MSTATUS_XS; 2900 write_mstatus(env, csrno, mstatus); 2901 return RISCV_EXCP_NONE; 2902 } 2903 2904 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 2905 target_ulong *val) 2906 { 2907 *val = env->spmbase; 2908 return RISCV_EXCP_NONE; 2909 } 2910 2911 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 2912 target_ulong val) 2913 { 2914 uint64_t mstatus; 2915 2916 /* if pm.current==0 we can't modify current PM CSRs */ 2917 if (check_pm_current_disabled(env, csrno)) { 2918 return RISCV_EXCP_NONE; 2919 } 2920 env->spmbase = val; 2921 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 2922 env->cur_pmbase = val; 2923 } 2924 env->mmte |= PM_EXT_DIRTY; 2925 2926 /* Set XS and SD bits, since PM CSRs are dirty */ 2927 mstatus = env->mstatus | MSTATUS_XS; 2928 write_mstatus(env, csrno, mstatus); 2929 return RISCV_EXCP_NONE; 2930 } 2931 2932 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 2933 target_ulong *val) 2934 { 2935 *val = env->upmbase; 2936 return RISCV_EXCP_NONE; 2937 } 2938 2939 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 2940 target_ulong val) 2941 { 2942 uint64_t mstatus; 2943 2944 /* if pm.current==0 we can't modify current PM CSRs */ 2945 if (check_pm_current_disabled(env, csrno)) { 2946 return RISCV_EXCP_NONE; 2947 } 2948 env->upmbase = val; 2949 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 2950 env->cur_pmbase = val; 2951 } 2952 env->mmte |= PM_EXT_DIRTY; 2953 2954 /* Set XS and SD bits, since PM CSRs are dirty */ 2955 mstatus = env->mstatus | MSTATUS_XS; 2956 write_mstatus(env, csrno, mstatus); 2957 return RISCV_EXCP_NONE; 2958 } 2959 2960 #endif 2961 2962 /* 2963 * riscv_csrrw - read and/or update control and status register 2964 * 2965 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 2966 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 2967 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 2968 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 2969 */ 2970 2971 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 2972 int csrno, 2973 bool write_mask, 2974 RISCVCPU *cpu) 2975 { 2976 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 2977 int read_only = get_field(csrno, 0xC00) == 3; 2978 #if !defined(CONFIG_USER_ONLY) 2979 int effective_priv = env->priv; 2980 2981 if (riscv_has_ext(env, RVH) && 2982 env->priv == PRV_S && 2983 !riscv_cpu_virt_enabled(env)) { 2984 /* 2985 * We are in S mode without virtualisation, therefore we are in HS Mode. 2986 * Add 1 to the effective privledge level to allow us to access the 2987 * Hypervisor CSRs. 2988 */ 2989 effective_priv++; 2990 } 2991 2992 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 2993 return RISCV_EXCP_ILLEGAL_INST; 2994 } 2995 #endif 2996 if (write_mask && read_only) { 2997 return RISCV_EXCP_ILLEGAL_INST; 2998 } 2999 3000 /* ensure the CSR extension is enabled. */ 3001 if (!cpu->cfg.ext_icsr) { 3002 return RISCV_EXCP_ILLEGAL_INST; 3003 } 3004 3005 /* check predicate */ 3006 if (!csr_ops[csrno].predicate) { 3007 return RISCV_EXCP_ILLEGAL_INST; 3008 } 3009 3010 return csr_ops[csrno].predicate(env, csrno); 3011 } 3012 3013 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 3014 target_ulong *ret_value, 3015 target_ulong new_value, 3016 target_ulong write_mask) 3017 { 3018 RISCVException ret; 3019 target_ulong old_value; 3020 3021 /* execute combined read/write operation if it exists */ 3022 if (csr_ops[csrno].op) { 3023 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 3024 } 3025 3026 /* if no accessor exists then return failure */ 3027 if (!csr_ops[csrno].read) { 3028 return RISCV_EXCP_ILLEGAL_INST; 3029 } 3030 /* read old value */ 3031 ret = csr_ops[csrno].read(env, csrno, &old_value); 3032 if (ret != RISCV_EXCP_NONE) { 3033 return ret; 3034 } 3035 3036 /* write value if writable and write mask set, otherwise drop writes */ 3037 if (write_mask) { 3038 new_value = (old_value & ~write_mask) | (new_value & write_mask); 3039 if (csr_ops[csrno].write) { 3040 ret = csr_ops[csrno].write(env, csrno, new_value); 3041 if (ret != RISCV_EXCP_NONE) { 3042 return ret; 3043 } 3044 } 3045 } 3046 3047 /* return old value */ 3048 if (ret_value) { 3049 *ret_value = old_value; 3050 } 3051 3052 return RISCV_EXCP_NONE; 3053 } 3054 3055 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 3056 target_ulong *ret_value, 3057 target_ulong new_value, target_ulong write_mask) 3058 { 3059 RISCVCPU *cpu = env_archcpu(env); 3060 3061 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); 3062 if (ret != RISCV_EXCP_NONE) { 3063 return ret; 3064 } 3065 3066 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 3067 } 3068 3069 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 3070 Int128 *ret_value, 3071 Int128 new_value, 3072 Int128 write_mask) 3073 { 3074 RISCVException ret; 3075 Int128 old_value; 3076 3077 /* read old value */ 3078 ret = csr_ops[csrno].read128(env, csrno, &old_value); 3079 if (ret != RISCV_EXCP_NONE) { 3080 return ret; 3081 } 3082 3083 /* write value if writable and write mask set, otherwise drop writes */ 3084 if (int128_nz(write_mask)) { 3085 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 3086 int128_and(new_value, write_mask)); 3087 if (csr_ops[csrno].write128) { 3088 ret = csr_ops[csrno].write128(env, csrno, new_value); 3089 if (ret != RISCV_EXCP_NONE) { 3090 return ret; 3091 } 3092 } else if (csr_ops[csrno].write) { 3093 /* avoids having to write wrappers for all registers */ 3094 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 3095 if (ret != RISCV_EXCP_NONE) { 3096 return ret; 3097 } 3098 } 3099 } 3100 3101 /* return old value */ 3102 if (ret_value) { 3103 *ret_value = old_value; 3104 } 3105 3106 return RISCV_EXCP_NONE; 3107 } 3108 3109 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 3110 Int128 *ret_value, 3111 Int128 new_value, Int128 write_mask) 3112 { 3113 RISCVException ret; 3114 RISCVCPU *cpu = env_archcpu(env); 3115 3116 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); 3117 if (ret != RISCV_EXCP_NONE) { 3118 return ret; 3119 } 3120 3121 if (csr_ops[csrno].read128) { 3122 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 3123 } 3124 3125 /* 3126 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 3127 * at all defined. 3128 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 3129 * significant), for those, this fallback is correctly handling the accesses 3130 */ 3131 target_ulong old_value; 3132 ret = riscv_csrrw_do64(env, csrno, &old_value, 3133 int128_getlo(new_value), 3134 int128_getlo(write_mask)); 3135 if (ret == RISCV_EXCP_NONE && ret_value) { 3136 *ret_value = int128_make64(old_value); 3137 } 3138 return ret; 3139 } 3140 3141 /* 3142 * Debugger support. If not in user mode, set env->debugger before the 3143 * riscv_csrrw call and clear it after the call. 3144 */ 3145 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 3146 target_ulong *ret_value, 3147 target_ulong new_value, 3148 target_ulong write_mask) 3149 { 3150 RISCVException ret; 3151 #if !defined(CONFIG_USER_ONLY) 3152 env->debugger = true; 3153 #endif 3154 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 3155 #if !defined(CONFIG_USER_ONLY) 3156 env->debugger = false; 3157 #endif 3158 return ret; 3159 } 3160 3161 /* Control and Status Register function table */ 3162 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 3163 /* User Floating-Point CSRs */ 3164 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 3165 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 3166 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 3167 /* Vector CSRs */ 3168 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, 3169 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3170 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, 3171 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3172 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, 3173 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3174 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, 3175 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3176 [CSR_VL] = { "vl", vs, read_vl, 3177 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3178 [CSR_VTYPE] = { "vtype", vs, read_vtype, 3179 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3180 [CSR_VLENB] = { "vlenb", vs, read_vlenb, 3181 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3182 /* User Timers and Counters */ 3183 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 3184 [CSR_INSTRET] = { "instret", ctr, read_instret }, 3185 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 3186 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 3187 3188 /* 3189 * In privileged mode, the monitor will have to emulate TIME CSRs only if 3190 * rdtime callback is not provided by machine/platform emulation. 3191 */ 3192 [CSR_TIME] = { "time", ctr, read_time }, 3193 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 3194 3195 #if !defined(CONFIG_USER_ONLY) 3196 /* Machine Timers and Counters */ 3197 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 3198 [CSR_MINSTRET] = { "minstret", any, read_instret }, 3199 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 3200 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 3201 3202 /* Machine Information Registers */ 3203 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 3204 [CSR_MARCHID] = { "marchid", any, read_zero }, 3205 [CSR_MIMPID] = { "mimpid", any, read_zero }, 3206 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 3207 3208 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 3209 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3210 /* Machine Trap Setup */ 3211 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, 3212 read_mstatus_i128 }, 3213 [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, 3214 read_misa_i128 }, 3215 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 3216 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 3217 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 3218 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 3219 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 3220 3221 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 3222 3223 /* Machine Trap Handling */ 3224 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, 3225 read_mscratch_i128, write_mscratch_i128 }, 3226 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 3227 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 3228 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 3229 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 3230 3231 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 3232 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 3233 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 3234 3235 /* Machine-Level Interrupts (AIA) */ 3236 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 3237 3238 /* Machine-Level IMSIC Interface (AIA) */ 3239 [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3240 [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3241 [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3242 [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3243 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 3244 3245 /* Virtual Interrupts for Supervisor Level (AIA) */ 3246 [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, 3247 [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, 3248 3249 /* Machine-Level High-Half CSRs (AIA) */ 3250 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 3251 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 3252 [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, 3253 [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, 3254 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 3255 3256 /* Execution environment configuration */ 3257 [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, 3258 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3259 [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, 3260 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3261 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 3262 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3263 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 3264 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3265 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 3266 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3267 3268 /* Supervisor Trap Setup */ 3269 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, 3270 read_sstatus_i128 }, 3271 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 3272 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 3273 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 3274 3275 /* Supervisor Trap Handling */ 3276 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, 3277 read_sscratch_i128, write_sscratch_i128 }, 3278 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 3279 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 3280 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 3281 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 3282 3283 /* Supervisor Protection and Translation */ 3284 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 3285 3286 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 3287 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 3288 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 3289 3290 /* Supervisor-Level Interrupts (AIA) */ 3291 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 3292 3293 /* Supervisor-Level IMSIC Interface (AIA) */ 3294 [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3295 [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3296 [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3297 [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3298 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 3299 3300 /* Supervisor-Level High-Half CSRs (AIA) */ 3301 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 3302 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 3303 3304 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 3305 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3306 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 3307 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3308 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 3309 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3310 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 3311 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3312 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 3313 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3314 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 3315 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3316 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, 3317 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3318 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 3319 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3320 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 3321 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3322 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 3323 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3324 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 3325 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3326 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, 3327 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3328 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, 3329 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3330 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, 3331 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3332 3333 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, 3334 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3335 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 3336 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3337 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 3338 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3339 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 3340 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3341 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, 3342 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3343 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 3344 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3345 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 3346 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3347 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 3348 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3349 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 3350 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3351 3352 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 3353 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3354 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 3355 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3356 3357 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 3358 [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, 3359 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, 3360 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, 3361 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, 3362 3363 /* 3364 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 3365 */ 3366 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, 3367 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 3368 3369 /* VS-Level Interrupts (H-extension with AIA) */ 3370 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 3371 3372 /* VS-Level IMSIC Interface (H-extension with AIA) */ 3373 [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3374 [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3375 [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3376 [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3377 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 3378 3379 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 3380 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, 3381 [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, 3382 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 3383 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, 3384 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, 3385 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 3386 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 3387 3388 /* Physical Memory Protection */ 3389 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 3390 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3391 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 3392 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 3393 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 3394 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 3395 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 3396 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 3397 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 3398 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 3399 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 3400 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 3401 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 3402 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 3403 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 3404 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 3405 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 3406 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 3407 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 3408 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 3409 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 3410 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 3411 3412 /* User Pointer Masking */ 3413 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 3414 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 3415 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 3416 /* Machine Pointer Masking */ 3417 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 3418 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 3419 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 3420 /* Supervisor Pointer Masking */ 3421 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 3422 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 3423 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 3424 3425 /* Performance Counters */ 3426 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 3427 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 3428 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 3429 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 3430 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 3431 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 3432 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 3433 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 3434 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 3435 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 3436 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 3437 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 3438 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 3439 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 3440 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 3441 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 3442 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 3443 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 3444 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 3445 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 3446 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 3447 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 3448 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 3449 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 3450 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 3451 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 3452 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 3453 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 3454 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 3455 3456 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 3457 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 3458 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 3459 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 3460 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 3461 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 3462 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 3463 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 3464 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 3465 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 3466 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 3467 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 3468 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 3469 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 3470 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 3471 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 3472 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 3473 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 3474 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 3475 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 3476 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 3477 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 3478 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 3479 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 3480 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 3481 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 3482 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 3483 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 3484 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 3485 3486 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 3487 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 3488 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 3489 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 3490 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 3491 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 3492 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 3493 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 3494 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 3495 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 3496 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 3497 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 3498 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 3499 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 3500 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 3501 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 3502 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 3503 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 3504 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 3505 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 3506 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 3507 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 3508 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 3509 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 3510 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 3511 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 3512 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 3513 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 3514 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 3515 3516 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 3517 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 3518 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 3519 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 3520 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 3521 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 3522 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 3523 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 3524 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 3525 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 3526 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 3527 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 3528 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 3529 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 3530 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 3531 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 3532 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 3533 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 3534 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 3535 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 3536 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 3537 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 3538 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 3539 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 3540 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 3541 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 3542 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 3543 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 3544 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 3545 3546 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 3547 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 3548 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 3549 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 3550 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 3551 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 3552 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 3553 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 3554 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 3555 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 3556 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 3557 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 3558 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 3559 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 3560 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 3561 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 3562 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 3563 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 3564 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 3565 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 3566 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 3567 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 3568 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 3569 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 3570 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 3571 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 3572 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 3573 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 3574 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 3575 #endif /* !CONFIG_USER_ONLY */ 3576 }; 3577