1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 50 return -1; 51 } 52 #endif 53 return 0; 54 } 55 56 static int ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 uint32_t ctr_en = ~0u; 60 61 if (env->priv < PRV_M) { 62 ctr_en &= env->mcounteren; 63 } 64 if (env->priv < PRV_S) { 65 ctr_en &= env->scounteren; 66 } 67 if (!(ctr_en & (1u << (csrno & 31)))) { 68 return -1; 69 } 70 #endif 71 return 0; 72 } 73 74 #if !defined(CONFIG_USER_ONLY) 75 static int any(CPURISCVState *env, int csrno) 76 { 77 return 0; 78 } 79 80 static int smode(CPURISCVState *env, int csrno) 81 { 82 return -!riscv_has_ext(env, RVS); 83 } 84 85 static int pmp(CPURISCVState *env, int csrno) 86 { 87 return -!riscv_feature(env, RISCV_FEATURE_PMP); 88 } 89 #endif 90 91 /* User Floating-Point CSRs */ 92 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 93 { 94 #if !defined(CONFIG_USER_ONLY) 95 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 96 return -1; 97 } 98 #endif 99 *val = riscv_cpu_get_fflags(env); 100 return 0; 101 } 102 103 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 104 { 105 #if !defined(CONFIG_USER_ONLY) 106 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 107 return -1; 108 } 109 env->mstatus |= MSTATUS_FS; 110 #endif 111 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 112 return 0; 113 } 114 115 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 116 { 117 #if !defined(CONFIG_USER_ONLY) 118 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 119 return -1; 120 } 121 #endif 122 *val = env->frm; 123 return 0; 124 } 125 126 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 127 { 128 #if !defined(CONFIG_USER_ONLY) 129 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 130 return -1; 131 } 132 env->mstatus |= MSTATUS_FS; 133 #endif 134 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 135 return 0; 136 } 137 138 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 139 { 140 #if !defined(CONFIG_USER_ONLY) 141 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 142 return -1; 143 } 144 #endif 145 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 146 | (env->frm << FSR_RD_SHIFT); 147 return 0; 148 } 149 150 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 151 { 152 #if !defined(CONFIG_USER_ONLY) 153 if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { 154 return -1; 155 } 156 env->mstatus |= MSTATUS_FS; 157 #endif 158 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 159 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 160 return 0; 161 } 162 163 /* User Timers and Counters */ 164 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 165 { 166 #if !defined(CONFIG_USER_ONLY) 167 if (use_icount) { 168 *val = cpu_get_icount(); 169 } else { 170 *val = cpu_get_host_ticks(); 171 } 172 #else 173 *val = cpu_get_host_ticks(); 174 #endif 175 return 0; 176 } 177 178 #if defined(TARGET_RISCV32) 179 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 180 { 181 #if !defined(CONFIG_USER_ONLY) 182 if (use_icount) { 183 *val = cpu_get_icount() >> 32; 184 } else { 185 *val = cpu_get_host_ticks() >> 32; 186 } 187 #else 188 *val = cpu_get_host_ticks() >> 32; 189 #endif 190 return 0; 191 } 192 #endif /* TARGET_RISCV32 */ 193 194 #if defined(CONFIG_USER_ONLY) 195 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 196 { 197 *val = cpu_get_host_ticks(); 198 return 0; 199 } 200 201 #if defined(TARGET_RISCV32) 202 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 203 { 204 *val = cpu_get_host_ticks() >> 32; 205 return 0; 206 } 207 #endif 208 209 #else /* CONFIG_USER_ONLY */ 210 211 /* Machine constants */ 212 213 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 214 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 215 216 static const target_ulong delegable_ints = S_MODE_INTERRUPTS; 217 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; 218 static const target_ulong delegable_excps = 219 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 220 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 221 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 222 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 223 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 224 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 225 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 226 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 227 (1ULL << (RISCV_EXCP_U_ECALL)) | 228 (1ULL << (RISCV_EXCP_S_ECALL)) | 229 (1ULL << (RISCV_EXCP_H_ECALL)) | 230 (1ULL << (RISCV_EXCP_M_ECALL)) | 231 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 232 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 233 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); 234 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 235 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 236 SSTATUS_SUM | SSTATUS_SD; 237 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 238 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 239 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 240 241 #if defined(TARGET_RISCV32) 242 static const char valid_vm_1_09[16] = { 243 [VM_1_09_MBARE] = 1, 244 [VM_1_09_SV32] = 1, 245 }; 246 static const char valid_vm_1_10[16] = { 247 [VM_1_10_MBARE] = 1, 248 [VM_1_10_SV32] = 1 249 }; 250 #elif defined(TARGET_RISCV64) 251 static const char valid_vm_1_09[16] = { 252 [VM_1_09_MBARE] = 1, 253 [VM_1_09_SV39] = 1, 254 [VM_1_09_SV48] = 1, 255 }; 256 static const char valid_vm_1_10[16] = { 257 [VM_1_10_MBARE] = 1, 258 [VM_1_10_SV39] = 1, 259 [VM_1_10_SV48] = 1, 260 [VM_1_10_SV57] = 1 261 }; 262 #endif /* CONFIG_USER_ONLY */ 263 264 /* Machine Information Registers */ 265 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 266 { 267 return *val = 0; 268 } 269 270 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 271 { 272 *val = env->mhartid; 273 return 0; 274 } 275 276 /* Machine Trap Setup */ 277 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 278 { 279 *val = env->mstatus; 280 return 0; 281 } 282 283 static int validate_vm(CPURISCVState *env, target_ulong vm) 284 { 285 return (env->priv_ver >= PRIV_VERSION_1_10_0) ? 286 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; 287 } 288 289 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 290 { 291 target_ulong mstatus = env->mstatus; 292 target_ulong mask = 0; 293 294 /* flush tlb on mstatus fields that affect VM */ 295 if (env->priv_ver <= PRIV_VERSION_1_09_1) { 296 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 297 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { 298 tlb_flush(CPU(riscv_env_get_cpu(env))); 299 } 300 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 301 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 302 MSTATUS_MPP | MSTATUS_MXR | 303 (validate_vm(env, get_field(val, MSTATUS_VM)) ? 304 MSTATUS_VM : 0); 305 } 306 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 307 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 308 MSTATUS_MPRV | MSTATUS_SUM)) { 309 tlb_flush(CPU(riscv_env_get_cpu(env))); 310 } 311 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 312 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 313 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 314 MSTATUS_TW; 315 #if defined(TARGET_RISCV64) 316 /* 317 * RV32: MPV and MTL are not in mstatus. The current plan is to 318 * add them to mstatush. For now, we just don't support it. 319 */ 320 mask |= MSTATUS_MPP | MSTATUS_MPV; 321 #endif 322 } 323 324 mstatus = (mstatus & ~mask) | (val & mask); 325 326 int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 327 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 328 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 329 env->mstatus = mstatus; 330 331 return 0; 332 } 333 334 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 335 { 336 *val = env->misa; 337 return 0; 338 } 339 340 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 341 { 342 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 343 /* drop write to misa */ 344 return 0; 345 } 346 347 /* 'I' or 'E' must be present */ 348 if (!(val & (RVI | RVE))) { 349 /* It is not, drop write to misa */ 350 return 0; 351 } 352 353 /* 'E' excludes all other extensions */ 354 if (val & RVE) { 355 /* when we support 'E' we can do "val = RVE;" however 356 * for now we just drop writes if 'E' is present. 357 */ 358 return 0; 359 } 360 361 /* Mask extensions that are not supported by this hart */ 362 val &= env->misa_mask; 363 364 /* Mask extensions that are not supported by QEMU */ 365 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 366 367 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 368 if ((val & RVD) && !(val & RVF)) { 369 val &= ~RVD; 370 } 371 372 /* Suppress 'C' if next instruction is not aligned 373 * TODO: this should check next_pc 374 */ 375 if ((val & RVC) && (GETPC() & ~3) != 0) { 376 val &= ~RVC; 377 } 378 379 /* misa.MXL writes are not supported by QEMU */ 380 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 381 382 /* flush translation cache */ 383 if (val != env->misa) { 384 tb_flush(CPU(riscv_env_get_cpu(env))); 385 } 386 387 env->misa = val; 388 389 return 0; 390 } 391 392 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 393 { 394 *val = env->medeleg; 395 return 0; 396 } 397 398 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 399 { 400 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 401 return 0; 402 } 403 404 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 405 { 406 *val = env->mideleg; 407 return 0; 408 } 409 410 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 411 { 412 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 413 return 0; 414 } 415 416 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 417 { 418 *val = env->mie; 419 return 0; 420 } 421 422 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 423 { 424 env->mie = (env->mie & ~all_ints) | (val & all_ints); 425 return 0; 426 } 427 428 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 429 { 430 *val = env->mtvec; 431 return 0; 432 } 433 434 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 435 { 436 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 437 if ((val & 3) < 2) { 438 env->mtvec = val; 439 } else { 440 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 441 } 442 return 0; 443 } 444 445 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 446 { 447 if (env->priv_ver < PRIV_VERSION_1_10_0) { 448 return -1; 449 } 450 *val = env->mcounteren; 451 return 0; 452 } 453 454 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 455 { 456 if (env->priv_ver < PRIV_VERSION_1_10_0) { 457 return -1; 458 } 459 env->mcounteren = val; 460 return 0; 461 } 462 463 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 464 { 465 if (env->priv_ver > PRIV_VERSION_1_09_1) { 466 return -1; 467 } 468 *val = env->mcounteren; 469 return 0; 470 } 471 472 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 473 { 474 if (env->priv_ver > PRIV_VERSION_1_09_1) { 475 return -1; 476 } 477 env->mcounteren = val; 478 return 0; 479 } 480 481 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) 482 { 483 if (env->priv_ver > PRIV_VERSION_1_09_1) { 484 return -1; 485 } 486 *val = env->scounteren; 487 return 0; 488 } 489 490 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) 491 { 492 if (env->priv_ver > PRIV_VERSION_1_09_1) { 493 return -1; 494 } 495 env->scounteren = val; 496 return 0; 497 } 498 499 /* Machine Trap Handling */ 500 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 501 { 502 *val = env->mscratch; 503 return 0; 504 } 505 506 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 507 { 508 env->mscratch = val; 509 return 0; 510 } 511 512 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 513 { 514 *val = env->mepc; 515 return 0; 516 } 517 518 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 519 { 520 env->mepc = val; 521 return 0; 522 } 523 524 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 525 { 526 *val = env->mcause; 527 return 0; 528 } 529 530 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 531 { 532 env->mcause = val; 533 return 0; 534 } 535 536 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 537 { 538 *val = env->mbadaddr; 539 return 0; 540 } 541 542 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 543 { 544 env->mbadaddr = val; 545 return 0; 546 } 547 548 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 549 target_ulong new_value, target_ulong write_mask) 550 { 551 RISCVCPU *cpu = riscv_env_get_cpu(env); 552 /* Allow software control of delegable interrupts not claimed by hardware */ 553 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 554 uint32_t old_mip; 555 556 if (mask) { 557 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 558 } else { 559 old_mip = atomic_read(&env->mip); 560 } 561 562 if (ret_value) { 563 *ret_value = old_mip; 564 } 565 566 return 0; 567 } 568 569 /* Supervisor Trap Setup */ 570 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 571 { 572 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 573 sstatus_v1_10_mask : sstatus_v1_9_mask); 574 *val = env->mstatus & mask; 575 return 0; 576 } 577 578 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 579 { 580 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 581 sstatus_v1_10_mask : sstatus_v1_9_mask); 582 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 583 return write_mstatus(env, CSR_MSTATUS, newval); 584 } 585 586 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 587 { 588 *val = env->mie & env->mideleg; 589 return 0; 590 } 591 592 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 593 { 594 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); 595 return write_mie(env, CSR_MIE, newval); 596 } 597 598 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 599 { 600 *val = env->stvec; 601 return 0; 602 } 603 604 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 605 { 606 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 607 if ((val & 3) < 2) { 608 env->stvec = val; 609 } else { 610 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 611 } 612 return 0; 613 } 614 615 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 616 { 617 if (env->priv_ver < PRIV_VERSION_1_10_0) { 618 return -1; 619 } 620 *val = env->scounteren; 621 return 0; 622 } 623 624 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 625 { 626 if (env->priv_ver < PRIV_VERSION_1_10_0) { 627 return -1; 628 } 629 env->scounteren = val; 630 return 0; 631 } 632 633 /* Supervisor Trap Handling */ 634 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 635 { 636 *val = env->sscratch; 637 return 0; 638 } 639 640 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 641 { 642 env->sscratch = val; 643 return 0; 644 } 645 646 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 647 { 648 *val = env->sepc; 649 return 0; 650 } 651 652 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 653 { 654 env->sepc = val; 655 return 0; 656 } 657 658 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 659 { 660 *val = env->scause; 661 return 0; 662 } 663 664 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 665 { 666 env->scause = val; 667 return 0; 668 } 669 670 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 671 { 672 *val = env->sbadaddr; 673 return 0; 674 } 675 676 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 677 { 678 env->sbadaddr = val; 679 return 0; 680 } 681 682 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 683 target_ulong new_value, target_ulong write_mask) 684 { 685 return rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 686 write_mask & env->mideleg); 687 } 688 689 /* Supervisor Protection and Translation */ 690 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 691 { 692 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 693 *val = 0; 694 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { 695 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 696 return -1; 697 } else { 698 *val = env->satp; 699 } 700 } else { 701 *val = env->sptbr; 702 } 703 return 0; 704 } 705 706 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 707 { 708 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 709 return 0; 710 } 711 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { 712 tlb_flush(CPU(riscv_env_get_cpu(env))); 713 env->sptbr = val & (((target_ulong) 714 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); 715 } 716 if (env->priv_ver >= PRIV_VERSION_1_10_0 && 717 validate_vm(env, get_field(val, SATP_MODE)) && 718 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 719 { 720 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 721 return -1; 722 } else { 723 tlb_flush(CPU(riscv_env_get_cpu(env))); 724 env->satp = val; 725 } 726 } 727 return 0; 728 } 729 730 /* Physical Memory Protection */ 731 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 732 { 733 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 734 return 0; 735 } 736 737 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 738 { 739 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 740 return 0; 741 } 742 743 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 744 { 745 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 746 return 0; 747 } 748 749 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 750 { 751 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 752 return 0; 753 } 754 755 #endif 756 757 /* 758 * riscv_csrrw - read and/or update control and status register 759 * 760 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 761 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 762 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 763 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 764 */ 765 766 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 767 target_ulong new_value, target_ulong write_mask) 768 { 769 int ret; 770 target_ulong old_value; 771 772 /* check privileges and return -1 if check fails */ 773 #if !defined(CONFIG_USER_ONLY) 774 int csr_priv = get_field(csrno, 0x300); 775 int read_only = get_field(csrno, 0xC00) == 3; 776 if ((write_mask && read_only) || (env->priv < csr_priv)) { 777 return -1; 778 } 779 #endif 780 781 /* check predicate */ 782 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { 783 return -1; 784 } 785 786 /* execute combined read/write operation if it exists */ 787 if (csr_ops[csrno].op) { 788 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 789 } 790 791 /* if no accessor exists then return failure */ 792 if (!csr_ops[csrno].read) { 793 return -1; 794 } 795 796 /* read old value */ 797 ret = csr_ops[csrno].read(env, csrno, &old_value); 798 if (ret < 0) { 799 return ret; 800 } 801 802 /* write value if writable and write mask set, otherwise drop writes */ 803 if (write_mask) { 804 new_value = (old_value & ~write_mask) | (new_value & write_mask); 805 if (csr_ops[csrno].write) { 806 ret = csr_ops[csrno].write(env, csrno, new_value); 807 if (ret < 0) { 808 return ret; 809 } 810 } 811 } 812 813 /* return old value */ 814 if (ret_value) { 815 *ret_value = old_value; 816 } 817 818 return 0; 819 } 820 821 /* 822 * Debugger support. If not in user mode, set env->debugger before the 823 * riscv_csrrw call and clear it after the call. 824 */ 825 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 826 target_ulong new_value, target_ulong write_mask) 827 { 828 int ret; 829 #if !defined(CONFIG_USER_ONLY) 830 env->debugger = true; 831 #endif 832 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 833 #if !defined(CONFIG_USER_ONLY) 834 env->debugger = false; 835 #endif 836 return ret; 837 } 838 839 /* Control and Status Register function table */ 840 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 841 /* User Floating-Point CSRs */ 842 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 843 [CSR_FRM] = { fs, read_frm, write_frm }, 844 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 845 846 /* User Timers and Counters */ 847 [CSR_CYCLE] = { ctr, read_instret }, 848 [CSR_INSTRET] = { ctr, read_instret }, 849 #if defined(TARGET_RISCV32) 850 [CSR_CYCLEH] = { ctr, read_instreth }, 851 [CSR_INSTRETH] = { ctr, read_instreth }, 852 #endif 853 854 /* User-level time CSRs are only available in linux-user 855 * In privileged mode, the monitor emulates these CSRs */ 856 #if defined(CONFIG_USER_ONLY) 857 [CSR_TIME] = { ctr, read_time }, 858 #if defined(TARGET_RISCV32) 859 [CSR_TIMEH] = { ctr, read_timeh }, 860 #endif 861 #endif 862 863 #if !defined(CONFIG_USER_ONLY) 864 /* Machine Timers and Counters */ 865 [CSR_MCYCLE] = { any, read_instret }, 866 [CSR_MINSTRET] = { any, read_instret }, 867 #if defined(TARGET_RISCV32) 868 [CSR_MCYCLEH] = { any, read_instreth }, 869 [CSR_MINSTRETH] = { any, read_instreth }, 870 #endif 871 872 /* Machine Information Registers */ 873 [CSR_MVENDORID] = { any, read_zero }, 874 [CSR_MARCHID] = { any, read_zero }, 875 [CSR_MIMPID] = { any, read_zero }, 876 [CSR_MHARTID] = { any, read_mhartid }, 877 878 /* Machine Trap Setup */ 879 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 880 [CSR_MISA] = { any, read_misa, write_misa }, 881 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 882 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 883 [CSR_MIE] = { any, read_mie, write_mie }, 884 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 885 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 886 887 /* Legacy Counter Setup (priv v1.9.1) */ 888 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, 889 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 890 891 /* Machine Trap Handling */ 892 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 893 [CSR_MEPC] = { any, read_mepc, write_mepc }, 894 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 895 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 896 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 897 898 /* Supervisor Trap Setup */ 899 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 900 [CSR_SIE] = { smode, read_sie, write_sie }, 901 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 902 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 903 904 /* Supervisor Trap Handling */ 905 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 906 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 907 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 908 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 909 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 910 911 /* Supervisor Protection and Translation */ 912 [CSR_SATP] = { smode, read_satp, write_satp }, 913 914 /* Physical Memory Protection */ 915 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, 916 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 917 918 /* Performance Counters */ 919 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 920 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 921 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 922 #if defined(TARGET_RISCV32) 923 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 924 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 925 #endif 926 #endif /* !CONFIG_USER_ONLY */ 927 }; 928