1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "qemu/main-loop.h" 25 #include "exec/exec-all.h" 26 #include "sysemu/cpu-timers.h" 27 #include "qemu/guest-random.h" 28 #include "qapi/error.h" 29 30 /* CSR function table public API */ 31 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 32 { 33 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 34 } 35 36 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 37 { 38 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 39 } 40 41 /* Predicates */ 42 static RISCVException fs(CPURISCVState *env, int csrno) 43 { 44 #if !defined(CONFIG_USER_ONLY) 45 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 46 !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 47 return RISCV_EXCP_ILLEGAL_INST; 48 } 49 #endif 50 return RISCV_EXCP_NONE; 51 } 52 53 static RISCVException vs(CPURISCVState *env, int csrno) 54 { 55 CPUState *cs = env_cpu(env); 56 RISCVCPU *cpu = RISCV_CPU(cs); 57 58 if (env->misa_ext & RVV || 59 cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 60 #if !defined(CONFIG_USER_ONLY) 61 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 62 return RISCV_EXCP_ILLEGAL_INST; 63 } 64 #endif 65 return RISCV_EXCP_NONE; 66 } 67 return RISCV_EXCP_ILLEGAL_INST; 68 } 69 70 static RISCVException ctr(CPURISCVState *env, int csrno) 71 { 72 #if !defined(CONFIG_USER_ONLY) 73 CPUState *cs = env_cpu(env); 74 RISCVCPU *cpu = RISCV_CPU(cs); 75 int ctr_index; 76 int base_csrno = CSR_HPMCOUNTER3; 77 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; 78 79 if (rv32 && csrno >= CSR_CYCLEH) { 80 /* Offset for RV32 hpmcounternh counters */ 81 base_csrno += 0x80; 82 } 83 ctr_index = csrno - base_csrno; 84 85 if (!cpu->cfg.pmu_num || ctr_index >= (cpu->cfg.pmu_num)) { 86 /* No counter is enabled in PMU or the counter is out of range */ 87 return RISCV_EXCP_ILLEGAL_INST; 88 } 89 90 if (env->priv == PRV_S) { 91 switch (csrno) { 92 case CSR_CYCLE: 93 if (!get_field(env->mcounteren, COUNTEREN_CY)) { 94 return RISCV_EXCP_ILLEGAL_INST; 95 } 96 break; 97 case CSR_TIME: 98 if (!get_field(env->mcounteren, COUNTEREN_TM)) { 99 return RISCV_EXCP_ILLEGAL_INST; 100 } 101 break; 102 case CSR_INSTRET: 103 if (!get_field(env->mcounteren, COUNTEREN_IR)) { 104 return RISCV_EXCP_ILLEGAL_INST; 105 } 106 break; 107 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 108 ctr_index = csrno - CSR_CYCLE; 109 if (!get_field(env->mcounteren, 1 << ctr_index)) { 110 return RISCV_EXCP_ILLEGAL_INST; 111 } 112 break; 113 } 114 if (rv32) { 115 switch (csrno) { 116 case CSR_CYCLEH: 117 if (!get_field(env->mcounteren, COUNTEREN_CY)) { 118 return RISCV_EXCP_ILLEGAL_INST; 119 } 120 break; 121 case CSR_TIMEH: 122 if (!get_field(env->mcounteren, COUNTEREN_TM)) { 123 return RISCV_EXCP_ILLEGAL_INST; 124 } 125 break; 126 case CSR_INSTRETH: 127 if (!get_field(env->mcounteren, COUNTEREN_IR)) { 128 return RISCV_EXCP_ILLEGAL_INST; 129 } 130 break; 131 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 132 ctr_index = csrno - CSR_CYCLEH; 133 if (!get_field(env->mcounteren, 1 << ctr_index)) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 break; 137 } 138 } 139 } 140 141 if (riscv_cpu_virt_enabled(env)) { 142 switch (csrno) { 143 case CSR_CYCLE: 144 if (!get_field(env->hcounteren, COUNTEREN_CY) && 145 get_field(env->mcounteren, COUNTEREN_CY)) { 146 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 147 } 148 break; 149 case CSR_TIME: 150 if (!get_field(env->hcounteren, COUNTEREN_TM) && 151 get_field(env->mcounteren, COUNTEREN_TM)) { 152 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 153 } 154 break; 155 case CSR_INSTRET: 156 if (!get_field(env->hcounteren, COUNTEREN_IR) && 157 get_field(env->mcounteren, COUNTEREN_IR)) { 158 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 159 } 160 break; 161 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 162 ctr_index = csrno - CSR_CYCLE; 163 if (!get_field(env->hcounteren, 1 << ctr_index) && 164 get_field(env->mcounteren, 1 << ctr_index)) { 165 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 166 } 167 break; 168 } 169 if (rv32) { 170 switch (csrno) { 171 case CSR_CYCLEH: 172 if (!get_field(env->hcounteren, COUNTEREN_CY) && 173 get_field(env->mcounteren, COUNTEREN_CY)) { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 break; 177 case CSR_TIMEH: 178 if (!get_field(env->hcounteren, COUNTEREN_TM) && 179 get_field(env->mcounteren, COUNTEREN_TM)) { 180 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 181 } 182 break; 183 case CSR_INSTRETH: 184 if (!get_field(env->hcounteren, COUNTEREN_IR) && 185 get_field(env->mcounteren, COUNTEREN_IR)) { 186 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 187 } 188 break; 189 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 190 ctr_index = csrno - CSR_CYCLEH; 191 if (!get_field(env->hcounteren, 1 << ctr_index) && 192 get_field(env->mcounteren, 1 << ctr_index)) { 193 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 194 } 195 break; 196 } 197 } 198 } 199 #endif 200 return RISCV_EXCP_NONE; 201 } 202 203 static RISCVException ctr32(CPURISCVState *env, int csrno) 204 { 205 if (riscv_cpu_mxl(env) != MXL_RV32) { 206 return RISCV_EXCP_ILLEGAL_INST; 207 } 208 209 return ctr(env, csrno); 210 } 211 212 #if !defined(CONFIG_USER_ONLY) 213 static RISCVException mctr(CPURISCVState *env, int csrno) 214 { 215 CPUState *cs = env_cpu(env); 216 RISCVCPU *cpu = RISCV_CPU(cs); 217 int ctr_index; 218 int base_csrno = CSR_MHPMCOUNTER3; 219 220 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { 221 /* Offset for RV32 mhpmcounternh counters */ 222 base_csrno += 0x80; 223 } 224 ctr_index = csrno - base_csrno; 225 if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) { 226 /* The PMU is not enabled or counter is out of range*/ 227 return RISCV_EXCP_ILLEGAL_INST; 228 } 229 230 return RISCV_EXCP_NONE; 231 } 232 233 static RISCVException any(CPURISCVState *env, int csrno) 234 { 235 return RISCV_EXCP_NONE; 236 } 237 238 static RISCVException any32(CPURISCVState *env, int csrno) 239 { 240 if (riscv_cpu_mxl(env) != MXL_RV32) { 241 return RISCV_EXCP_ILLEGAL_INST; 242 } 243 244 return any(env, csrno); 245 246 } 247 248 static int aia_any(CPURISCVState *env, int csrno) 249 { 250 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 251 return RISCV_EXCP_ILLEGAL_INST; 252 } 253 254 return any(env, csrno); 255 } 256 257 static int aia_any32(CPURISCVState *env, int csrno) 258 { 259 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 260 return RISCV_EXCP_ILLEGAL_INST; 261 } 262 263 return any32(env, csrno); 264 } 265 266 static RISCVException smode(CPURISCVState *env, int csrno) 267 { 268 if (riscv_has_ext(env, RVS)) { 269 return RISCV_EXCP_NONE; 270 } 271 272 return RISCV_EXCP_ILLEGAL_INST; 273 } 274 275 static int smode32(CPURISCVState *env, int csrno) 276 { 277 if (riscv_cpu_mxl(env) != MXL_RV32) { 278 return RISCV_EXCP_ILLEGAL_INST; 279 } 280 281 return smode(env, csrno); 282 } 283 284 static int aia_smode(CPURISCVState *env, int csrno) 285 { 286 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 287 return RISCV_EXCP_ILLEGAL_INST; 288 } 289 290 return smode(env, csrno); 291 } 292 293 static int aia_smode32(CPURISCVState *env, int csrno) 294 { 295 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 296 return RISCV_EXCP_ILLEGAL_INST; 297 } 298 299 return smode32(env, csrno); 300 } 301 302 static RISCVException hmode(CPURISCVState *env, int csrno) 303 { 304 if (riscv_has_ext(env, RVS) && 305 riscv_has_ext(env, RVH)) { 306 /* Hypervisor extension is supported */ 307 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 308 env->priv == PRV_M) { 309 return RISCV_EXCP_NONE; 310 } else { 311 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 312 } 313 } 314 315 return RISCV_EXCP_ILLEGAL_INST; 316 } 317 318 static RISCVException hmode32(CPURISCVState *env, int csrno) 319 { 320 if (riscv_cpu_mxl(env) != MXL_RV32) { 321 if (!riscv_cpu_virt_enabled(env)) { 322 return RISCV_EXCP_ILLEGAL_INST; 323 } else { 324 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 325 } 326 } 327 328 return hmode(env, csrno); 329 330 } 331 332 /* Checks if PointerMasking registers could be accessed */ 333 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 334 { 335 /* Check if j-ext is present */ 336 if (riscv_has_ext(env, RVJ)) { 337 return RISCV_EXCP_NONE; 338 } 339 return RISCV_EXCP_ILLEGAL_INST; 340 } 341 342 static int aia_hmode(CPURISCVState *env, int csrno) 343 { 344 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 345 return RISCV_EXCP_ILLEGAL_INST; 346 } 347 348 return hmode(env, csrno); 349 } 350 351 static int aia_hmode32(CPURISCVState *env, int csrno) 352 { 353 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 354 return RISCV_EXCP_ILLEGAL_INST; 355 } 356 357 return hmode32(env, csrno); 358 } 359 360 static RISCVException pmp(CPURISCVState *env, int csrno) 361 { 362 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 363 return RISCV_EXCP_NONE; 364 } 365 366 return RISCV_EXCP_ILLEGAL_INST; 367 } 368 369 static RISCVException epmp(CPURISCVState *env, int csrno) 370 { 371 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 372 return RISCV_EXCP_NONE; 373 } 374 375 return RISCV_EXCP_ILLEGAL_INST; 376 } 377 378 static RISCVException debug(CPURISCVState *env, int csrno) 379 { 380 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 381 return RISCV_EXCP_NONE; 382 } 383 384 return RISCV_EXCP_ILLEGAL_INST; 385 } 386 #endif 387 388 static RISCVException seed(CPURISCVState *env, int csrno) 389 { 390 RISCVCPU *cpu = env_archcpu(env); 391 392 if (!cpu->cfg.ext_zkr) { 393 return RISCV_EXCP_ILLEGAL_INST; 394 } 395 396 #if !defined(CONFIG_USER_ONLY) 397 /* 398 * With a CSR read-write instruction: 399 * 1) The seed CSR is always available in machine mode as normal. 400 * 2) Attempted access to seed from virtual modes VS and VU always raises 401 * an exception(virtual instruction exception only if mseccfg.sseed=1). 402 * 3) Without the corresponding access control bit set to 1, any attempted 403 * access to seed from U, S or HS modes will raise an illegal instruction 404 * exception. 405 */ 406 if (env->priv == PRV_M) { 407 return RISCV_EXCP_NONE; 408 } else if (riscv_cpu_virt_enabled(env)) { 409 if (env->mseccfg & MSECCFG_SSEED) { 410 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 411 } else { 412 return RISCV_EXCP_ILLEGAL_INST; 413 } 414 } else { 415 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { 416 return RISCV_EXCP_NONE; 417 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { 418 return RISCV_EXCP_NONE; 419 } else { 420 return RISCV_EXCP_ILLEGAL_INST; 421 } 422 } 423 #else 424 return RISCV_EXCP_NONE; 425 #endif 426 } 427 428 /* User Floating-Point CSRs */ 429 static RISCVException read_fflags(CPURISCVState *env, int csrno, 430 target_ulong *val) 431 { 432 *val = riscv_cpu_get_fflags(env); 433 return RISCV_EXCP_NONE; 434 } 435 436 static RISCVException write_fflags(CPURISCVState *env, int csrno, 437 target_ulong val) 438 { 439 #if !defined(CONFIG_USER_ONLY) 440 if (riscv_has_ext(env, RVF)) { 441 env->mstatus |= MSTATUS_FS; 442 } 443 #endif 444 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 445 return RISCV_EXCP_NONE; 446 } 447 448 static RISCVException read_frm(CPURISCVState *env, int csrno, 449 target_ulong *val) 450 { 451 *val = env->frm; 452 return RISCV_EXCP_NONE; 453 } 454 455 static RISCVException write_frm(CPURISCVState *env, int csrno, 456 target_ulong val) 457 { 458 #if !defined(CONFIG_USER_ONLY) 459 if (riscv_has_ext(env, RVF)) { 460 env->mstatus |= MSTATUS_FS; 461 } 462 #endif 463 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 464 return RISCV_EXCP_NONE; 465 } 466 467 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 468 target_ulong *val) 469 { 470 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 471 | (env->frm << FSR_RD_SHIFT); 472 return RISCV_EXCP_NONE; 473 } 474 475 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 476 target_ulong val) 477 { 478 #if !defined(CONFIG_USER_ONLY) 479 if (riscv_has_ext(env, RVF)) { 480 env->mstatus |= MSTATUS_FS; 481 } 482 #endif 483 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 484 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 485 return RISCV_EXCP_NONE; 486 } 487 488 static RISCVException read_vtype(CPURISCVState *env, int csrno, 489 target_ulong *val) 490 { 491 uint64_t vill; 492 switch (env->xl) { 493 case MXL_RV32: 494 vill = (uint32_t)env->vill << 31; 495 break; 496 case MXL_RV64: 497 vill = (uint64_t)env->vill << 63; 498 break; 499 default: 500 g_assert_not_reached(); 501 } 502 *val = (target_ulong)vill | env->vtype; 503 return RISCV_EXCP_NONE; 504 } 505 506 static RISCVException read_vl(CPURISCVState *env, int csrno, 507 target_ulong *val) 508 { 509 *val = env->vl; 510 return RISCV_EXCP_NONE; 511 } 512 513 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 514 { 515 *val = env_archcpu(env)->cfg.vlen >> 3; 516 return RISCV_EXCP_NONE; 517 } 518 519 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 520 target_ulong *val) 521 { 522 *val = env->vxrm; 523 return RISCV_EXCP_NONE; 524 } 525 526 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 527 target_ulong val) 528 { 529 #if !defined(CONFIG_USER_ONLY) 530 env->mstatus |= MSTATUS_VS; 531 #endif 532 env->vxrm = val; 533 return RISCV_EXCP_NONE; 534 } 535 536 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 537 target_ulong *val) 538 { 539 *val = env->vxsat; 540 return RISCV_EXCP_NONE; 541 } 542 543 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 544 target_ulong val) 545 { 546 #if !defined(CONFIG_USER_ONLY) 547 env->mstatus |= MSTATUS_VS; 548 #endif 549 env->vxsat = val; 550 return RISCV_EXCP_NONE; 551 } 552 553 static RISCVException read_vstart(CPURISCVState *env, int csrno, 554 target_ulong *val) 555 { 556 *val = env->vstart; 557 return RISCV_EXCP_NONE; 558 } 559 560 static RISCVException write_vstart(CPURISCVState *env, int csrno, 561 target_ulong val) 562 { 563 #if !defined(CONFIG_USER_ONLY) 564 env->mstatus |= MSTATUS_VS; 565 #endif 566 /* 567 * The vstart CSR is defined to have only enough writable bits 568 * to hold the largest element index, i.e. lg2(VLEN) bits. 569 */ 570 env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); 571 return RISCV_EXCP_NONE; 572 } 573 574 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 575 { 576 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 577 return RISCV_EXCP_NONE; 578 } 579 580 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 581 { 582 #if !defined(CONFIG_USER_ONLY) 583 env->mstatus |= MSTATUS_VS; 584 #endif 585 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 586 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 587 return RISCV_EXCP_NONE; 588 } 589 590 /* User Timers and Counters */ 591 static RISCVException read_instret(CPURISCVState *env, int csrno, 592 target_ulong *val) 593 { 594 #if !defined(CONFIG_USER_ONLY) 595 if (icount_enabled()) { 596 *val = icount_get(); 597 } else { 598 *val = cpu_get_host_ticks(); 599 } 600 #else 601 *val = cpu_get_host_ticks(); 602 #endif 603 return RISCV_EXCP_NONE; 604 } 605 606 static RISCVException read_instreth(CPURISCVState *env, int csrno, 607 target_ulong *val) 608 { 609 #if !defined(CONFIG_USER_ONLY) 610 if (icount_enabled()) { 611 *val = icount_get() >> 32; 612 } else { 613 *val = cpu_get_host_ticks() >> 32; 614 } 615 #else 616 *val = cpu_get_host_ticks() >> 32; 617 #endif 618 return RISCV_EXCP_NONE; 619 } 620 621 #if defined(CONFIG_USER_ONLY) 622 static RISCVException read_time(CPURISCVState *env, int csrno, 623 target_ulong *val) 624 { 625 *val = cpu_get_host_ticks(); 626 return RISCV_EXCP_NONE; 627 } 628 629 static RISCVException read_timeh(CPURISCVState *env, int csrno, 630 target_ulong *val) 631 { 632 *val = cpu_get_host_ticks() >> 32; 633 return RISCV_EXCP_NONE; 634 } 635 636 #else /* CONFIG_USER_ONLY */ 637 638 static RISCVException read_time(CPURISCVState *env, int csrno, 639 target_ulong *val) 640 { 641 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 642 643 if (!env->rdtime_fn) { 644 return RISCV_EXCP_ILLEGAL_INST; 645 } 646 647 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 648 return RISCV_EXCP_NONE; 649 } 650 651 static RISCVException read_timeh(CPURISCVState *env, int csrno, 652 target_ulong *val) 653 { 654 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 655 656 if (!env->rdtime_fn) { 657 return RISCV_EXCP_ILLEGAL_INST; 658 } 659 660 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 661 return RISCV_EXCP_NONE; 662 } 663 664 /* Machine constants */ 665 666 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 667 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 668 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 669 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 670 671 #define VSTOPI_NUM_SRCS 5 672 673 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | 674 VS_MODE_INTERRUPTS; 675 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; 676 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 677 HS_MODE_INTERRUPTS; 678 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 679 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 680 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 681 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 682 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 683 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 684 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 685 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 686 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 687 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 688 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 689 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 690 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 691 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 692 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 693 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 694 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 695 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 696 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 697 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 698 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 699 (1ULL << (RISCV_EXCP_VS_ECALL)) | 700 (1ULL << (RISCV_EXCP_M_ECALL)) | 701 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 702 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 703 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 704 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 705 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 706 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 707 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 708 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 709 static const target_ulong hip_writable_mask = MIP_VSSIP; 710 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 711 static const target_ulong vsip_writable_mask = MIP_VSSIP; 712 713 static const char valid_vm_1_10_32[16] = { 714 [VM_1_10_MBARE] = 1, 715 [VM_1_10_SV32] = 1 716 }; 717 718 static const char valid_vm_1_10_64[16] = { 719 [VM_1_10_MBARE] = 1, 720 [VM_1_10_SV39] = 1, 721 [VM_1_10_SV48] = 1, 722 [VM_1_10_SV57] = 1 723 }; 724 725 /* Machine Information Registers */ 726 static RISCVException read_zero(CPURISCVState *env, int csrno, 727 target_ulong *val) 728 { 729 *val = 0; 730 return RISCV_EXCP_NONE; 731 } 732 733 static RISCVException write_ignore(CPURISCVState *env, int csrno, 734 target_ulong val) 735 { 736 return RISCV_EXCP_NONE; 737 } 738 739 static RISCVException read_mvendorid(CPURISCVState *env, int csrno, 740 target_ulong *val) 741 { 742 CPUState *cs = env_cpu(env); 743 RISCVCPU *cpu = RISCV_CPU(cs); 744 745 *val = cpu->cfg.mvendorid; 746 return RISCV_EXCP_NONE; 747 } 748 749 static RISCVException read_marchid(CPURISCVState *env, int csrno, 750 target_ulong *val) 751 { 752 CPUState *cs = env_cpu(env); 753 RISCVCPU *cpu = RISCV_CPU(cs); 754 755 *val = cpu->cfg.marchid; 756 return RISCV_EXCP_NONE; 757 } 758 759 static RISCVException read_mimpid(CPURISCVState *env, int csrno, 760 target_ulong *val) 761 { 762 CPUState *cs = env_cpu(env); 763 RISCVCPU *cpu = RISCV_CPU(cs); 764 765 *val = cpu->cfg.mimpid; 766 return RISCV_EXCP_NONE; 767 } 768 769 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 770 target_ulong *val) 771 { 772 *val = env->mhartid; 773 return RISCV_EXCP_NONE; 774 } 775 776 /* Machine Trap Setup */ 777 778 /* We do not store SD explicitly, only compute it on demand. */ 779 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 780 { 781 if ((status & MSTATUS_FS) == MSTATUS_FS || 782 (status & MSTATUS_VS) == MSTATUS_VS || 783 (status & MSTATUS_XS) == MSTATUS_XS) { 784 switch (xl) { 785 case MXL_RV32: 786 return status | MSTATUS32_SD; 787 case MXL_RV64: 788 return status | MSTATUS64_SD; 789 case MXL_RV128: 790 return MSTATUSH128_SD; 791 default: 792 g_assert_not_reached(); 793 } 794 } 795 return status; 796 } 797 798 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 799 target_ulong *val) 800 { 801 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 802 return RISCV_EXCP_NONE; 803 } 804 805 static int validate_vm(CPURISCVState *env, target_ulong vm) 806 { 807 if (riscv_cpu_mxl(env) == MXL_RV32) { 808 return valid_vm_1_10_32[vm & 0xf]; 809 } else { 810 return valid_vm_1_10_64[vm & 0xf]; 811 } 812 } 813 814 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 815 target_ulong val) 816 { 817 uint64_t mstatus = env->mstatus; 818 uint64_t mask = 0; 819 RISCVMXL xl = riscv_cpu_mxl(env); 820 821 /* flush tlb on mstatus fields that affect VM */ 822 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 823 MSTATUS_MPRV | MSTATUS_SUM)) { 824 tlb_flush(env_cpu(env)); 825 } 826 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 827 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 828 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 829 MSTATUS_TW | MSTATUS_VS; 830 831 if (riscv_has_ext(env, RVF)) { 832 mask |= MSTATUS_FS; 833 } 834 835 if (xl != MXL_RV32 || env->debugger) { 836 /* 837 * RV32: MPV and GVA are not in mstatus. The current plan is to 838 * add them to mstatush. For now, we just don't support it. 839 */ 840 mask |= MSTATUS_MPV | MSTATUS_GVA; 841 if ((val & MSTATUS64_UXL) != 0) { 842 mask |= MSTATUS64_UXL; 843 } 844 } 845 846 mstatus = (mstatus & ~mask) | (val & mask); 847 848 if (xl > MXL_RV32) { 849 /* SXL field is for now read only */ 850 mstatus = set_field(mstatus, MSTATUS64_SXL, xl); 851 } 852 env->mstatus = mstatus; 853 env->xl = cpu_recompute_xl(env); 854 855 return RISCV_EXCP_NONE; 856 } 857 858 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 859 target_ulong *val) 860 { 861 *val = env->mstatus >> 32; 862 return RISCV_EXCP_NONE; 863 } 864 865 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 866 target_ulong val) 867 { 868 uint64_t valh = (uint64_t)val << 32; 869 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 870 871 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 872 tlb_flush(env_cpu(env)); 873 } 874 875 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 876 877 return RISCV_EXCP_NONE; 878 } 879 880 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 881 Int128 *val) 882 { 883 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); 884 return RISCV_EXCP_NONE; 885 } 886 887 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 888 Int128 *val) 889 { 890 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 891 return RISCV_EXCP_NONE; 892 } 893 894 static RISCVException read_misa(CPURISCVState *env, int csrno, 895 target_ulong *val) 896 { 897 target_ulong misa; 898 899 switch (env->misa_mxl) { 900 case MXL_RV32: 901 misa = (target_ulong)MXL_RV32 << 30; 902 break; 903 #ifdef TARGET_RISCV64 904 case MXL_RV64: 905 misa = (target_ulong)MXL_RV64 << 62; 906 break; 907 #endif 908 default: 909 g_assert_not_reached(); 910 } 911 912 *val = misa | env->misa_ext; 913 return RISCV_EXCP_NONE; 914 } 915 916 static RISCVException write_misa(CPURISCVState *env, int csrno, 917 target_ulong val) 918 { 919 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 920 /* drop write to misa */ 921 return RISCV_EXCP_NONE; 922 } 923 924 /* 'I' or 'E' must be present */ 925 if (!(val & (RVI | RVE))) { 926 /* It is not, drop write to misa */ 927 return RISCV_EXCP_NONE; 928 } 929 930 /* 'E' excludes all other extensions */ 931 if (val & RVE) { 932 /* when we support 'E' we can do "val = RVE;" however 933 * for now we just drop writes if 'E' is present. 934 */ 935 return RISCV_EXCP_NONE; 936 } 937 938 /* 939 * misa.MXL writes are not supported by QEMU. 940 * Drop writes to those bits. 941 */ 942 943 /* Mask extensions that are not supported by this hart */ 944 val &= env->misa_ext_mask; 945 946 /* Mask extensions that are not supported by QEMU */ 947 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 948 949 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 950 if ((val & RVD) && !(val & RVF)) { 951 val &= ~RVD; 952 } 953 954 /* Suppress 'C' if next instruction is not aligned 955 * TODO: this should check next_pc 956 */ 957 if ((val & RVC) && (GETPC() & ~3) != 0) { 958 val &= ~RVC; 959 } 960 961 /* If nothing changed, do nothing. */ 962 if (val == env->misa_ext) { 963 return RISCV_EXCP_NONE; 964 } 965 966 if (!(val & RVF)) { 967 env->mstatus &= ~MSTATUS_FS; 968 } 969 970 /* flush translation cache */ 971 tb_flush(env_cpu(env)); 972 env->misa_ext = val; 973 env->xl = riscv_cpu_mxl(env); 974 return RISCV_EXCP_NONE; 975 } 976 977 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 978 target_ulong *val) 979 { 980 *val = env->medeleg; 981 return RISCV_EXCP_NONE; 982 } 983 984 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 985 target_ulong val) 986 { 987 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 988 return RISCV_EXCP_NONE; 989 } 990 991 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 992 uint64_t *ret_val, 993 uint64_t new_val, uint64_t wr_mask) 994 { 995 uint64_t mask = wr_mask & delegable_ints; 996 997 if (ret_val) { 998 *ret_val = env->mideleg; 999 } 1000 1001 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 1002 1003 if (riscv_has_ext(env, RVH)) { 1004 env->mideleg |= HS_MODE_INTERRUPTS; 1005 } 1006 1007 return RISCV_EXCP_NONE; 1008 } 1009 1010 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 1011 target_ulong *ret_val, 1012 target_ulong new_val, target_ulong wr_mask) 1013 { 1014 uint64_t rval; 1015 RISCVException ret; 1016 1017 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 1018 if (ret_val) { 1019 *ret_val = rval; 1020 } 1021 1022 return ret; 1023 } 1024 1025 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 1026 target_ulong *ret_val, 1027 target_ulong new_val, 1028 target_ulong wr_mask) 1029 { 1030 uint64_t rval; 1031 RISCVException ret; 1032 1033 ret = rmw_mideleg64(env, csrno, &rval, 1034 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1035 if (ret_val) { 1036 *ret_val = rval >> 32; 1037 } 1038 1039 return ret; 1040 } 1041 1042 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 1043 uint64_t *ret_val, 1044 uint64_t new_val, uint64_t wr_mask) 1045 { 1046 uint64_t mask = wr_mask & all_ints; 1047 1048 if (ret_val) { 1049 *ret_val = env->mie; 1050 } 1051 1052 env->mie = (env->mie & ~mask) | (new_val & mask); 1053 1054 if (!riscv_has_ext(env, RVH)) { 1055 env->mie &= ~((uint64_t)MIP_SGEIP); 1056 } 1057 1058 return RISCV_EXCP_NONE; 1059 } 1060 1061 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 1062 target_ulong *ret_val, 1063 target_ulong new_val, target_ulong wr_mask) 1064 { 1065 uint64_t rval; 1066 RISCVException ret; 1067 1068 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 1069 if (ret_val) { 1070 *ret_val = rval; 1071 } 1072 1073 return ret; 1074 } 1075 1076 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 1077 target_ulong *ret_val, 1078 target_ulong new_val, target_ulong wr_mask) 1079 { 1080 uint64_t rval; 1081 RISCVException ret; 1082 1083 ret = rmw_mie64(env, csrno, &rval, 1084 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1085 if (ret_val) { 1086 *ret_val = rval >> 32; 1087 } 1088 1089 return ret; 1090 } 1091 1092 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 1093 { 1094 int irq; 1095 uint8_t iprio; 1096 1097 irq = riscv_cpu_mirq_pending(env); 1098 if (irq <= 0 || irq > 63) { 1099 *val = 0; 1100 } else { 1101 iprio = env->miprio[irq]; 1102 if (!iprio) { 1103 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 1104 iprio = IPRIO_MMAXIPRIO; 1105 } 1106 } 1107 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 1108 *val |= iprio; 1109 } 1110 1111 return RISCV_EXCP_NONE; 1112 } 1113 1114 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 1115 { 1116 if (!riscv_cpu_virt_enabled(env)) { 1117 return csrno; 1118 } 1119 1120 switch (csrno) { 1121 case CSR_SISELECT: 1122 return CSR_VSISELECT; 1123 case CSR_SIREG: 1124 return CSR_VSIREG; 1125 case CSR_SSETEIPNUM: 1126 return CSR_VSSETEIPNUM; 1127 case CSR_SCLREIPNUM: 1128 return CSR_VSCLREIPNUM; 1129 case CSR_SSETEIENUM: 1130 return CSR_VSSETEIENUM; 1131 case CSR_SCLREIENUM: 1132 return CSR_VSCLREIENUM; 1133 case CSR_STOPEI: 1134 return CSR_VSTOPEI; 1135 default: 1136 return csrno; 1137 }; 1138 } 1139 1140 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 1141 target_ulong new_val, target_ulong wr_mask) 1142 { 1143 target_ulong *iselect; 1144 1145 /* Translate CSR number for VS-mode */ 1146 csrno = aia_xlate_vs_csrno(env, csrno); 1147 1148 /* Find the iselect CSR based on CSR number */ 1149 switch (csrno) { 1150 case CSR_MISELECT: 1151 iselect = &env->miselect; 1152 break; 1153 case CSR_SISELECT: 1154 iselect = &env->siselect; 1155 break; 1156 case CSR_VSISELECT: 1157 iselect = &env->vsiselect; 1158 break; 1159 default: 1160 return RISCV_EXCP_ILLEGAL_INST; 1161 }; 1162 1163 if (val) { 1164 *val = *iselect; 1165 } 1166 1167 wr_mask &= ISELECT_MASK; 1168 if (wr_mask) { 1169 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1170 } 1171 1172 return RISCV_EXCP_NONE; 1173 } 1174 1175 static int rmw_iprio(target_ulong xlen, 1176 target_ulong iselect, uint8_t *iprio, 1177 target_ulong *val, target_ulong new_val, 1178 target_ulong wr_mask, int ext_irq_no) 1179 { 1180 int i, firq, nirqs; 1181 target_ulong old_val; 1182 1183 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1184 return -EINVAL; 1185 } 1186 if (xlen != 32 && iselect & 0x1) { 1187 return -EINVAL; 1188 } 1189 1190 nirqs = 4 * (xlen / 32); 1191 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1192 1193 old_val = 0; 1194 for (i = 0; i < nirqs; i++) { 1195 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1196 } 1197 1198 if (val) { 1199 *val = old_val; 1200 } 1201 1202 if (wr_mask) { 1203 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1204 for (i = 0; i < nirqs; i++) { 1205 /* 1206 * M-level and S-level external IRQ priority always read-only 1207 * zero. This means default priority order is always preferred 1208 * for M-level and S-level external IRQs. 1209 */ 1210 if ((firq + i) == ext_irq_no) { 1211 continue; 1212 } 1213 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1214 } 1215 } 1216 1217 return 0; 1218 } 1219 1220 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1221 target_ulong new_val, target_ulong wr_mask) 1222 { 1223 bool virt; 1224 uint8_t *iprio; 1225 int ret = -EINVAL; 1226 target_ulong priv, isel, vgein; 1227 1228 /* Translate CSR number for VS-mode */ 1229 csrno = aia_xlate_vs_csrno(env, csrno); 1230 1231 /* Decode register details from CSR number */ 1232 virt = false; 1233 switch (csrno) { 1234 case CSR_MIREG: 1235 iprio = env->miprio; 1236 isel = env->miselect; 1237 priv = PRV_M; 1238 break; 1239 case CSR_SIREG: 1240 iprio = env->siprio; 1241 isel = env->siselect; 1242 priv = PRV_S; 1243 break; 1244 case CSR_VSIREG: 1245 iprio = env->hviprio; 1246 isel = env->vsiselect; 1247 priv = PRV_S; 1248 virt = true; 1249 break; 1250 default: 1251 goto done; 1252 }; 1253 1254 /* Find the selected guest interrupt file */ 1255 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1256 1257 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1258 /* Local interrupt priority registers not available for VS-mode */ 1259 if (!virt) { 1260 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1261 isel, iprio, val, new_val, wr_mask, 1262 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1263 } 1264 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1265 /* IMSIC registers only available when machine implements it. */ 1266 if (env->aia_ireg_rmw_fn[priv]) { 1267 /* Selected guest interrupt file should not be zero */ 1268 if (virt && (!vgein || env->geilen < vgein)) { 1269 goto done; 1270 } 1271 /* Call machine specific IMSIC register emulation */ 1272 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1273 AIA_MAKE_IREG(isel, priv, virt, vgein, 1274 riscv_cpu_mxl_bits(env)), 1275 val, new_val, wr_mask); 1276 } 1277 } 1278 1279 done: 1280 if (ret) { 1281 return (riscv_cpu_virt_enabled(env) && virt) ? 1282 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1283 } 1284 return RISCV_EXCP_NONE; 1285 } 1286 1287 static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val, 1288 target_ulong new_val, target_ulong wr_mask) 1289 { 1290 int ret = -EINVAL; 1291 bool set, pend, virt; 1292 target_ulong priv, isel, vgein, xlen, nval, wmask; 1293 1294 /* Translate CSR number for VS-mode */ 1295 csrno = aia_xlate_vs_csrno(env, csrno); 1296 1297 /* Decode register details from CSR number */ 1298 virt = set = pend = false; 1299 switch (csrno) { 1300 case CSR_MSETEIPNUM: 1301 priv = PRV_M; 1302 set = true; 1303 pend = true; 1304 break; 1305 case CSR_MCLREIPNUM: 1306 priv = PRV_M; 1307 pend = true; 1308 break; 1309 case CSR_MSETEIENUM: 1310 priv = PRV_M; 1311 set = true; 1312 break; 1313 case CSR_MCLREIENUM: 1314 priv = PRV_M; 1315 break; 1316 case CSR_SSETEIPNUM: 1317 priv = PRV_S; 1318 set = true; 1319 pend = true; 1320 break; 1321 case CSR_SCLREIPNUM: 1322 priv = PRV_S; 1323 pend = true; 1324 break; 1325 case CSR_SSETEIENUM: 1326 priv = PRV_S; 1327 set = true; 1328 break; 1329 case CSR_SCLREIENUM: 1330 priv = PRV_S; 1331 break; 1332 case CSR_VSSETEIPNUM: 1333 priv = PRV_S; 1334 virt = true; 1335 set = true; 1336 pend = true; 1337 break; 1338 case CSR_VSCLREIPNUM: 1339 priv = PRV_S; 1340 virt = true; 1341 pend = true; 1342 break; 1343 case CSR_VSSETEIENUM: 1344 priv = PRV_S; 1345 virt = true; 1346 set = true; 1347 break; 1348 case CSR_VSCLREIENUM: 1349 priv = PRV_S; 1350 virt = true; 1351 break; 1352 default: 1353 goto done; 1354 }; 1355 1356 /* IMSIC CSRs only available when machine implements IMSIC. */ 1357 if (!env->aia_ireg_rmw_fn[priv]) { 1358 goto done; 1359 } 1360 1361 /* Find the selected guest interrupt file */ 1362 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1363 1364 /* Selected guest interrupt file should be valid */ 1365 if (virt && (!vgein || env->geilen < vgein)) { 1366 goto done; 1367 } 1368 1369 /* Set/Clear CSRs always read zero */ 1370 if (val) { 1371 *val = 0; 1372 } 1373 1374 if (wr_mask) { 1375 /* Get interrupt number */ 1376 new_val &= wr_mask; 1377 1378 /* Find target interrupt pending/enable register */ 1379 xlen = riscv_cpu_mxl_bits(env); 1380 isel = (new_val / xlen); 1381 isel *= (xlen / IMSIC_EIPx_BITS); 1382 isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; 1383 1384 /* Find the interrupt bit to be set/clear */ 1385 wmask = ((target_ulong)1) << (new_val % xlen); 1386 nval = (set) ? wmask : 0; 1387 1388 /* Call machine specific IMSIC register emulation */ 1389 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1390 AIA_MAKE_IREG(isel, priv, virt, 1391 vgein, xlen), 1392 NULL, nval, wmask); 1393 } else { 1394 ret = 0; 1395 } 1396 1397 done: 1398 if (ret) { 1399 return (riscv_cpu_virt_enabled(env) && virt) ? 1400 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1401 } 1402 return RISCV_EXCP_NONE; 1403 } 1404 1405 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1406 target_ulong new_val, target_ulong wr_mask) 1407 { 1408 bool virt; 1409 int ret = -EINVAL; 1410 target_ulong priv, vgein; 1411 1412 /* Translate CSR number for VS-mode */ 1413 csrno = aia_xlate_vs_csrno(env, csrno); 1414 1415 /* Decode register details from CSR number */ 1416 virt = false; 1417 switch (csrno) { 1418 case CSR_MTOPEI: 1419 priv = PRV_M; 1420 break; 1421 case CSR_STOPEI: 1422 priv = PRV_S; 1423 break; 1424 case CSR_VSTOPEI: 1425 priv = PRV_S; 1426 virt = true; 1427 break; 1428 default: 1429 goto done; 1430 }; 1431 1432 /* IMSIC CSRs only available when machine implements IMSIC. */ 1433 if (!env->aia_ireg_rmw_fn[priv]) { 1434 goto done; 1435 } 1436 1437 /* Find the selected guest interrupt file */ 1438 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1439 1440 /* Selected guest interrupt file should be valid */ 1441 if (virt && (!vgein || env->geilen < vgein)) { 1442 goto done; 1443 } 1444 1445 /* Call machine specific IMSIC register emulation for TOPEI */ 1446 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1447 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1448 riscv_cpu_mxl_bits(env)), 1449 val, new_val, wr_mask); 1450 1451 done: 1452 if (ret) { 1453 return (riscv_cpu_virt_enabled(env) && virt) ? 1454 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1455 } 1456 return RISCV_EXCP_NONE; 1457 } 1458 1459 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1460 target_ulong *val) 1461 { 1462 *val = env->mtvec; 1463 return RISCV_EXCP_NONE; 1464 } 1465 1466 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1467 target_ulong val) 1468 { 1469 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1470 if ((val & 3) < 2) { 1471 env->mtvec = val; 1472 } else { 1473 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1474 } 1475 return RISCV_EXCP_NONE; 1476 } 1477 1478 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1479 target_ulong *val) 1480 { 1481 *val = env->mcounteren; 1482 return RISCV_EXCP_NONE; 1483 } 1484 1485 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1486 target_ulong val) 1487 { 1488 env->mcounteren = val; 1489 return RISCV_EXCP_NONE; 1490 } 1491 1492 /* Machine Trap Handling */ 1493 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1494 Int128 *val) 1495 { 1496 *val = int128_make128(env->mscratch, env->mscratchh); 1497 return RISCV_EXCP_NONE; 1498 } 1499 1500 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1501 Int128 val) 1502 { 1503 env->mscratch = int128_getlo(val); 1504 env->mscratchh = int128_gethi(val); 1505 return RISCV_EXCP_NONE; 1506 } 1507 1508 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1509 target_ulong *val) 1510 { 1511 *val = env->mscratch; 1512 return RISCV_EXCP_NONE; 1513 } 1514 1515 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1516 target_ulong val) 1517 { 1518 env->mscratch = val; 1519 return RISCV_EXCP_NONE; 1520 } 1521 1522 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1523 target_ulong *val) 1524 { 1525 *val = env->mepc; 1526 return RISCV_EXCP_NONE; 1527 } 1528 1529 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1530 target_ulong val) 1531 { 1532 env->mepc = val; 1533 return RISCV_EXCP_NONE; 1534 } 1535 1536 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1537 target_ulong *val) 1538 { 1539 *val = env->mcause; 1540 return RISCV_EXCP_NONE; 1541 } 1542 1543 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1544 target_ulong val) 1545 { 1546 env->mcause = val; 1547 return RISCV_EXCP_NONE; 1548 } 1549 1550 static RISCVException read_mtval(CPURISCVState *env, int csrno, 1551 target_ulong *val) 1552 { 1553 *val = env->mtval; 1554 return RISCV_EXCP_NONE; 1555 } 1556 1557 static RISCVException write_mtval(CPURISCVState *env, int csrno, 1558 target_ulong val) 1559 { 1560 env->mtval = val; 1561 return RISCV_EXCP_NONE; 1562 } 1563 1564 /* Execution environment configuration setup */ 1565 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 1566 target_ulong *val) 1567 { 1568 *val = env->menvcfg; 1569 return RISCV_EXCP_NONE; 1570 } 1571 1572 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 1573 target_ulong val) 1574 { 1575 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 1576 1577 if (riscv_cpu_mxl(env) == MXL_RV64) { 1578 mask |= MENVCFG_PBMTE | MENVCFG_STCE; 1579 } 1580 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 1581 1582 return RISCV_EXCP_NONE; 1583 } 1584 1585 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 1586 target_ulong *val) 1587 { 1588 *val = env->menvcfg >> 32; 1589 return RISCV_EXCP_NONE; 1590 } 1591 1592 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 1593 target_ulong val) 1594 { 1595 uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; 1596 uint64_t valh = (uint64_t)val << 32; 1597 1598 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 1599 1600 return RISCV_EXCP_NONE; 1601 } 1602 1603 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 1604 target_ulong *val) 1605 { 1606 *val = env->senvcfg; 1607 return RISCV_EXCP_NONE; 1608 } 1609 1610 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 1611 target_ulong val) 1612 { 1613 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 1614 1615 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 1616 1617 return RISCV_EXCP_NONE; 1618 } 1619 1620 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 1621 target_ulong *val) 1622 { 1623 *val = env->henvcfg; 1624 return RISCV_EXCP_NONE; 1625 } 1626 1627 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 1628 target_ulong val) 1629 { 1630 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 1631 1632 if (riscv_cpu_mxl(env) == MXL_RV64) { 1633 mask |= HENVCFG_PBMTE | HENVCFG_STCE; 1634 } 1635 1636 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 1637 1638 return RISCV_EXCP_NONE; 1639 } 1640 1641 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 1642 target_ulong *val) 1643 { 1644 *val = env->henvcfg >> 32; 1645 return RISCV_EXCP_NONE; 1646 } 1647 1648 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 1649 target_ulong val) 1650 { 1651 uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; 1652 uint64_t valh = (uint64_t)val << 32; 1653 1654 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 1655 1656 return RISCV_EXCP_NONE; 1657 } 1658 1659 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 1660 uint64_t *ret_val, 1661 uint64_t new_val, uint64_t wr_mask) 1662 { 1663 RISCVCPU *cpu = env_archcpu(env); 1664 uint64_t old_mip, mask = wr_mask & delegable_ints; 1665 uint32_t gin; 1666 1667 if (mask & MIP_SEIP) { 1668 env->software_seip = new_val & MIP_SEIP; 1669 new_val |= env->external_seip * MIP_SEIP; 1670 } 1671 1672 if (mask) { 1673 old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); 1674 } else { 1675 old_mip = env->mip; 1676 } 1677 1678 if (csrno != CSR_HVIP) { 1679 gin = get_field(env->hstatus, HSTATUS_VGEIN); 1680 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 1681 } 1682 1683 if (ret_val) { 1684 *ret_val = old_mip; 1685 } 1686 1687 return RISCV_EXCP_NONE; 1688 } 1689 1690 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 1691 target_ulong *ret_val, 1692 target_ulong new_val, target_ulong wr_mask) 1693 { 1694 uint64_t rval; 1695 RISCVException ret; 1696 1697 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 1698 if (ret_val) { 1699 *ret_val = rval; 1700 } 1701 1702 return ret; 1703 } 1704 1705 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 1706 target_ulong *ret_val, 1707 target_ulong new_val, target_ulong wr_mask) 1708 { 1709 uint64_t rval; 1710 RISCVException ret; 1711 1712 ret = rmw_mip64(env, csrno, &rval, 1713 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1714 if (ret_val) { 1715 *ret_val = rval >> 32; 1716 } 1717 1718 return ret; 1719 } 1720 1721 /* Supervisor Trap Setup */ 1722 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 1723 Int128 *val) 1724 { 1725 uint64_t mask = sstatus_v1_10_mask; 1726 uint64_t sstatus = env->mstatus & mask; 1727 if (env->xl != MXL_RV32 || env->debugger) { 1728 mask |= SSTATUS64_UXL; 1729 } 1730 1731 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 1732 return RISCV_EXCP_NONE; 1733 } 1734 1735 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 1736 target_ulong *val) 1737 { 1738 target_ulong mask = (sstatus_v1_10_mask); 1739 if (env->xl != MXL_RV32 || env->debugger) { 1740 mask |= SSTATUS64_UXL; 1741 } 1742 /* TODO: Use SXL not MXL. */ 1743 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 1744 return RISCV_EXCP_NONE; 1745 } 1746 1747 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 1748 target_ulong val) 1749 { 1750 target_ulong mask = (sstatus_v1_10_mask); 1751 1752 if (env->xl != MXL_RV32 || env->debugger) { 1753 if ((val & SSTATUS64_UXL) != 0) { 1754 mask |= SSTATUS64_UXL; 1755 } 1756 } 1757 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 1758 return write_mstatus(env, CSR_MSTATUS, newval); 1759 } 1760 1761 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 1762 uint64_t *ret_val, 1763 uint64_t new_val, uint64_t wr_mask) 1764 { 1765 RISCVException ret; 1766 uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; 1767 1768 /* Bring VS-level bits to correct position */ 1769 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1770 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1771 new_val |= vsbits << 1; 1772 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1773 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1774 wr_mask |= vsbits << 1; 1775 1776 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); 1777 if (ret_val) { 1778 rval &= mask; 1779 vsbits = rval & VS_MODE_INTERRUPTS; 1780 rval &= ~VS_MODE_INTERRUPTS; 1781 *ret_val = rval | (vsbits >> 1); 1782 } 1783 1784 return ret; 1785 } 1786 1787 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 1788 target_ulong *ret_val, 1789 target_ulong new_val, target_ulong wr_mask) 1790 { 1791 uint64_t rval; 1792 RISCVException ret; 1793 1794 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 1795 if (ret_val) { 1796 *ret_val = rval; 1797 } 1798 1799 return ret; 1800 } 1801 1802 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 1803 target_ulong *ret_val, 1804 target_ulong new_val, target_ulong wr_mask) 1805 { 1806 uint64_t rval; 1807 RISCVException ret; 1808 1809 ret = rmw_vsie64(env, csrno, &rval, 1810 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1811 if (ret_val) { 1812 *ret_val = rval >> 32; 1813 } 1814 1815 return ret; 1816 } 1817 1818 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 1819 uint64_t *ret_val, 1820 uint64_t new_val, uint64_t wr_mask) 1821 { 1822 RISCVException ret; 1823 uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; 1824 1825 if (riscv_cpu_virt_enabled(env)) { 1826 if (env->hvictl & HVICTL_VTI) { 1827 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1828 } 1829 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 1830 } else { 1831 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); 1832 } 1833 1834 if (ret_val) { 1835 *ret_val &= mask; 1836 } 1837 1838 return ret; 1839 } 1840 1841 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 1842 target_ulong *ret_val, 1843 target_ulong new_val, target_ulong wr_mask) 1844 { 1845 uint64_t rval; 1846 RISCVException ret; 1847 1848 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 1849 if (ret == RISCV_EXCP_NONE && ret_val) { 1850 *ret_val = rval; 1851 } 1852 1853 return ret; 1854 } 1855 1856 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 1857 target_ulong *ret_val, 1858 target_ulong new_val, target_ulong wr_mask) 1859 { 1860 uint64_t rval; 1861 RISCVException ret; 1862 1863 ret = rmw_sie64(env, csrno, &rval, 1864 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1865 if (ret_val) { 1866 *ret_val = rval >> 32; 1867 } 1868 1869 return ret; 1870 } 1871 1872 static RISCVException read_stvec(CPURISCVState *env, int csrno, 1873 target_ulong *val) 1874 { 1875 *val = env->stvec; 1876 return RISCV_EXCP_NONE; 1877 } 1878 1879 static RISCVException write_stvec(CPURISCVState *env, int csrno, 1880 target_ulong val) 1881 { 1882 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1883 if ((val & 3) < 2) { 1884 env->stvec = val; 1885 } else { 1886 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 1887 } 1888 return RISCV_EXCP_NONE; 1889 } 1890 1891 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 1892 target_ulong *val) 1893 { 1894 *val = env->scounteren; 1895 return RISCV_EXCP_NONE; 1896 } 1897 1898 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 1899 target_ulong val) 1900 { 1901 env->scounteren = val; 1902 return RISCV_EXCP_NONE; 1903 } 1904 1905 /* Supervisor Trap Handling */ 1906 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 1907 Int128 *val) 1908 { 1909 *val = int128_make128(env->sscratch, env->sscratchh); 1910 return RISCV_EXCP_NONE; 1911 } 1912 1913 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 1914 Int128 val) 1915 { 1916 env->sscratch = int128_getlo(val); 1917 env->sscratchh = int128_gethi(val); 1918 return RISCV_EXCP_NONE; 1919 } 1920 1921 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 1922 target_ulong *val) 1923 { 1924 *val = env->sscratch; 1925 return RISCV_EXCP_NONE; 1926 } 1927 1928 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 1929 target_ulong val) 1930 { 1931 env->sscratch = val; 1932 return RISCV_EXCP_NONE; 1933 } 1934 1935 static RISCVException read_sepc(CPURISCVState *env, int csrno, 1936 target_ulong *val) 1937 { 1938 *val = env->sepc; 1939 return RISCV_EXCP_NONE; 1940 } 1941 1942 static RISCVException write_sepc(CPURISCVState *env, int csrno, 1943 target_ulong val) 1944 { 1945 env->sepc = val; 1946 return RISCV_EXCP_NONE; 1947 } 1948 1949 static RISCVException read_scause(CPURISCVState *env, int csrno, 1950 target_ulong *val) 1951 { 1952 *val = env->scause; 1953 return RISCV_EXCP_NONE; 1954 } 1955 1956 static RISCVException write_scause(CPURISCVState *env, int csrno, 1957 target_ulong val) 1958 { 1959 env->scause = val; 1960 return RISCV_EXCP_NONE; 1961 } 1962 1963 static RISCVException read_stval(CPURISCVState *env, int csrno, 1964 target_ulong *val) 1965 { 1966 *val = env->stval; 1967 return RISCV_EXCP_NONE; 1968 } 1969 1970 static RISCVException write_stval(CPURISCVState *env, int csrno, 1971 target_ulong val) 1972 { 1973 env->stval = val; 1974 return RISCV_EXCP_NONE; 1975 } 1976 1977 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 1978 uint64_t *ret_val, 1979 uint64_t new_val, uint64_t wr_mask) 1980 { 1981 RISCVException ret; 1982 uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; 1983 1984 /* Bring VS-level bits to correct position */ 1985 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1986 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1987 new_val |= vsbits << 1; 1988 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1989 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1990 wr_mask |= vsbits << 1; 1991 1992 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); 1993 if (ret_val) { 1994 rval &= mask; 1995 vsbits = rval & VS_MODE_INTERRUPTS; 1996 rval &= ~VS_MODE_INTERRUPTS; 1997 *ret_val = rval | (vsbits >> 1); 1998 } 1999 2000 return ret; 2001 } 2002 2003 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 2004 target_ulong *ret_val, 2005 target_ulong new_val, target_ulong wr_mask) 2006 { 2007 uint64_t rval; 2008 RISCVException ret; 2009 2010 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 2011 if (ret_val) { 2012 *ret_val = rval; 2013 } 2014 2015 return ret; 2016 } 2017 2018 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 2019 target_ulong *ret_val, 2020 target_ulong new_val, target_ulong wr_mask) 2021 { 2022 uint64_t rval; 2023 RISCVException ret; 2024 2025 ret = rmw_vsip64(env, csrno, &rval, 2026 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2027 if (ret_val) { 2028 *ret_val = rval >> 32; 2029 } 2030 2031 return ret; 2032 } 2033 2034 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 2035 uint64_t *ret_val, 2036 uint64_t new_val, uint64_t wr_mask) 2037 { 2038 RISCVException ret; 2039 uint64_t mask = env->mideleg & sip_writable_mask; 2040 2041 if (riscv_cpu_virt_enabled(env)) { 2042 if (env->hvictl & HVICTL_VTI) { 2043 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2044 } 2045 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 2046 } else { 2047 ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); 2048 } 2049 2050 if (ret_val) { 2051 *ret_val &= env->mideleg & S_MODE_INTERRUPTS; 2052 } 2053 2054 return ret; 2055 } 2056 2057 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 2058 target_ulong *ret_val, 2059 target_ulong new_val, target_ulong wr_mask) 2060 { 2061 uint64_t rval; 2062 RISCVException ret; 2063 2064 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 2065 if (ret_val) { 2066 *ret_val = rval; 2067 } 2068 2069 return ret; 2070 } 2071 2072 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 2073 target_ulong *ret_val, 2074 target_ulong new_val, target_ulong wr_mask) 2075 { 2076 uint64_t rval; 2077 RISCVException ret; 2078 2079 ret = rmw_sip64(env, csrno, &rval, 2080 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2081 if (ret_val) { 2082 *ret_val = rval >> 32; 2083 } 2084 2085 return ret; 2086 } 2087 2088 /* Supervisor Protection and Translation */ 2089 static RISCVException read_satp(CPURISCVState *env, int csrno, 2090 target_ulong *val) 2091 { 2092 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2093 *val = 0; 2094 return RISCV_EXCP_NONE; 2095 } 2096 2097 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2098 return RISCV_EXCP_ILLEGAL_INST; 2099 } else { 2100 *val = env->satp; 2101 } 2102 2103 return RISCV_EXCP_NONE; 2104 } 2105 2106 static RISCVException write_satp(CPURISCVState *env, int csrno, 2107 target_ulong val) 2108 { 2109 target_ulong vm, mask; 2110 2111 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 2112 return RISCV_EXCP_NONE; 2113 } 2114 2115 if (riscv_cpu_mxl(env) == MXL_RV32) { 2116 vm = validate_vm(env, get_field(val, SATP32_MODE)); 2117 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 2118 } else { 2119 vm = validate_vm(env, get_field(val, SATP64_MODE)); 2120 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 2121 } 2122 2123 if (vm && mask) { 2124 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 2125 return RISCV_EXCP_ILLEGAL_INST; 2126 } else { 2127 /* 2128 * The ISA defines SATP.MODE=Bare as "no translation", but we still 2129 * pass these through QEMU's TLB emulation as it improves 2130 * performance. Flushing the TLB on SATP writes with paging 2131 * enabled avoids leaking those invalid cached mappings. 2132 */ 2133 tlb_flush(env_cpu(env)); 2134 env->satp = val; 2135 } 2136 } 2137 return RISCV_EXCP_NONE; 2138 } 2139 2140 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 2141 { 2142 int irq, ret; 2143 target_ulong topei; 2144 uint64_t vseip, vsgein; 2145 uint32_t iid, iprio, hviid, hviprio, gein; 2146 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 2147 2148 gein = get_field(env->hstatus, HSTATUS_VGEIN); 2149 hviid = get_field(env->hvictl, HVICTL_IID); 2150 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 2151 2152 if (gein) { 2153 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 2154 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 2155 if (gein <= env->geilen && vseip) { 2156 siid[scount] = IRQ_S_EXT; 2157 siprio[scount] = IPRIO_MMAXIPRIO + 1; 2158 if (env->aia_ireg_rmw_fn[PRV_S]) { 2159 /* 2160 * Call machine specific IMSIC register emulation for 2161 * reading TOPEI. 2162 */ 2163 ret = env->aia_ireg_rmw_fn[PRV_S]( 2164 env->aia_ireg_rmw_fn_arg[PRV_S], 2165 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 2166 riscv_cpu_mxl_bits(env)), 2167 &topei, 0, 0); 2168 if (!ret && topei) { 2169 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 2170 } 2171 } 2172 scount++; 2173 } 2174 } else { 2175 if (hviid == IRQ_S_EXT && hviprio) { 2176 siid[scount] = IRQ_S_EXT; 2177 siprio[scount] = hviprio; 2178 scount++; 2179 } 2180 } 2181 2182 if (env->hvictl & HVICTL_VTI) { 2183 if (hviid != IRQ_S_EXT) { 2184 siid[scount] = hviid; 2185 siprio[scount] = hviprio; 2186 scount++; 2187 } 2188 } else { 2189 irq = riscv_cpu_vsirq_pending(env); 2190 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 2191 siid[scount] = irq; 2192 siprio[scount] = env->hviprio[irq]; 2193 scount++; 2194 } 2195 } 2196 2197 iid = 0; 2198 iprio = UINT_MAX; 2199 for (s = 0; s < scount; s++) { 2200 if (siprio[s] < iprio) { 2201 iid = siid[s]; 2202 iprio = siprio[s]; 2203 } 2204 } 2205 2206 if (iid) { 2207 if (env->hvictl & HVICTL_IPRIOM) { 2208 if (iprio > IPRIO_MMAXIPRIO) { 2209 iprio = IPRIO_MMAXIPRIO; 2210 } 2211 if (!iprio) { 2212 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 2213 iprio = IPRIO_MMAXIPRIO; 2214 } 2215 } 2216 } else { 2217 iprio = 1; 2218 } 2219 } else { 2220 iprio = 0; 2221 } 2222 2223 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2224 *val |= iprio; 2225 return RISCV_EXCP_NONE; 2226 } 2227 2228 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 2229 { 2230 int irq; 2231 uint8_t iprio; 2232 2233 if (riscv_cpu_virt_enabled(env)) { 2234 return read_vstopi(env, CSR_VSTOPI, val); 2235 } 2236 2237 irq = riscv_cpu_sirq_pending(env); 2238 if (irq <= 0 || irq > 63) { 2239 *val = 0; 2240 } else { 2241 iprio = env->siprio[irq]; 2242 if (!iprio) { 2243 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 2244 iprio = IPRIO_MMAXIPRIO; 2245 } 2246 } 2247 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2248 *val |= iprio; 2249 } 2250 2251 return RISCV_EXCP_NONE; 2252 } 2253 2254 /* Hypervisor Extensions */ 2255 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 2256 target_ulong *val) 2257 { 2258 *val = env->hstatus; 2259 if (riscv_cpu_mxl(env) != MXL_RV32) { 2260 /* We only support 64-bit VSXL */ 2261 *val = set_field(*val, HSTATUS_VSXL, 2); 2262 } 2263 /* We only support little endian */ 2264 *val = set_field(*val, HSTATUS_VSBE, 0); 2265 return RISCV_EXCP_NONE; 2266 } 2267 2268 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 2269 target_ulong val) 2270 { 2271 env->hstatus = val; 2272 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 2273 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 2274 } 2275 if (get_field(val, HSTATUS_VSBE) != 0) { 2276 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 2277 } 2278 return RISCV_EXCP_NONE; 2279 } 2280 2281 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 2282 target_ulong *val) 2283 { 2284 *val = env->hedeleg; 2285 return RISCV_EXCP_NONE; 2286 } 2287 2288 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 2289 target_ulong val) 2290 { 2291 env->hedeleg = val & vs_delegable_excps; 2292 return RISCV_EXCP_NONE; 2293 } 2294 2295 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 2296 uint64_t *ret_val, 2297 uint64_t new_val, uint64_t wr_mask) 2298 { 2299 uint64_t mask = wr_mask & vs_delegable_ints; 2300 2301 if (ret_val) { 2302 *ret_val = env->hideleg & vs_delegable_ints; 2303 } 2304 2305 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 2306 return RISCV_EXCP_NONE; 2307 } 2308 2309 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 2310 target_ulong *ret_val, 2311 target_ulong new_val, target_ulong wr_mask) 2312 { 2313 uint64_t rval; 2314 RISCVException ret; 2315 2316 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 2317 if (ret_val) { 2318 *ret_val = rval; 2319 } 2320 2321 return ret; 2322 } 2323 2324 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 2325 target_ulong *ret_val, 2326 target_ulong new_val, target_ulong wr_mask) 2327 { 2328 uint64_t rval; 2329 RISCVException ret; 2330 2331 ret = rmw_hideleg64(env, csrno, &rval, 2332 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2333 if (ret_val) { 2334 *ret_val = rval >> 32; 2335 } 2336 2337 return ret; 2338 } 2339 2340 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2341 uint64_t *ret_val, 2342 uint64_t new_val, uint64_t wr_mask) 2343 { 2344 RISCVException ret; 2345 2346 ret = rmw_mip64(env, csrno, ret_val, new_val, 2347 wr_mask & hvip_writable_mask); 2348 if (ret_val) { 2349 *ret_val &= VS_MODE_INTERRUPTS; 2350 } 2351 2352 return ret; 2353 } 2354 2355 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 2356 target_ulong *ret_val, 2357 target_ulong new_val, target_ulong wr_mask) 2358 { 2359 uint64_t rval; 2360 RISCVException ret; 2361 2362 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 2363 if (ret_val) { 2364 *ret_val = rval; 2365 } 2366 2367 return ret; 2368 } 2369 2370 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 2371 target_ulong *ret_val, 2372 target_ulong new_val, target_ulong wr_mask) 2373 { 2374 uint64_t rval; 2375 RISCVException ret; 2376 2377 ret = rmw_hvip64(env, csrno, &rval, 2378 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2379 if (ret_val) { 2380 *ret_val = rval >> 32; 2381 } 2382 2383 return ret; 2384 } 2385 2386 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 2387 target_ulong *ret_value, 2388 target_ulong new_value, target_ulong write_mask) 2389 { 2390 int ret = rmw_mip(env, csrno, ret_value, new_value, 2391 write_mask & hip_writable_mask); 2392 2393 if (ret_value) { 2394 *ret_value &= HS_MODE_INTERRUPTS; 2395 } 2396 return ret; 2397 } 2398 2399 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 2400 target_ulong *ret_val, 2401 target_ulong new_val, target_ulong wr_mask) 2402 { 2403 uint64_t rval; 2404 RISCVException ret; 2405 2406 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 2407 if (ret_val) { 2408 *ret_val = rval & HS_MODE_INTERRUPTS; 2409 } 2410 2411 return ret; 2412 } 2413 2414 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 2415 target_ulong *val) 2416 { 2417 *val = env->hcounteren; 2418 return RISCV_EXCP_NONE; 2419 } 2420 2421 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 2422 target_ulong val) 2423 { 2424 env->hcounteren = val; 2425 return RISCV_EXCP_NONE; 2426 } 2427 2428 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 2429 target_ulong *val) 2430 { 2431 if (val) { 2432 *val = env->hgeie; 2433 } 2434 return RISCV_EXCP_NONE; 2435 } 2436 2437 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 2438 target_ulong val) 2439 { 2440 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 2441 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 2442 env->hgeie = val; 2443 /* Update mip.SGEIP bit */ 2444 riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, 2445 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 2446 return RISCV_EXCP_NONE; 2447 } 2448 2449 static RISCVException read_htval(CPURISCVState *env, int csrno, 2450 target_ulong *val) 2451 { 2452 *val = env->htval; 2453 return RISCV_EXCP_NONE; 2454 } 2455 2456 static RISCVException write_htval(CPURISCVState *env, int csrno, 2457 target_ulong val) 2458 { 2459 env->htval = val; 2460 return RISCV_EXCP_NONE; 2461 } 2462 2463 static RISCVException read_htinst(CPURISCVState *env, int csrno, 2464 target_ulong *val) 2465 { 2466 *val = env->htinst; 2467 return RISCV_EXCP_NONE; 2468 } 2469 2470 static RISCVException write_htinst(CPURISCVState *env, int csrno, 2471 target_ulong val) 2472 { 2473 return RISCV_EXCP_NONE; 2474 } 2475 2476 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 2477 target_ulong *val) 2478 { 2479 if (val) { 2480 *val = env->hgeip; 2481 } 2482 return RISCV_EXCP_NONE; 2483 } 2484 2485 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 2486 target_ulong *val) 2487 { 2488 *val = env->hgatp; 2489 return RISCV_EXCP_NONE; 2490 } 2491 2492 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 2493 target_ulong val) 2494 { 2495 env->hgatp = val; 2496 return RISCV_EXCP_NONE; 2497 } 2498 2499 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 2500 target_ulong *val) 2501 { 2502 if (!env->rdtime_fn) { 2503 return RISCV_EXCP_ILLEGAL_INST; 2504 } 2505 2506 *val = env->htimedelta; 2507 return RISCV_EXCP_NONE; 2508 } 2509 2510 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 2511 target_ulong val) 2512 { 2513 if (!env->rdtime_fn) { 2514 return RISCV_EXCP_ILLEGAL_INST; 2515 } 2516 2517 if (riscv_cpu_mxl(env) == MXL_RV32) { 2518 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 2519 } else { 2520 env->htimedelta = val; 2521 } 2522 return RISCV_EXCP_NONE; 2523 } 2524 2525 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 2526 target_ulong *val) 2527 { 2528 if (!env->rdtime_fn) { 2529 return RISCV_EXCP_ILLEGAL_INST; 2530 } 2531 2532 *val = env->htimedelta >> 32; 2533 return RISCV_EXCP_NONE; 2534 } 2535 2536 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 2537 target_ulong val) 2538 { 2539 if (!env->rdtime_fn) { 2540 return RISCV_EXCP_ILLEGAL_INST; 2541 } 2542 2543 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 2544 return RISCV_EXCP_NONE; 2545 } 2546 2547 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 2548 { 2549 *val = env->hvictl; 2550 return RISCV_EXCP_NONE; 2551 } 2552 2553 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 2554 { 2555 env->hvictl = val & HVICTL_VALID_MASK; 2556 return RISCV_EXCP_NONE; 2557 } 2558 2559 static int read_hvipriox(CPURISCVState *env, int first_index, 2560 uint8_t *iprio, target_ulong *val) 2561 { 2562 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2563 2564 /* First index has to be a multiple of number of irqs per register */ 2565 if (first_index % num_irqs) { 2566 return (riscv_cpu_virt_enabled(env)) ? 2567 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2568 } 2569 2570 /* Fill-up return value */ 2571 *val = 0; 2572 for (i = 0; i < num_irqs; i++) { 2573 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2574 continue; 2575 } 2576 if (rdzero) { 2577 continue; 2578 } 2579 *val |= ((target_ulong)iprio[irq]) << (i * 8); 2580 } 2581 2582 return RISCV_EXCP_NONE; 2583 } 2584 2585 static int write_hvipriox(CPURISCVState *env, int first_index, 2586 uint8_t *iprio, target_ulong val) 2587 { 2588 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2589 2590 /* First index has to be a multiple of number of irqs per register */ 2591 if (first_index % num_irqs) { 2592 return (riscv_cpu_virt_enabled(env)) ? 2593 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2594 } 2595 2596 /* Fill-up priority arrary */ 2597 for (i = 0; i < num_irqs; i++) { 2598 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2599 continue; 2600 } 2601 if (rdzero) { 2602 iprio[irq] = 0; 2603 } else { 2604 iprio[irq] = (val >> (i * 8)) & 0xff; 2605 } 2606 } 2607 2608 return RISCV_EXCP_NONE; 2609 } 2610 2611 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 2612 { 2613 return read_hvipriox(env, 0, env->hviprio, val); 2614 } 2615 2616 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 2617 { 2618 return write_hvipriox(env, 0, env->hviprio, val); 2619 } 2620 2621 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 2622 { 2623 return read_hvipriox(env, 4, env->hviprio, val); 2624 } 2625 2626 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 2627 { 2628 return write_hvipriox(env, 4, env->hviprio, val); 2629 } 2630 2631 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 2632 { 2633 return read_hvipriox(env, 8, env->hviprio, val); 2634 } 2635 2636 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 2637 { 2638 return write_hvipriox(env, 8, env->hviprio, val); 2639 } 2640 2641 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 2642 { 2643 return read_hvipriox(env, 12, env->hviprio, val); 2644 } 2645 2646 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 2647 { 2648 return write_hvipriox(env, 12, env->hviprio, val); 2649 } 2650 2651 /* Virtual CSR Registers */ 2652 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 2653 target_ulong *val) 2654 { 2655 *val = env->vsstatus; 2656 return RISCV_EXCP_NONE; 2657 } 2658 2659 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 2660 target_ulong val) 2661 { 2662 uint64_t mask = (target_ulong)-1; 2663 if ((val & VSSTATUS64_UXL) == 0) { 2664 mask &= ~VSSTATUS64_UXL; 2665 } 2666 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 2667 return RISCV_EXCP_NONE; 2668 } 2669 2670 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 2671 { 2672 *val = env->vstvec; 2673 return RISCV_EXCP_NONE; 2674 } 2675 2676 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 2677 target_ulong val) 2678 { 2679 env->vstvec = val; 2680 return RISCV_EXCP_NONE; 2681 } 2682 2683 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 2684 target_ulong *val) 2685 { 2686 *val = env->vsscratch; 2687 return RISCV_EXCP_NONE; 2688 } 2689 2690 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 2691 target_ulong val) 2692 { 2693 env->vsscratch = val; 2694 return RISCV_EXCP_NONE; 2695 } 2696 2697 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 2698 target_ulong *val) 2699 { 2700 *val = env->vsepc; 2701 return RISCV_EXCP_NONE; 2702 } 2703 2704 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 2705 target_ulong val) 2706 { 2707 env->vsepc = val; 2708 return RISCV_EXCP_NONE; 2709 } 2710 2711 static RISCVException read_vscause(CPURISCVState *env, int csrno, 2712 target_ulong *val) 2713 { 2714 *val = env->vscause; 2715 return RISCV_EXCP_NONE; 2716 } 2717 2718 static RISCVException write_vscause(CPURISCVState *env, int csrno, 2719 target_ulong val) 2720 { 2721 env->vscause = val; 2722 return RISCV_EXCP_NONE; 2723 } 2724 2725 static RISCVException read_vstval(CPURISCVState *env, int csrno, 2726 target_ulong *val) 2727 { 2728 *val = env->vstval; 2729 return RISCV_EXCP_NONE; 2730 } 2731 2732 static RISCVException write_vstval(CPURISCVState *env, int csrno, 2733 target_ulong val) 2734 { 2735 env->vstval = val; 2736 return RISCV_EXCP_NONE; 2737 } 2738 2739 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 2740 target_ulong *val) 2741 { 2742 *val = env->vsatp; 2743 return RISCV_EXCP_NONE; 2744 } 2745 2746 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 2747 target_ulong val) 2748 { 2749 env->vsatp = val; 2750 return RISCV_EXCP_NONE; 2751 } 2752 2753 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 2754 target_ulong *val) 2755 { 2756 *val = env->mtval2; 2757 return RISCV_EXCP_NONE; 2758 } 2759 2760 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 2761 target_ulong val) 2762 { 2763 env->mtval2 = val; 2764 return RISCV_EXCP_NONE; 2765 } 2766 2767 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 2768 target_ulong *val) 2769 { 2770 *val = env->mtinst; 2771 return RISCV_EXCP_NONE; 2772 } 2773 2774 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 2775 target_ulong val) 2776 { 2777 env->mtinst = val; 2778 return RISCV_EXCP_NONE; 2779 } 2780 2781 /* Physical Memory Protection */ 2782 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 2783 target_ulong *val) 2784 { 2785 *val = mseccfg_csr_read(env); 2786 return RISCV_EXCP_NONE; 2787 } 2788 2789 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 2790 target_ulong val) 2791 { 2792 mseccfg_csr_write(env, val); 2793 return RISCV_EXCP_NONE; 2794 } 2795 2796 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) 2797 { 2798 /* TODO: RV128 restriction check */ 2799 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 2800 return false; 2801 } 2802 return true; 2803 } 2804 2805 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 2806 target_ulong *val) 2807 { 2808 uint32_t reg_index = csrno - CSR_PMPCFG0; 2809 2810 if (!check_pmp_reg_index(env, reg_index)) { 2811 return RISCV_EXCP_ILLEGAL_INST; 2812 } 2813 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 2814 return RISCV_EXCP_NONE; 2815 } 2816 2817 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 2818 target_ulong val) 2819 { 2820 uint32_t reg_index = csrno - CSR_PMPCFG0; 2821 2822 if (!check_pmp_reg_index(env, reg_index)) { 2823 return RISCV_EXCP_ILLEGAL_INST; 2824 } 2825 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 2826 return RISCV_EXCP_NONE; 2827 } 2828 2829 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 2830 target_ulong *val) 2831 { 2832 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 2833 return RISCV_EXCP_NONE; 2834 } 2835 2836 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 2837 target_ulong val) 2838 { 2839 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 2840 return RISCV_EXCP_NONE; 2841 } 2842 2843 static RISCVException read_tselect(CPURISCVState *env, int csrno, 2844 target_ulong *val) 2845 { 2846 *val = tselect_csr_read(env); 2847 return RISCV_EXCP_NONE; 2848 } 2849 2850 static RISCVException write_tselect(CPURISCVState *env, int csrno, 2851 target_ulong val) 2852 { 2853 tselect_csr_write(env, val); 2854 return RISCV_EXCP_NONE; 2855 } 2856 2857 static RISCVException read_tdata(CPURISCVState *env, int csrno, 2858 target_ulong *val) 2859 { 2860 /* return 0 in tdata1 to end the trigger enumeration */ 2861 if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { 2862 *val = 0; 2863 return RISCV_EXCP_NONE; 2864 } 2865 2866 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2867 return RISCV_EXCP_ILLEGAL_INST; 2868 } 2869 2870 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 2871 return RISCV_EXCP_NONE; 2872 } 2873 2874 static RISCVException write_tdata(CPURISCVState *env, int csrno, 2875 target_ulong val) 2876 { 2877 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2878 return RISCV_EXCP_ILLEGAL_INST; 2879 } 2880 2881 tdata_csr_write(env, csrno - CSR_TDATA1, val); 2882 return RISCV_EXCP_NONE; 2883 } 2884 2885 /* 2886 * Functions to access Pointer Masking feature registers 2887 * We have to check if current priv lvl could modify 2888 * csr in given mode 2889 */ 2890 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 2891 { 2892 int csr_priv = get_field(csrno, 0x300); 2893 int pm_current; 2894 2895 if (env->debugger) { 2896 return false; 2897 } 2898 /* 2899 * If priv lvls differ that means we're accessing csr from higher priv lvl, 2900 * so allow the access 2901 */ 2902 if (env->priv != csr_priv) { 2903 return false; 2904 } 2905 switch (env->priv) { 2906 case PRV_M: 2907 pm_current = get_field(env->mmte, M_PM_CURRENT); 2908 break; 2909 case PRV_S: 2910 pm_current = get_field(env->mmte, S_PM_CURRENT); 2911 break; 2912 case PRV_U: 2913 pm_current = get_field(env->mmte, U_PM_CURRENT); 2914 break; 2915 default: 2916 g_assert_not_reached(); 2917 } 2918 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 2919 return !pm_current; 2920 } 2921 2922 static RISCVException read_mmte(CPURISCVState *env, int csrno, 2923 target_ulong *val) 2924 { 2925 *val = env->mmte & MMTE_MASK; 2926 return RISCV_EXCP_NONE; 2927 } 2928 2929 static RISCVException write_mmte(CPURISCVState *env, int csrno, 2930 target_ulong val) 2931 { 2932 uint64_t mstatus; 2933 target_ulong wpri_val = val & MMTE_MASK; 2934 2935 if (val != wpri_val) { 2936 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2937 "MMTE: WPRI violation written 0x", val, 2938 "vs expected 0x", wpri_val); 2939 } 2940 /* for machine mode pm.current is hardwired to 1 */ 2941 wpri_val |= MMTE_M_PM_CURRENT; 2942 2943 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 2944 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 2945 env->mmte = wpri_val | PM_EXT_DIRTY; 2946 riscv_cpu_update_mask(env); 2947 2948 /* Set XS and SD bits, since PM CSRs are dirty */ 2949 mstatus = env->mstatus | MSTATUS_XS; 2950 write_mstatus(env, csrno, mstatus); 2951 return RISCV_EXCP_NONE; 2952 } 2953 2954 static RISCVException read_smte(CPURISCVState *env, int csrno, 2955 target_ulong *val) 2956 { 2957 *val = env->mmte & SMTE_MASK; 2958 return RISCV_EXCP_NONE; 2959 } 2960 2961 static RISCVException write_smte(CPURISCVState *env, int csrno, 2962 target_ulong val) 2963 { 2964 target_ulong wpri_val = val & SMTE_MASK; 2965 2966 if (val != wpri_val) { 2967 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2968 "SMTE: WPRI violation written 0x", val, 2969 "vs expected 0x", wpri_val); 2970 } 2971 2972 /* if pm.current==0 we can't modify current PM CSRs */ 2973 if (check_pm_current_disabled(env, csrno)) { 2974 return RISCV_EXCP_NONE; 2975 } 2976 2977 wpri_val |= (env->mmte & ~SMTE_MASK); 2978 write_mmte(env, csrno, wpri_val); 2979 return RISCV_EXCP_NONE; 2980 } 2981 2982 static RISCVException read_umte(CPURISCVState *env, int csrno, 2983 target_ulong *val) 2984 { 2985 *val = env->mmte & UMTE_MASK; 2986 return RISCV_EXCP_NONE; 2987 } 2988 2989 static RISCVException write_umte(CPURISCVState *env, int csrno, 2990 target_ulong val) 2991 { 2992 target_ulong wpri_val = val & UMTE_MASK; 2993 2994 if (val != wpri_val) { 2995 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2996 "UMTE: WPRI violation written 0x", val, 2997 "vs expected 0x", wpri_val); 2998 } 2999 3000 if (check_pm_current_disabled(env, csrno)) { 3001 return RISCV_EXCP_NONE; 3002 } 3003 3004 wpri_val |= (env->mmte & ~UMTE_MASK); 3005 write_mmte(env, csrno, wpri_val); 3006 return RISCV_EXCP_NONE; 3007 } 3008 3009 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 3010 target_ulong *val) 3011 { 3012 *val = env->mpmmask; 3013 return RISCV_EXCP_NONE; 3014 } 3015 3016 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 3017 target_ulong val) 3018 { 3019 uint64_t mstatus; 3020 3021 env->mpmmask = val; 3022 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 3023 env->cur_pmmask = val; 3024 } 3025 env->mmte |= PM_EXT_DIRTY; 3026 3027 /* Set XS and SD bits, since PM CSRs are dirty */ 3028 mstatus = env->mstatus | MSTATUS_XS; 3029 write_mstatus(env, csrno, mstatus); 3030 return RISCV_EXCP_NONE; 3031 } 3032 3033 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 3034 target_ulong *val) 3035 { 3036 *val = env->spmmask; 3037 return RISCV_EXCP_NONE; 3038 } 3039 3040 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 3041 target_ulong val) 3042 { 3043 uint64_t mstatus; 3044 3045 /* if pm.current==0 we can't modify current PM CSRs */ 3046 if (check_pm_current_disabled(env, csrno)) { 3047 return RISCV_EXCP_NONE; 3048 } 3049 env->spmmask = val; 3050 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3051 env->cur_pmmask = val; 3052 } 3053 env->mmte |= PM_EXT_DIRTY; 3054 3055 /* Set XS and SD bits, since PM CSRs are dirty */ 3056 mstatus = env->mstatus | MSTATUS_XS; 3057 write_mstatus(env, csrno, mstatus); 3058 return RISCV_EXCP_NONE; 3059 } 3060 3061 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 3062 target_ulong *val) 3063 { 3064 *val = env->upmmask; 3065 return RISCV_EXCP_NONE; 3066 } 3067 3068 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 3069 target_ulong val) 3070 { 3071 uint64_t mstatus; 3072 3073 /* if pm.current==0 we can't modify current PM CSRs */ 3074 if (check_pm_current_disabled(env, csrno)) { 3075 return RISCV_EXCP_NONE; 3076 } 3077 env->upmmask = val; 3078 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3079 env->cur_pmmask = val; 3080 } 3081 env->mmte |= PM_EXT_DIRTY; 3082 3083 /* Set XS and SD bits, since PM CSRs are dirty */ 3084 mstatus = env->mstatus | MSTATUS_XS; 3085 write_mstatus(env, csrno, mstatus); 3086 return RISCV_EXCP_NONE; 3087 } 3088 3089 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 3090 target_ulong *val) 3091 { 3092 *val = env->mpmbase; 3093 return RISCV_EXCP_NONE; 3094 } 3095 3096 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 3097 target_ulong val) 3098 { 3099 uint64_t mstatus; 3100 3101 env->mpmbase = val; 3102 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 3103 env->cur_pmbase = val; 3104 } 3105 env->mmte |= PM_EXT_DIRTY; 3106 3107 /* Set XS and SD bits, since PM CSRs are dirty */ 3108 mstatus = env->mstatus | MSTATUS_XS; 3109 write_mstatus(env, csrno, mstatus); 3110 return RISCV_EXCP_NONE; 3111 } 3112 3113 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 3114 target_ulong *val) 3115 { 3116 *val = env->spmbase; 3117 return RISCV_EXCP_NONE; 3118 } 3119 3120 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 3121 target_ulong val) 3122 { 3123 uint64_t mstatus; 3124 3125 /* if pm.current==0 we can't modify current PM CSRs */ 3126 if (check_pm_current_disabled(env, csrno)) { 3127 return RISCV_EXCP_NONE; 3128 } 3129 env->spmbase = val; 3130 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 3131 env->cur_pmbase = val; 3132 } 3133 env->mmte |= PM_EXT_DIRTY; 3134 3135 /* Set XS and SD bits, since PM CSRs are dirty */ 3136 mstatus = env->mstatus | MSTATUS_XS; 3137 write_mstatus(env, csrno, mstatus); 3138 return RISCV_EXCP_NONE; 3139 } 3140 3141 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 3142 target_ulong *val) 3143 { 3144 *val = env->upmbase; 3145 return RISCV_EXCP_NONE; 3146 } 3147 3148 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 3149 target_ulong val) 3150 { 3151 uint64_t mstatus; 3152 3153 /* if pm.current==0 we can't modify current PM CSRs */ 3154 if (check_pm_current_disabled(env, csrno)) { 3155 return RISCV_EXCP_NONE; 3156 } 3157 env->upmbase = val; 3158 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3159 env->cur_pmbase = val; 3160 } 3161 env->mmte |= PM_EXT_DIRTY; 3162 3163 /* Set XS and SD bits, since PM CSRs are dirty */ 3164 mstatus = env->mstatus | MSTATUS_XS; 3165 write_mstatus(env, csrno, mstatus); 3166 return RISCV_EXCP_NONE; 3167 } 3168 3169 #endif 3170 3171 /* Crypto Extension */ 3172 static RISCVException rmw_seed(CPURISCVState *env, int csrno, 3173 target_ulong *ret_value, 3174 target_ulong new_value, 3175 target_ulong write_mask) 3176 { 3177 uint16_t random_v; 3178 Error *random_e = NULL; 3179 int random_r; 3180 target_ulong rval; 3181 3182 random_r = qemu_guest_getrandom(&random_v, 2, &random_e); 3183 if (unlikely(random_r < 0)) { 3184 /* 3185 * Failed, for unknown reasons in the crypto subsystem. 3186 * The best we can do is log the reason and return a 3187 * failure indication to the guest. There is no reason 3188 * we know to expect the failure to be transitory, so 3189 * indicate DEAD to avoid having the guest spin on WAIT. 3190 */ 3191 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 3192 __func__, error_get_pretty(random_e)); 3193 error_free(random_e); 3194 rval = SEED_OPST_DEAD; 3195 } else { 3196 rval = random_v | SEED_OPST_ES16; 3197 } 3198 3199 if (ret_value) { 3200 *ret_value = rval; 3201 } 3202 3203 return RISCV_EXCP_NONE; 3204 } 3205 3206 /* 3207 * riscv_csrrw - read and/or update control and status register 3208 * 3209 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 3210 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 3211 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 3212 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 3213 */ 3214 3215 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 3216 int csrno, 3217 bool write_mask, 3218 RISCVCPU *cpu) 3219 { 3220 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 3221 int read_only = get_field(csrno, 0xC00) == 3; 3222 int csr_min_priv = csr_ops[csrno].min_priv_ver; 3223 #if !defined(CONFIG_USER_ONLY) 3224 int csr_priv, effective_priv = env->priv; 3225 3226 if (riscv_has_ext(env, RVH) && env->priv == PRV_S) { 3227 /* 3228 * We are in either HS or VS mode. 3229 * Add 1 to the effective privledge level to allow us to access the 3230 * Hypervisor CSRs. The `hmode` predicate will determine if access 3231 * should be allowed(HS) or if a virtual instruction exception should be 3232 * raised(VS). 3233 */ 3234 effective_priv++; 3235 } 3236 3237 csr_priv = get_field(csrno, 0x300); 3238 if (!env->debugger && (effective_priv < csr_priv)) { 3239 if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { 3240 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 3241 } 3242 return RISCV_EXCP_ILLEGAL_INST; 3243 } 3244 #endif 3245 if (write_mask && read_only) { 3246 return RISCV_EXCP_ILLEGAL_INST; 3247 } 3248 3249 /* ensure the CSR extension is enabled. */ 3250 if (!cpu->cfg.ext_icsr) { 3251 return RISCV_EXCP_ILLEGAL_INST; 3252 } 3253 3254 /* check predicate */ 3255 if (!csr_ops[csrno].predicate) { 3256 return RISCV_EXCP_ILLEGAL_INST; 3257 } 3258 3259 if (env->priv_ver < csr_min_priv) { 3260 return RISCV_EXCP_ILLEGAL_INST; 3261 } 3262 3263 return csr_ops[csrno].predicate(env, csrno); 3264 } 3265 3266 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 3267 target_ulong *ret_value, 3268 target_ulong new_value, 3269 target_ulong write_mask) 3270 { 3271 RISCVException ret; 3272 target_ulong old_value; 3273 3274 /* execute combined read/write operation if it exists */ 3275 if (csr_ops[csrno].op) { 3276 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 3277 } 3278 3279 /* if no accessor exists then return failure */ 3280 if (!csr_ops[csrno].read) { 3281 return RISCV_EXCP_ILLEGAL_INST; 3282 } 3283 /* read old value */ 3284 ret = csr_ops[csrno].read(env, csrno, &old_value); 3285 if (ret != RISCV_EXCP_NONE) { 3286 return ret; 3287 } 3288 3289 /* write value if writable and write mask set, otherwise drop writes */ 3290 if (write_mask) { 3291 new_value = (old_value & ~write_mask) | (new_value & write_mask); 3292 if (csr_ops[csrno].write) { 3293 ret = csr_ops[csrno].write(env, csrno, new_value); 3294 if (ret != RISCV_EXCP_NONE) { 3295 return ret; 3296 } 3297 } 3298 } 3299 3300 /* return old value */ 3301 if (ret_value) { 3302 *ret_value = old_value; 3303 } 3304 3305 return RISCV_EXCP_NONE; 3306 } 3307 3308 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 3309 target_ulong *ret_value, 3310 target_ulong new_value, target_ulong write_mask) 3311 { 3312 RISCVCPU *cpu = env_archcpu(env); 3313 3314 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); 3315 if (ret != RISCV_EXCP_NONE) { 3316 return ret; 3317 } 3318 3319 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 3320 } 3321 3322 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 3323 Int128 *ret_value, 3324 Int128 new_value, 3325 Int128 write_mask) 3326 { 3327 RISCVException ret; 3328 Int128 old_value; 3329 3330 /* read old value */ 3331 ret = csr_ops[csrno].read128(env, csrno, &old_value); 3332 if (ret != RISCV_EXCP_NONE) { 3333 return ret; 3334 } 3335 3336 /* write value if writable and write mask set, otherwise drop writes */ 3337 if (int128_nz(write_mask)) { 3338 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 3339 int128_and(new_value, write_mask)); 3340 if (csr_ops[csrno].write128) { 3341 ret = csr_ops[csrno].write128(env, csrno, new_value); 3342 if (ret != RISCV_EXCP_NONE) { 3343 return ret; 3344 } 3345 } else if (csr_ops[csrno].write) { 3346 /* avoids having to write wrappers for all registers */ 3347 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 3348 if (ret != RISCV_EXCP_NONE) { 3349 return ret; 3350 } 3351 } 3352 } 3353 3354 /* return old value */ 3355 if (ret_value) { 3356 *ret_value = old_value; 3357 } 3358 3359 return RISCV_EXCP_NONE; 3360 } 3361 3362 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 3363 Int128 *ret_value, 3364 Int128 new_value, Int128 write_mask) 3365 { 3366 RISCVException ret; 3367 RISCVCPU *cpu = env_archcpu(env); 3368 3369 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); 3370 if (ret != RISCV_EXCP_NONE) { 3371 return ret; 3372 } 3373 3374 if (csr_ops[csrno].read128) { 3375 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 3376 } 3377 3378 /* 3379 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 3380 * at all defined. 3381 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 3382 * significant), for those, this fallback is correctly handling the accesses 3383 */ 3384 target_ulong old_value; 3385 ret = riscv_csrrw_do64(env, csrno, &old_value, 3386 int128_getlo(new_value), 3387 int128_getlo(write_mask)); 3388 if (ret == RISCV_EXCP_NONE && ret_value) { 3389 *ret_value = int128_make64(old_value); 3390 } 3391 return ret; 3392 } 3393 3394 /* 3395 * Debugger support. If not in user mode, set env->debugger before the 3396 * riscv_csrrw call and clear it after the call. 3397 */ 3398 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 3399 target_ulong *ret_value, 3400 target_ulong new_value, 3401 target_ulong write_mask) 3402 { 3403 RISCVException ret; 3404 #if !defined(CONFIG_USER_ONLY) 3405 env->debugger = true; 3406 #endif 3407 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 3408 #if !defined(CONFIG_USER_ONLY) 3409 env->debugger = false; 3410 #endif 3411 return ret; 3412 } 3413 3414 /* Control and Status Register function table */ 3415 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 3416 /* User Floating-Point CSRs */ 3417 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 3418 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 3419 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 3420 /* Vector CSRs */ 3421 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, 3422 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3423 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, 3424 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3425 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, 3426 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3427 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, 3428 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3429 [CSR_VL] = { "vl", vs, read_vl, 3430 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3431 [CSR_VTYPE] = { "vtype", vs, read_vtype, 3432 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3433 [CSR_VLENB] = { "vlenb", vs, read_vlenb, 3434 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3435 /* User Timers and Counters */ 3436 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 3437 [CSR_INSTRET] = { "instret", ctr, read_instret }, 3438 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 3439 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 3440 3441 /* 3442 * In privileged mode, the monitor will have to emulate TIME CSRs only if 3443 * rdtime callback is not provided by machine/platform emulation. 3444 */ 3445 [CSR_TIME] = { "time", ctr, read_time }, 3446 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 3447 3448 /* Crypto Extension */ 3449 [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, 3450 3451 #if !defined(CONFIG_USER_ONLY) 3452 /* Machine Timers and Counters */ 3453 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 3454 [CSR_MINSTRET] = { "minstret", any, read_instret }, 3455 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 3456 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 3457 3458 /* Machine Information Registers */ 3459 [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, 3460 [CSR_MARCHID] = { "marchid", any, read_marchid }, 3461 [CSR_MIMPID] = { "mimpid", any, read_mimpid }, 3462 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 3463 3464 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 3465 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3466 /* Machine Trap Setup */ 3467 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, 3468 read_mstatus_i128 }, 3469 [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, 3470 read_misa_i128 }, 3471 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 3472 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 3473 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 3474 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 3475 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 3476 3477 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 3478 3479 /* Machine Trap Handling */ 3480 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, 3481 read_mscratch_i128, write_mscratch_i128 }, 3482 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 3483 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 3484 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 3485 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 3486 3487 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 3488 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 3489 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 3490 3491 /* Machine-Level Interrupts (AIA) */ 3492 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 3493 3494 /* Machine-Level IMSIC Interface (AIA) */ 3495 [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3496 [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3497 [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3498 [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3499 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 3500 3501 /* Virtual Interrupts for Supervisor Level (AIA) */ 3502 [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, 3503 [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, 3504 3505 /* Machine-Level High-Half CSRs (AIA) */ 3506 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 3507 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 3508 [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, 3509 [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, 3510 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 3511 3512 /* Execution environment configuration */ 3513 [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, 3514 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3515 [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, 3516 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3517 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 3518 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3519 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 3520 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3521 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 3522 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3523 3524 /* Supervisor Trap Setup */ 3525 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, 3526 read_sstatus_i128 }, 3527 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 3528 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 3529 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 3530 3531 /* Supervisor Trap Handling */ 3532 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, 3533 read_sscratch_i128, write_sscratch_i128 }, 3534 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 3535 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 3536 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 3537 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 3538 3539 /* Supervisor Protection and Translation */ 3540 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 3541 3542 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 3543 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 3544 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 3545 3546 /* Supervisor-Level Interrupts (AIA) */ 3547 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 3548 3549 /* Supervisor-Level IMSIC Interface (AIA) */ 3550 [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3551 [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3552 [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3553 [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3554 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 3555 3556 /* Supervisor-Level High-Half CSRs (AIA) */ 3557 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 3558 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 3559 3560 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 3561 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3562 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 3563 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3564 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 3565 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3566 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 3567 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3568 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 3569 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3570 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 3571 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3572 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, 3573 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3574 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 3575 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3576 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 3577 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3578 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 3579 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3580 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 3581 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3582 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, 3583 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3584 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, 3585 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3586 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, 3587 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3588 3589 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, 3590 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3591 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 3592 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3593 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 3594 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3595 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 3596 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3597 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, 3598 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3599 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 3600 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3601 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 3602 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3603 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 3604 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3605 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 3606 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3607 3608 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 3609 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3610 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 3611 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3612 3613 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 3614 [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, 3615 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, 3616 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, 3617 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, 3618 3619 /* 3620 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 3621 */ 3622 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, 3623 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 3624 3625 /* VS-Level Interrupts (H-extension with AIA) */ 3626 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 3627 3628 /* VS-Level IMSIC Interface (H-extension with AIA) */ 3629 [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3630 [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3631 [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3632 [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3633 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 3634 3635 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 3636 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, 3637 [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, 3638 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 3639 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, 3640 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, 3641 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 3642 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 3643 3644 /* Physical Memory Protection */ 3645 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 3646 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3647 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 3648 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 3649 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 3650 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 3651 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 3652 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 3653 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 3654 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 3655 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 3656 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 3657 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 3658 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 3659 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 3660 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 3661 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 3662 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 3663 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 3664 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 3665 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 3666 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 3667 3668 /* Debug CSRs */ 3669 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 3670 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 3671 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 3672 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 3673 3674 /* User Pointer Masking */ 3675 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 3676 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 3677 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 3678 /* Machine Pointer Masking */ 3679 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 3680 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 3681 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 3682 /* Supervisor Pointer Masking */ 3683 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 3684 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 3685 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 3686 3687 /* Performance Counters */ 3688 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 3689 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 3690 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 3691 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 3692 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 3693 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 3694 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 3695 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 3696 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 3697 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 3698 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 3699 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 3700 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 3701 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 3702 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 3703 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 3704 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 3705 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 3706 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 3707 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 3708 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 3709 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 3710 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 3711 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 3712 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 3713 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 3714 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 3715 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 3716 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 3717 3718 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero }, 3719 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero }, 3720 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero }, 3721 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero }, 3722 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero }, 3723 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero }, 3724 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero }, 3725 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero }, 3726 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero }, 3727 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero }, 3728 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero }, 3729 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero }, 3730 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero }, 3731 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero }, 3732 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero }, 3733 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero }, 3734 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero }, 3735 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero }, 3736 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero }, 3737 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero }, 3738 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero }, 3739 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero }, 3740 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero }, 3741 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero }, 3742 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero }, 3743 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero }, 3744 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero }, 3745 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero }, 3746 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero }, 3747 3748 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 3749 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 3750 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 3751 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 3752 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 3753 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 3754 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 3755 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 3756 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 3757 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 3758 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 3759 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 3760 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 3761 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 3762 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 3763 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 3764 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 3765 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 3766 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 3767 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 3768 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 3769 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 3770 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 3771 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 3772 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 3773 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 3774 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 3775 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 3776 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 3777 3778 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 3779 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 3780 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 3781 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 3782 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 3783 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 3784 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 3785 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 3786 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 3787 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 3788 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 3789 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 3790 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 3791 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 3792 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 3793 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 3794 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 3795 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 3796 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 3797 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 3798 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 3799 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 3800 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 3801 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 3802 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 3803 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 3804 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 3805 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 3806 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 3807 3808 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 3809 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 3810 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 3811 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 3812 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 3813 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 3814 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 3815 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 3816 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 3817 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 3818 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 3819 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 3820 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 3821 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 3822 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 3823 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 3824 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 3825 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 3826 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 3827 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 3828 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 3829 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 3830 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 3831 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 3832 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 3833 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 3834 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 3835 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 3836 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 3837 #endif /* !CONFIG_USER_ONLY */ 3838 }; 3839