1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 /* loose check condition for fcsr in vector extension */ 50 if ((csrno == CSR_FCSR) && (env->misa & RVV)) { 51 return 0; 52 } 53 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 54 return -RISCV_EXCP_ILLEGAL_INST; 55 } 56 #endif 57 return 0; 58 } 59 60 static int vs(CPURISCVState *env, int csrno) 61 { 62 if (env->misa & RVV) { 63 return 0; 64 } 65 return -1; 66 } 67 68 static int ctr(CPURISCVState *env, int csrno) 69 { 70 #if !defined(CONFIG_USER_ONLY) 71 CPUState *cs = env_cpu(env); 72 RISCVCPU *cpu = RISCV_CPU(cs); 73 74 if (!cpu->cfg.ext_counters) { 75 /* The Counters extensions is not enabled */ 76 return -RISCV_EXCP_ILLEGAL_INST; 77 } 78 79 if (riscv_cpu_virt_enabled(env)) { 80 switch (csrno) { 81 case CSR_CYCLE: 82 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 83 get_field(env->mcounteren, HCOUNTEREN_CY)) { 84 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 85 } 86 break; 87 case CSR_TIME: 88 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 89 get_field(env->mcounteren, HCOUNTEREN_TM)) { 90 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 91 } 92 break; 93 case CSR_INSTRET: 94 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 95 get_field(env->mcounteren, HCOUNTEREN_IR)) { 96 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 97 } 98 break; 99 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 100 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 101 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 102 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 103 } 104 break; 105 #if defined(TARGET_RISCV32) 106 case CSR_CYCLEH: 107 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 108 get_field(env->mcounteren, HCOUNTEREN_CY)) { 109 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_TIMEH: 113 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 114 get_field(env->mcounteren, HCOUNTEREN_TM)) { 115 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_INSTRETH: 119 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 120 get_field(env->mcounteren, HCOUNTEREN_IR)) { 121 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 125 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 126 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 127 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 128 } 129 break; 130 #endif 131 } 132 } 133 #endif 134 return 0; 135 } 136 137 #if !defined(CONFIG_USER_ONLY) 138 static int any(CPURISCVState *env, int csrno) 139 { 140 return 0; 141 } 142 143 static int smode(CPURISCVState *env, int csrno) 144 { 145 return -!riscv_has_ext(env, RVS); 146 } 147 148 static int hmode(CPURISCVState *env, int csrno) 149 { 150 if (riscv_has_ext(env, RVS) && 151 riscv_has_ext(env, RVH)) { 152 /* Hypervisor extension is supported */ 153 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 154 env->priv == PRV_M) { 155 return 0; 156 } else { 157 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 158 } 159 } 160 161 return -RISCV_EXCP_ILLEGAL_INST; 162 } 163 164 static int pmp(CPURISCVState *env, int csrno) 165 { 166 return -!riscv_feature(env, RISCV_FEATURE_PMP); 167 } 168 #endif 169 170 /* User Floating-Point CSRs */ 171 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 172 { 173 #if !defined(CONFIG_USER_ONLY) 174 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 175 return -RISCV_EXCP_ILLEGAL_INST; 176 } 177 #endif 178 *val = riscv_cpu_get_fflags(env); 179 return 0; 180 } 181 182 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 183 { 184 #if !defined(CONFIG_USER_ONLY) 185 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 186 return -RISCV_EXCP_ILLEGAL_INST; 187 } 188 env->mstatus |= MSTATUS_FS; 189 #endif 190 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 191 return 0; 192 } 193 194 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 195 { 196 #if !defined(CONFIG_USER_ONLY) 197 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 198 return -RISCV_EXCP_ILLEGAL_INST; 199 } 200 #endif 201 *val = env->frm; 202 return 0; 203 } 204 205 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 206 { 207 #if !defined(CONFIG_USER_ONLY) 208 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 209 return -RISCV_EXCP_ILLEGAL_INST; 210 } 211 env->mstatus |= MSTATUS_FS; 212 #endif 213 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 214 return 0; 215 } 216 217 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 218 { 219 #if !defined(CONFIG_USER_ONLY) 220 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 221 return -RISCV_EXCP_ILLEGAL_INST; 222 } 223 #endif 224 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 225 | (env->frm << FSR_RD_SHIFT); 226 if (vs(env, csrno) >= 0) { 227 *val |= (env->vxrm << FSR_VXRM_SHIFT) 228 | (env->vxsat << FSR_VXSAT_SHIFT); 229 } 230 return 0; 231 } 232 233 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 234 { 235 #if !defined(CONFIG_USER_ONLY) 236 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 237 return -RISCV_EXCP_ILLEGAL_INST; 238 } 239 env->mstatus |= MSTATUS_FS; 240 #endif 241 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 242 if (vs(env, csrno) >= 0) { 243 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 244 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 245 } 246 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 247 return 0; 248 } 249 250 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) 251 { 252 *val = env->vtype; 253 return 0; 254 } 255 256 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) 257 { 258 *val = env->vl; 259 return 0; 260 } 261 262 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) 263 { 264 *val = env->vxrm; 265 return 0; 266 } 267 268 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) 269 { 270 env->vxrm = val; 271 return 0; 272 } 273 274 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) 275 { 276 *val = env->vxsat; 277 return 0; 278 } 279 280 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) 281 { 282 env->vxsat = val; 283 return 0; 284 } 285 286 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) 287 { 288 *val = env->vstart; 289 return 0; 290 } 291 292 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) 293 { 294 env->vstart = val; 295 return 0; 296 } 297 298 /* User Timers and Counters */ 299 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 300 { 301 #if !defined(CONFIG_USER_ONLY) 302 if (use_icount) { 303 *val = cpu_get_icount(); 304 } else { 305 *val = cpu_get_host_ticks(); 306 } 307 #else 308 *val = cpu_get_host_ticks(); 309 #endif 310 return 0; 311 } 312 313 #if defined(TARGET_RISCV32) 314 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 315 { 316 #if !defined(CONFIG_USER_ONLY) 317 if (use_icount) { 318 *val = cpu_get_icount() >> 32; 319 } else { 320 *val = cpu_get_host_ticks() >> 32; 321 } 322 #else 323 *val = cpu_get_host_ticks() >> 32; 324 #endif 325 return 0; 326 } 327 #endif /* TARGET_RISCV32 */ 328 329 #if defined(CONFIG_USER_ONLY) 330 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 331 { 332 *val = cpu_get_host_ticks(); 333 return 0; 334 } 335 336 #if defined(TARGET_RISCV32) 337 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 338 { 339 *val = cpu_get_host_ticks() >> 32; 340 return 0; 341 } 342 #endif 343 344 #else /* CONFIG_USER_ONLY */ 345 346 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 347 { 348 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 349 350 if (!env->rdtime_fn) { 351 return -RISCV_EXCP_ILLEGAL_INST; 352 } 353 354 *val = env->rdtime_fn() + delta; 355 return 0; 356 } 357 358 #if defined(TARGET_RISCV32) 359 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 360 { 361 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 362 363 if (!env->rdtime_fn) { 364 return -RISCV_EXCP_ILLEGAL_INST; 365 } 366 367 *val = (env->rdtime_fn() + delta) >> 32; 368 return 0; 369 } 370 #endif 371 372 /* Machine constants */ 373 374 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 375 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 376 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 377 378 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 379 VS_MODE_INTERRUPTS; 380 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 381 VS_MODE_INTERRUPTS; 382 static const target_ulong delegable_excps = 383 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 384 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 385 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 386 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 387 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 388 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 389 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 390 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 391 (1ULL << (RISCV_EXCP_U_ECALL)) | 392 (1ULL << (RISCV_EXCP_S_ECALL)) | 393 (1ULL << (RISCV_EXCP_VS_ECALL)) | 394 (1ULL << (RISCV_EXCP_M_ECALL)) | 395 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 396 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 397 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 398 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 399 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 400 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 401 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 402 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 403 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 404 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 405 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 406 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 407 static const target_ulong vsip_writable_mask = MIP_VSSIP; 408 409 #if defined(TARGET_RISCV32) 410 static const char valid_vm_1_10[16] = { 411 [VM_1_10_MBARE] = 1, 412 [VM_1_10_SV32] = 1 413 }; 414 #elif defined(TARGET_RISCV64) 415 static const char valid_vm_1_10[16] = { 416 [VM_1_10_MBARE] = 1, 417 [VM_1_10_SV39] = 1, 418 [VM_1_10_SV48] = 1, 419 [VM_1_10_SV57] = 1 420 }; 421 #endif /* CONFIG_USER_ONLY */ 422 423 /* Machine Information Registers */ 424 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 425 { 426 return *val = 0; 427 } 428 429 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 430 { 431 *val = env->mhartid; 432 return 0; 433 } 434 435 /* Machine Trap Setup */ 436 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 437 { 438 *val = env->mstatus; 439 return 0; 440 } 441 442 static int validate_vm(CPURISCVState *env, target_ulong vm) 443 { 444 return valid_vm_1_10[vm & 0xf]; 445 } 446 447 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 448 { 449 target_ulong mstatus = env->mstatus; 450 target_ulong mask = 0; 451 int dirty; 452 453 /* flush tlb on mstatus fields that affect VM */ 454 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 455 MSTATUS_MPRV | MSTATUS_SUM)) { 456 tlb_flush(env_cpu(env)); 457 } 458 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 459 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 460 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 461 MSTATUS_TW; 462 #if defined(TARGET_RISCV64) 463 /* 464 * RV32: MPV and GVA are not in mstatus. The current plan is to 465 * add them to mstatush. For now, we just don't support it. 466 */ 467 mask |= MSTATUS_MPV | MSTATUS_GVA; 468 #endif 469 470 mstatus = (mstatus & ~mask) | (val & mask); 471 472 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 473 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 474 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 475 env->mstatus = mstatus; 476 477 return 0; 478 } 479 480 #ifdef TARGET_RISCV32 481 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) 482 { 483 *val = env->mstatush; 484 return 0; 485 } 486 487 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) 488 { 489 if ((val ^ env->mstatush) & (MSTATUS_MPV)) { 490 tlb_flush(env_cpu(env)); 491 } 492 493 val &= MSTATUS_MPV | MSTATUS_GVA; 494 495 env->mstatush = val; 496 497 return 0; 498 } 499 #endif 500 501 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 502 { 503 *val = env->misa; 504 return 0; 505 } 506 507 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 508 { 509 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 510 /* drop write to misa */ 511 return 0; 512 } 513 514 /* 'I' or 'E' must be present */ 515 if (!(val & (RVI | RVE))) { 516 /* It is not, drop write to misa */ 517 return 0; 518 } 519 520 /* 'E' excludes all other extensions */ 521 if (val & RVE) { 522 /* when we support 'E' we can do "val = RVE;" however 523 * for now we just drop writes if 'E' is present. 524 */ 525 return 0; 526 } 527 528 /* Mask extensions that are not supported by this hart */ 529 val &= env->misa_mask; 530 531 /* Mask extensions that are not supported by QEMU */ 532 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 533 534 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 535 if ((val & RVD) && !(val & RVF)) { 536 val &= ~RVD; 537 } 538 539 /* Suppress 'C' if next instruction is not aligned 540 * TODO: this should check next_pc 541 */ 542 if ((val & RVC) && (GETPC() & ~3) != 0) { 543 val &= ~RVC; 544 } 545 546 /* misa.MXL writes are not supported by QEMU */ 547 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 548 549 /* flush translation cache */ 550 if (val != env->misa) { 551 tb_flush(env_cpu(env)); 552 } 553 554 env->misa = val; 555 556 return 0; 557 } 558 559 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 560 { 561 *val = env->medeleg; 562 return 0; 563 } 564 565 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 566 { 567 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 568 return 0; 569 } 570 571 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 572 { 573 *val = env->mideleg; 574 return 0; 575 } 576 577 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 578 { 579 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 580 if (riscv_has_ext(env, RVH)) { 581 env->mideleg |= VS_MODE_INTERRUPTS; 582 } 583 return 0; 584 } 585 586 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 587 { 588 *val = env->mie; 589 return 0; 590 } 591 592 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 593 { 594 env->mie = (env->mie & ~all_ints) | (val & all_ints); 595 return 0; 596 } 597 598 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 599 { 600 *val = env->mtvec; 601 return 0; 602 } 603 604 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 605 { 606 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 607 if ((val & 3) < 2) { 608 env->mtvec = val; 609 } else { 610 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 611 } 612 return 0; 613 } 614 615 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 616 { 617 *val = env->mcounteren; 618 return 0; 619 } 620 621 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 622 { 623 env->mcounteren = val; 624 return 0; 625 } 626 627 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ 628 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 629 { 630 if (env->priv_ver < PRIV_VERSION_1_11_0) { 631 return -RISCV_EXCP_ILLEGAL_INST; 632 } 633 *val = env->mcounteren; 634 return 0; 635 } 636 637 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ 638 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 639 { 640 if (env->priv_ver < PRIV_VERSION_1_11_0) { 641 return -RISCV_EXCP_ILLEGAL_INST; 642 } 643 env->mcounteren = val; 644 return 0; 645 } 646 647 /* Machine Trap Handling */ 648 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 649 { 650 *val = env->mscratch; 651 return 0; 652 } 653 654 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 655 { 656 env->mscratch = val; 657 return 0; 658 } 659 660 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 661 { 662 *val = env->mepc; 663 return 0; 664 } 665 666 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 667 { 668 env->mepc = val; 669 return 0; 670 } 671 672 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 673 { 674 *val = env->mcause; 675 return 0; 676 } 677 678 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 679 { 680 env->mcause = val; 681 return 0; 682 } 683 684 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 685 { 686 *val = env->mbadaddr; 687 return 0; 688 } 689 690 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 691 { 692 env->mbadaddr = val; 693 return 0; 694 } 695 696 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 697 target_ulong new_value, target_ulong write_mask) 698 { 699 RISCVCPU *cpu = env_archcpu(env); 700 /* Allow software control of delegable interrupts not claimed by hardware */ 701 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 702 uint32_t old_mip; 703 704 if (mask) { 705 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 706 } else { 707 old_mip = env->mip; 708 } 709 710 if (ret_value) { 711 *ret_value = old_mip; 712 } 713 714 return 0; 715 } 716 717 /* Supervisor Trap Setup */ 718 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 719 { 720 target_ulong mask = (sstatus_v1_10_mask); 721 *val = env->mstatus & mask; 722 return 0; 723 } 724 725 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 726 { 727 target_ulong mask = (sstatus_v1_10_mask); 728 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 729 return write_mstatus(env, CSR_MSTATUS, newval); 730 } 731 732 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 733 { 734 if (riscv_cpu_virt_enabled(env)) { 735 /* Tell the guest the VS bits, shifted to the S bit locations */ 736 *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; 737 } else { 738 *val = env->mie & env->mideleg; 739 } 740 return 0; 741 } 742 743 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 744 { 745 target_ulong newval; 746 747 if (riscv_cpu_virt_enabled(env)) { 748 /* Shift the guests S bits to VS */ 749 newval = (env->mie & ~VS_MODE_INTERRUPTS) | 750 ((val << 1) & VS_MODE_INTERRUPTS); 751 } else { 752 newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); 753 } 754 755 return write_mie(env, CSR_MIE, newval); 756 } 757 758 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 759 { 760 *val = env->stvec; 761 return 0; 762 } 763 764 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 765 { 766 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 767 if ((val & 3) < 2) { 768 env->stvec = val; 769 } else { 770 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 771 } 772 return 0; 773 } 774 775 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 776 { 777 *val = env->scounteren; 778 return 0; 779 } 780 781 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 782 { 783 env->scounteren = val; 784 return 0; 785 } 786 787 /* Supervisor Trap Handling */ 788 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 789 { 790 *val = env->sscratch; 791 return 0; 792 } 793 794 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 795 { 796 env->sscratch = val; 797 return 0; 798 } 799 800 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 801 { 802 *val = env->sepc; 803 return 0; 804 } 805 806 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 807 { 808 env->sepc = val; 809 return 0; 810 } 811 812 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 813 { 814 *val = env->scause; 815 return 0; 816 } 817 818 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 819 { 820 env->scause = val; 821 return 0; 822 } 823 824 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 825 { 826 *val = env->sbadaddr; 827 return 0; 828 } 829 830 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 831 { 832 env->sbadaddr = val; 833 return 0; 834 } 835 836 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 837 target_ulong new_value, target_ulong write_mask) 838 { 839 int ret; 840 841 if (riscv_cpu_virt_enabled(env)) { 842 /* Shift the new values to line up with the VS bits */ 843 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, 844 (write_mask & sip_writable_mask) << 1 & env->mideleg); 845 ret &= vsip_writable_mask; 846 ret >>= 1; 847 } else { 848 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 849 write_mask & env->mideleg & sip_writable_mask); 850 } 851 852 *ret_value &= env->mideleg; 853 return ret; 854 } 855 856 /* Supervisor Protection and Translation */ 857 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 858 { 859 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 860 *val = 0; 861 return 0; 862 } 863 864 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 865 return -RISCV_EXCP_ILLEGAL_INST; 866 } else { 867 *val = env->satp; 868 } 869 870 return 0; 871 } 872 873 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 874 { 875 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 876 return 0; 877 } 878 if (validate_vm(env, get_field(val, SATP_MODE)) && 879 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 880 { 881 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 882 return -RISCV_EXCP_ILLEGAL_INST; 883 } else { 884 if((val ^ env->satp) & SATP_ASID) { 885 tlb_flush(env_cpu(env)); 886 } 887 env->satp = val; 888 } 889 } 890 return 0; 891 } 892 893 /* Hypervisor Extensions */ 894 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) 895 { 896 *val = env->hstatus; 897 #ifdef TARGET_RISCV64 898 /* We only support 64-bit VSXL */ 899 *val = set_field(*val, HSTATUS_VSXL, 2); 900 #endif 901 /* We only support little endian */ 902 *val = set_field(*val, HSTATUS_VSBE, 0); 903 return 0; 904 } 905 906 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) 907 { 908 env->hstatus = val; 909 #ifdef TARGET_RISCV64 910 if (get_field(val, HSTATUS_VSXL) != 2) { 911 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 912 } 913 #endif 914 if (get_field(val, HSTATUS_VSBE) != 0) { 915 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 916 } 917 return 0; 918 } 919 920 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) 921 { 922 *val = env->hedeleg; 923 return 0; 924 } 925 926 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) 927 { 928 env->hedeleg = val; 929 return 0; 930 } 931 932 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) 933 { 934 *val = env->hideleg; 935 return 0; 936 } 937 938 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) 939 { 940 env->hideleg = val; 941 return 0; 942 } 943 944 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, 945 target_ulong new_value, target_ulong write_mask) 946 { 947 int ret = rmw_mip(env, 0, ret_value, new_value, 948 write_mask & hip_writable_mask); 949 950 *ret_value &= hip_writable_mask; 951 952 return ret; 953 } 954 955 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, 956 target_ulong new_value, target_ulong write_mask) 957 { 958 int ret = rmw_mip(env, 0, ret_value, new_value, 959 write_mask & hip_writable_mask); 960 961 *ret_value &= hip_writable_mask; 962 963 return ret; 964 } 965 966 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) 967 { 968 *val = env->mie & VS_MODE_INTERRUPTS; 969 return 0; 970 } 971 972 static int write_hie(CPURISCVState *env, int csrno, target_ulong val) 973 { 974 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 975 return write_mie(env, CSR_MIE, newval); 976 } 977 978 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val) 979 { 980 *val = env->hcounteren; 981 return 0; 982 } 983 984 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) 985 { 986 env->hcounteren = val; 987 return 0; 988 } 989 990 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) 991 { 992 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 993 return 0; 994 } 995 996 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) 997 { 998 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 999 return 0; 1000 } 1001 1002 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) 1003 { 1004 *val = env->htval; 1005 return 0; 1006 } 1007 1008 static int write_htval(CPURISCVState *env, int csrno, target_ulong val) 1009 { 1010 env->htval = val; 1011 return 0; 1012 } 1013 1014 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) 1015 { 1016 *val = env->htinst; 1017 return 0; 1018 } 1019 1020 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) 1021 { 1022 return 0; 1023 } 1024 1025 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) 1026 { 1027 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1028 return 0; 1029 } 1030 1031 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) 1032 { 1033 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1034 return 0; 1035 } 1036 1037 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) 1038 { 1039 *val = env->hgatp; 1040 return 0; 1041 } 1042 1043 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) 1044 { 1045 env->hgatp = val; 1046 return 0; 1047 } 1048 1049 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val) 1050 { 1051 if (!env->rdtime_fn) { 1052 return -RISCV_EXCP_ILLEGAL_INST; 1053 } 1054 1055 #if defined(TARGET_RISCV32) 1056 *val = env->htimedelta & 0xffffffff; 1057 #else 1058 *val = env->htimedelta; 1059 #endif 1060 return 0; 1061 } 1062 1063 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) 1064 { 1065 if (!env->rdtime_fn) { 1066 return -RISCV_EXCP_ILLEGAL_INST; 1067 } 1068 1069 #if defined(TARGET_RISCV32) 1070 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1071 #else 1072 env->htimedelta = val; 1073 #endif 1074 return 0; 1075 } 1076 1077 #if defined(TARGET_RISCV32) 1078 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) 1079 { 1080 if (!env->rdtime_fn) { 1081 return -RISCV_EXCP_ILLEGAL_INST; 1082 } 1083 1084 *val = env->htimedelta >> 32; 1085 return 0; 1086 } 1087 1088 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) 1089 { 1090 if (!env->rdtime_fn) { 1091 return -RISCV_EXCP_ILLEGAL_INST; 1092 } 1093 1094 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1095 return 0; 1096 } 1097 #endif 1098 1099 /* Virtual CSR Registers */ 1100 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) 1101 { 1102 *val = env->vsstatus; 1103 return 0; 1104 } 1105 1106 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) 1107 { 1108 env->vsstatus = val; 1109 return 0; 1110 } 1111 1112 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, 1113 target_ulong new_value, target_ulong write_mask) 1114 { 1115 int ret = rmw_mip(env, 0, ret_value, new_value, 1116 write_mask & env->mideleg & vsip_writable_mask); 1117 return ret; 1118 } 1119 1120 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) 1121 { 1122 *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; 1123 return 0; 1124 } 1125 1126 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) 1127 { 1128 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); 1129 return write_mie(env, CSR_MIE, newval); 1130 } 1131 1132 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1133 { 1134 *val = env->vstvec; 1135 return 0; 1136 } 1137 1138 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) 1139 { 1140 env->vstvec = val; 1141 return 0; 1142 } 1143 1144 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) 1145 { 1146 *val = env->vsscratch; 1147 return 0; 1148 } 1149 1150 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) 1151 { 1152 env->vsscratch = val; 1153 return 0; 1154 } 1155 1156 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) 1157 { 1158 *val = env->vsepc; 1159 return 0; 1160 } 1161 1162 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) 1163 { 1164 env->vsepc = val; 1165 return 0; 1166 } 1167 1168 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) 1169 { 1170 *val = env->vscause; 1171 return 0; 1172 } 1173 1174 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) 1175 { 1176 env->vscause = val; 1177 return 0; 1178 } 1179 1180 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) 1181 { 1182 *val = env->vstval; 1183 return 0; 1184 } 1185 1186 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) 1187 { 1188 env->vstval = val; 1189 return 0; 1190 } 1191 1192 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) 1193 { 1194 *val = env->vsatp; 1195 return 0; 1196 } 1197 1198 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) 1199 { 1200 env->vsatp = val; 1201 return 0; 1202 } 1203 1204 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) 1205 { 1206 *val = env->mtval2; 1207 return 0; 1208 } 1209 1210 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) 1211 { 1212 env->mtval2 = val; 1213 return 0; 1214 } 1215 1216 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) 1217 { 1218 *val = env->mtinst; 1219 return 0; 1220 } 1221 1222 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) 1223 { 1224 env->mtinst = val; 1225 return 0; 1226 } 1227 1228 /* Physical Memory Protection */ 1229 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 1230 { 1231 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1232 return 0; 1233 } 1234 1235 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 1236 { 1237 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1238 return 0; 1239 } 1240 1241 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 1242 { 1243 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1244 return 0; 1245 } 1246 1247 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 1248 { 1249 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1250 return 0; 1251 } 1252 1253 #endif 1254 1255 /* 1256 * riscv_csrrw - read and/or update control and status register 1257 * 1258 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1259 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1260 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1261 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1262 */ 1263 1264 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 1265 target_ulong new_value, target_ulong write_mask) 1266 { 1267 int ret; 1268 target_ulong old_value; 1269 RISCVCPU *cpu = env_archcpu(env); 1270 1271 /* check privileges and return -1 if check fails */ 1272 #if !defined(CONFIG_USER_ONLY) 1273 int effective_priv = env->priv; 1274 int read_only = get_field(csrno, 0xC00) == 3; 1275 1276 if (riscv_has_ext(env, RVH) && 1277 env->priv == PRV_S && 1278 !riscv_cpu_virt_enabled(env)) { 1279 /* 1280 * We are in S mode without virtualisation, therefore we are in HS Mode. 1281 * Add 1 to the effective privledge level to allow us to access the 1282 * Hypervisor CSRs. 1283 */ 1284 effective_priv++; 1285 } 1286 1287 if ((write_mask && read_only) || 1288 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1289 return -RISCV_EXCP_ILLEGAL_INST; 1290 } 1291 #endif 1292 1293 /* ensure the CSR extension is enabled. */ 1294 if (!cpu->cfg.ext_icsr) { 1295 return -RISCV_EXCP_ILLEGAL_INST; 1296 } 1297 1298 /* check predicate */ 1299 if (!csr_ops[csrno].predicate) { 1300 return -RISCV_EXCP_ILLEGAL_INST; 1301 } 1302 ret = csr_ops[csrno].predicate(env, csrno); 1303 if (ret < 0) { 1304 return ret; 1305 } 1306 1307 /* execute combined read/write operation if it exists */ 1308 if (csr_ops[csrno].op) { 1309 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1310 } 1311 1312 /* if no accessor exists then return failure */ 1313 if (!csr_ops[csrno].read) { 1314 return -RISCV_EXCP_ILLEGAL_INST; 1315 } 1316 1317 /* read old value */ 1318 ret = csr_ops[csrno].read(env, csrno, &old_value); 1319 if (ret < 0) { 1320 return ret; 1321 } 1322 1323 /* write value if writable and write mask set, otherwise drop writes */ 1324 if (write_mask) { 1325 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1326 if (csr_ops[csrno].write) { 1327 ret = csr_ops[csrno].write(env, csrno, new_value); 1328 if (ret < 0) { 1329 return ret; 1330 } 1331 } 1332 } 1333 1334 /* return old value */ 1335 if (ret_value) { 1336 *ret_value = old_value; 1337 } 1338 1339 return 0; 1340 } 1341 1342 /* 1343 * Debugger support. If not in user mode, set env->debugger before the 1344 * riscv_csrrw call and clear it after the call. 1345 */ 1346 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 1347 target_ulong new_value, target_ulong write_mask) 1348 { 1349 int ret; 1350 #if !defined(CONFIG_USER_ONLY) 1351 env->debugger = true; 1352 #endif 1353 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1354 #if !defined(CONFIG_USER_ONLY) 1355 env->debugger = false; 1356 #endif 1357 return ret; 1358 } 1359 1360 /* Control and Status Register function table */ 1361 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1362 /* User Floating-Point CSRs */ 1363 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 1364 [CSR_FRM] = { fs, read_frm, write_frm }, 1365 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 1366 /* Vector CSRs */ 1367 [CSR_VSTART] = { vs, read_vstart, write_vstart }, 1368 [CSR_VXSAT] = { vs, read_vxsat, write_vxsat }, 1369 [CSR_VXRM] = { vs, read_vxrm, write_vxrm }, 1370 [CSR_VL] = { vs, read_vl }, 1371 [CSR_VTYPE] = { vs, read_vtype }, 1372 /* User Timers and Counters */ 1373 [CSR_CYCLE] = { ctr, read_instret }, 1374 [CSR_INSTRET] = { ctr, read_instret }, 1375 #if defined(TARGET_RISCV32) 1376 [CSR_CYCLEH] = { ctr, read_instreth }, 1377 [CSR_INSTRETH] = { ctr, read_instreth }, 1378 #endif 1379 1380 /* In privileged mode, the monitor will have to emulate TIME CSRs only if 1381 * rdtime callback is not provided by machine/platform emulation */ 1382 [CSR_TIME] = { ctr, read_time }, 1383 #if defined(TARGET_RISCV32) 1384 [CSR_TIMEH] = { ctr, read_timeh }, 1385 #endif 1386 1387 #if !defined(CONFIG_USER_ONLY) 1388 /* Machine Timers and Counters */ 1389 [CSR_MCYCLE] = { any, read_instret }, 1390 [CSR_MINSTRET] = { any, read_instret }, 1391 #if defined(TARGET_RISCV32) 1392 [CSR_MCYCLEH] = { any, read_instreth }, 1393 [CSR_MINSTRETH] = { any, read_instreth }, 1394 #endif 1395 1396 /* Machine Information Registers */ 1397 [CSR_MVENDORID] = { any, read_zero }, 1398 [CSR_MARCHID] = { any, read_zero }, 1399 [CSR_MIMPID] = { any, read_zero }, 1400 [CSR_MHARTID] = { any, read_mhartid }, 1401 1402 /* Machine Trap Setup */ 1403 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 1404 [CSR_MISA] = { any, read_misa, write_misa }, 1405 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 1406 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 1407 [CSR_MIE] = { any, read_mie, write_mie }, 1408 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 1409 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 1410 1411 #if defined(TARGET_RISCV32) 1412 [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush }, 1413 #endif 1414 1415 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 1416 1417 /* Machine Trap Handling */ 1418 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 1419 [CSR_MEPC] = { any, read_mepc, write_mepc }, 1420 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 1421 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 1422 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 1423 1424 /* Supervisor Trap Setup */ 1425 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 1426 [CSR_SIE] = { smode, read_sie, write_sie }, 1427 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 1428 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 1429 1430 /* Supervisor Trap Handling */ 1431 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 1432 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 1433 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 1434 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 1435 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 1436 1437 /* Supervisor Protection and Translation */ 1438 [CSR_SATP] = { smode, read_satp, write_satp }, 1439 1440 [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, 1441 [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, 1442 [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, 1443 [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip }, 1444 [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, 1445 [CSR_HIE] = { hmode, read_hie, write_hie }, 1446 [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, 1447 [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie }, 1448 [CSR_HTVAL] = { hmode, read_htval, write_htval }, 1449 [CSR_HTINST] = { hmode, read_htinst, write_htinst }, 1450 [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip }, 1451 [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, 1452 [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta }, 1453 #if defined(TARGET_RISCV32) 1454 [CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah}, 1455 #endif 1456 1457 [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, 1458 [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip }, 1459 [CSR_VSIE] = { hmode, read_vsie, write_vsie }, 1460 [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, 1461 [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, 1462 [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, 1463 [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, 1464 [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, 1465 [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, 1466 1467 [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 }, 1468 [CSR_MTINST] = { hmode, read_mtinst, write_mtinst }, 1469 1470 /* Physical Memory Protection */ 1471 [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, 1472 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 1473 1474 /* Performance Counters */ 1475 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 1476 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 1477 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 1478 #if defined(TARGET_RISCV32) 1479 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 1480 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 1481 #endif 1482 #endif /* !CONFIG_USER_ONLY */ 1483 }; 1484