1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table public API */ 27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 28 { 29 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 30 } 31 32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 33 { 34 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 35 } 36 37 /* Predicates */ 38 static RISCVException fs(CPURISCVState *env, int csrno) 39 { 40 #if !defined(CONFIG_USER_ONLY) 41 /* loose check condition for fcsr in vector extension */ 42 if ((csrno == CSR_FCSR) && (env->misa & RVV)) { 43 return RISCV_EXCP_NONE; 44 } 45 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 46 return RISCV_EXCP_ILLEGAL_INST; 47 } 48 #endif 49 return RISCV_EXCP_NONE; 50 } 51 52 static RISCVException vs(CPURISCVState *env, int csrno) 53 { 54 if (env->misa & RVV) { 55 return RISCV_EXCP_NONE; 56 } 57 return RISCV_EXCP_ILLEGAL_INST; 58 } 59 60 static RISCVException ctr(CPURISCVState *env, int csrno) 61 { 62 #if !defined(CONFIG_USER_ONLY) 63 CPUState *cs = env_cpu(env); 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 66 if (!cpu->cfg.ext_counters) { 67 /* The Counters extensions is not enabled */ 68 return RISCV_EXCP_ILLEGAL_INST; 69 } 70 71 if (riscv_cpu_virt_enabled(env)) { 72 switch (csrno) { 73 case CSR_CYCLE: 74 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 75 get_field(env->mcounteren, HCOUNTEREN_CY)) { 76 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 77 } 78 break; 79 case CSR_TIME: 80 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 81 get_field(env->mcounteren, HCOUNTEREN_TM)) { 82 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 83 } 84 break; 85 case CSR_INSTRET: 86 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 87 get_field(env->mcounteren, HCOUNTEREN_IR)) { 88 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 89 } 90 break; 91 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 92 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 93 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 94 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 95 } 96 break; 97 } 98 if (riscv_cpu_is_32bit(env)) { 99 switch (csrno) { 100 case CSR_CYCLEH: 101 if (!get_field(env->hcounteren, HCOUNTEREN_CY) && 102 get_field(env->mcounteren, HCOUNTEREN_CY)) { 103 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 104 } 105 break; 106 case CSR_TIMEH: 107 if (!get_field(env->hcounteren, HCOUNTEREN_TM) && 108 get_field(env->mcounteren, HCOUNTEREN_TM)) { 109 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 110 } 111 break; 112 case CSR_INSTRETH: 113 if (!get_field(env->hcounteren, HCOUNTEREN_IR) && 114 get_field(env->mcounteren, HCOUNTEREN_IR)) { 115 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 116 } 117 break; 118 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 119 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 120 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 121 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 122 } 123 break; 124 } 125 } 126 } 127 #endif 128 return RISCV_EXCP_NONE; 129 } 130 131 static RISCVException ctr32(CPURISCVState *env, int csrno) 132 { 133 if (!riscv_cpu_is_32bit(env)) { 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 return ctr(env, csrno); 138 } 139 140 #if !defined(CONFIG_USER_ONLY) 141 static RISCVException any(CPURISCVState *env, int csrno) 142 { 143 return RISCV_EXCP_NONE; 144 } 145 146 static RISCVException any32(CPURISCVState *env, int csrno) 147 { 148 if (!riscv_cpu_is_32bit(env)) { 149 return RISCV_EXCP_ILLEGAL_INST; 150 } 151 152 return any(env, csrno); 153 154 } 155 156 static RISCVException smode(CPURISCVState *env, int csrno) 157 { 158 if (riscv_has_ext(env, RVS)) { 159 return RISCV_EXCP_NONE; 160 } 161 162 return RISCV_EXCP_ILLEGAL_INST; 163 } 164 165 static RISCVException hmode(CPURISCVState *env, int csrno) 166 { 167 if (riscv_has_ext(env, RVS) && 168 riscv_has_ext(env, RVH)) { 169 /* Hypervisor extension is supported */ 170 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 171 env->priv == PRV_M) { 172 return RISCV_EXCP_NONE; 173 } else { 174 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 175 } 176 } 177 178 return RISCV_EXCP_ILLEGAL_INST; 179 } 180 181 static RISCVException hmode32(CPURISCVState *env, int csrno) 182 { 183 if (!riscv_cpu_is_32bit(env)) { 184 return RISCV_EXCP_NONE; 185 } 186 187 return hmode(env, csrno); 188 189 } 190 191 static RISCVException pmp(CPURISCVState *env, int csrno) 192 { 193 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 194 return RISCV_EXCP_NONE; 195 } 196 197 return RISCV_EXCP_ILLEGAL_INST; 198 } 199 #endif 200 201 /* User Floating-Point CSRs */ 202 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 203 { 204 #if !defined(CONFIG_USER_ONLY) 205 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 206 return -RISCV_EXCP_ILLEGAL_INST; 207 } 208 #endif 209 *val = riscv_cpu_get_fflags(env); 210 return 0; 211 } 212 213 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 214 { 215 #if !defined(CONFIG_USER_ONLY) 216 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 217 return -RISCV_EXCP_ILLEGAL_INST; 218 } 219 env->mstatus |= MSTATUS_FS; 220 #endif 221 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 222 return 0; 223 } 224 225 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 226 { 227 #if !defined(CONFIG_USER_ONLY) 228 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 229 return -RISCV_EXCP_ILLEGAL_INST; 230 } 231 #endif 232 *val = env->frm; 233 return 0; 234 } 235 236 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 237 { 238 #if !defined(CONFIG_USER_ONLY) 239 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 240 return -RISCV_EXCP_ILLEGAL_INST; 241 } 242 env->mstatus |= MSTATUS_FS; 243 #endif 244 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 245 return 0; 246 } 247 248 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 249 { 250 #if !defined(CONFIG_USER_ONLY) 251 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 252 return -RISCV_EXCP_ILLEGAL_INST; 253 } 254 #endif 255 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 256 | (env->frm << FSR_RD_SHIFT); 257 if (vs(env, csrno) >= 0) { 258 *val |= (env->vxrm << FSR_VXRM_SHIFT) 259 | (env->vxsat << FSR_VXSAT_SHIFT); 260 } 261 return 0; 262 } 263 264 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 265 { 266 #if !defined(CONFIG_USER_ONLY) 267 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 268 return -RISCV_EXCP_ILLEGAL_INST; 269 } 270 env->mstatus |= MSTATUS_FS; 271 #endif 272 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 273 if (vs(env, csrno) >= 0) { 274 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; 275 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; 276 } 277 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 278 return 0; 279 } 280 281 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) 282 { 283 *val = env->vtype; 284 return 0; 285 } 286 287 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) 288 { 289 *val = env->vl; 290 return 0; 291 } 292 293 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) 294 { 295 *val = env->vxrm; 296 return 0; 297 } 298 299 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) 300 { 301 env->vxrm = val; 302 return 0; 303 } 304 305 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) 306 { 307 *val = env->vxsat; 308 return 0; 309 } 310 311 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) 312 { 313 env->vxsat = val; 314 return 0; 315 } 316 317 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) 318 { 319 *val = env->vstart; 320 return 0; 321 } 322 323 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) 324 { 325 env->vstart = val; 326 return 0; 327 } 328 329 /* User Timers and Counters */ 330 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 331 { 332 #if !defined(CONFIG_USER_ONLY) 333 if (icount_enabled()) { 334 *val = icount_get(); 335 } else { 336 *val = cpu_get_host_ticks(); 337 } 338 #else 339 *val = cpu_get_host_ticks(); 340 #endif 341 return 0; 342 } 343 344 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 345 { 346 #if !defined(CONFIG_USER_ONLY) 347 if (icount_enabled()) { 348 *val = icount_get() >> 32; 349 } else { 350 *val = cpu_get_host_ticks() >> 32; 351 } 352 #else 353 *val = cpu_get_host_ticks() >> 32; 354 #endif 355 return 0; 356 } 357 358 #if defined(CONFIG_USER_ONLY) 359 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 360 { 361 *val = cpu_get_host_ticks(); 362 return 0; 363 } 364 365 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 366 { 367 *val = cpu_get_host_ticks() >> 32; 368 return 0; 369 } 370 371 #else /* CONFIG_USER_ONLY */ 372 373 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 374 { 375 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 376 377 if (!env->rdtime_fn) { 378 return -RISCV_EXCP_ILLEGAL_INST; 379 } 380 381 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 382 return 0; 383 } 384 385 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 386 { 387 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 388 389 if (!env->rdtime_fn) { 390 return -RISCV_EXCP_ILLEGAL_INST; 391 } 392 393 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 394 return 0; 395 } 396 397 /* Machine constants */ 398 399 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 400 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 401 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 402 403 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 404 VS_MODE_INTERRUPTS; 405 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 406 VS_MODE_INTERRUPTS; 407 static const target_ulong delegable_excps = 408 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 409 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 410 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 411 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 412 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 413 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 414 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 415 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 416 (1ULL << (RISCV_EXCP_U_ECALL)) | 417 (1ULL << (RISCV_EXCP_S_ECALL)) | 418 (1ULL << (RISCV_EXCP_VS_ECALL)) | 419 (1ULL << (RISCV_EXCP_M_ECALL)) | 420 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 421 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 422 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 423 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 424 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 425 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 426 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 427 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 428 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 429 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 430 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 431 static const target_ulong hip_writable_mask = MIP_VSSIP; 432 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 433 static const target_ulong vsip_writable_mask = MIP_VSSIP; 434 435 static const char valid_vm_1_10_32[16] = { 436 [VM_1_10_MBARE] = 1, 437 [VM_1_10_SV32] = 1 438 }; 439 440 static const char valid_vm_1_10_64[16] = { 441 [VM_1_10_MBARE] = 1, 442 [VM_1_10_SV39] = 1, 443 [VM_1_10_SV48] = 1, 444 [VM_1_10_SV57] = 1 445 }; 446 447 /* Machine Information Registers */ 448 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 449 { 450 return *val = 0; 451 } 452 453 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 454 { 455 *val = env->mhartid; 456 return 0; 457 } 458 459 /* Machine Trap Setup */ 460 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 461 { 462 *val = env->mstatus; 463 return 0; 464 } 465 466 static int validate_vm(CPURISCVState *env, target_ulong vm) 467 { 468 if (riscv_cpu_is_32bit(env)) { 469 return valid_vm_1_10_32[vm & 0xf]; 470 } else { 471 return valid_vm_1_10_64[vm & 0xf]; 472 } 473 } 474 475 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 476 { 477 uint64_t mstatus = env->mstatus; 478 uint64_t mask = 0; 479 int dirty; 480 481 /* flush tlb on mstatus fields that affect VM */ 482 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 483 MSTATUS_MPRV | MSTATUS_SUM)) { 484 tlb_flush(env_cpu(env)); 485 } 486 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 487 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 488 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 489 MSTATUS_TW; 490 491 if (!riscv_cpu_is_32bit(env)) { 492 /* 493 * RV32: MPV and GVA are not in mstatus. The current plan is to 494 * add them to mstatush. For now, we just don't support it. 495 */ 496 mask |= MSTATUS_MPV | MSTATUS_GVA; 497 } 498 499 mstatus = (mstatus & ~mask) | (val & mask); 500 501 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 502 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 503 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 504 env->mstatus = mstatus; 505 506 return 0; 507 } 508 509 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) 510 { 511 *val = env->mstatus >> 32; 512 return 0; 513 } 514 515 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) 516 { 517 uint64_t valh = (uint64_t)val << 32; 518 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 519 520 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 521 tlb_flush(env_cpu(env)); 522 } 523 524 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 525 526 return 0; 527 } 528 529 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 530 { 531 *val = env->misa; 532 return 0; 533 } 534 535 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 536 { 537 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 538 /* drop write to misa */ 539 return 0; 540 } 541 542 /* 'I' or 'E' must be present */ 543 if (!(val & (RVI | RVE))) { 544 /* It is not, drop write to misa */ 545 return 0; 546 } 547 548 /* 'E' excludes all other extensions */ 549 if (val & RVE) { 550 /* when we support 'E' we can do "val = RVE;" however 551 * for now we just drop writes if 'E' is present. 552 */ 553 return 0; 554 } 555 556 /* Mask extensions that are not supported by this hart */ 557 val &= env->misa_mask; 558 559 /* Mask extensions that are not supported by QEMU */ 560 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 561 562 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 563 if ((val & RVD) && !(val & RVF)) { 564 val &= ~RVD; 565 } 566 567 /* Suppress 'C' if next instruction is not aligned 568 * TODO: this should check next_pc 569 */ 570 if ((val & RVC) && (GETPC() & ~3) != 0) { 571 val &= ~RVC; 572 } 573 574 /* misa.MXL writes are not supported by QEMU */ 575 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 576 577 /* flush translation cache */ 578 if (val != env->misa) { 579 tb_flush(env_cpu(env)); 580 } 581 582 env->misa = val; 583 584 return 0; 585 } 586 587 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 588 { 589 *val = env->medeleg; 590 return 0; 591 } 592 593 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 594 { 595 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 596 return 0; 597 } 598 599 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 600 { 601 *val = env->mideleg; 602 return 0; 603 } 604 605 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 606 { 607 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 608 if (riscv_has_ext(env, RVH)) { 609 env->mideleg |= VS_MODE_INTERRUPTS; 610 } 611 return 0; 612 } 613 614 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 615 { 616 *val = env->mie; 617 return 0; 618 } 619 620 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 621 { 622 env->mie = (env->mie & ~all_ints) | (val & all_ints); 623 return 0; 624 } 625 626 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 627 { 628 *val = env->mtvec; 629 return 0; 630 } 631 632 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 633 { 634 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 635 if ((val & 3) < 2) { 636 env->mtvec = val; 637 } else { 638 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 639 } 640 return 0; 641 } 642 643 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 644 { 645 *val = env->mcounteren; 646 return 0; 647 } 648 649 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 650 { 651 env->mcounteren = val; 652 return 0; 653 } 654 655 /* Machine Trap Handling */ 656 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 657 { 658 *val = env->mscratch; 659 return 0; 660 } 661 662 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 663 { 664 env->mscratch = val; 665 return 0; 666 } 667 668 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 669 { 670 *val = env->mepc; 671 return 0; 672 } 673 674 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 675 { 676 env->mepc = val; 677 return 0; 678 } 679 680 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 681 { 682 *val = env->mcause; 683 return 0; 684 } 685 686 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 687 { 688 env->mcause = val; 689 return 0; 690 } 691 692 static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val) 693 { 694 *val = env->mtval; 695 return 0; 696 } 697 698 static int write_mtval(CPURISCVState *env, int csrno, target_ulong val) 699 { 700 env->mtval = val; 701 return 0; 702 } 703 704 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 705 target_ulong new_value, target_ulong write_mask) 706 { 707 RISCVCPU *cpu = env_archcpu(env); 708 /* Allow software control of delegable interrupts not claimed by hardware */ 709 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 710 uint32_t old_mip; 711 712 if (mask) { 713 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 714 } else { 715 old_mip = env->mip; 716 } 717 718 if (ret_value) { 719 *ret_value = old_mip; 720 } 721 722 return 0; 723 } 724 725 /* Supervisor Trap Setup */ 726 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 727 { 728 target_ulong mask = (sstatus_v1_10_mask); 729 *val = env->mstatus & mask; 730 return 0; 731 } 732 733 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 734 { 735 target_ulong mask = (sstatus_v1_10_mask); 736 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 737 return write_mstatus(env, CSR_MSTATUS, newval); 738 } 739 740 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) 741 { 742 /* Shift the VS bits to their S bit location in vsie */ 743 *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; 744 return 0; 745 } 746 747 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 748 { 749 if (riscv_cpu_virt_enabled(env)) { 750 read_vsie(env, CSR_VSIE, val); 751 } else { 752 *val = env->mie & env->mideleg; 753 } 754 return 0; 755 } 756 757 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) 758 { 759 /* Shift the S bits to their VS bit location in mie */ 760 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | 761 ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); 762 return write_mie(env, CSR_MIE, newval); 763 } 764 765 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 766 { 767 if (riscv_cpu_virt_enabled(env)) { 768 write_vsie(env, CSR_VSIE, val); 769 } else { 770 target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | 771 (val & S_MODE_INTERRUPTS); 772 write_mie(env, CSR_MIE, newval); 773 } 774 775 return 0; 776 } 777 778 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 779 { 780 *val = env->stvec; 781 return 0; 782 } 783 784 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 785 { 786 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 787 if ((val & 3) < 2) { 788 env->stvec = val; 789 } else { 790 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 791 } 792 return 0; 793 } 794 795 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 796 { 797 *val = env->scounteren; 798 return 0; 799 } 800 801 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 802 { 803 env->scounteren = val; 804 return 0; 805 } 806 807 /* Supervisor Trap Handling */ 808 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 809 { 810 *val = env->sscratch; 811 return 0; 812 } 813 814 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 815 { 816 env->sscratch = val; 817 return 0; 818 } 819 820 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 821 { 822 *val = env->sepc; 823 return 0; 824 } 825 826 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 827 { 828 env->sepc = val; 829 return 0; 830 } 831 832 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 833 { 834 *val = env->scause; 835 return 0; 836 } 837 838 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 839 { 840 env->scause = val; 841 return 0; 842 } 843 844 static int read_stval(CPURISCVState *env, int csrno, target_ulong *val) 845 { 846 *val = env->stval; 847 return 0; 848 } 849 850 static int write_stval(CPURISCVState *env, int csrno, target_ulong val) 851 { 852 env->stval = val; 853 return 0; 854 } 855 856 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, 857 target_ulong new_value, target_ulong write_mask) 858 { 859 /* Shift the S bits to their VS bit location in mip */ 860 int ret = rmw_mip(env, 0, ret_value, new_value << 1, 861 (write_mask << 1) & vsip_writable_mask & env->hideleg); 862 *ret_value &= VS_MODE_INTERRUPTS; 863 /* Shift the VS bits to their S bit location in vsip */ 864 *ret_value >>= 1; 865 return ret; 866 } 867 868 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 869 target_ulong new_value, target_ulong write_mask) 870 { 871 int ret; 872 873 if (riscv_cpu_virt_enabled(env)) { 874 ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); 875 } else { 876 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 877 write_mask & env->mideleg & sip_writable_mask); 878 } 879 880 *ret_value &= env->mideleg; 881 return ret; 882 } 883 884 /* Supervisor Protection and Translation */ 885 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 886 { 887 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 888 *val = 0; 889 return 0; 890 } 891 892 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 893 return -RISCV_EXCP_ILLEGAL_INST; 894 } else { 895 *val = env->satp; 896 } 897 898 return 0; 899 } 900 901 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 902 { 903 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 904 return 0; 905 } 906 if (validate_vm(env, get_field(val, SATP_MODE)) && 907 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 908 { 909 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 910 return -RISCV_EXCP_ILLEGAL_INST; 911 } else { 912 if ((val ^ env->satp) & SATP_ASID) { 913 tlb_flush(env_cpu(env)); 914 } 915 env->satp = val; 916 } 917 } 918 return 0; 919 } 920 921 /* Hypervisor Extensions */ 922 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) 923 { 924 *val = env->hstatus; 925 if (!riscv_cpu_is_32bit(env)) { 926 /* We only support 64-bit VSXL */ 927 *val = set_field(*val, HSTATUS_VSXL, 2); 928 } 929 /* We only support little endian */ 930 *val = set_field(*val, HSTATUS_VSBE, 0); 931 return 0; 932 } 933 934 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) 935 { 936 env->hstatus = val; 937 if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) { 938 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 939 } 940 if (get_field(val, HSTATUS_VSBE) != 0) { 941 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 942 } 943 return 0; 944 } 945 946 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) 947 { 948 *val = env->hedeleg; 949 return 0; 950 } 951 952 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) 953 { 954 env->hedeleg = val; 955 return 0; 956 } 957 958 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) 959 { 960 *val = env->hideleg; 961 return 0; 962 } 963 964 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) 965 { 966 env->hideleg = val; 967 return 0; 968 } 969 970 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, 971 target_ulong new_value, target_ulong write_mask) 972 { 973 int ret = rmw_mip(env, 0, ret_value, new_value, 974 write_mask & hvip_writable_mask); 975 976 *ret_value &= hvip_writable_mask; 977 978 return ret; 979 } 980 981 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, 982 target_ulong new_value, target_ulong write_mask) 983 { 984 int ret = rmw_mip(env, 0, ret_value, new_value, 985 write_mask & hip_writable_mask); 986 987 *ret_value &= hip_writable_mask; 988 989 return ret; 990 } 991 992 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) 993 { 994 *val = env->mie & VS_MODE_INTERRUPTS; 995 return 0; 996 } 997 998 static int write_hie(CPURISCVState *env, int csrno, target_ulong val) 999 { 1000 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 1001 return write_mie(env, CSR_MIE, newval); 1002 } 1003 1004 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val) 1005 { 1006 *val = env->hcounteren; 1007 return 0; 1008 } 1009 1010 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) 1011 { 1012 env->hcounteren = val; 1013 return 0; 1014 } 1015 1016 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) 1017 { 1018 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1019 return 0; 1020 } 1021 1022 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) 1023 { 1024 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1025 return 0; 1026 } 1027 1028 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) 1029 { 1030 *val = env->htval; 1031 return 0; 1032 } 1033 1034 static int write_htval(CPURISCVState *env, int csrno, target_ulong val) 1035 { 1036 env->htval = val; 1037 return 0; 1038 } 1039 1040 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) 1041 { 1042 *val = env->htinst; 1043 return 0; 1044 } 1045 1046 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) 1047 { 1048 return 0; 1049 } 1050 1051 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) 1052 { 1053 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1054 return 0; 1055 } 1056 1057 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) 1058 { 1059 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); 1060 return 0; 1061 } 1062 1063 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) 1064 { 1065 *val = env->hgatp; 1066 return 0; 1067 } 1068 1069 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) 1070 { 1071 env->hgatp = val; 1072 return 0; 1073 } 1074 1075 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val) 1076 { 1077 if (!env->rdtime_fn) { 1078 return -RISCV_EXCP_ILLEGAL_INST; 1079 } 1080 1081 *val = env->htimedelta; 1082 return 0; 1083 } 1084 1085 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) 1086 { 1087 if (!env->rdtime_fn) { 1088 return -RISCV_EXCP_ILLEGAL_INST; 1089 } 1090 1091 if (riscv_cpu_is_32bit(env)) { 1092 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 1093 } else { 1094 env->htimedelta = val; 1095 } 1096 return 0; 1097 } 1098 1099 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) 1100 { 1101 if (!env->rdtime_fn) { 1102 return -RISCV_EXCP_ILLEGAL_INST; 1103 } 1104 1105 *val = env->htimedelta >> 32; 1106 return 0; 1107 } 1108 1109 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) 1110 { 1111 if (!env->rdtime_fn) { 1112 return -RISCV_EXCP_ILLEGAL_INST; 1113 } 1114 1115 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 1116 return 0; 1117 } 1118 1119 /* Virtual CSR Registers */ 1120 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) 1121 { 1122 *val = env->vsstatus; 1123 return 0; 1124 } 1125 1126 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) 1127 { 1128 uint64_t mask = (target_ulong)-1; 1129 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 1130 return 0; 1131 } 1132 1133 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 1134 { 1135 *val = env->vstvec; 1136 return 0; 1137 } 1138 1139 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) 1140 { 1141 env->vstvec = val; 1142 return 0; 1143 } 1144 1145 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) 1146 { 1147 *val = env->vsscratch; 1148 return 0; 1149 } 1150 1151 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) 1152 { 1153 env->vsscratch = val; 1154 return 0; 1155 } 1156 1157 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) 1158 { 1159 *val = env->vsepc; 1160 return 0; 1161 } 1162 1163 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) 1164 { 1165 env->vsepc = val; 1166 return 0; 1167 } 1168 1169 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) 1170 { 1171 *val = env->vscause; 1172 return 0; 1173 } 1174 1175 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) 1176 { 1177 env->vscause = val; 1178 return 0; 1179 } 1180 1181 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) 1182 { 1183 *val = env->vstval; 1184 return 0; 1185 } 1186 1187 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) 1188 { 1189 env->vstval = val; 1190 return 0; 1191 } 1192 1193 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) 1194 { 1195 *val = env->vsatp; 1196 return 0; 1197 } 1198 1199 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) 1200 { 1201 env->vsatp = val; 1202 return 0; 1203 } 1204 1205 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) 1206 { 1207 *val = env->mtval2; 1208 return 0; 1209 } 1210 1211 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) 1212 { 1213 env->mtval2 = val; 1214 return 0; 1215 } 1216 1217 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) 1218 { 1219 *val = env->mtinst; 1220 return 0; 1221 } 1222 1223 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) 1224 { 1225 env->mtinst = val; 1226 return 0; 1227 } 1228 1229 /* Physical Memory Protection */ 1230 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 1231 { 1232 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1233 return 0; 1234 } 1235 1236 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 1237 { 1238 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1239 return 0; 1240 } 1241 1242 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 1243 { 1244 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1245 return 0; 1246 } 1247 1248 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 1249 { 1250 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1251 return 0; 1252 } 1253 1254 #endif 1255 1256 /* 1257 * riscv_csrrw - read and/or update control and status register 1258 * 1259 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1260 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1261 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1262 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1263 */ 1264 1265 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 1266 target_ulong new_value, target_ulong write_mask) 1267 { 1268 int ret; 1269 target_ulong old_value; 1270 RISCVCPU *cpu = env_archcpu(env); 1271 1272 /* check privileges and return -1 if check fails */ 1273 #if !defined(CONFIG_USER_ONLY) 1274 int effective_priv = env->priv; 1275 int read_only = get_field(csrno, 0xC00) == 3; 1276 1277 if (riscv_has_ext(env, RVH) && 1278 env->priv == PRV_S && 1279 !riscv_cpu_virt_enabled(env)) { 1280 /* 1281 * We are in S mode without virtualisation, therefore we are in HS Mode. 1282 * Add 1 to the effective privledge level to allow us to access the 1283 * Hypervisor CSRs. 1284 */ 1285 effective_priv++; 1286 } 1287 1288 if ((write_mask && read_only) || 1289 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1290 return -RISCV_EXCP_ILLEGAL_INST; 1291 } 1292 #endif 1293 1294 /* ensure the CSR extension is enabled. */ 1295 if (!cpu->cfg.ext_icsr) { 1296 return -RISCV_EXCP_ILLEGAL_INST; 1297 } 1298 1299 /* check predicate */ 1300 if (!csr_ops[csrno].predicate) { 1301 return -RISCV_EXCP_ILLEGAL_INST; 1302 } 1303 ret = csr_ops[csrno].predicate(env, csrno); 1304 if (ret != RISCV_EXCP_NONE) { 1305 return -ret; 1306 } 1307 1308 /* execute combined read/write operation if it exists */ 1309 if (csr_ops[csrno].op) { 1310 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1311 } 1312 1313 /* if no accessor exists then return failure */ 1314 if (!csr_ops[csrno].read) { 1315 return -RISCV_EXCP_ILLEGAL_INST; 1316 } 1317 1318 /* read old value */ 1319 ret = csr_ops[csrno].read(env, csrno, &old_value); 1320 if (ret < 0) { 1321 return ret; 1322 } 1323 1324 /* write value if writable and write mask set, otherwise drop writes */ 1325 if (write_mask) { 1326 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1327 if (csr_ops[csrno].write) { 1328 ret = csr_ops[csrno].write(env, csrno, new_value); 1329 if (ret < 0) { 1330 return ret; 1331 } 1332 } 1333 } 1334 1335 /* return old value */ 1336 if (ret_value) { 1337 *ret_value = old_value; 1338 } 1339 1340 return 0; 1341 } 1342 1343 /* 1344 * Debugger support. If not in user mode, set env->debugger before the 1345 * riscv_csrrw call and clear it after the call. 1346 */ 1347 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 1348 target_ulong new_value, target_ulong write_mask) 1349 { 1350 int ret; 1351 #if !defined(CONFIG_USER_ONLY) 1352 env->debugger = true; 1353 #endif 1354 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1355 #if !defined(CONFIG_USER_ONLY) 1356 env->debugger = false; 1357 #endif 1358 return ret; 1359 } 1360 1361 /* Control and Status Register function table */ 1362 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1363 /* User Floating-Point CSRs */ 1364 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 1365 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 1366 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 1367 /* Vector CSRs */ 1368 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 1369 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 1370 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 1371 [CSR_VL] = { "vl", vs, read_vl }, 1372 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 1373 /* User Timers and Counters */ 1374 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 1375 [CSR_INSTRET] = { "instret", ctr, read_instret }, 1376 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 1377 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 1378 1379 /* 1380 * In privileged mode, the monitor will have to emulate TIME CSRs only if 1381 * rdtime callback is not provided by machine/platform emulation. 1382 */ 1383 [CSR_TIME] = { "time", ctr, read_time }, 1384 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 1385 1386 #if !defined(CONFIG_USER_ONLY) 1387 /* Machine Timers and Counters */ 1388 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 1389 [CSR_MINSTRET] = { "minstret", any, read_instret }, 1390 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 1391 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 1392 1393 /* Machine Information Registers */ 1394 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 1395 [CSR_MARCHID] = { "marchid", any, read_zero }, 1396 [CSR_MIMPID] = { "mimpid", any, read_zero }, 1397 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 1398 1399 /* Machine Trap Setup */ 1400 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, 1401 [CSR_MISA] = { "misa", any, read_misa, write_misa }, 1402 [CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg }, 1403 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 1404 [CSR_MIE] = { "mie", any, read_mie, write_mie }, 1405 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 1406 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 1407 1408 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 1409 1410 /* Machine Trap Handling */ 1411 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch }, 1412 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 1413 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 1414 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 1415 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 1416 1417 /* Supervisor Trap Setup */ 1418 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, 1419 [CSR_SIE] = { "sie", smode, read_sie, write_sie }, 1420 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 1421 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 1422 1423 /* Supervisor Trap Handling */ 1424 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch }, 1425 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 1426 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 1427 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 1428 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 1429 1430 /* Supervisor Protection and Translation */ 1431 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 1432 1433 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, 1434 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, 1435 [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg }, 1436 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, 1437 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, 1438 [CSR_HIE] = { "hie", hmode, read_hie, write_hie }, 1439 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, 1440 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, 1441 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, 1442 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, 1443 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip }, 1444 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, 1445 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, 1446 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, 1447 1448 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, 1449 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, 1450 [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie }, 1451 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, 1452 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, 1453 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, 1454 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, 1455 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, 1456 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, 1457 1458 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, 1459 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, 1460 1461 /* Physical Memory Protection */ 1462 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 1463 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 1464 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 1465 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 1466 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 1467 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 1468 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 1469 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 1470 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 1471 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 1472 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 1473 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 1474 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 1475 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 1476 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 1477 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 1478 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 1479 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 1480 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 1481 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 1482 1483 /* Performance Counters */ 1484 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 1485 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 1486 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 1487 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 1488 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 1489 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 1490 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 1491 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 1492 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 1493 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 1494 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 1495 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 1496 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 1497 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 1498 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 1499 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 1500 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 1501 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 1502 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 1503 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 1504 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 1505 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 1506 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 1507 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 1508 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 1509 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 1510 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 1511 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 1512 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 1513 1514 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 1515 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 1516 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 1517 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 1518 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 1519 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 1520 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 1521 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 1522 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 1523 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 1524 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 1525 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 1526 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 1527 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 1528 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 1529 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 1530 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 1531 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 1532 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 1533 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 1534 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 1535 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 1536 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 1537 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 1538 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 1539 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 1540 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 1541 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 1542 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 1543 1544 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 1545 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 1546 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 1547 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 1548 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 1549 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 1550 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 1551 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 1552 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 1553 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 1554 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 1555 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 1556 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 1557 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 1558 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 1559 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 1560 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 1561 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 1562 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 1563 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 1564 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 1565 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 1566 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 1567 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 1568 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 1569 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 1570 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 1571 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 1572 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 1573 1574 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 1575 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 1576 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 1577 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 1578 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 1579 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 1580 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 1581 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 1582 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 1583 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 1584 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 1585 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 1586 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 1587 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 1588 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 1589 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 1590 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 1591 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 1592 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 1593 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 1594 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 1595 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 1596 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 1597 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 1598 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 1599 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 1600 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 1601 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 1602 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 1603 1604 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 1605 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 1606 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 1607 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 1608 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 1609 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 1610 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 1611 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 1612 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 1613 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 1614 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 1615 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 1616 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 1617 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 1618 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 1619 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 1620 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 1621 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 1622 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 1623 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 1624 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 1625 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 1626 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 1627 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 1628 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 1629 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 1630 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 1631 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 1632 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 1633 #endif /* !CONFIG_USER_ONLY */ 1634 }; 1635