1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (cpu->cfg.ext_zve32f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 } else { 78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 79 } 80 81 #ifdef CONFIG_USER_ONLY 82 flags |= TB_FLAGS_MSTATUS_FS; 83 flags |= TB_FLAGS_MSTATUS_VS; 84 #else 85 flags |= cpu_mmu_index(env, 0); 86 if (riscv_cpu_fp_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_FS; 88 } 89 90 if (riscv_cpu_vector_enabled(env)) { 91 flags |= env->mstatus & MSTATUS_VS; 92 } 93 94 if (riscv_has_ext(env, RVH)) { 95 if (env->priv == PRV_M || 96 (env->priv == PRV_S && !env->virt_enabled) || 97 (env->priv == PRV_U && !env->virt_enabled && 98 get_field(env->hstatus, HSTATUS_HU))) { 99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 100 } 101 102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 103 get_field(env->mstatus_hs, MSTATUS_FS)); 104 105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 106 get_field(env->mstatus_hs, MSTATUS_VS)); 107 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled); 108 } 109 if (cpu->cfg.debug && !icount_enabled()) { 110 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 111 } 112 #endif 113 114 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 115 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 116 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 117 } 118 if (env->cur_pmbase != 0) { 119 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 120 } 121 122 *pflags = flags; 123 } 124 125 void riscv_cpu_update_mask(CPURISCVState *env) 126 { 127 target_ulong mask = -1, base = 0; 128 /* 129 * TODO: Current RVJ spec does not specify 130 * how the extension interacts with XLEN. 131 */ 132 #ifndef CONFIG_USER_ONLY 133 if (riscv_has_ext(env, RVJ)) { 134 switch (env->priv) { 135 case PRV_M: 136 if (env->mmte & M_PM_ENABLE) { 137 mask = env->mpmmask; 138 base = env->mpmbase; 139 } 140 break; 141 case PRV_S: 142 if (env->mmte & S_PM_ENABLE) { 143 mask = env->spmmask; 144 base = env->spmbase; 145 } 146 break; 147 case PRV_U: 148 if (env->mmte & U_PM_ENABLE) { 149 mask = env->upmmask; 150 base = env->upmbase; 151 } 152 break; 153 default: 154 g_assert_not_reached(); 155 } 156 } 157 #endif 158 if (env->xl == MXL_RV32) { 159 env->cur_pmmask = mask & UINT32_MAX; 160 env->cur_pmbase = base & UINT32_MAX; 161 } else { 162 env->cur_pmmask = mask; 163 env->cur_pmbase = base; 164 } 165 } 166 167 #ifndef CONFIG_USER_ONLY 168 169 /* 170 * The HS-mode is allowed to configure priority only for the 171 * following VS-mode local interrupts: 172 * 173 * 0 (Reserved interrupt, reads as zero) 174 * 1 Supervisor software interrupt 175 * 4 (Reserved interrupt, reads as zero) 176 * 5 Supervisor timer interrupt 177 * 8 (Reserved interrupt, reads as zero) 178 * 13 (Reserved interrupt) 179 * 14 " 180 * 15 " 181 * 16 " 182 * 17 " 183 * 18 " 184 * 19 " 185 * 20 " 186 * 21 " 187 * 22 " 188 * 23 " 189 */ 190 191 static const int hviprio_index2irq[] = { 192 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 193 static const int hviprio_index2rdzero[] = { 194 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 195 196 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 197 { 198 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 199 return -EINVAL; 200 } 201 202 if (out_irq) { 203 *out_irq = hviprio_index2irq[index]; 204 } 205 206 if (out_rdzero) { 207 *out_rdzero = hviprio_index2rdzero[index]; 208 } 209 210 return 0; 211 } 212 213 /* 214 * Default priorities of local interrupts are defined in the 215 * RISC-V Advanced Interrupt Architecture specification. 216 * 217 * ---------------------------------------------------------------- 218 * Default | 219 * Priority | Major Interrupt Numbers 220 * ---------------------------------------------------------------- 221 * Highest | 47, 23, 46, 45, 22, 44, 222 * | 43, 21, 42, 41, 20, 40 223 * | 224 * | 11 (0b), 3 (03), 7 (07) 225 * | 9 (09), 1 (01), 5 (05) 226 * | 12 (0c) 227 * | 10 (0a), 2 (02), 6 (06) 228 * | 229 * | 39, 19, 38, 37, 18, 36, 230 * Lowest | 35, 17, 34, 33, 16, 32 231 * ---------------------------------------------------------------- 232 */ 233 static const uint8_t default_iprio[64] = { 234 /* Custom interrupts 48 to 63 */ 235 [63] = IPRIO_MMAXIPRIO, 236 [62] = IPRIO_MMAXIPRIO, 237 [61] = IPRIO_MMAXIPRIO, 238 [60] = IPRIO_MMAXIPRIO, 239 [59] = IPRIO_MMAXIPRIO, 240 [58] = IPRIO_MMAXIPRIO, 241 [57] = IPRIO_MMAXIPRIO, 242 [56] = IPRIO_MMAXIPRIO, 243 [55] = IPRIO_MMAXIPRIO, 244 [54] = IPRIO_MMAXIPRIO, 245 [53] = IPRIO_MMAXIPRIO, 246 [52] = IPRIO_MMAXIPRIO, 247 [51] = IPRIO_MMAXIPRIO, 248 [50] = IPRIO_MMAXIPRIO, 249 [49] = IPRIO_MMAXIPRIO, 250 [48] = IPRIO_MMAXIPRIO, 251 252 /* Custom interrupts 24 to 31 */ 253 [31] = IPRIO_MMAXIPRIO, 254 [30] = IPRIO_MMAXIPRIO, 255 [29] = IPRIO_MMAXIPRIO, 256 [28] = IPRIO_MMAXIPRIO, 257 [27] = IPRIO_MMAXIPRIO, 258 [26] = IPRIO_MMAXIPRIO, 259 [25] = IPRIO_MMAXIPRIO, 260 [24] = IPRIO_MMAXIPRIO, 261 262 [47] = IPRIO_DEFAULT_UPPER, 263 [23] = IPRIO_DEFAULT_UPPER + 1, 264 [46] = IPRIO_DEFAULT_UPPER + 2, 265 [45] = IPRIO_DEFAULT_UPPER + 3, 266 [22] = IPRIO_DEFAULT_UPPER + 4, 267 [44] = IPRIO_DEFAULT_UPPER + 5, 268 269 [43] = IPRIO_DEFAULT_UPPER + 6, 270 [21] = IPRIO_DEFAULT_UPPER + 7, 271 [42] = IPRIO_DEFAULT_UPPER + 8, 272 [41] = IPRIO_DEFAULT_UPPER + 9, 273 [20] = IPRIO_DEFAULT_UPPER + 10, 274 [40] = IPRIO_DEFAULT_UPPER + 11, 275 276 [11] = IPRIO_DEFAULT_M, 277 [3] = IPRIO_DEFAULT_M + 1, 278 [7] = IPRIO_DEFAULT_M + 2, 279 280 [9] = IPRIO_DEFAULT_S, 281 [1] = IPRIO_DEFAULT_S + 1, 282 [5] = IPRIO_DEFAULT_S + 2, 283 284 [12] = IPRIO_DEFAULT_SGEXT, 285 286 [10] = IPRIO_DEFAULT_VS, 287 [2] = IPRIO_DEFAULT_VS + 1, 288 [6] = IPRIO_DEFAULT_VS + 2, 289 290 [39] = IPRIO_DEFAULT_LOWER, 291 [19] = IPRIO_DEFAULT_LOWER + 1, 292 [38] = IPRIO_DEFAULT_LOWER + 2, 293 [37] = IPRIO_DEFAULT_LOWER + 3, 294 [18] = IPRIO_DEFAULT_LOWER + 4, 295 [36] = IPRIO_DEFAULT_LOWER + 5, 296 297 [35] = IPRIO_DEFAULT_LOWER + 6, 298 [17] = IPRIO_DEFAULT_LOWER + 7, 299 [34] = IPRIO_DEFAULT_LOWER + 8, 300 [33] = IPRIO_DEFAULT_LOWER + 9, 301 [16] = IPRIO_DEFAULT_LOWER + 10, 302 [32] = IPRIO_DEFAULT_LOWER + 11, 303 }; 304 305 uint8_t riscv_cpu_default_priority(int irq) 306 { 307 if (irq < 0 || irq > 63) { 308 return IPRIO_MMAXIPRIO; 309 } 310 311 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 312 }; 313 314 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 315 int extirq, unsigned int extirq_def_prio, 316 uint64_t pending, uint8_t *iprio) 317 { 318 int irq, best_irq = RISCV_EXCP_NONE; 319 unsigned int prio, best_prio = UINT_MAX; 320 321 if (!pending) { 322 return RISCV_EXCP_NONE; 323 } 324 325 irq = ctz64(pending); 326 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 327 riscv_cpu_cfg(env)->ext_ssaia)) { 328 return irq; 329 } 330 331 pending = pending >> irq; 332 while (pending) { 333 prio = iprio[irq]; 334 if (!prio) { 335 if (irq == extirq) { 336 prio = extirq_def_prio; 337 } else { 338 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 339 1 : IPRIO_MMAXIPRIO; 340 } 341 } 342 if ((pending & 0x1) && (prio <= best_prio)) { 343 best_irq = irq; 344 best_prio = prio; 345 } 346 irq++; 347 pending = pending >> 1; 348 } 349 350 return best_irq; 351 } 352 353 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 354 { 355 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 356 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 357 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 358 359 return (env->mip | vsgein | vstip) & env->mie; 360 } 361 362 int riscv_cpu_mirq_pending(CPURISCVState *env) 363 { 364 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 365 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 366 367 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 368 irqs, env->miprio); 369 } 370 371 int riscv_cpu_sirq_pending(CPURISCVState *env) 372 { 373 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 374 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 375 376 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 377 irqs, env->siprio); 378 } 379 380 int riscv_cpu_vsirq_pending(CPURISCVState *env) 381 { 382 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 383 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 384 385 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 386 irqs >> 1, env->hviprio); 387 } 388 389 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 390 { 391 int virq; 392 uint64_t irqs, pending, mie, hsie, vsie; 393 394 /* Determine interrupt enable state of all privilege modes */ 395 if (env->virt_enabled) { 396 mie = 1; 397 hsie = 1; 398 vsie = (env->priv < PRV_S) || 399 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 400 } else { 401 mie = (env->priv < PRV_M) || 402 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 403 hsie = (env->priv < PRV_S) || 404 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 405 vsie = 0; 406 } 407 408 /* Determine all pending interrupts */ 409 pending = riscv_cpu_all_pending(env); 410 411 /* Check M-mode interrupts */ 412 irqs = pending & ~env->mideleg & -mie; 413 if (irqs) { 414 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 415 irqs, env->miprio); 416 } 417 418 /* Check HS-mode interrupts */ 419 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 420 if (irqs) { 421 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 422 irqs, env->siprio); 423 } 424 425 /* Check VS-mode interrupts */ 426 irqs = pending & env->mideleg & env->hideleg & -vsie; 427 if (irqs) { 428 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 429 irqs >> 1, env->hviprio); 430 return (virq <= 0) ? virq : virq + 1; 431 } 432 433 /* Indicate no pending interrupt */ 434 return RISCV_EXCP_NONE; 435 } 436 437 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 438 { 439 if (interrupt_request & CPU_INTERRUPT_HARD) { 440 RISCVCPU *cpu = RISCV_CPU(cs); 441 CPURISCVState *env = &cpu->env; 442 int interruptno = riscv_cpu_local_irq_pending(env); 443 if (interruptno >= 0) { 444 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 445 riscv_cpu_do_interrupt(cs); 446 return true; 447 } 448 } 449 return false; 450 } 451 452 /* Return true is floating point support is currently enabled */ 453 bool riscv_cpu_fp_enabled(CPURISCVState *env) 454 { 455 if (env->mstatus & MSTATUS_FS) { 456 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 457 return false; 458 } 459 return true; 460 } 461 462 return false; 463 } 464 465 /* Return true is vector support is currently enabled */ 466 bool riscv_cpu_vector_enabled(CPURISCVState *env) 467 { 468 if (env->mstatus & MSTATUS_VS) { 469 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 470 return false; 471 } 472 return true; 473 } 474 475 return false; 476 } 477 478 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 479 { 480 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 481 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 482 MSTATUS64_UXL | MSTATUS_VS; 483 484 if (riscv_has_ext(env, RVF)) { 485 mstatus_mask |= MSTATUS_FS; 486 } 487 bool current_virt = env->virt_enabled; 488 489 g_assert(riscv_has_ext(env, RVH)); 490 491 if (current_virt) { 492 /* Current V=1 and we are about to change to V=0 */ 493 env->vsstatus = env->mstatus & mstatus_mask; 494 env->mstatus &= ~mstatus_mask; 495 env->mstatus |= env->mstatus_hs; 496 497 env->vstvec = env->stvec; 498 env->stvec = env->stvec_hs; 499 500 env->vsscratch = env->sscratch; 501 env->sscratch = env->sscratch_hs; 502 503 env->vsepc = env->sepc; 504 env->sepc = env->sepc_hs; 505 506 env->vscause = env->scause; 507 env->scause = env->scause_hs; 508 509 env->vstval = env->stval; 510 env->stval = env->stval_hs; 511 512 env->vsatp = env->satp; 513 env->satp = env->satp_hs; 514 } else { 515 /* Current V=0 and we are about to change to V=1 */ 516 env->mstatus_hs = env->mstatus & mstatus_mask; 517 env->mstatus &= ~mstatus_mask; 518 env->mstatus |= env->vsstatus; 519 520 env->stvec_hs = env->stvec; 521 env->stvec = env->vstvec; 522 523 env->sscratch_hs = env->sscratch; 524 env->sscratch = env->vsscratch; 525 526 env->sepc_hs = env->sepc; 527 env->sepc = env->vsepc; 528 529 env->scause_hs = env->scause; 530 env->scause = env->vscause; 531 532 env->stval_hs = env->stval; 533 env->stval = env->vstval; 534 535 env->satp_hs = env->satp; 536 env->satp = env->vsatp; 537 } 538 } 539 540 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 541 { 542 if (!riscv_has_ext(env, RVH)) { 543 return 0; 544 } 545 546 return env->geilen; 547 } 548 549 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 550 { 551 if (!riscv_has_ext(env, RVH)) { 552 return; 553 } 554 555 if (geilen > (TARGET_LONG_BITS - 1)) { 556 return; 557 } 558 559 env->geilen = geilen; 560 } 561 562 /* This function can only be called to set virt when RVH is enabled */ 563 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 564 { 565 /* Flush the TLB on all virt mode changes. */ 566 if (env->virt_enabled != enable) { 567 tlb_flush(env_cpu(env)); 568 } 569 570 env->virt_enabled = enable; 571 572 if (enable) { 573 /* 574 * The guest external interrupts from an interrupt controller are 575 * delivered only when the Guest/VM is running (i.e. V=1). This means 576 * any guest external interrupt which is triggered while the Guest/VM 577 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 578 * with sluggish response to serial console input and other I/O events. 579 * 580 * To solve this, we check and inject interrupt after setting V=1. 581 */ 582 riscv_cpu_update_mip(env, 0, 0); 583 } 584 } 585 586 bool riscv_cpu_two_stage_lookup(int mmu_idx) 587 { 588 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 589 } 590 591 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 592 { 593 CPURISCVState *env = &cpu->env; 594 if (env->miclaim & interrupts) { 595 return -1; 596 } else { 597 env->miclaim |= interrupts; 598 return 0; 599 } 600 } 601 602 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 603 uint64_t value) 604 { 605 CPUState *cs = env_cpu(env); 606 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 607 608 if (env->virt_enabled) { 609 gein = get_field(env->hstatus, HSTATUS_VGEIN); 610 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 611 } 612 613 vstip = env->vstime_irq ? MIP_VSTIP : 0; 614 615 QEMU_IOTHREAD_LOCK_GUARD(); 616 617 env->mip = (env->mip & ~mask) | (value & mask); 618 619 if (env->mip | vsgein | vstip) { 620 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 621 } else { 622 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 623 } 624 625 return old; 626 } 627 628 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 629 void *arg) 630 { 631 env->rdtime_fn = fn; 632 env->rdtime_fn_arg = arg; 633 } 634 635 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 636 int (*rmw_fn)(void *arg, 637 target_ulong reg, 638 target_ulong *val, 639 target_ulong new_val, 640 target_ulong write_mask), 641 void *rmw_fn_arg) 642 { 643 if (priv <= PRV_M) { 644 env->aia_ireg_rmw_fn[priv] = rmw_fn; 645 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 646 } 647 } 648 649 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 650 { 651 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); 652 653 if (icount_enabled() && newpriv != env->priv) { 654 riscv_itrigger_update_priv(env); 655 } 656 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 657 env->priv = newpriv; 658 env->xl = cpu_recompute_xl(env); 659 riscv_cpu_update_mask(env); 660 661 /* 662 * Clear the load reservation - otherwise a reservation placed in one 663 * context/process can be used by another, resulting in an SC succeeding 664 * incorrectly. Version 2.2 of the ISA specification explicitly requires 665 * this behaviour, while later revisions say that the kernel "should" use 666 * an SC instruction to force the yielding of a load reservation on a 667 * preemptive context switch. As a result, do both. 668 */ 669 env->load_res = -1; 670 } 671 672 /* 673 * get_physical_address_pmp - check PMP permission for this physical address 674 * 675 * Match the PMP region and check permission for this physical address and it's 676 * TLB page. Returns 0 if the permission checking was successful 677 * 678 * @env: CPURISCVState 679 * @prot: The returned protection attributes 680 * @tlb_size: TLB page size containing addr. It could be modified after PMP 681 * permission checking. NULL if not set TLB page for addr. 682 * @addr: The physical address to be checked permission 683 * @access_type: The type of MMU access 684 * @mode: Indicates current privilege level. 685 */ 686 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 687 target_ulong *tlb_size, hwaddr addr, 688 int size, MMUAccessType access_type, 689 int mode) 690 { 691 pmp_priv_t pmp_priv; 692 int pmp_index = -1; 693 694 if (!riscv_cpu_cfg(env)->pmp) { 695 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 696 return TRANSLATE_SUCCESS; 697 } 698 699 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 700 &pmp_priv, mode); 701 if (pmp_index < 0) { 702 *prot = 0; 703 return TRANSLATE_PMP_FAIL; 704 } 705 706 *prot = pmp_priv_to_page_prot(pmp_priv); 707 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 708 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 709 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 710 711 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 712 } 713 714 return TRANSLATE_SUCCESS; 715 } 716 717 /* 718 * get_physical_address - get the physical address for this virtual address 719 * 720 * Do a page table walk to obtain the physical address corresponding to a 721 * virtual address. Returns 0 if the translation was successful 722 * 723 * Adapted from Spike's mmu_t::translate and mmu_t::walk 724 * 725 * @env: CPURISCVState 726 * @physical: This will be set to the calculated physical address 727 * @prot: The returned protection attributes 728 * @addr: The virtual address or guest physical address to be translated 729 * @fault_pte_addr: If not NULL, this will be set to fault pte address 730 * when a error occurs on pte address translation. 731 * This will already be shifted to match htval. 732 * @access_type: The type of MMU access 733 * @mmu_idx: Indicates current privilege level 734 * @first_stage: Are we in first stage translation? 735 * Second stage is used for hypervisor guest translation 736 * @two_stage: Are we going to perform two stage translation 737 * @is_debug: Is this access from a debugger or the monitor? 738 */ 739 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 740 int *prot, vaddr addr, 741 target_ulong *fault_pte_addr, 742 int access_type, int mmu_idx, 743 bool first_stage, bool two_stage, 744 bool is_debug) 745 { 746 /* 747 * NOTE: the env->pc value visible here will not be 748 * correct, but the value visible to the exception handler 749 * (riscv_cpu_do_interrupt) is correct 750 */ 751 MemTxResult res; 752 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 753 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 754 bool use_background = false; 755 hwaddr ppn; 756 int napot_bits = 0; 757 target_ulong napot_mask; 758 759 /* 760 * Check if we should use the background registers for the two 761 * stage translation. We don't need to check if we actually need 762 * two stage translation as that happened before this function 763 * was called. Background registers will be used if the guest has 764 * forced a two stage translation to be on (in HS or M mode). 765 */ 766 if (!env->virt_enabled && two_stage) { 767 use_background = true; 768 } 769 770 /* 771 * MPRV does not affect the virtual-machine load/store 772 * instructions, HLV, HLVX, and HSV. 773 */ 774 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 775 mode = get_field(env->hstatus, HSTATUS_SPVP); 776 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 777 if (get_field(env->mstatus, MSTATUS_MPRV)) { 778 mode = get_field(env->mstatus, MSTATUS_MPP); 779 } 780 } 781 782 if (first_stage == false) { 783 /* 784 * We are in stage 2 translation, this is similar to stage 1. 785 * Stage 2 is always taken as U-mode 786 */ 787 mode = PRV_U; 788 } 789 790 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 791 *physical = addr; 792 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 793 return TRANSLATE_SUCCESS; 794 } 795 796 *prot = 0; 797 798 hwaddr base; 799 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 800 801 if (first_stage == true) { 802 mxr = get_field(env->mstatus, MSTATUS_MXR); 803 } else { 804 mxr = get_field(env->vsstatus, MSTATUS_MXR); 805 } 806 807 if (first_stage == true) { 808 if (use_background) { 809 if (riscv_cpu_mxl(env) == MXL_RV32) { 810 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 811 vm = get_field(env->vsatp, SATP32_MODE); 812 } else { 813 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 814 vm = get_field(env->vsatp, SATP64_MODE); 815 } 816 } else { 817 if (riscv_cpu_mxl(env) == MXL_RV32) { 818 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 819 vm = get_field(env->satp, SATP32_MODE); 820 } else { 821 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 822 vm = get_field(env->satp, SATP64_MODE); 823 } 824 } 825 widened = 0; 826 } else { 827 if (riscv_cpu_mxl(env) == MXL_RV32) { 828 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 829 vm = get_field(env->hgatp, SATP32_MODE); 830 } else { 831 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 832 vm = get_field(env->hgatp, SATP64_MODE); 833 } 834 widened = 2; 835 } 836 /* status.SUM will be ignored if execute on background */ 837 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 838 switch (vm) { 839 case VM_1_10_SV32: 840 levels = 2; ptidxbits = 10; ptesize = 4; break; 841 case VM_1_10_SV39: 842 levels = 3; ptidxbits = 9; ptesize = 8; break; 843 case VM_1_10_SV48: 844 levels = 4; ptidxbits = 9; ptesize = 8; break; 845 case VM_1_10_SV57: 846 levels = 5; ptidxbits = 9; ptesize = 8; break; 847 case VM_1_10_MBARE: 848 *physical = addr; 849 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 850 return TRANSLATE_SUCCESS; 851 default: 852 g_assert_not_reached(); 853 } 854 855 CPUState *cs = env_cpu(env); 856 int va_bits = PGSHIFT + levels * ptidxbits + widened; 857 target_ulong mask, masked_msbs; 858 859 if (TARGET_LONG_BITS > (va_bits - 1)) { 860 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 861 } else { 862 mask = 0; 863 } 864 masked_msbs = (addr >> (va_bits - 1)) & mask; 865 866 if (masked_msbs != 0 && masked_msbs != mask) { 867 return TRANSLATE_FAIL; 868 } 869 870 int ptshift = (levels - 1) * ptidxbits; 871 int i; 872 873 #if !TCG_OVERSIZED_GUEST 874 restart: 875 #endif 876 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 877 target_ulong idx; 878 if (i == 0) { 879 idx = (addr >> (PGSHIFT + ptshift)) & 880 ((1 << (ptidxbits + widened)) - 1); 881 } else { 882 idx = (addr >> (PGSHIFT + ptshift)) & 883 ((1 << ptidxbits) - 1); 884 } 885 886 /* check that physical address of PTE is legal */ 887 hwaddr pte_addr; 888 889 if (two_stage && first_stage) { 890 int vbase_prot; 891 hwaddr vbase; 892 893 /* Do the second stage translation on the base PTE address. */ 894 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 895 base, NULL, MMU_DATA_LOAD, 896 mmu_idx, false, true, 897 is_debug); 898 899 if (vbase_ret != TRANSLATE_SUCCESS) { 900 if (fault_pte_addr) { 901 *fault_pte_addr = (base + idx * ptesize) >> 2; 902 } 903 return TRANSLATE_G_STAGE_FAIL; 904 } 905 906 pte_addr = vbase + idx * ptesize; 907 } else { 908 pte_addr = base + idx * ptesize; 909 } 910 911 int pmp_prot; 912 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 913 sizeof(target_ulong), 914 MMU_DATA_LOAD, PRV_S); 915 if (pmp_ret != TRANSLATE_SUCCESS) { 916 return TRANSLATE_PMP_FAIL; 917 } 918 919 target_ulong pte; 920 if (riscv_cpu_mxl(env) == MXL_RV32) { 921 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 922 } else { 923 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 924 } 925 926 if (res != MEMTX_OK) { 927 return TRANSLATE_FAIL; 928 } 929 930 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 931 bool hade = env->menvcfg & MENVCFG_HADE; 932 933 if (first_stage && two_stage && env->virt_enabled) { 934 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 935 hade = hade && (env->henvcfg & HENVCFG_HADE); 936 } 937 938 if (riscv_cpu_sxl(env) == MXL_RV32) { 939 ppn = pte >> PTE_PPN_SHIFT; 940 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 941 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 942 } else { 943 ppn = pte >> PTE_PPN_SHIFT; 944 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 945 return TRANSLATE_FAIL; 946 } 947 } 948 949 if (!(pte & PTE_V)) { 950 /* Invalid PTE */ 951 return TRANSLATE_FAIL; 952 } else if (!pbmte && (pte & PTE_PBMT)) { 953 return TRANSLATE_FAIL; 954 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 955 /* Inner PTE, continue walking */ 956 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 957 return TRANSLATE_FAIL; 958 } 959 base = ppn << PGSHIFT; 960 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 961 /* Reserved leaf PTE flags: PTE_W */ 962 return TRANSLATE_FAIL; 963 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 964 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 965 return TRANSLATE_FAIL; 966 } else if ((pte & PTE_U) && ((mode != PRV_U) && 967 (!sum || access_type == MMU_INST_FETCH))) { 968 /* User PTE flags when not U mode and mstatus.SUM is not set, 969 or the access type is an instruction fetch */ 970 return TRANSLATE_FAIL; 971 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 972 /* Supervisor PTE flags when not S mode */ 973 return TRANSLATE_FAIL; 974 } else if (ppn & ((1ULL << ptshift) - 1)) { 975 /* Misaligned PPN */ 976 return TRANSLATE_FAIL; 977 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 978 ((pte & PTE_X) && mxr))) { 979 /* Read access check failed */ 980 return TRANSLATE_FAIL; 981 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 982 /* Write access check failed */ 983 return TRANSLATE_FAIL; 984 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 985 /* Fetch access check failed */ 986 return TRANSLATE_FAIL; 987 } else { 988 /* if necessary, set accessed and dirty bits. */ 989 target_ulong updated_pte = pte | PTE_A | 990 (access_type == MMU_DATA_STORE ? PTE_D : 0); 991 992 /* Page table updates need to be atomic with MTTCG enabled */ 993 if (updated_pte != pte) { 994 if (!hade) { 995 return TRANSLATE_FAIL; 996 } 997 998 /* 999 * - if accessed or dirty bits need updating, and the PTE is 1000 * in RAM, then we do so atomically with a compare and swap. 1001 * - if the PTE is in IO space or ROM, then it can't be updated 1002 * and we return TRANSLATE_FAIL. 1003 * - if the PTE changed by the time we went to update it, then 1004 * it is no longer valid and we must re-walk the page table. 1005 */ 1006 MemoryRegion *mr; 1007 hwaddr l = sizeof(target_ulong), addr1; 1008 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1009 false, MEMTXATTRS_UNSPECIFIED); 1010 if (memory_region_is_ram(mr)) { 1011 target_ulong *pte_pa = 1012 qemu_map_ram_ptr(mr->ram_block, addr1); 1013 #if TCG_OVERSIZED_GUEST 1014 /* 1015 * MTTCG is not enabled on oversized TCG guests so 1016 * page table updates do not need to be atomic 1017 */ 1018 *pte_pa = pte = updated_pte; 1019 #else 1020 target_ulong old_pte = 1021 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1022 if (old_pte != pte) { 1023 goto restart; 1024 } else { 1025 pte = updated_pte; 1026 } 1027 #endif 1028 } else { 1029 /* 1030 * misconfigured PTE in ROM (AD bits are not preset) or 1031 * PTE is in IO space and can't be updated atomically 1032 */ 1033 return TRANSLATE_FAIL; 1034 } 1035 } 1036 1037 /* 1038 * for superpage mappings, make a fake leaf PTE for the TLB's 1039 * benefit. 1040 */ 1041 target_ulong vpn = addr >> PGSHIFT; 1042 1043 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1044 napot_bits = ctzl(ppn) + 1; 1045 if ((i != (levels - 1)) || (napot_bits != 4)) { 1046 return TRANSLATE_FAIL; 1047 } 1048 } 1049 1050 napot_mask = (1 << napot_bits) - 1; 1051 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1052 (vpn & (((target_ulong)1 << ptshift) - 1)) 1053 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1054 1055 /* set permissions on the TLB entry */ 1056 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1057 *prot |= PAGE_READ; 1058 } 1059 if (pte & PTE_X) { 1060 *prot |= PAGE_EXEC; 1061 } 1062 /* 1063 * add write permission on stores or if the page is already dirty, 1064 * so that we TLB miss on later writes to update the dirty bit 1065 */ 1066 if ((pte & PTE_W) && 1067 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1068 *prot |= PAGE_WRITE; 1069 } 1070 return TRANSLATE_SUCCESS; 1071 } 1072 } 1073 return TRANSLATE_FAIL; 1074 } 1075 1076 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1077 MMUAccessType access_type, bool pmp_violation, 1078 bool first_stage, bool two_stage, 1079 bool two_stage_indirect) 1080 { 1081 CPUState *cs = env_cpu(env); 1082 int page_fault_exceptions, vm; 1083 uint64_t stap_mode; 1084 1085 if (riscv_cpu_mxl(env) == MXL_RV32) { 1086 stap_mode = SATP32_MODE; 1087 } else { 1088 stap_mode = SATP64_MODE; 1089 } 1090 1091 if (first_stage) { 1092 vm = get_field(env->satp, stap_mode); 1093 } else { 1094 vm = get_field(env->hgatp, stap_mode); 1095 } 1096 1097 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1098 1099 switch (access_type) { 1100 case MMU_INST_FETCH: 1101 if (env->virt_enabled && !first_stage) { 1102 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1103 } else { 1104 cs->exception_index = page_fault_exceptions ? 1105 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1106 } 1107 break; 1108 case MMU_DATA_LOAD: 1109 if (two_stage && !first_stage) { 1110 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1111 } else { 1112 cs->exception_index = page_fault_exceptions ? 1113 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1114 } 1115 break; 1116 case MMU_DATA_STORE: 1117 if (two_stage && !first_stage) { 1118 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1119 } else { 1120 cs->exception_index = page_fault_exceptions ? 1121 RISCV_EXCP_STORE_PAGE_FAULT : 1122 RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1123 } 1124 break; 1125 default: 1126 g_assert_not_reached(); 1127 } 1128 env->badaddr = address; 1129 env->two_stage_lookup = two_stage; 1130 env->two_stage_indirect_lookup = two_stage_indirect; 1131 } 1132 1133 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1134 { 1135 RISCVCPU *cpu = RISCV_CPU(cs); 1136 CPURISCVState *env = &cpu->env; 1137 hwaddr phys_addr; 1138 int prot; 1139 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1140 1141 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1142 true, env->virt_enabled, true)) { 1143 return -1; 1144 } 1145 1146 if (env->virt_enabled) { 1147 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1148 0, mmu_idx, false, true, true)) { 1149 return -1; 1150 } 1151 } 1152 1153 return phys_addr & TARGET_PAGE_MASK; 1154 } 1155 1156 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1157 vaddr addr, unsigned size, 1158 MMUAccessType access_type, 1159 int mmu_idx, MemTxAttrs attrs, 1160 MemTxResult response, uintptr_t retaddr) 1161 { 1162 RISCVCPU *cpu = RISCV_CPU(cs); 1163 CPURISCVState *env = &cpu->env; 1164 1165 if (access_type == MMU_DATA_STORE) { 1166 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1167 } else if (access_type == MMU_DATA_LOAD) { 1168 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1169 } else { 1170 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1171 } 1172 1173 env->badaddr = addr; 1174 env->two_stage_lookup = env->virt_enabled || 1175 riscv_cpu_two_stage_lookup(mmu_idx); 1176 env->two_stage_indirect_lookup = false; 1177 cpu_loop_exit_restore(cs, retaddr); 1178 } 1179 1180 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1181 MMUAccessType access_type, int mmu_idx, 1182 uintptr_t retaddr) 1183 { 1184 RISCVCPU *cpu = RISCV_CPU(cs); 1185 CPURISCVState *env = &cpu->env; 1186 switch (access_type) { 1187 case MMU_INST_FETCH: 1188 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1189 break; 1190 case MMU_DATA_LOAD: 1191 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1192 break; 1193 case MMU_DATA_STORE: 1194 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1195 break; 1196 default: 1197 g_assert_not_reached(); 1198 } 1199 env->badaddr = addr; 1200 env->two_stage_lookup = env->virt_enabled || 1201 riscv_cpu_two_stage_lookup(mmu_idx); 1202 env->two_stage_indirect_lookup = false; 1203 cpu_loop_exit_restore(cs, retaddr); 1204 } 1205 1206 1207 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1208 { 1209 enum riscv_pmu_event_idx pmu_event_type; 1210 1211 switch (access_type) { 1212 case MMU_INST_FETCH: 1213 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1214 break; 1215 case MMU_DATA_LOAD: 1216 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1217 break; 1218 case MMU_DATA_STORE: 1219 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1220 break; 1221 default: 1222 return; 1223 } 1224 1225 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1226 } 1227 1228 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1229 MMUAccessType access_type, int mmu_idx, 1230 bool probe, uintptr_t retaddr) 1231 { 1232 RISCVCPU *cpu = RISCV_CPU(cs); 1233 CPURISCVState *env = &cpu->env; 1234 vaddr im_address; 1235 hwaddr pa = 0; 1236 int prot, prot2, prot_pmp; 1237 bool pmp_violation = false; 1238 bool first_stage_error = true; 1239 bool two_stage_lookup = false; 1240 bool two_stage_indirect_error = false; 1241 int ret = TRANSLATE_FAIL; 1242 int mode = mmu_idx; 1243 /* default TLB page size */ 1244 target_ulong tlb_size = TARGET_PAGE_SIZE; 1245 1246 env->guest_phys_fault_addr = 0; 1247 1248 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1249 __func__, address, access_type, mmu_idx); 1250 1251 /* 1252 * MPRV does not affect the virtual-machine load/store 1253 * instructions, HLV, HLVX, and HSV. 1254 */ 1255 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1256 mode = get_field(env->hstatus, HSTATUS_SPVP); 1257 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1258 get_field(env->mstatus, MSTATUS_MPRV)) { 1259 mode = get_field(env->mstatus, MSTATUS_MPP); 1260 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1261 two_stage_lookup = true; 1262 } 1263 } 1264 1265 pmu_tlb_fill_incr_ctr(cpu, access_type); 1266 if (env->virt_enabled || 1267 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1268 access_type != MMU_INST_FETCH)) { 1269 /* Two stage lookup */ 1270 ret = get_physical_address(env, &pa, &prot, address, 1271 &env->guest_phys_fault_addr, access_type, 1272 mmu_idx, true, true, false); 1273 1274 /* 1275 * A G-stage exception may be triggered during two state lookup. 1276 * And the env->guest_phys_fault_addr has already been set in 1277 * get_physical_address(). 1278 */ 1279 if (ret == TRANSLATE_G_STAGE_FAIL) { 1280 first_stage_error = false; 1281 two_stage_indirect_error = true; 1282 access_type = MMU_DATA_LOAD; 1283 } 1284 1285 qemu_log_mask(CPU_LOG_MMU, 1286 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1287 HWADDR_FMT_plx " prot %d\n", 1288 __func__, address, ret, pa, prot); 1289 1290 if (ret == TRANSLATE_SUCCESS) { 1291 /* Second stage lookup */ 1292 im_address = pa; 1293 1294 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1295 access_type, mmu_idx, false, true, 1296 false); 1297 1298 qemu_log_mask(CPU_LOG_MMU, 1299 "%s 2nd-stage address=%" VADDR_PRIx 1300 " ret %d physical " 1301 HWADDR_FMT_plx " prot %d\n", 1302 __func__, im_address, ret, pa, prot2); 1303 1304 prot &= prot2; 1305 1306 if (ret == TRANSLATE_SUCCESS) { 1307 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1308 size, access_type, mode); 1309 1310 qemu_log_mask(CPU_LOG_MMU, 1311 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1312 " %d tlb_size " TARGET_FMT_lu "\n", 1313 __func__, pa, ret, prot_pmp, tlb_size); 1314 1315 prot &= prot_pmp; 1316 } 1317 1318 if (ret != TRANSLATE_SUCCESS) { 1319 /* 1320 * Guest physical address translation failed, this is a HS 1321 * level exception 1322 */ 1323 first_stage_error = false; 1324 env->guest_phys_fault_addr = (im_address | 1325 (address & 1326 (TARGET_PAGE_SIZE - 1))) >> 2; 1327 } 1328 } 1329 } else { 1330 /* Single stage lookup */ 1331 ret = get_physical_address(env, &pa, &prot, address, NULL, 1332 access_type, mmu_idx, true, false, false); 1333 1334 qemu_log_mask(CPU_LOG_MMU, 1335 "%s address=%" VADDR_PRIx " ret %d physical " 1336 HWADDR_FMT_plx " prot %d\n", 1337 __func__, address, ret, pa, prot); 1338 1339 if (ret == TRANSLATE_SUCCESS) { 1340 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1341 size, access_type, mode); 1342 1343 qemu_log_mask(CPU_LOG_MMU, 1344 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1345 " %d tlb_size " TARGET_FMT_lu "\n", 1346 __func__, pa, ret, prot_pmp, tlb_size); 1347 1348 prot &= prot_pmp; 1349 } 1350 } 1351 1352 if (ret == TRANSLATE_PMP_FAIL) { 1353 pmp_violation = true; 1354 } 1355 1356 if (ret == TRANSLATE_SUCCESS) { 1357 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1358 prot, mmu_idx, tlb_size); 1359 return true; 1360 } else if (probe) { 1361 return false; 1362 } else { 1363 raise_mmu_exception(env, address, access_type, pmp_violation, 1364 first_stage_error, 1365 env->virt_enabled || 1366 riscv_cpu_two_stage_lookup(mmu_idx), 1367 two_stage_indirect_error); 1368 cpu_loop_exit_restore(cs, retaddr); 1369 } 1370 1371 return true; 1372 } 1373 1374 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1375 target_ulong insn, 1376 target_ulong taddr) 1377 { 1378 target_ulong xinsn = 0; 1379 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1380 1381 /* 1382 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1383 * be uncompressed. The Quadrant 1 of RVC instruction space need 1384 * not be transformed because these instructions won't generate 1385 * any load/store trap. 1386 */ 1387 1388 if ((insn & 0x3) != 0x3) { 1389 /* Transform 16bit instruction into 32bit instruction */ 1390 switch (GET_C_OP(insn)) { 1391 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1392 switch (GET_C_FUNC(insn)) { 1393 case OPC_RISC_C_FUNC_FLD_LQ: 1394 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1395 xinsn = OPC_RISC_FLD; 1396 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1397 access_rs1 = GET_C_RS1S(insn); 1398 access_imm = GET_C_LD_IMM(insn); 1399 access_size = 8; 1400 } 1401 break; 1402 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1403 xinsn = OPC_RISC_LW; 1404 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1405 access_rs1 = GET_C_RS1S(insn); 1406 access_imm = GET_C_LW_IMM(insn); 1407 access_size = 4; 1408 break; 1409 case OPC_RISC_C_FUNC_FLW_LD: 1410 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1411 xinsn = OPC_RISC_FLW; 1412 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1413 access_rs1 = GET_C_RS1S(insn); 1414 access_imm = GET_C_LW_IMM(insn); 1415 access_size = 4; 1416 } else { /* C.LD (RV64/RV128) */ 1417 xinsn = OPC_RISC_LD; 1418 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1419 access_rs1 = GET_C_RS1S(insn); 1420 access_imm = GET_C_LD_IMM(insn); 1421 access_size = 8; 1422 } 1423 break; 1424 case OPC_RISC_C_FUNC_FSD_SQ: 1425 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1426 xinsn = OPC_RISC_FSD; 1427 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1428 access_rs1 = GET_C_RS1S(insn); 1429 access_imm = GET_C_SD_IMM(insn); 1430 access_size = 8; 1431 } 1432 break; 1433 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1434 xinsn = OPC_RISC_SW; 1435 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1436 access_rs1 = GET_C_RS1S(insn); 1437 access_imm = GET_C_SW_IMM(insn); 1438 access_size = 4; 1439 break; 1440 case OPC_RISC_C_FUNC_FSW_SD: 1441 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1442 xinsn = OPC_RISC_FSW; 1443 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1444 access_rs1 = GET_C_RS1S(insn); 1445 access_imm = GET_C_SW_IMM(insn); 1446 access_size = 4; 1447 } else { /* C.SD (RV64/RV128) */ 1448 xinsn = OPC_RISC_SD; 1449 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1450 access_rs1 = GET_C_RS1S(insn); 1451 access_imm = GET_C_SD_IMM(insn); 1452 access_size = 8; 1453 } 1454 break; 1455 default: 1456 break; 1457 } 1458 break; 1459 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1460 switch (GET_C_FUNC(insn)) { 1461 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1462 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1463 xinsn = OPC_RISC_FLD; 1464 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1465 access_rs1 = 2; 1466 access_imm = GET_C_LDSP_IMM(insn); 1467 access_size = 8; 1468 } 1469 break; 1470 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1471 xinsn = OPC_RISC_LW; 1472 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1473 access_rs1 = 2; 1474 access_imm = GET_C_LWSP_IMM(insn); 1475 access_size = 4; 1476 break; 1477 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1478 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1479 xinsn = OPC_RISC_FLW; 1480 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1481 access_rs1 = 2; 1482 access_imm = GET_C_LWSP_IMM(insn); 1483 access_size = 4; 1484 } else { /* C.LDSP (RV64/RV128) */ 1485 xinsn = OPC_RISC_LD; 1486 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1487 access_rs1 = 2; 1488 access_imm = GET_C_LDSP_IMM(insn); 1489 access_size = 8; 1490 } 1491 break; 1492 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1493 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1494 xinsn = OPC_RISC_FSD; 1495 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1496 access_rs1 = 2; 1497 access_imm = GET_C_SDSP_IMM(insn); 1498 access_size = 8; 1499 } 1500 break; 1501 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1502 xinsn = OPC_RISC_SW; 1503 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1504 access_rs1 = 2; 1505 access_imm = GET_C_SWSP_IMM(insn); 1506 access_size = 4; 1507 break; 1508 case 7: 1509 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1510 xinsn = OPC_RISC_FSW; 1511 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1512 access_rs1 = 2; 1513 access_imm = GET_C_SWSP_IMM(insn); 1514 access_size = 4; 1515 } else { /* C.SDSP (RV64/RV128) */ 1516 xinsn = OPC_RISC_SD; 1517 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1518 access_rs1 = 2; 1519 access_imm = GET_C_SDSP_IMM(insn); 1520 access_size = 8; 1521 } 1522 break; 1523 default: 1524 break; 1525 } 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 /* 1532 * Clear Bit1 of transformed instruction to indicate that 1533 * original insruction was a 16bit instruction 1534 */ 1535 xinsn &= ~((target_ulong)0x2); 1536 } else { 1537 /* Transform 32bit (or wider) instructions */ 1538 switch (MASK_OP_MAJOR(insn)) { 1539 case OPC_RISC_ATOMIC: 1540 xinsn = insn; 1541 access_rs1 = GET_RS1(insn); 1542 access_size = 1 << GET_FUNCT3(insn); 1543 break; 1544 case OPC_RISC_LOAD: 1545 case OPC_RISC_FP_LOAD: 1546 xinsn = SET_I_IMM(insn, 0); 1547 access_rs1 = GET_RS1(insn); 1548 access_imm = GET_IMM(insn); 1549 access_size = 1 << GET_FUNCT3(insn); 1550 break; 1551 case OPC_RISC_STORE: 1552 case OPC_RISC_FP_STORE: 1553 xinsn = SET_S_IMM(insn, 0); 1554 access_rs1 = GET_RS1(insn); 1555 access_imm = GET_STORE_IMM(insn); 1556 access_size = 1 << GET_FUNCT3(insn); 1557 break; 1558 case OPC_RISC_SYSTEM: 1559 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1560 xinsn = insn; 1561 access_rs1 = GET_RS1(insn); 1562 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1563 access_size = 1 << access_size; 1564 } 1565 break; 1566 default: 1567 break; 1568 } 1569 } 1570 1571 if (access_size) { 1572 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1573 (access_size - 1)); 1574 } 1575 1576 return xinsn; 1577 } 1578 #endif /* !CONFIG_USER_ONLY */ 1579 1580 /* 1581 * Handle Traps 1582 * 1583 * Adapted from Spike's processor_t::take_trap. 1584 * 1585 */ 1586 void riscv_cpu_do_interrupt(CPUState *cs) 1587 { 1588 #if !defined(CONFIG_USER_ONLY) 1589 1590 RISCVCPU *cpu = RISCV_CPU(cs); 1591 CPURISCVState *env = &cpu->env; 1592 bool write_gva = false; 1593 uint64_t s; 1594 1595 /* 1596 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1597 * so we mask off the MSB and separate into trap type and cause. 1598 */ 1599 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1600 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1601 uint64_t deleg = async ? env->mideleg : env->medeleg; 1602 target_ulong tval = 0; 1603 target_ulong tinst = 0; 1604 target_ulong htval = 0; 1605 target_ulong mtval2 = 0; 1606 1607 if (cause == RISCV_EXCP_SEMIHOST) { 1608 do_common_semihosting(cs); 1609 env->pc += 4; 1610 return; 1611 } 1612 1613 if (!async) { 1614 /* set tval to badaddr for traps with address information */ 1615 switch (cause) { 1616 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1617 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1618 case RISCV_EXCP_LOAD_ADDR_MIS: 1619 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1620 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1621 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1622 case RISCV_EXCP_LOAD_PAGE_FAULT: 1623 case RISCV_EXCP_STORE_PAGE_FAULT: 1624 write_gva = env->two_stage_lookup; 1625 tval = env->badaddr; 1626 if (env->two_stage_indirect_lookup) { 1627 /* 1628 * special pseudoinstruction for G-stage fault taken while 1629 * doing VS-stage page table walk. 1630 */ 1631 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1632 } else { 1633 /* 1634 * The "Addr. Offset" field in transformed instruction is 1635 * non-zero only for misaligned access. 1636 */ 1637 tinst = riscv_transformed_insn(env, env->bins, tval); 1638 } 1639 break; 1640 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1641 case RISCV_EXCP_INST_ADDR_MIS: 1642 case RISCV_EXCP_INST_ACCESS_FAULT: 1643 case RISCV_EXCP_INST_PAGE_FAULT: 1644 write_gva = env->two_stage_lookup; 1645 tval = env->badaddr; 1646 if (env->two_stage_indirect_lookup) { 1647 /* 1648 * special pseudoinstruction for G-stage fault taken while 1649 * doing VS-stage page table walk. 1650 */ 1651 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1652 } 1653 break; 1654 case RISCV_EXCP_ILLEGAL_INST: 1655 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1656 tval = env->bins; 1657 break; 1658 case RISCV_EXCP_BREAKPOINT: 1659 if (cs->watchpoint_hit) { 1660 tval = cs->watchpoint_hit->hitaddr; 1661 cs->watchpoint_hit = NULL; 1662 } 1663 break; 1664 default: 1665 break; 1666 } 1667 /* ecall is dispatched as one cause so translate based on mode */ 1668 if (cause == RISCV_EXCP_U_ECALL) { 1669 assert(env->priv <= 3); 1670 1671 if (env->priv == PRV_M) { 1672 cause = RISCV_EXCP_M_ECALL; 1673 } else if (env->priv == PRV_S && env->virt_enabled) { 1674 cause = RISCV_EXCP_VS_ECALL; 1675 } else if (env->priv == PRV_S && !env->virt_enabled) { 1676 cause = RISCV_EXCP_S_ECALL; 1677 } else if (env->priv == PRV_U) { 1678 cause = RISCV_EXCP_U_ECALL; 1679 } 1680 } 1681 } 1682 1683 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1684 riscv_cpu_get_trap_name(cause, async)); 1685 1686 qemu_log_mask(CPU_LOG_INT, 1687 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1688 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1689 __func__, env->mhartid, async, cause, env->pc, tval, 1690 riscv_cpu_get_trap_name(cause, async)); 1691 1692 if (env->priv <= PRV_S && 1693 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1694 /* handle the trap in S-mode */ 1695 if (riscv_has_ext(env, RVH)) { 1696 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1697 1698 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1699 /* Trap to VS mode */ 1700 /* 1701 * See if we need to adjust cause. Yes if its VS mode interrupt 1702 * no if hypervisor has delegated one of hs mode's interrupt 1703 */ 1704 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1705 cause == IRQ_VS_EXT) { 1706 cause = cause - 1; 1707 } 1708 write_gva = false; 1709 } else if (env->virt_enabled) { 1710 /* Trap into HS mode, from virt */ 1711 riscv_cpu_swap_hypervisor_regs(env); 1712 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1713 env->priv); 1714 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1715 1716 htval = env->guest_phys_fault_addr; 1717 1718 riscv_cpu_set_virt_enabled(env, 0); 1719 } else { 1720 /* Trap into HS mode */ 1721 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1722 htval = env->guest_phys_fault_addr; 1723 } 1724 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1725 } 1726 1727 s = env->mstatus; 1728 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1729 s = set_field(s, MSTATUS_SPP, env->priv); 1730 s = set_field(s, MSTATUS_SIE, 0); 1731 env->mstatus = s; 1732 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1733 env->sepc = env->pc; 1734 env->stval = tval; 1735 env->htval = htval; 1736 env->htinst = tinst; 1737 env->pc = (env->stvec >> 2 << 2) + 1738 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1739 riscv_cpu_set_mode(env, PRV_S); 1740 } else { 1741 /* handle the trap in M-mode */ 1742 if (riscv_has_ext(env, RVH)) { 1743 if (env->virt_enabled) { 1744 riscv_cpu_swap_hypervisor_regs(env); 1745 } 1746 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1747 env->virt_enabled); 1748 if (env->virt_enabled && tval) { 1749 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1750 } 1751 1752 mtval2 = env->guest_phys_fault_addr; 1753 1754 /* Trapping to M mode, virt is disabled */ 1755 riscv_cpu_set_virt_enabled(env, 0); 1756 } 1757 1758 s = env->mstatus; 1759 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1760 s = set_field(s, MSTATUS_MPP, env->priv); 1761 s = set_field(s, MSTATUS_MIE, 0); 1762 env->mstatus = s; 1763 env->mcause = cause | ~(((target_ulong)-1) >> async); 1764 env->mepc = env->pc; 1765 env->mtval = tval; 1766 env->mtval2 = mtval2; 1767 env->mtinst = tinst; 1768 env->pc = (env->mtvec >> 2 << 2) + 1769 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1770 riscv_cpu_set_mode(env, PRV_M); 1771 } 1772 1773 /* 1774 * NOTE: it is not necessary to yield load reservations here. It is only 1775 * necessary for an SC from "another hart" to cause a load reservation 1776 * to be yielded. Refer to the memory consistency model section of the 1777 * RISC-V ISA Specification. 1778 */ 1779 1780 env->two_stage_lookup = false; 1781 env->two_stage_indirect_lookup = false; 1782 #endif 1783 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1784 } 1785