1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 #include "semihosting/common-semi.h" 28 29 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 30 { 31 #ifdef CONFIG_USER_ONLY 32 return 0; 33 #else 34 return env->priv; 35 #endif 36 } 37 38 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 39 target_ulong *cs_base, uint32_t *pflags) 40 { 41 uint32_t flags = 0; 42 43 *pc = env->pc; 44 *cs_base = 0; 45 46 if (riscv_has_ext(env, RVV)) { 47 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 48 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 49 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 50 FIELD_EX64(env->vtype, VTYPE, VILL)); 51 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 52 FIELD_EX64(env->vtype, VTYPE, VSEW)); 53 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 54 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 55 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 56 } else { 57 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 58 } 59 60 #ifdef CONFIG_USER_ONLY 61 flags |= TB_FLAGS_MSTATUS_FS; 62 #else 63 flags |= cpu_mmu_index(env, 0); 64 if (riscv_cpu_fp_enabled(env)) { 65 flags |= env->mstatus & MSTATUS_FS; 66 } 67 68 if (riscv_has_ext(env, RVH)) { 69 if (env->priv == PRV_M || 70 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 71 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 72 get_field(env->hstatus, HSTATUS_HU))) { 73 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 74 } 75 76 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 77 get_field(env->mstatus_hs, MSTATUS_FS)); 78 } 79 #endif 80 81 *pflags = flags; 82 } 83 84 #ifndef CONFIG_USER_ONLY 85 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 86 { 87 target_ulong irqs; 88 89 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 90 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 91 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 92 93 target_ulong pending = env->mip & env->mie & 94 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 95 target_ulong vspending = (env->mip & env->mie & 96 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); 97 98 target_ulong mie = env->priv < PRV_M || 99 (env->priv == PRV_M && mstatus_mie); 100 target_ulong sie = env->priv < PRV_S || 101 (env->priv == PRV_S && mstatus_sie); 102 target_ulong hs_sie = env->priv < PRV_S || 103 (env->priv == PRV_S && hs_mstatus_sie); 104 105 if (riscv_cpu_virt_enabled(env)) { 106 target_ulong pending_hs_irq = pending & -hs_sie; 107 108 if (pending_hs_irq) { 109 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 110 return ctz64(pending_hs_irq); 111 } 112 113 pending = vspending; 114 } 115 116 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 117 118 if (irqs) { 119 return ctz64(irqs); /* since non-zero */ 120 } else { 121 return RISCV_EXCP_NONE; /* indicates no pending interrupt */ 122 } 123 } 124 125 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 126 { 127 if (interrupt_request & CPU_INTERRUPT_HARD) { 128 RISCVCPU *cpu = RISCV_CPU(cs); 129 CPURISCVState *env = &cpu->env; 130 int interruptno = riscv_cpu_local_irq_pending(env); 131 if (interruptno >= 0) { 132 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 133 riscv_cpu_do_interrupt(cs); 134 return true; 135 } 136 } 137 return false; 138 } 139 140 /* Return true is floating point support is currently enabled */ 141 bool riscv_cpu_fp_enabled(CPURISCVState *env) 142 { 143 if (env->mstatus & MSTATUS_FS) { 144 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 145 return false; 146 } 147 return true; 148 } 149 150 return false; 151 } 152 153 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 154 { 155 uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD; 156 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 157 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 158 MSTATUS64_UXL | sd; 159 bool current_virt = riscv_cpu_virt_enabled(env); 160 161 g_assert(riscv_has_ext(env, RVH)); 162 163 if (current_virt) { 164 /* Current V=1 and we are about to change to V=0 */ 165 env->vsstatus = env->mstatus & mstatus_mask; 166 env->mstatus &= ~mstatus_mask; 167 env->mstatus |= env->mstatus_hs; 168 169 env->vstvec = env->stvec; 170 env->stvec = env->stvec_hs; 171 172 env->vsscratch = env->sscratch; 173 env->sscratch = env->sscratch_hs; 174 175 env->vsepc = env->sepc; 176 env->sepc = env->sepc_hs; 177 178 env->vscause = env->scause; 179 env->scause = env->scause_hs; 180 181 env->vstval = env->stval; 182 env->stval = env->stval_hs; 183 184 env->vsatp = env->satp; 185 env->satp = env->satp_hs; 186 } else { 187 /* Current V=0 and we are about to change to V=1 */ 188 env->mstatus_hs = env->mstatus & mstatus_mask; 189 env->mstatus &= ~mstatus_mask; 190 env->mstatus |= env->vsstatus; 191 192 env->stvec_hs = env->stvec; 193 env->stvec = env->vstvec; 194 195 env->sscratch_hs = env->sscratch; 196 env->sscratch = env->vsscratch; 197 198 env->sepc_hs = env->sepc; 199 env->sepc = env->vsepc; 200 201 env->scause_hs = env->scause; 202 env->scause = env->vscause; 203 204 env->stval_hs = env->stval; 205 env->stval = env->vstval; 206 207 env->satp_hs = env->satp; 208 env->satp = env->vsatp; 209 } 210 } 211 212 bool riscv_cpu_virt_enabled(CPURISCVState *env) 213 { 214 if (!riscv_has_ext(env, RVH)) { 215 return false; 216 } 217 218 return get_field(env->virt, VIRT_ONOFF); 219 } 220 221 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 222 { 223 if (!riscv_has_ext(env, RVH)) { 224 return; 225 } 226 227 /* Flush the TLB on all virt mode changes. */ 228 if (get_field(env->virt, VIRT_ONOFF) != enable) { 229 tlb_flush(env_cpu(env)); 230 } 231 232 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 233 } 234 235 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 236 { 237 if (!riscv_has_ext(env, RVH)) { 238 return false; 239 } 240 241 return get_field(env->virt, FORCE_HS_EXCEP); 242 } 243 244 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 245 { 246 if (!riscv_has_ext(env, RVH)) { 247 return; 248 } 249 250 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 251 } 252 253 bool riscv_cpu_two_stage_lookup(int mmu_idx) 254 { 255 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 256 } 257 258 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 259 { 260 CPURISCVState *env = &cpu->env; 261 if (env->miclaim & interrupts) { 262 return -1; 263 } else { 264 env->miclaim |= interrupts; 265 return 0; 266 } 267 } 268 269 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 270 { 271 CPURISCVState *env = &cpu->env; 272 CPUState *cs = CPU(cpu); 273 uint32_t old = env->mip; 274 bool locked = false; 275 276 if (!qemu_mutex_iothread_locked()) { 277 locked = true; 278 qemu_mutex_lock_iothread(); 279 } 280 281 env->mip = (env->mip & ~mask) | (value & mask); 282 283 if (env->mip) { 284 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 285 } else { 286 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 287 } 288 289 if (locked) { 290 qemu_mutex_unlock_iothread(); 291 } 292 293 return old; 294 } 295 296 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 297 uint32_t arg) 298 { 299 env->rdtime_fn = fn; 300 env->rdtime_fn_arg = arg; 301 } 302 303 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 304 { 305 if (newpriv > PRV_M) { 306 g_assert_not_reached(); 307 } 308 if (newpriv == PRV_H) { 309 newpriv = PRV_U; 310 } 311 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 312 env->priv = newpriv; 313 314 /* 315 * Clear the load reservation - otherwise a reservation placed in one 316 * context/process can be used by another, resulting in an SC succeeding 317 * incorrectly. Version 2.2 of the ISA specification explicitly requires 318 * this behaviour, while later revisions say that the kernel "should" use 319 * an SC instruction to force the yielding of a load reservation on a 320 * preemptive context switch. As a result, do both. 321 */ 322 env->load_res = -1; 323 } 324 325 /* 326 * get_physical_address_pmp - check PMP permission for this physical address 327 * 328 * Match the PMP region and check permission for this physical address and it's 329 * TLB page. Returns 0 if the permission checking was successful 330 * 331 * @env: CPURISCVState 332 * @prot: The returned protection attributes 333 * @tlb_size: TLB page size containing addr. It could be modified after PMP 334 * permission checking. NULL if not set TLB page for addr. 335 * @addr: The physical address to be checked permission 336 * @access_type: The type of MMU access 337 * @mode: Indicates current privilege level. 338 */ 339 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 340 target_ulong *tlb_size, hwaddr addr, 341 int size, MMUAccessType access_type, 342 int mode) 343 { 344 pmp_priv_t pmp_priv; 345 target_ulong tlb_size_pmp = 0; 346 347 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 348 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 349 return TRANSLATE_SUCCESS; 350 } 351 352 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, 353 mode)) { 354 *prot = 0; 355 return TRANSLATE_PMP_FAIL; 356 } 357 358 *prot = pmp_priv_to_page_prot(pmp_priv); 359 if (tlb_size != NULL) { 360 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { 361 *tlb_size = tlb_size_pmp; 362 } 363 } 364 365 return TRANSLATE_SUCCESS; 366 } 367 368 /* get_physical_address - get the physical address for this virtual address 369 * 370 * Do a page table walk to obtain the physical address corresponding to a 371 * virtual address. Returns 0 if the translation was successful 372 * 373 * Adapted from Spike's mmu_t::translate and mmu_t::walk 374 * 375 * @env: CPURISCVState 376 * @physical: This will be set to the calculated physical address 377 * @prot: The returned protection attributes 378 * @addr: The virtual address to be translated 379 * @fault_pte_addr: If not NULL, this will be set to fault pte address 380 * when a error occurs on pte address translation. 381 * This will already be shifted to match htval. 382 * @access_type: The type of MMU access 383 * @mmu_idx: Indicates current privilege level 384 * @first_stage: Are we in first stage translation? 385 * Second stage is used for hypervisor guest translation 386 * @two_stage: Are we going to perform two stage translation 387 * @is_debug: Is this access from a debugger or the monitor? 388 */ 389 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 390 int *prot, target_ulong addr, 391 target_ulong *fault_pte_addr, 392 int access_type, int mmu_idx, 393 bool first_stage, bool two_stage, 394 bool is_debug) 395 { 396 /* NOTE: the env->pc value visible here will not be 397 * correct, but the value visible to the exception handler 398 * (riscv_cpu_do_interrupt) is correct */ 399 MemTxResult res; 400 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 401 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 402 bool use_background = false; 403 404 /* 405 * Check if we should use the background registers for the two 406 * stage translation. We don't need to check if we actually need 407 * two stage translation as that happened before this function 408 * was called. Background registers will be used if the guest has 409 * forced a two stage translation to be on (in HS or M mode). 410 */ 411 if (!riscv_cpu_virt_enabled(env) && two_stage) { 412 use_background = true; 413 } 414 415 /* MPRV does not affect the virtual-machine load/store 416 instructions, HLV, HLVX, and HSV. */ 417 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 418 mode = get_field(env->hstatus, HSTATUS_SPVP); 419 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 420 if (get_field(env->mstatus, MSTATUS_MPRV)) { 421 mode = get_field(env->mstatus, MSTATUS_MPP); 422 } 423 } 424 425 if (first_stage == false) { 426 /* We are in stage 2 translation, this is similar to stage 1. */ 427 /* Stage 2 is always taken as U-mode */ 428 mode = PRV_U; 429 } 430 431 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 432 *physical = addr; 433 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 434 return TRANSLATE_SUCCESS; 435 } 436 437 *prot = 0; 438 439 hwaddr base; 440 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 441 442 if (first_stage == true) { 443 mxr = get_field(env->mstatus, MSTATUS_MXR); 444 } else { 445 mxr = get_field(env->vsstatus, MSTATUS_MXR); 446 } 447 448 if (first_stage == true) { 449 if (use_background) { 450 if (riscv_cpu_mxl(env) == MXL_RV32) { 451 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 452 vm = get_field(env->vsatp, SATP32_MODE); 453 } else { 454 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 455 vm = get_field(env->vsatp, SATP64_MODE); 456 } 457 } else { 458 if (riscv_cpu_mxl(env) == MXL_RV32) { 459 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 460 vm = get_field(env->satp, SATP32_MODE); 461 } else { 462 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 463 vm = get_field(env->satp, SATP64_MODE); 464 } 465 } 466 widened = 0; 467 } else { 468 if (riscv_cpu_mxl(env) == MXL_RV32) { 469 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 470 vm = get_field(env->hgatp, SATP32_MODE); 471 } else { 472 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 473 vm = get_field(env->hgatp, SATP64_MODE); 474 } 475 widened = 2; 476 } 477 /* status.SUM will be ignored if execute on background */ 478 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 479 switch (vm) { 480 case VM_1_10_SV32: 481 levels = 2; ptidxbits = 10; ptesize = 4; break; 482 case VM_1_10_SV39: 483 levels = 3; ptidxbits = 9; ptesize = 8; break; 484 case VM_1_10_SV48: 485 levels = 4; ptidxbits = 9; ptesize = 8; break; 486 case VM_1_10_SV57: 487 levels = 5; ptidxbits = 9; ptesize = 8; break; 488 case VM_1_10_MBARE: 489 *physical = addr; 490 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 491 return TRANSLATE_SUCCESS; 492 default: 493 g_assert_not_reached(); 494 } 495 496 CPUState *cs = env_cpu(env); 497 int va_bits = PGSHIFT + levels * ptidxbits + widened; 498 target_ulong mask, masked_msbs; 499 500 if (TARGET_LONG_BITS > (va_bits - 1)) { 501 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 502 } else { 503 mask = 0; 504 } 505 masked_msbs = (addr >> (va_bits - 1)) & mask; 506 507 if (masked_msbs != 0 && masked_msbs != mask) { 508 return TRANSLATE_FAIL; 509 } 510 511 int ptshift = (levels - 1) * ptidxbits; 512 int i; 513 514 #if !TCG_OVERSIZED_GUEST 515 restart: 516 #endif 517 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 518 target_ulong idx; 519 if (i == 0) { 520 idx = (addr >> (PGSHIFT + ptshift)) & 521 ((1 << (ptidxbits + widened)) - 1); 522 } else { 523 idx = (addr >> (PGSHIFT + ptshift)) & 524 ((1 << ptidxbits) - 1); 525 } 526 527 /* check that physical address of PTE is legal */ 528 hwaddr pte_addr; 529 530 if (two_stage && first_stage) { 531 int vbase_prot; 532 hwaddr vbase; 533 534 /* Do the second stage translation on the base PTE address. */ 535 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 536 base, NULL, MMU_DATA_LOAD, 537 mmu_idx, false, true, 538 is_debug); 539 540 if (vbase_ret != TRANSLATE_SUCCESS) { 541 if (fault_pte_addr) { 542 *fault_pte_addr = (base + idx * ptesize) >> 2; 543 } 544 return TRANSLATE_G_STAGE_FAIL; 545 } 546 547 pte_addr = vbase + idx * ptesize; 548 } else { 549 pte_addr = base + idx * ptesize; 550 } 551 552 int pmp_prot; 553 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 554 sizeof(target_ulong), 555 MMU_DATA_LOAD, PRV_S); 556 if (pmp_ret != TRANSLATE_SUCCESS) { 557 return TRANSLATE_PMP_FAIL; 558 } 559 560 target_ulong pte; 561 if (riscv_cpu_mxl(env) == MXL_RV32) { 562 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 563 } else { 564 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 565 } 566 567 if (res != MEMTX_OK) { 568 return TRANSLATE_FAIL; 569 } 570 571 hwaddr ppn = pte >> PTE_PPN_SHIFT; 572 573 if (!(pte & PTE_V)) { 574 /* Invalid PTE */ 575 return TRANSLATE_FAIL; 576 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 577 /* Inner PTE, continue walking */ 578 base = ppn << PGSHIFT; 579 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 580 /* Reserved leaf PTE flags: PTE_W */ 581 return TRANSLATE_FAIL; 582 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 583 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 584 return TRANSLATE_FAIL; 585 } else if ((pte & PTE_U) && ((mode != PRV_U) && 586 (!sum || access_type == MMU_INST_FETCH))) { 587 /* User PTE flags when not U mode and mstatus.SUM is not set, 588 or the access type is an instruction fetch */ 589 return TRANSLATE_FAIL; 590 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 591 /* Supervisor PTE flags when not S mode */ 592 return TRANSLATE_FAIL; 593 } else if (ppn & ((1ULL << ptshift) - 1)) { 594 /* Misaligned PPN */ 595 return TRANSLATE_FAIL; 596 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 597 ((pte & PTE_X) && mxr))) { 598 /* Read access check failed */ 599 return TRANSLATE_FAIL; 600 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 601 /* Write access check failed */ 602 return TRANSLATE_FAIL; 603 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 604 /* Fetch access check failed */ 605 return TRANSLATE_FAIL; 606 } else { 607 /* if necessary, set accessed and dirty bits. */ 608 target_ulong updated_pte = pte | PTE_A | 609 (access_type == MMU_DATA_STORE ? PTE_D : 0); 610 611 /* Page table updates need to be atomic with MTTCG enabled */ 612 if (updated_pte != pte) { 613 /* 614 * - if accessed or dirty bits need updating, and the PTE is 615 * in RAM, then we do so atomically with a compare and swap. 616 * - if the PTE is in IO space or ROM, then it can't be updated 617 * and we return TRANSLATE_FAIL. 618 * - if the PTE changed by the time we went to update it, then 619 * it is no longer valid and we must re-walk the page table. 620 */ 621 MemoryRegion *mr; 622 hwaddr l = sizeof(target_ulong), addr1; 623 mr = address_space_translate(cs->as, pte_addr, 624 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 625 if (memory_region_is_ram(mr)) { 626 target_ulong *pte_pa = 627 qemu_map_ram_ptr(mr->ram_block, addr1); 628 #if TCG_OVERSIZED_GUEST 629 /* MTTCG is not enabled on oversized TCG guests so 630 * page table updates do not need to be atomic */ 631 *pte_pa = pte = updated_pte; 632 #else 633 target_ulong old_pte = 634 qatomic_cmpxchg(pte_pa, pte, updated_pte); 635 if (old_pte != pte) { 636 goto restart; 637 } else { 638 pte = updated_pte; 639 } 640 #endif 641 } else { 642 /* misconfigured PTE in ROM (AD bits are not preset) or 643 * PTE is in IO space and can't be updated atomically */ 644 return TRANSLATE_FAIL; 645 } 646 } 647 648 /* for superpage mappings, make a fake leaf PTE for the TLB's 649 benefit. */ 650 target_ulong vpn = addr >> PGSHIFT; 651 *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | 652 (addr & ~TARGET_PAGE_MASK); 653 654 /* set permissions on the TLB entry */ 655 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 656 *prot |= PAGE_READ; 657 } 658 if ((pte & PTE_X)) { 659 *prot |= PAGE_EXEC; 660 } 661 /* add write permission on stores or if the page is already dirty, 662 so that we TLB miss on later writes to update the dirty bit */ 663 if ((pte & PTE_W) && 664 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 665 *prot |= PAGE_WRITE; 666 } 667 return TRANSLATE_SUCCESS; 668 } 669 } 670 return TRANSLATE_FAIL; 671 } 672 673 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 674 MMUAccessType access_type, bool pmp_violation, 675 bool first_stage, bool two_stage) 676 { 677 CPUState *cs = env_cpu(env); 678 int page_fault_exceptions, vm; 679 uint64_t stap_mode; 680 681 if (riscv_cpu_mxl(env) == MXL_RV32) { 682 stap_mode = SATP32_MODE; 683 } else { 684 stap_mode = SATP64_MODE; 685 } 686 687 if (first_stage) { 688 vm = get_field(env->satp, stap_mode); 689 } else { 690 vm = get_field(env->hgatp, stap_mode); 691 } 692 693 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 694 695 switch (access_type) { 696 case MMU_INST_FETCH: 697 if (riscv_cpu_virt_enabled(env) && !first_stage) { 698 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 699 } else { 700 cs->exception_index = page_fault_exceptions ? 701 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 702 } 703 break; 704 case MMU_DATA_LOAD: 705 if (two_stage && !first_stage) { 706 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 707 } else { 708 cs->exception_index = page_fault_exceptions ? 709 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 710 } 711 break; 712 case MMU_DATA_STORE: 713 if (two_stage && !first_stage) { 714 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 715 } else { 716 cs->exception_index = page_fault_exceptions ? 717 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 718 } 719 break; 720 default: 721 g_assert_not_reached(); 722 } 723 env->badaddr = address; 724 env->two_stage_lookup = two_stage; 725 } 726 727 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 728 { 729 RISCVCPU *cpu = RISCV_CPU(cs); 730 CPURISCVState *env = &cpu->env; 731 hwaddr phys_addr; 732 int prot; 733 int mmu_idx = cpu_mmu_index(&cpu->env, false); 734 735 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 736 true, riscv_cpu_virt_enabled(env), true)) { 737 return -1; 738 } 739 740 if (riscv_cpu_virt_enabled(env)) { 741 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 742 0, mmu_idx, false, true, true)) { 743 return -1; 744 } 745 } 746 747 return phys_addr & TARGET_PAGE_MASK; 748 } 749 750 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 751 vaddr addr, unsigned size, 752 MMUAccessType access_type, 753 int mmu_idx, MemTxAttrs attrs, 754 MemTxResult response, uintptr_t retaddr) 755 { 756 RISCVCPU *cpu = RISCV_CPU(cs); 757 CPURISCVState *env = &cpu->env; 758 759 if (access_type == MMU_DATA_STORE) { 760 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 761 } else if (access_type == MMU_DATA_LOAD) { 762 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 763 } else { 764 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 765 } 766 767 env->badaddr = addr; 768 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 769 riscv_cpu_two_stage_lookup(mmu_idx); 770 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 771 } 772 773 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 774 MMUAccessType access_type, int mmu_idx, 775 uintptr_t retaddr) 776 { 777 RISCVCPU *cpu = RISCV_CPU(cs); 778 CPURISCVState *env = &cpu->env; 779 switch (access_type) { 780 case MMU_INST_FETCH: 781 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 782 break; 783 case MMU_DATA_LOAD: 784 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 785 break; 786 case MMU_DATA_STORE: 787 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 788 break; 789 default: 790 g_assert_not_reached(); 791 } 792 env->badaddr = addr; 793 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 794 riscv_cpu_two_stage_lookup(mmu_idx); 795 riscv_raise_exception(env, cs->exception_index, retaddr); 796 } 797 #endif /* !CONFIG_USER_ONLY */ 798 799 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 800 MMUAccessType access_type, int mmu_idx, 801 bool probe, uintptr_t retaddr) 802 { 803 RISCVCPU *cpu = RISCV_CPU(cs); 804 CPURISCVState *env = &cpu->env; 805 #ifndef CONFIG_USER_ONLY 806 vaddr im_address; 807 hwaddr pa = 0; 808 int prot, prot2, prot_pmp; 809 bool pmp_violation = false; 810 bool first_stage_error = true; 811 bool two_stage_lookup = false; 812 int ret = TRANSLATE_FAIL; 813 int mode = mmu_idx; 814 /* default TLB page size */ 815 target_ulong tlb_size = TARGET_PAGE_SIZE; 816 817 env->guest_phys_fault_addr = 0; 818 819 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 820 __func__, address, access_type, mmu_idx); 821 822 /* MPRV does not affect the virtual-machine load/store 823 instructions, HLV, HLVX, and HSV. */ 824 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 825 mode = get_field(env->hstatus, HSTATUS_SPVP); 826 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 827 get_field(env->mstatus, MSTATUS_MPRV)) { 828 mode = get_field(env->mstatus, MSTATUS_MPP); 829 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 830 two_stage_lookup = true; 831 } 832 } 833 834 if (riscv_cpu_virt_enabled(env) || 835 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 836 access_type != MMU_INST_FETCH)) { 837 /* Two stage lookup */ 838 ret = get_physical_address(env, &pa, &prot, address, 839 &env->guest_phys_fault_addr, access_type, 840 mmu_idx, true, true, false); 841 842 /* 843 * A G-stage exception may be triggered during two state lookup. 844 * And the env->guest_phys_fault_addr has already been set in 845 * get_physical_address(). 846 */ 847 if (ret == TRANSLATE_G_STAGE_FAIL) { 848 first_stage_error = false; 849 access_type = MMU_DATA_LOAD; 850 } 851 852 qemu_log_mask(CPU_LOG_MMU, 853 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 854 TARGET_FMT_plx " prot %d\n", 855 __func__, address, ret, pa, prot); 856 857 if (ret == TRANSLATE_SUCCESS) { 858 /* Second stage lookup */ 859 im_address = pa; 860 861 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 862 access_type, mmu_idx, false, true, 863 false); 864 865 qemu_log_mask(CPU_LOG_MMU, 866 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 867 TARGET_FMT_plx " prot %d\n", 868 __func__, im_address, ret, pa, prot2); 869 870 prot &= prot2; 871 872 if (ret == TRANSLATE_SUCCESS) { 873 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 874 size, access_type, mode); 875 876 qemu_log_mask(CPU_LOG_MMU, 877 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 878 " %d tlb_size " TARGET_FMT_lu "\n", 879 __func__, pa, ret, prot_pmp, tlb_size); 880 881 prot &= prot_pmp; 882 } 883 884 if (ret != TRANSLATE_SUCCESS) { 885 /* 886 * Guest physical address translation failed, this is a HS 887 * level exception 888 */ 889 first_stage_error = false; 890 env->guest_phys_fault_addr = (im_address | 891 (address & 892 (TARGET_PAGE_SIZE - 1))) >> 2; 893 } 894 } 895 } else { 896 /* Single stage lookup */ 897 ret = get_physical_address(env, &pa, &prot, address, NULL, 898 access_type, mmu_idx, true, false, false); 899 900 qemu_log_mask(CPU_LOG_MMU, 901 "%s address=%" VADDR_PRIx " ret %d physical " 902 TARGET_FMT_plx " prot %d\n", 903 __func__, address, ret, pa, prot); 904 905 if (ret == TRANSLATE_SUCCESS) { 906 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 907 size, access_type, mode); 908 909 qemu_log_mask(CPU_LOG_MMU, 910 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 911 " %d tlb_size " TARGET_FMT_lu "\n", 912 __func__, pa, ret, prot_pmp, tlb_size); 913 914 prot &= prot_pmp; 915 } 916 } 917 918 if (ret == TRANSLATE_PMP_FAIL) { 919 pmp_violation = true; 920 } 921 922 if (ret == TRANSLATE_SUCCESS) { 923 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 924 prot, mmu_idx, tlb_size); 925 return true; 926 } else if (probe) { 927 return false; 928 } else { 929 raise_mmu_exception(env, address, access_type, pmp_violation, 930 first_stage_error, 931 riscv_cpu_virt_enabled(env) || 932 riscv_cpu_two_stage_lookup(mmu_idx)); 933 riscv_raise_exception(env, cs->exception_index, retaddr); 934 } 935 936 return true; 937 938 #else 939 switch (access_type) { 940 case MMU_INST_FETCH: 941 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 942 break; 943 case MMU_DATA_LOAD: 944 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 945 break; 946 case MMU_DATA_STORE: 947 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 948 break; 949 default: 950 g_assert_not_reached(); 951 } 952 env->badaddr = address; 953 cpu_loop_exit_restore(cs, retaddr); 954 #endif 955 } 956 957 /* 958 * Handle Traps 959 * 960 * Adapted from Spike's processor_t::take_trap. 961 * 962 */ 963 void riscv_cpu_do_interrupt(CPUState *cs) 964 { 965 #if !defined(CONFIG_USER_ONLY) 966 967 RISCVCPU *cpu = RISCV_CPU(cs); 968 CPURISCVState *env = &cpu->env; 969 bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); 970 uint64_t s; 971 972 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 973 * so we mask off the MSB and separate into trap type and cause. 974 */ 975 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 976 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 977 target_ulong deleg = async ? env->mideleg : env->medeleg; 978 bool write_tval = false; 979 target_ulong tval = 0; 980 target_ulong htval = 0; 981 target_ulong mtval2 = 0; 982 983 if (cause == RISCV_EXCP_SEMIHOST) { 984 if (env->priv >= PRV_S) { 985 env->gpr[xA0] = do_common_semihosting(cs); 986 env->pc += 4; 987 return; 988 } 989 cause = RISCV_EXCP_BREAKPOINT; 990 } 991 992 if (!async) { 993 /* set tval to badaddr for traps with address information */ 994 switch (cause) { 995 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 996 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 997 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 998 force_hs_execp = true; 999 /* fallthrough */ 1000 case RISCV_EXCP_INST_ADDR_MIS: 1001 case RISCV_EXCP_INST_ACCESS_FAULT: 1002 case RISCV_EXCP_LOAD_ADDR_MIS: 1003 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1004 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1005 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1006 case RISCV_EXCP_INST_PAGE_FAULT: 1007 case RISCV_EXCP_LOAD_PAGE_FAULT: 1008 case RISCV_EXCP_STORE_PAGE_FAULT: 1009 write_tval = true; 1010 tval = env->badaddr; 1011 break; 1012 default: 1013 break; 1014 } 1015 /* ecall is dispatched as one cause so translate based on mode */ 1016 if (cause == RISCV_EXCP_U_ECALL) { 1017 assert(env->priv <= 3); 1018 1019 if (env->priv == PRV_M) { 1020 cause = RISCV_EXCP_M_ECALL; 1021 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1022 cause = RISCV_EXCP_VS_ECALL; 1023 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1024 cause = RISCV_EXCP_S_ECALL; 1025 } else if (env->priv == PRV_U) { 1026 cause = RISCV_EXCP_U_ECALL; 1027 } 1028 } 1029 } 1030 1031 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1032 riscv_cpu_get_trap_name(cause, async)); 1033 1034 qemu_log_mask(CPU_LOG_INT, 1035 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1036 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1037 __func__, env->mhartid, async, cause, env->pc, tval, 1038 riscv_cpu_get_trap_name(cause, async)); 1039 1040 if (env->priv <= PRV_S && 1041 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1042 /* handle the trap in S-mode */ 1043 if (riscv_has_ext(env, RVH)) { 1044 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 1045 1046 if (env->two_stage_lookup && write_tval) { 1047 /* 1048 * If we are writing a guest virtual address to stval, set 1049 * this to 1. If we are trapping to VS we will set this to 0 1050 * later. 1051 */ 1052 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); 1053 } else { 1054 /* For other HS-mode traps, we set this to 0. */ 1055 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); 1056 } 1057 1058 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && 1059 !force_hs_execp) { 1060 /* Trap to VS mode */ 1061 /* 1062 * See if we need to adjust cause. Yes if its VS mode interrupt 1063 * no if hypervisor has delegated one of hs mode's interrupt 1064 */ 1065 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1066 cause == IRQ_VS_EXT) { 1067 cause = cause - 1; 1068 } 1069 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); 1070 } else if (riscv_cpu_virt_enabled(env)) { 1071 /* Trap into HS mode, from virt */ 1072 riscv_cpu_swap_hypervisor_regs(env); 1073 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1074 env->priv); 1075 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1076 riscv_cpu_virt_enabled(env)); 1077 1078 htval = env->guest_phys_fault_addr; 1079 1080 riscv_cpu_set_virt_enabled(env, 0); 1081 riscv_cpu_set_force_hs_excep(env, 0); 1082 } else { 1083 /* Trap into HS mode */ 1084 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1085 htval = env->guest_phys_fault_addr; 1086 } 1087 } 1088 1089 s = env->mstatus; 1090 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1091 s = set_field(s, MSTATUS_SPP, env->priv); 1092 s = set_field(s, MSTATUS_SIE, 0); 1093 env->mstatus = s; 1094 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1095 env->sepc = env->pc; 1096 env->stval = tval; 1097 env->htval = htval; 1098 env->pc = (env->stvec >> 2 << 2) + 1099 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1100 riscv_cpu_set_mode(env, PRV_S); 1101 } else { 1102 /* handle the trap in M-mode */ 1103 if (riscv_has_ext(env, RVH)) { 1104 if (riscv_cpu_virt_enabled(env)) { 1105 riscv_cpu_swap_hypervisor_regs(env); 1106 } 1107 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1108 riscv_cpu_virt_enabled(env)); 1109 if (riscv_cpu_virt_enabled(env) && tval) { 1110 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1111 } 1112 1113 mtval2 = env->guest_phys_fault_addr; 1114 1115 /* Trapping to M mode, virt is disabled */ 1116 riscv_cpu_set_virt_enabled(env, 0); 1117 riscv_cpu_set_force_hs_excep(env, 0); 1118 } 1119 1120 s = env->mstatus; 1121 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1122 s = set_field(s, MSTATUS_MPP, env->priv); 1123 s = set_field(s, MSTATUS_MIE, 0); 1124 env->mstatus = s; 1125 env->mcause = cause | ~(((target_ulong)-1) >> async); 1126 env->mepc = env->pc; 1127 env->mtval = tval; 1128 env->mtval2 = mtval2; 1129 env->pc = (env->mtvec >> 2 << 2) + 1130 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1131 riscv_cpu_set_mode(env, PRV_M); 1132 } 1133 1134 /* NOTE: it is not necessary to yield load reservations here. It is only 1135 * necessary for an SC from "another hart" to cause a load reservation 1136 * to be yielded. Refer to the memory consistency model section of the 1137 * RISC-V ISA Specification. 1138 */ 1139 1140 env->two_stage_lookup = false; 1141 #endif 1142 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1143 } 1144