1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg-op.h" 25 #include "trace.h" 26 27 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 28 { 29 #ifdef CONFIG_USER_ONLY 30 return 0; 31 #else 32 return env->priv; 33 #endif 34 } 35 36 #ifndef CONFIG_USER_ONLY 37 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 38 { 39 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 40 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 41 target_ulong pending = atomic_read(&env->mip) & env->mie; 42 target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); 43 target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); 44 target_ulong irqs = (pending & ~env->mideleg & -mie) | 45 (pending & env->mideleg & -sie); 46 47 if (irqs) { 48 return ctz64(irqs); /* since non-zero */ 49 } else { 50 return EXCP_NONE; /* indicates no pending interrupt */ 51 } 52 } 53 #endif 54 55 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 56 { 57 #if !defined(CONFIG_USER_ONLY) 58 if (interrupt_request & CPU_INTERRUPT_HARD) { 59 RISCVCPU *cpu = RISCV_CPU(cs); 60 CPURISCVState *env = &cpu->env; 61 int interruptno = riscv_cpu_local_irq_pending(env); 62 if (interruptno >= 0) { 63 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 64 riscv_cpu_do_interrupt(cs); 65 return true; 66 } 67 } 68 #endif 69 return false; 70 } 71 72 #if !defined(CONFIG_USER_ONLY) 73 74 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 75 { 76 CPURISCVState *env = &cpu->env; 77 if (env->miclaim & interrupts) { 78 return -1; 79 } else { 80 env->miclaim |= interrupts; 81 return 0; 82 } 83 } 84 85 struct CpuAsyncInfo { 86 uint32_t new_mip; 87 }; 88 89 static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, 90 run_on_cpu_data data) 91 { 92 struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr; 93 94 if (info->new_mip) { 95 cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); 96 } else { 97 cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); 98 } 99 100 g_free(info); 101 } 102 103 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 104 { 105 CPURISCVState *env = &cpu->env; 106 CPUState *cs = CPU(cpu); 107 struct CpuAsyncInfo *info; 108 uint32_t old, new, cmp = atomic_read(&env->mip); 109 110 do { 111 old = cmp; 112 new = (old & ~mask) | (value & mask); 113 cmp = atomic_cmpxchg(&env->mip, old, new); 114 } while (old != cmp); 115 116 info = g_new(struct CpuAsyncInfo, 1); 117 info->new_mip = new; 118 119 async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async, 120 RUN_ON_CPU_HOST_PTR(info)); 121 122 return old; 123 } 124 125 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 126 { 127 if (newpriv > PRV_M) { 128 g_assert_not_reached(); 129 } 130 if (newpriv == PRV_H) { 131 newpriv = PRV_U; 132 } 133 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 134 env->priv = newpriv; 135 } 136 137 /* get_physical_address - get the physical address for this virtual address 138 * 139 * Do a page table walk to obtain the physical address corresponding to a 140 * virtual address. Returns 0 if the translation was successful 141 * 142 * Adapted from Spike's mmu_t::translate and mmu_t::walk 143 * 144 */ 145 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 146 int *prot, target_ulong addr, 147 int access_type, int mmu_idx) 148 { 149 /* NOTE: the env->pc value visible here will not be 150 * correct, but the value visible to the exception handler 151 * (riscv_cpu_do_interrupt) is correct */ 152 153 int mode = mmu_idx; 154 155 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 156 if (get_field(env->mstatus, MSTATUS_MPRV)) { 157 mode = get_field(env->mstatus, MSTATUS_MPP); 158 } 159 } 160 161 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 162 *physical = addr; 163 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 164 return TRANSLATE_SUCCESS; 165 } 166 167 *prot = 0; 168 169 target_ulong base; 170 int levels, ptidxbits, ptesize, vm, sum; 171 int mxr = get_field(env->mstatus, MSTATUS_MXR); 172 173 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 174 base = get_field(env->satp, SATP_PPN) << PGSHIFT; 175 sum = get_field(env->mstatus, MSTATUS_SUM); 176 vm = get_field(env->satp, SATP_MODE); 177 switch (vm) { 178 case VM_1_10_SV32: 179 levels = 2; ptidxbits = 10; ptesize = 4; break; 180 case VM_1_10_SV39: 181 levels = 3; ptidxbits = 9; ptesize = 8; break; 182 case VM_1_10_SV48: 183 levels = 4; ptidxbits = 9; ptesize = 8; break; 184 case VM_1_10_SV57: 185 levels = 5; ptidxbits = 9; ptesize = 8; break; 186 case VM_1_10_MBARE: 187 *physical = addr; 188 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 189 return TRANSLATE_SUCCESS; 190 default: 191 g_assert_not_reached(); 192 } 193 } else { 194 base = env->sptbr << PGSHIFT; 195 sum = !get_field(env->mstatus, MSTATUS_PUM); 196 vm = get_field(env->mstatus, MSTATUS_VM); 197 switch (vm) { 198 case VM_1_09_SV32: 199 levels = 2; ptidxbits = 10; ptesize = 4; break; 200 case VM_1_09_SV39: 201 levels = 3; ptidxbits = 9; ptesize = 8; break; 202 case VM_1_09_SV48: 203 levels = 4; ptidxbits = 9; ptesize = 8; break; 204 case VM_1_09_MBARE: 205 *physical = addr; 206 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 207 return TRANSLATE_SUCCESS; 208 default: 209 g_assert_not_reached(); 210 } 211 } 212 213 CPUState *cs = env_cpu(env); 214 int va_bits = PGSHIFT + levels * ptidxbits; 215 target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 216 target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; 217 if (masked_msbs != 0 && masked_msbs != mask) { 218 return TRANSLATE_FAIL; 219 } 220 221 int ptshift = (levels - 1) * ptidxbits; 222 int i; 223 224 #if !TCG_OVERSIZED_GUEST 225 restart: 226 #endif 227 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 228 target_ulong idx = (addr >> (PGSHIFT + ptshift)) & 229 ((1 << ptidxbits) - 1); 230 231 /* check that physical address of PTE is legal */ 232 target_ulong pte_addr = base + idx * ptesize; 233 #if defined(TARGET_RISCV32) 234 target_ulong pte = ldl_phys(cs->as, pte_addr); 235 #elif defined(TARGET_RISCV64) 236 target_ulong pte = ldq_phys(cs->as, pte_addr); 237 #endif 238 target_ulong ppn = pte >> PTE_PPN_SHIFT; 239 240 if (!(pte & PTE_V)) { 241 /* Invalid PTE */ 242 return TRANSLATE_FAIL; 243 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 244 /* Inner PTE, continue walking */ 245 base = ppn << PGSHIFT; 246 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 247 /* Reserved leaf PTE flags: PTE_W */ 248 return TRANSLATE_FAIL; 249 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 250 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 251 return TRANSLATE_FAIL; 252 } else if ((pte & PTE_U) && ((mode != PRV_U) && 253 (!sum || access_type == MMU_INST_FETCH))) { 254 /* User PTE flags when not U mode and mstatus.SUM is not set, 255 or the access type is an instruction fetch */ 256 return TRANSLATE_FAIL; 257 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 258 /* Supervisor PTE flags when not S mode */ 259 return TRANSLATE_FAIL; 260 } else if (ppn & ((1ULL << ptshift) - 1)) { 261 /* Misaligned PPN */ 262 return TRANSLATE_FAIL; 263 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 264 ((pte & PTE_X) && mxr))) { 265 /* Read access check failed */ 266 return TRANSLATE_FAIL; 267 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 268 /* Write access check failed */ 269 return TRANSLATE_FAIL; 270 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 271 /* Fetch access check failed */ 272 return TRANSLATE_FAIL; 273 } else { 274 /* if necessary, set accessed and dirty bits. */ 275 target_ulong updated_pte = pte | PTE_A | 276 (access_type == MMU_DATA_STORE ? PTE_D : 0); 277 278 /* Page table updates need to be atomic with MTTCG enabled */ 279 if (updated_pte != pte) { 280 /* 281 * - if accessed or dirty bits need updating, and the PTE is 282 * in RAM, then we do so atomically with a compare and swap. 283 * - if the PTE is in IO space or ROM, then it can't be updated 284 * and we return TRANSLATE_FAIL. 285 * - if the PTE changed by the time we went to update it, then 286 * it is no longer valid and we must re-walk the page table. 287 */ 288 MemoryRegion *mr; 289 hwaddr l = sizeof(target_ulong), addr1; 290 mr = address_space_translate(cs->as, pte_addr, 291 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 292 if (memory_region_is_ram(mr)) { 293 target_ulong *pte_pa = 294 qemu_map_ram_ptr(mr->ram_block, addr1); 295 #if TCG_OVERSIZED_GUEST 296 /* MTTCG is not enabled on oversized TCG guests so 297 * page table updates do not need to be atomic */ 298 *pte_pa = pte = updated_pte; 299 #else 300 target_ulong old_pte = 301 atomic_cmpxchg(pte_pa, pte, updated_pte); 302 if (old_pte != pte) { 303 goto restart; 304 } else { 305 pte = updated_pte; 306 } 307 #endif 308 } else { 309 /* misconfigured PTE in ROM (AD bits are not preset) or 310 * PTE is in IO space and can't be updated atomically */ 311 return TRANSLATE_FAIL; 312 } 313 } 314 315 /* for superpage mappings, make a fake leaf PTE for the TLB's 316 benefit. */ 317 target_ulong vpn = addr >> PGSHIFT; 318 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 319 320 /* set permissions on the TLB entry */ 321 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 322 *prot |= PAGE_READ; 323 } 324 if ((pte & PTE_X)) { 325 *prot |= PAGE_EXEC; 326 } 327 /* add write permission on stores or if the page is already dirty, 328 so that we TLB miss on later writes to update the dirty bit */ 329 if ((pte & PTE_W) && 330 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 331 *prot |= PAGE_WRITE; 332 } 333 return TRANSLATE_SUCCESS; 334 } 335 } 336 return TRANSLATE_FAIL; 337 } 338 339 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 340 MMUAccessType access_type, bool pmp_violation) 341 { 342 CPUState *cs = env_cpu(env); 343 int page_fault_exceptions = 344 (env->priv_ver >= PRIV_VERSION_1_10_0) && 345 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 346 !pmp_violation; 347 switch (access_type) { 348 case MMU_INST_FETCH: 349 cs->exception_index = page_fault_exceptions ? 350 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 351 break; 352 case MMU_DATA_LOAD: 353 cs->exception_index = page_fault_exceptions ? 354 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 355 break; 356 case MMU_DATA_STORE: 357 cs->exception_index = page_fault_exceptions ? 358 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 359 break; 360 default: 361 g_assert_not_reached(); 362 } 363 env->badaddr = address; 364 } 365 366 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 367 { 368 RISCVCPU *cpu = RISCV_CPU(cs); 369 hwaddr phys_addr; 370 int prot; 371 int mmu_idx = cpu_mmu_index(&cpu->env, false); 372 373 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { 374 return -1; 375 } 376 return phys_addr; 377 } 378 379 void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, 380 bool is_exec, int unused, unsigned size) 381 { 382 RISCVCPU *cpu = RISCV_CPU(cs); 383 CPURISCVState *env = &cpu->env; 384 385 if (is_write) { 386 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 387 } else { 388 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 389 } 390 391 env->badaddr = addr; 392 riscv_raise_exception(&cpu->env, cs->exception_index, GETPC()); 393 } 394 395 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 396 MMUAccessType access_type, int mmu_idx, 397 uintptr_t retaddr) 398 { 399 RISCVCPU *cpu = RISCV_CPU(cs); 400 CPURISCVState *env = &cpu->env; 401 switch (access_type) { 402 case MMU_INST_FETCH: 403 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 404 break; 405 case MMU_DATA_LOAD: 406 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 407 break; 408 case MMU_DATA_STORE: 409 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 410 break; 411 default: 412 g_assert_not_reached(); 413 } 414 env->badaddr = addr; 415 riscv_raise_exception(env, cs->exception_index, retaddr); 416 } 417 #endif 418 419 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 420 MMUAccessType access_type, int mmu_idx, 421 bool probe, uintptr_t retaddr) 422 { 423 #ifndef CONFIG_USER_ONLY 424 RISCVCPU *cpu = RISCV_CPU(cs); 425 CPURISCVState *env = &cpu->env; 426 hwaddr pa = 0; 427 int prot; 428 bool pmp_violation = false; 429 int ret = TRANSLATE_FAIL; 430 int mode = mmu_idx; 431 432 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 433 __func__, address, access_type, mmu_idx); 434 435 ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); 436 437 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 438 if (get_field(env->mstatus, MSTATUS_MPRV)) { 439 mode = get_field(env->mstatus, MSTATUS_MPP); 440 } 441 } 442 443 qemu_log_mask(CPU_LOG_MMU, 444 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx 445 " prot %d\n", __func__, address, ret, pa, prot); 446 447 if (riscv_feature(env, RISCV_FEATURE_PMP) && 448 (ret == TRANSLATE_SUCCESS) && 449 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, 450 mode)) { 451 pmp_violation = true; 452 ret = TRANSLATE_FAIL; 453 } 454 if (ret == TRANSLATE_SUCCESS) { 455 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 456 prot, mmu_idx, TARGET_PAGE_SIZE); 457 return true; 458 } else if (probe) { 459 return false; 460 } else { 461 raise_mmu_exception(env, address, access_type, pmp_violation); 462 riscv_raise_exception(env, cs->exception_index, retaddr); 463 } 464 #else 465 switch (access_type) { 466 case MMU_INST_FETCH: 467 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 468 break; 469 case MMU_DATA_LOAD: 470 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 471 break; 472 case MMU_DATA_STORE: 473 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 474 break; 475 } 476 cpu_loop_exit_restore(cs, retaddr); 477 #endif 478 } 479 480 /* 481 * Handle Traps 482 * 483 * Adapted from Spike's processor_t::take_trap. 484 * 485 */ 486 void riscv_cpu_do_interrupt(CPUState *cs) 487 { 488 #if !defined(CONFIG_USER_ONLY) 489 490 RISCVCPU *cpu = RISCV_CPU(cs); 491 CPURISCVState *env = &cpu->env; 492 493 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 494 * so we mask off the MSB and separate into trap type and cause. 495 */ 496 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 497 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 498 target_ulong deleg = async ? env->mideleg : env->medeleg; 499 target_ulong tval = 0; 500 501 static const int ecall_cause_map[] = { 502 [PRV_U] = RISCV_EXCP_U_ECALL, 503 [PRV_S] = RISCV_EXCP_S_ECALL, 504 [PRV_H] = RISCV_EXCP_H_ECALL, 505 [PRV_M] = RISCV_EXCP_M_ECALL 506 }; 507 508 if (!async) { 509 /* set tval to badaddr for traps with address information */ 510 switch (cause) { 511 case RISCV_EXCP_INST_ADDR_MIS: 512 case RISCV_EXCP_INST_ACCESS_FAULT: 513 case RISCV_EXCP_LOAD_ADDR_MIS: 514 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 515 case RISCV_EXCP_LOAD_ACCESS_FAULT: 516 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 517 case RISCV_EXCP_INST_PAGE_FAULT: 518 case RISCV_EXCP_LOAD_PAGE_FAULT: 519 case RISCV_EXCP_STORE_PAGE_FAULT: 520 tval = env->badaddr; 521 break; 522 default: 523 break; 524 } 525 /* ecall is dispatched as one cause so translate based on mode */ 526 if (cause == RISCV_EXCP_U_ECALL) { 527 assert(env->priv <= 3); 528 cause = ecall_cause_map[env->priv]; 529 } 530 } 531 532 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ? 533 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 534 535 if (env->priv <= PRV_S && 536 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 537 /* handle the trap in S-mode */ 538 target_ulong s = env->mstatus; 539 s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 540 get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); 541 s = set_field(s, MSTATUS_SPP, env->priv); 542 s = set_field(s, MSTATUS_SIE, 0); 543 env->mstatus = s; 544 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 545 env->sepc = env->pc; 546 env->sbadaddr = tval; 547 env->pc = (env->stvec >> 2 << 2) + 548 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 549 riscv_cpu_set_mode(env, PRV_S); 550 } else { 551 /* handle the trap in M-mode */ 552 target_ulong s = env->mstatus; 553 s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 554 get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); 555 s = set_field(s, MSTATUS_MPP, env->priv); 556 s = set_field(s, MSTATUS_MIE, 0); 557 env->mstatus = s; 558 env->mcause = cause | ~(((target_ulong)-1) >> async); 559 env->mepc = env->pc; 560 env->mbadaddr = tval; 561 env->pc = (env->mtvec >> 2 << 2) + 562 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 563 riscv_cpu_set_mode(env, PRV_M); 564 } 565 566 /* NOTE: it is not necessary to yield load reservations here. It is only 567 * necessary for an SC from "another hart" to cause a load reservation 568 * to be yielded. Refer to the memory consistency model section of the 569 * RISC-V ISA Specification. 570 */ 571 572 #endif 573 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 574 } 575