1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "internals.h" 25 #include "pmu.h" 26 #include "exec/exec-all.h" 27 #include "instmap.h" 28 #include "tcg/tcg-op.h" 29 #include "trace.h" 30 #include "semihosting/common-semi.h" 31 #include "sysemu/cpu-timers.h" 32 #include "cpu_bits.h" 33 #include "debug.h" 34 35 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 36 { 37 #ifdef CONFIG_USER_ONLY 38 return 0; 39 #else 40 if (ifetch) { 41 return env->priv; 42 } 43 44 /* All priv -> mmu_idx mapping are here */ 45 int mode = env->priv; 46 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 47 mode = get_field(env->mstatus, MSTATUS_MPP); 48 } 49 if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { 50 return MMUIdx_S_SUM; 51 } 52 return mode; 53 #endif 54 } 55 56 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 57 target_ulong *cs_base, uint32_t *pflags) 58 { 59 CPUState *cs = env_cpu(env); 60 RISCVCPU *cpu = RISCV_CPU(cs); 61 RISCVExtStatus fs, vs; 62 uint32_t flags = 0; 63 64 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 65 *cs_base = 0; 66 67 if (cpu->cfg.ext_zve32f) { 68 /* 69 * If env->vl equals to VLMAX, we can use generic vector operation 70 * expanders (GVEC) to accerlate the vector operations. 71 * However, as LMUL could be a fractional number. The maximum 72 * vector size can be operated might be less than 8 bytes, 73 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 74 * only when maxsz >= 8 bytes. 75 */ 76 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 77 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 78 uint32_t maxsz = vlmax << sew; 79 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 80 (maxsz >= 8); 81 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 82 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 83 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 84 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 85 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 86 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 87 FIELD_EX64(env->vtype, VTYPE, VTA)); 88 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 89 FIELD_EX64(env->vtype, VTYPE, VMA)); 90 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); 91 } else { 92 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 93 } 94 95 #ifdef CONFIG_USER_ONLY 96 fs = EXT_STATUS_DIRTY; 97 vs = EXT_STATUS_DIRTY; 98 #else 99 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); 100 101 flags |= cpu_mmu_index(env, 0); 102 fs = get_field(env->mstatus, MSTATUS_FS); 103 vs = get_field(env->mstatus, MSTATUS_VS); 104 105 if (riscv_has_ext(env, RVH)) { 106 if (env->priv == PRV_M || 107 (env->priv == PRV_S && !env->virt_enabled) || 108 (env->priv == PRV_U && !env->virt_enabled && 109 get_field(env->hstatus, HSTATUS_HU))) { 110 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 111 } 112 113 if (env->virt_enabled) { 114 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); 115 /* 116 * Merge DISABLED and !DIRTY states using MIN. 117 * We will set both fields when dirtying. 118 */ 119 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); 120 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); 121 } 122 } 123 if (cpu->cfg.debug && !icount_enabled()) { 124 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 125 } 126 #endif 127 128 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); 129 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); 130 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 131 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 132 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 133 } 134 if (env->cur_pmbase != 0) { 135 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 136 } 137 138 *pflags = flags; 139 } 140 141 void riscv_cpu_update_mask(CPURISCVState *env) 142 { 143 target_ulong mask = -1, base = 0; 144 /* 145 * TODO: Current RVJ spec does not specify 146 * how the extension interacts with XLEN. 147 */ 148 #ifndef CONFIG_USER_ONLY 149 if (riscv_has_ext(env, RVJ)) { 150 switch (env->priv) { 151 case PRV_M: 152 if (env->mmte & M_PM_ENABLE) { 153 mask = env->mpmmask; 154 base = env->mpmbase; 155 } 156 break; 157 case PRV_S: 158 if (env->mmte & S_PM_ENABLE) { 159 mask = env->spmmask; 160 base = env->spmbase; 161 } 162 break; 163 case PRV_U: 164 if (env->mmte & U_PM_ENABLE) { 165 mask = env->upmmask; 166 base = env->upmbase; 167 } 168 break; 169 default: 170 g_assert_not_reached(); 171 } 172 } 173 #endif 174 if (env->xl == MXL_RV32) { 175 env->cur_pmmask = mask & UINT32_MAX; 176 env->cur_pmbase = base & UINT32_MAX; 177 } else { 178 env->cur_pmmask = mask; 179 env->cur_pmbase = base; 180 } 181 } 182 183 #ifndef CONFIG_USER_ONLY 184 185 /* 186 * The HS-mode is allowed to configure priority only for the 187 * following VS-mode local interrupts: 188 * 189 * 0 (Reserved interrupt, reads as zero) 190 * 1 Supervisor software interrupt 191 * 4 (Reserved interrupt, reads as zero) 192 * 5 Supervisor timer interrupt 193 * 8 (Reserved interrupt, reads as zero) 194 * 13 (Reserved interrupt) 195 * 14 " 196 * 15 " 197 * 16 " 198 * 17 " 199 * 18 " 200 * 19 " 201 * 20 " 202 * 21 " 203 * 22 " 204 * 23 " 205 */ 206 207 static const int hviprio_index2irq[] = { 208 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 209 static const int hviprio_index2rdzero[] = { 210 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 211 212 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 213 { 214 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 215 return -EINVAL; 216 } 217 218 if (out_irq) { 219 *out_irq = hviprio_index2irq[index]; 220 } 221 222 if (out_rdzero) { 223 *out_rdzero = hviprio_index2rdzero[index]; 224 } 225 226 return 0; 227 } 228 229 /* 230 * Default priorities of local interrupts are defined in the 231 * RISC-V Advanced Interrupt Architecture specification. 232 * 233 * ---------------------------------------------------------------- 234 * Default | 235 * Priority | Major Interrupt Numbers 236 * ---------------------------------------------------------------- 237 * Highest | 47, 23, 46, 45, 22, 44, 238 * | 43, 21, 42, 41, 20, 40 239 * | 240 * | 11 (0b), 3 (03), 7 (07) 241 * | 9 (09), 1 (01), 5 (05) 242 * | 12 (0c) 243 * | 10 (0a), 2 (02), 6 (06) 244 * | 245 * | 39, 19, 38, 37, 18, 36, 246 * Lowest | 35, 17, 34, 33, 16, 32 247 * ---------------------------------------------------------------- 248 */ 249 static const uint8_t default_iprio[64] = { 250 /* Custom interrupts 48 to 63 */ 251 [63] = IPRIO_MMAXIPRIO, 252 [62] = IPRIO_MMAXIPRIO, 253 [61] = IPRIO_MMAXIPRIO, 254 [60] = IPRIO_MMAXIPRIO, 255 [59] = IPRIO_MMAXIPRIO, 256 [58] = IPRIO_MMAXIPRIO, 257 [57] = IPRIO_MMAXIPRIO, 258 [56] = IPRIO_MMAXIPRIO, 259 [55] = IPRIO_MMAXIPRIO, 260 [54] = IPRIO_MMAXIPRIO, 261 [53] = IPRIO_MMAXIPRIO, 262 [52] = IPRIO_MMAXIPRIO, 263 [51] = IPRIO_MMAXIPRIO, 264 [50] = IPRIO_MMAXIPRIO, 265 [49] = IPRIO_MMAXIPRIO, 266 [48] = IPRIO_MMAXIPRIO, 267 268 /* Custom interrupts 24 to 31 */ 269 [31] = IPRIO_MMAXIPRIO, 270 [30] = IPRIO_MMAXIPRIO, 271 [29] = IPRIO_MMAXIPRIO, 272 [28] = IPRIO_MMAXIPRIO, 273 [27] = IPRIO_MMAXIPRIO, 274 [26] = IPRIO_MMAXIPRIO, 275 [25] = IPRIO_MMAXIPRIO, 276 [24] = IPRIO_MMAXIPRIO, 277 278 [47] = IPRIO_DEFAULT_UPPER, 279 [23] = IPRIO_DEFAULT_UPPER + 1, 280 [46] = IPRIO_DEFAULT_UPPER + 2, 281 [45] = IPRIO_DEFAULT_UPPER + 3, 282 [22] = IPRIO_DEFAULT_UPPER + 4, 283 [44] = IPRIO_DEFAULT_UPPER + 5, 284 285 [43] = IPRIO_DEFAULT_UPPER + 6, 286 [21] = IPRIO_DEFAULT_UPPER + 7, 287 [42] = IPRIO_DEFAULT_UPPER + 8, 288 [41] = IPRIO_DEFAULT_UPPER + 9, 289 [20] = IPRIO_DEFAULT_UPPER + 10, 290 [40] = IPRIO_DEFAULT_UPPER + 11, 291 292 [11] = IPRIO_DEFAULT_M, 293 [3] = IPRIO_DEFAULT_M + 1, 294 [7] = IPRIO_DEFAULT_M + 2, 295 296 [9] = IPRIO_DEFAULT_S, 297 [1] = IPRIO_DEFAULT_S + 1, 298 [5] = IPRIO_DEFAULT_S + 2, 299 300 [12] = IPRIO_DEFAULT_SGEXT, 301 302 [10] = IPRIO_DEFAULT_VS, 303 [2] = IPRIO_DEFAULT_VS + 1, 304 [6] = IPRIO_DEFAULT_VS + 2, 305 306 [39] = IPRIO_DEFAULT_LOWER, 307 [19] = IPRIO_DEFAULT_LOWER + 1, 308 [38] = IPRIO_DEFAULT_LOWER + 2, 309 [37] = IPRIO_DEFAULT_LOWER + 3, 310 [18] = IPRIO_DEFAULT_LOWER + 4, 311 [36] = IPRIO_DEFAULT_LOWER + 5, 312 313 [35] = IPRIO_DEFAULT_LOWER + 6, 314 [17] = IPRIO_DEFAULT_LOWER + 7, 315 [34] = IPRIO_DEFAULT_LOWER + 8, 316 [33] = IPRIO_DEFAULT_LOWER + 9, 317 [16] = IPRIO_DEFAULT_LOWER + 10, 318 [32] = IPRIO_DEFAULT_LOWER + 11, 319 }; 320 321 uint8_t riscv_cpu_default_priority(int irq) 322 { 323 if (irq < 0 || irq > 63) { 324 return IPRIO_MMAXIPRIO; 325 } 326 327 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 328 }; 329 330 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 331 int extirq, unsigned int extirq_def_prio, 332 uint64_t pending, uint8_t *iprio) 333 { 334 int irq, best_irq = RISCV_EXCP_NONE; 335 unsigned int prio, best_prio = UINT_MAX; 336 337 if (!pending) { 338 return RISCV_EXCP_NONE; 339 } 340 341 irq = ctz64(pending); 342 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 343 riscv_cpu_cfg(env)->ext_ssaia)) { 344 return irq; 345 } 346 347 pending = pending >> irq; 348 while (pending) { 349 prio = iprio[irq]; 350 if (!prio) { 351 if (irq == extirq) { 352 prio = extirq_def_prio; 353 } else { 354 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 355 1 : IPRIO_MMAXIPRIO; 356 } 357 } 358 if ((pending & 0x1) && (prio <= best_prio)) { 359 best_irq = irq; 360 best_prio = prio; 361 } 362 irq++; 363 pending = pending >> 1; 364 } 365 366 return best_irq; 367 } 368 369 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 370 { 371 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 372 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 373 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 374 375 return (env->mip | vsgein | vstip) & env->mie; 376 } 377 378 int riscv_cpu_mirq_pending(CPURISCVState *env) 379 { 380 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 381 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 382 383 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 384 irqs, env->miprio); 385 } 386 387 int riscv_cpu_sirq_pending(CPURISCVState *env) 388 { 389 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 390 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 391 392 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 393 irqs, env->siprio); 394 } 395 396 int riscv_cpu_vsirq_pending(CPURISCVState *env) 397 { 398 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 399 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 400 401 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 402 irqs >> 1, env->hviprio); 403 } 404 405 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 406 { 407 int virq; 408 uint64_t irqs, pending, mie, hsie, vsie; 409 410 /* Determine interrupt enable state of all privilege modes */ 411 if (env->virt_enabled) { 412 mie = 1; 413 hsie = 1; 414 vsie = (env->priv < PRV_S) || 415 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 416 } else { 417 mie = (env->priv < PRV_M) || 418 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 419 hsie = (env->priv < PRV_S) || 420 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 421 vsie = 0; 422 } 423 424 /* Determine all pending interrupts */ 425 pending = riscv_cpu_all_pending(env); 426 427 /* Check M-mode interrupts */ 428 irqs = pending & ~env->mideleg & -mie; 429 if (irqs) { 430 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 431 irqs, env->miprio); 432 } 433 434 /* Check HS-mode interrupts */ 435 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 436 if (irqs) { 437 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 438 irqs, env->siprio); 439 } 440 441 /* Check VS-mode interrupts */ 442 irqs = pending & env->mideleg & env->hideleg & -vsie; 443 if (irqs) { 444 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 445 irqs >> 1, env->hviprio); 446 return (virq <= 0) ? virq : virq + 1; 447 } 448 449 /* Indicate no pending interrupt */ 450 return RISCV_EXCP_NONE; 451 } 452 453 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 454 { 455 if (interrupt_request & CPU_INTERRUPT_HARD) { 456 RISCVCPU *cpu = RISCV_CPU(cs); 457 CPURISCVState *env = &cpu->env; 458 int interruptno = riscv_cpu_local_irq_pending(env); 459 if (interruptno >= 0) { 460 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 461 riscv_cpu_do_interrupt(cs); 462 return true; 463 } 464 } 465 return false; 466 } 467 468 /* Return true is floating point support is currently enabled */ 469 bool riscv_cpu_fp_enabled(CPURISCVState *env) 470 { 471 if (env->mstatus & MSTATUS_FS) { 472 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 473 return false; 474 } 475 return true; 476 } 477 478 return false; 479 } 480 481 /* Return true is vector support is currently enabled */ 482 bool riscv_cpu_vector_enabled(CPURISCVState *env) 483 { 484 if (env->mstatus & MSTATUS_VS) { 485 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 486 return false; 487 } 488 return true; 489 } 490 491 return false; 492 } 493 494 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 495 { 496 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 497 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 498 MSTATUS64_UXL | MSTATUS_VS; 499 500 if (riscv_has_ext(env, RVF)) { 501 mstatus_mask |= MSTATUS_FS; 502 } 503 bool current_virt = env->virt_enabled; 504 505 g_assert(riscv_has_ext(env, RVH)); 506 507 if (current_virt) { 508 /* Current V=1 and we are about to change to V=0 */ 509 env->vsstatus = env->mstatus & mstatus_mask; 510 env->mstatus &= ~mstatus_mask; 511 env->mstatus |= env->mstatus_hs; 512 513 env->vstvec = env->stvec; 514 env->stvec = env->stvec_hs; 515 516 env->vsscratch = env->sscratch; 517 env->sscratch = env->sscratch_hs; 518 519 env->vsepc = env->sepc; 520 env->sepc = env->sepc_hs; 521 522 env->vscause = env->scause; 523 env->scause = env->scause_hs; 524 525 env->vstval = env->stval; 526 env->stval = env->stval_hs; 527 528 env->vsatp = env->satp; 529 env->satp = env->satp_hs; 530 } else { 531 /* Current V=0 and we are about to change to V=1 */ 532 env->mstatus_hs = env->mstatus & mstatus_mask; 533 env->mstatus &= ~mstatus_mask; 534 env->mstatus |= env->vsstatus; 535 536 env->stvec_hs = env->stvec; 537 env->stvec = env->vstvec; 538 539 env->sscratch_hs = env->sscratch; 540 env->sscratch = env->vsscratch; 541 542 env->sepc_hs = env->sepc; 543 env->sepc = env->vsepc; 544 545 env->scause_hs = env->scause; 546 env->scause = env->vscause; 547 548 env->stval_hs = env->stval; 549 env->stval = env->vstval; 550 551 env->satp_hs = env->satp; 552 env->satp = env->vsatp; 553 } 554 } 555 556 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 557 { 558 if (!riscv_has_ext(env, RVH)) { 559 return 0; 560 } 561 562 return env->geilen; 563 } 564 565 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 566 { 567 if (!riscv_has_ext(env, RVH)) { 568 return; 569 } 570 571 if (geilen > (TARGET_LONG_BITS - 1)) { 572 return; 573 } 574 575 env->geilen = geilen; 576 } 577 578 /* This function can only be called to set virt when RVH is enabled */ 579 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 580 { 581 /* Flush the TLB on all virt mode changes. */ 582 if (env->virt_enabled != enable) { 583 tlb_flush(env_cpu(env)); 584 } 585 586 env->virt_enabled = enable; 587 588 if (enable) { 589 /* 590 * The guest external interrupts from an interrupt controller are 591 * delivered only when the Guest/VM is running (i.e. V=1). This means 592 * any guest external interrupt which is triggered while the Guest/VM 593 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 594 * with sluggish response to serial console input and other I/O events. 595 * 596 * To solve this, we check and inject interrupt after setting V=1. 597 */ 598 riscv_cpu_update_mip(env, 0, 0); 599 } 600 } 601 602 bool riscv_cpu_two_stage_lookup(int mmu_idx) 603 { 604 return mmu_idx & MMU_HYP_ACCESS_BIT; 605 } 606 607 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 608 { 609 CPURISCVState *env = &cpu->env; 610 if (env->miclaim & interrupts) { 611 return -1; 612 } else { 613 env->miclaim |= interrupts; 614 return 0; 615 } 616 } 617 618 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 619 uint64_t value) 620 { 621 CPUState *cs = env_cpu(env); 622 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 623 624 if (env->virt_enabled) { 625 gein = get_field(env->hstatus, HSTATUS_VGEIN); 626 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 627 } 628 629 vstip = env->vstime_irq ? MIP_VSTIP : 0; 630 631 QEMU_IOTHREAD_LOCK_GUARD(); 632 633 env->mip = (env->mip & ~mask) | (value & mask); 634 635 if (env->mip | vsgein | vstip) { 636 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 637 } else { 638 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 639 } 640 641 return old; 642 } 643 644 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 645 void *arg) 646 { 647 env->rdtime_fn = fn; 648 env->rdtime_fn_arg = arg; 649 } 650 651 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 652 int (*rmw_fn)(void *arg, 653 target_ulong reg, 654 target_ulong *val, 655 target_ulong new_val, 656 target_ulong write_mask), 657 void *rmw_fn_arg) 658 { 659 if (priv <= PRV_M) { 660 env->aia_ireg_rmw_fn[priv] = rmw_fn; 661 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 662 } 663 } 664 665 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 666 { 667 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); 668 669 if (icount_enabled() && newpriv != env->priv) { 670 riscv_itrigger_update_priv(env); 671 } 672 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 673 env->priv = newpriv; 674 env->xl = cpu_recompute_xl(env); 675 riscv_cpu_update_mask(env); 676 677 /* 678 * Clear the load reservation - otherwise a reservation placed in one 679 * context/process can be used by another, resulting in an SC succeeding 680 * incorrectly. Version 2.2 of the ISA specification explicitly requires 681 * this behaviour, while later revisions say that the kernel "should" use 682 * an SC instruction to force the yielding of a load reservation on a 683 * preemptive context switch. As a result, do both. 684 */ 685 env->load_res = -1; 686 } 687 688 /* 689 * get_physical_address_pmp - check PMP permission for this physical address 690 * 691 * Match the PMP region and check permission for this physical address and it's 692 * TLB page. Returns 0 if the permission checking was successful 693 * 694 * @env: CPURISCVState 695 * @prot: The returned protection attributes 696 * @tlb_size: TLB page size containing addr. It could be modified after PMP 697 * permission checking. NULL if not set TLB page for addr. 698 * @addr: The physical address to be checked permission 699 * @access_type: The type of MMU access 700 * @mode: Indicates current privilege level. 701 */ 702 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 703 target_ulong *tlb_size, hwaddr addr, 704 int size, MMUAccessType access_type, 705 int mode) 706 { 707 pmp_priv_t pmp_priv; 708 int pmp_index = -1; 709 710 if (!riscv_cpu_cfg(env)->pmp) { 711 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 712 return TRANSLATE_SUCCESS; 713 } 714 715 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 716 &pmp_priv, mode); 717 if (pmp_index < 0) { 718 *prot = 0; 719 return TRANSLATE_PMP_FAIL; 720 } 721 722 *prot = pmp_priv_to_page_prot(pmp_priv); 723 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 724 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 725 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 726 727 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 728 } 729 730 return TRANSLATE_SUCCESS; 731 } 732 733 /* 734 * get_physical_address - get the physical address for this virtual address 735 * 736 * Do a page table walk to obtain the physical address corresponding to a 737 * virtual address. Returns 0 if the translation was successful 738 * 739 * Adapted from Spike's mmu_t::translate and mmu_t::walk 740 * 741 * @env: CPURISCVState 742 * @physical: This will be set to the calculated physical address 743 * @prot: The returned protection attributes 744 * @addr: The virtual address or guest physical address to be translated 745 * @fault_pte_addr: If not NULL, this will be set to fault pte address 746 * when a error occurs on pte address translation. 747 * This will already be shifted to match htval. 748 * @access_type: The type of MMU access 749 * @mmu_idx: Indicates current privilege level 750 * @first_stage: Are we in first stage translation? 751 * Second stage is used for hypervisor guest translation 752 * @two_stage: Are we going to perform two stage translation 753 * @is_debug: Is this access from a debugger or the monitor? 754 */ 755 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 756 int *prot, vaddr addr, 757 target_ulong *fault_pte_addr, 758 int access_type, int mmu_idx, 759 bool first_stage, bool two_stage, 760 bool is_debug) 761 { 762 /* 763 * NOTE: the env->pc value visible here will not be 764 * correct, but the value visible to the exception handler 765 * (riscv_cpu_do_interrupt) is correct 766 */ 767 MemTxResult res; 768 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 769 int mode = env->priv; 770 bool use_background = false; 771 hwaddr ppn; 772 int napot_bits = 0; 773 target_ulong napot_mask; 774 775 /* 776 * Check if we should use the background registers for the two 777 * stage translation. We don't need to check if we actually need 778 * two stage translation as that happened before this function 779 * was called. Background registers will be used if the guest has 780 * forced a two stage translation to be on (in HS or M mode). 781 */ 782 if (!env->virt_enabled && two_stage) { 783 use_background = true; 784 } 785 786 /* 787 * MPRV does not affect the virtual-machine load/store 788 * instructions, HLV, HLVX, and HSV. 789 */ 790 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 791 mode = get_field(env->hstatus, HSTATUS_SPVP); 792 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 793 if (get_field(env->mstatus, MSTATUS_MPRV)) { 794 mode = get_field(env->mstatus, MSTATUS_MPP); 795 } 796 } 797 798 if (first_stage == false) { 799 /* 800 * We are in stage 2 translation, this is similar to stage 1. 801 * Stage 2 is always taken as U-mode 802 */ 803 mode = PRV_U; 804 } 805 806 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 807 *physical = addr; 808 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 809 return TRANSLATE_SUCCESS; 810 } 811 812 *prot = 0; 813 814 hwaddr base; 815 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 816 817 if (first_stage == true) { 818 mxr = get_field(env->mstatus, MSTATUS_MXR); 819 } else { 820 mxr = get_field(env->vsstatus, MSTATUS_MXR); 821 } 822 823 if (first_stage == true) { 824 if (use_background) { 825 if (riscv_cpu_mxl(env) == MXL_RV32) { 826 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 827 vm = get_field(env->vsatp, SATP32_MODE); 828 } else { 829 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 830 vm = get_field(env->vsatp, SATP64_MODE); 831 } 832 } else { 833 if (riscv_cpu_mxl(env) == MXL_RV32) { 834 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 835 vm = get_field(env->satp, SATP32_MODE); 836 } else { 837 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 838 vm = get_field(env->satp, SATP64_MODE); 839 } 840 } 841 widened = 0; 842 } else { 843 if (riscv_cpu_mxl(env) == MXL_RV32) { 844 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 845 vm = get_field(env->hgatp, SATP32_MODE); 846 } else { 847 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 848 vm = get_field(env->hgatp, SATP64_MODE); 849 } 850 widened = 2; 851 } 852 /* status.SUM will be ignored if execute on background */ 853 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 854 switch (vm) { 855 case VM_1_10_SV32: 856 levels = 2; ptidxbits = 10; ptesize = 4; break; 857 case VM_1_10_SV39: 858 levels = 3; ptidxbits = 9; ptesize = 8; break; 859 case VM_1_10_SV48: 860 levels = 4; ptidxbits = 9; ptesize = 8; break; 861 case VM_1_10_SV57: 862 levels = 5; ptidxbits = 9; ptesize = 8; break; 863 case VM_1_10_MBARE: 864 *physical = addr; 865 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 866 return TRANSLATE_SUCCESS; 867 default: 868 g_assert_not_reached(); 869 } 870 871 CPUState *cs = env_cpu(env); 872 int va_bits = PGSHIFT + levels * ptidxbits + widened; 873 target_ulong mask, masked_msbs; 874 875 if (TARGET_LONG_BITS > (va_bits - 1)) { 876 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 877 } else { 878 mask = 0; 879 } 880 masked_msbs = (addr >> (va_bits - 1)) & mask; 881 882 if (masked_msbs != 0 && masked_msbs != mask) { 883 return TRANSLATE_FAIL; 884 } 885 886 int ptshift = (levels - 1) * ptidxbits; 887 int i; 888 889 #if !TCG_OVERSIZED_GUEST 890 restart: 891 #endif 892 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 893 target_ulong idx; 894 if (i == 0) { 895 idx = (addr >> (PGSHIFT + ptshift)) & 896 ((1 << (ptidxbits + widened)) - 1); 897 } else { 898 idx = (addr >> (PGSHIFT + ptshift)) & 899 ((1 << ptidxbits) - 1); 900 } 901 902 /* check that physical address of PTE is legal */ 903 hwaddr pte_addr; 904 905 if (two_stage && first_stage) { 906 int vbase_prot; 907 hwaddr vbase; 908 909 /* Do the second stage translation on the base PTE address. */ 910 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 911 base, NULL, MMU_DATA_LOAD, 912 mmu_idx, false, true, 913 is_debug); 914 915 if (vbase_ret != TRANSLATE_SUCCESS) { 916 if (fault_pte_addr) { 917 *fault_pte_addr = (base + idx * ptesize) >> 2; 918 } 919 return TRANSLATE_G_STAGE_FAIL; 920 } 921 922 pte_addr = vbase + idx * ptesize; 923 } else { 924 pte_addr = base + idx * ptesize; 925 } 926 927 int pmp_prot; 928 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 929 sizeof(target_ulong), 930 MMU_DATA_LOAD, PRV_S); 931 if (pmp_ret != TRANSLATE_SUCCESS) { 932 return TRANSLATE_PMP_FAIL; 933 } 934 935 target_ulong pte; 936 if (riscv_cpu_mxl(env) == MXL_RV32) { 937 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 938 } else { 939 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 940 } 941 942 if (res != MEMTX_OK) { 943 return TRANSLATE_FAIL; 944 } 945 946 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 947 bool hade = env->menvcfg & MENVCFG_HADE; 948 949 if (first_stage && two_stage && env->virt_enabled) { 950 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 951 hade = hade && (env->henvcfg & HENVCFG_HADE); 952 } 953 954 if (riscv_cpu_sxl(env) == MXL_RV32) { 955 ppn = pte >> PTE_PPN_SHIFT; 956 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 957 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 958 } else { 959 ppn = pte >> PTE_PPN_SHIFT; 960 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 961 return TRANSLATE_FAIL; 962 } 963 } 964 965 if (!(pte & PTE_V)) { 966 /* Invalid PTE */ 967 return TRANSLATE_FAIL; 968 } else if (!pbmte && (pte & PTE_PBMT)) { 969 return TRANSLATE_FAIL; 970 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 971 /* Inner PTE, continue walking */ 972 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 973 return TRANSLATE_FAIL; 974 } 975 base = ppn << PGSHIFT; 976 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 977 /* Reserved leaf PTE flags: PTE_W */ 978 return TRANSLATE_FAIL; 979 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 980 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 981 return TRANSLATE_FAIL; 982 } else if ((pte & PTE_U) && ((mode != PRV_U) && 983 (!sum || access_type == MMU_INST_FETCH))) { 984 /* User PTE flags when not U mode and mstatus.SUM is not set, 985 or the access type is an instruction fetch */ 986 return TRANSLATE_FAIL; 987 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 988 /* Supervisor PTE flags when not S mode */ 989 return TRANSLATE_FAIL; 990 } else if (ppn & ((1ULL << ptshift) - 1)) { 991 /* Misaligned PPN */ 992 return TRANSLATE_FAIL; 993 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 994 ((pte & PTE_X) && mxr))) { 995 /* Read access check failed */ 996 return TRANSLATE_FAIL; 997 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 998 /* Write access check failed */ 999 return TRANSLATE_FAIL; 1000 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 1001 /* Fetch access check failed */ 1002 return TRANSLATE_FAIL; 1003 } else { 1004 /* if necessary, set accessed and dirty bits. */ 1005 target_ulong updated_pte = pte | PTE_A | 1006 (access_type == MMU_DATA_STORE ? PTE_D : 0); 1007 1008 /* Page table updates need to be atomic with MTTCG enabled */ 1009 if (updated_pte != pte) { 1010 if (!hade) { 1011 return TRANSLATE_FAIL; 1012 } 1013 1014 /* 1015 * - if accessed or dirty bits need updating, and the PTE is 1016 * in RAM, then we do so atomically with a compare and swap. 1017 * - if the PTE is in IO space or ROM, then it can't be updated 1018 * and we return TRANSLATE_FAIL. 1019 * - if the PTE changed by the time we went to update it, then 1020 * it is no longer valid and we must re-walk the page table. 1021 */ 1022 MemoryRegion *mr; 1023 hwaddr l = sizeof(target_ulong), addr1; 1024 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1025 false, MEMTXATTRS_UNSPECIFIED); 1026 if (memory_region_is_ram(mr)) { 1027 target_ulong *pte_pa = 1028 qemu_map_ram_ptr(mr->ram_block, addr1); 1029 #if TCG_OVERSIZED_GUEST 1030 /* 1031 * MTTCG is not enabled on oversized TCG guests so 1032 * page table updates do not need to be atomic 1033 */ 1034 *pte_pa = pte = updated_pte; 1035 #else 1036 target_ulong old_pte = 1037 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1038 if (old_pte != pte) { 1039 goto restart; 1040 } else { 1041 pte = updated_pte; 1042 } 1043 #endif 1044 } else { 1045 /* 1046 * misconfigured PTE in ROM (AD bits are not preset) or 1047 * PTE is in IO space and can't be updated atomically 1048 */ 1049 return TRANSLATE_FAIL; 1050 } 1051 } 1052 1053 /* 1054 * for superpage mappings, make a fake leaf PTE for the TLB's 1055 * benefit. 1056 */ 1057 target_ulong vpn = addr >> PGSHIFT; 1058 1059 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1060 napot_bits = ctzl(ppn) + 1; 1061 if ((i != (levels - 1)) || (napot_bits != 4)) { 1062 return TRANSLATE_FAIL; 1063 } 1064 } 1065 1066 napot_mask = (1 << napot_bits) - 1; 1067 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1068 (vpn & (((target_ulong)1 << ptshift) - 1)) 1069 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1070 1071 /* set permissions on the TLB entry */ 1072 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1073 *prot |= PAGE_READ; 1074 } 1075 if (pte & PTE_X) { 1076 *prot |= PAGE_EXEC; 1077 } 1078 /* 1079 * add write permission on stores or if the page is already dirty, 1080 * so that we TLB miss on later writes to update the dirty bit 1081 */ 1082 if ((pte & PTE_W) && 1083 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1084 *prot |= PAGE_WRITE; 1085 } 1086 return TRANSLATE_SUCCESS; 1087 } 1088 } 1089 return TRANSLATE_FAIL; 1090 } 1091 1092 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1093 MMUAccessType access_type, bool pmp_violation, 1094 bool first_stage, bool two_stage, 1095 bool two_stage_indirect) 1096 { 1097 CPUState *cs = env_cpu(env); 1098 int page_fault_exceptions, vm; 1099 uint64_t stap_mode; 1100 1101 if (riscv_cpu_mxl(env) == MXL_RV32) { 1102 stap_mode = SATP32_MODE; 1103 } else { 1104 stap_mode = SATP64_MODE; 1105 } 1106 1107 if (first_stage) { 1108 vm = get_field(env->satp, stap_mode); 1109 } else { 1110 vm = get_field(env->hgatp, stap_mode); 1111 } 1112 1113 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1114 1115 switch (access_type) { 1116 case MMU_INST_FETCH: 1117 if (env->virt_enabled && !first_stage) { 1118 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1119 } else { 1120 cs->exception_index = page_fault_exceptions ? 1121 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1122 } 1123 break; 1124 case MMU_DATA_LOAD: 1125 if (two_stage && !first_stage) { 1126 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1127 } else { 1128 cs->exception_index = page_fault_exceptions ? 1129 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1130 } 1131 break; 1132 case MMU_DATA_STORE: 1133 if (two_stage && !first_stage) { 1134 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1135 } else { 1136 cs->exception_index = page_fault_exceptions ? 1137 RISCV_EXCP_STORE_PAGE_FAULT : 1138 RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1139 } 1140 break; 1141 default: 1142 g_assert_not_reached(); 1143 } 1144 env->badaddr = address; 1145 env->two_stage_lookup = two_stage; 1146 env->two_stage_indirect_lookup = two_stage_indirect; 1147 } 1148 1149 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1150 { 1151 RISCVCPU *cpu = RISCV_CPU(cs); 1152 CPURISCVState *env = &cpu->env; 1153 hwaddr phys_addr; 1154 int prot; 1155 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1156 1157 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1158 true, env->virt_enabled, true)) { 1159 return -1; 1160 } 1161 1162 if (env->virt_enabled) { 1163 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1164 0, mmu_idx, false, true, true)) { 1165 return -1; 1166 } 1167 } 1168 1169 return phys_addr & TARGET_PAGE_MASK; 1170 } 1171 1172 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1173 vaddr addr, unsigned size, 1174 MMUAccessType access_type, 1175 int mmu_idx, MemTxAttrs attrs, 1176 MemTxResult response, uintptr_t retaddr) 1177 { 1178 RISCVCPU *cpu = RISCV_CPU(cs); 1179 CPURISCVState *env = &cpu->env; 1180 1181 if (access_type == MMU_DATA_STORE) { 1182 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1183 } else if (access_type == MMU_DATA_LOAD) { 1184 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1185 } else { 1186 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1187 } 1188 1189 env->badaddr = addr; 1190 env->two_stage_lookup = env->virt_enabled || 1191 riscv_cpu_two_stage_lookup(mmu_idx); 1192 env->two_stage_indirect_lookup = false; 1193 cpu_loop_exit_restore(cs, retaddr); 1194 } 1195 1196 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1197 MMUAccessType access_type, int mmu_idx, 1198 uintptr_t retaddr) 1199 { 1200 RISCVCPU *cpu = RISCV_CPU(cs); 1201 CPURISCVState *env = &cpu->env; 1202 switch (access_type) { 1203 case MMU_INST_FETCH: 1204 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1205 break; 1206 case MMU_DATA_LOAD: 1207 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1208 break; 1209 case MMU_DATA_STORE: 1210 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1211 break; 1212 default: 1213 g_assert_not_reached(); 1214 } 1215 env->badaddr = addr; 1216 env->two_stage_lookup = env->virt_enabled || 1217 riscv_cpu_two_stage_lookup(mmu_idx); 1218 env->two_stage_indirect_lookup = false; 1219 cpu_loop_exit_restore(cs, retaddr); 1220 } 1221 1222 1223 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1224 { 1225 enum riscv_pmu_event_idx pmu_event_type; 1226 1227 switch (access_type) { 1228 case MMU_INST_FETCH: 1229 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1230 break; 1231 case MMU_DATA_LOAD: 1232 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1233 break; 1234 case MMU_DATA_STORE: 1235 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1236 break; 1237 default: 1238 return; 1239 } 1240 1241 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1242 } 1243 1244 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1245 MMUAccessType access_type, int mmu_idx, 1246 bool probe, uintptr_t retaddr) 1247 { 1248 RISCVCPU *cpu = RISCV_CPU(cs); 1249 CPURISCVState *env = &cpu->env; 1250 vaddr im_address; 1251 hwaddr pa = 0; 1252 int prot, prot2, prot_pmp; 1253 bool pmp_violation = false; 1254 bool first_stage_error = true; 1255 bool two_stage_lookup = false; 1256 bool two_stage_indirect_error = false; 1257 int ret = TRANSLATE_FAIL; 1258 int mode = mmu_idx; 1259 /* default TLB page size */ 1260 target_ulong tlb_size = TARGET_PAGE_SIZE; 1261 1262 env->guest_phys_fault_addr = 0; 1263 1264 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1265 __func__, address, access_type, mmu_idx); 1266 1267 /* 1268 * MPRV does not affect the virtual-machine load/store 1269 * instructions, HLV, HLVX, and HSV. 1270 */ 1271 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1272 mode = get_field(env->hstatus, HSTATUS_SPVP); 1273 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1274 get_field(env->mstatus, MSTATUS_MPRV)) { 1275 mode = get_field(env->mstatus, MSTATUS_MPP); 1276 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1277 two_stage_lookup = true; 1278 } 1279 } 1280 1281 pmu_tlb_fill_incr_ctr(cpu, access_type); 1282 if (env->virt_enabled || 1283 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1284 access_type != MMU_INST_FETCH)) { 1285 /* Two stage lookup */ 1286 ret = get_physical_address(env, &pa, &prot, address, 1287 &env->guest_phys_fault_addr, access_type, 1288 mmu_idx, true, true, false); 1289 1290 /* 1291 * A G-stage exception may be triggered during two state lookup. 1292 * And the env->guest_phys_fault_addr has already been set in 1293 * get_physical_address(). 1294 */ 1295 if (ret == TRANSLATE_G_STAGE_FAIL) { 1296 first_stage_error = false; 1297 two_stage_indirect_error = true; 1298 access_type = MMU_DATA_LOAD; 1299 } 1300 1301 qemu_log_mask(CPU_LOG_MMU, 1302 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1303 HWADDR_FMT_plx " prot %d\n", 1304 __func__, address, ret, pa, prot); 1305 1306 if (ret == TRANSLATE_SUCCESS) { 1307 /* Second stage lookup */ 1308 im_address = pa; 1309 1310 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1311 access_type, mmu_idx, false, true, 1312 false); 1313 1314 qemu_log_mask(CPU_LOG_MMU, 1315 "%s 2nd-stage address=%" VADDR_PRIx 1316 " ret %d physical " 1317 HWADDR_FMT_plx " prot %d\n", 1318 __func__, im_address, ret, pa, prot2); 1319 1320 prot &= prot2; 1321 1322 if (ret == TRANSLATE_SUCCESS) { 1323 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1324 size, access_type, mode); 1325 1326 qemu_log_mask(CPU_LOG_MMU, 1327 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1328 " %d tlb_size " TARGET_FMT_lu "\n", 1329 __func__, pa, ret, prot_pmp, tlb_size); 1330 1331 prot &= prot_pmp; 1332 } 1333 1334 if (ret != TRANSLATE_SUCCESS) { 1335 /* 1336 * Guest physical address translation failed, this is a HS 1337 * level exception 1338 */ 1339 first_stage_error = false; 1340 env->guest_phys_fault_addr = (im_address | 1341 (address & 1342 (TARGET_PAGE_SIZE - 1))) >> 2; 1343 } 1344 } 1345 } else { 1346 /* Single stage lookup */ 1347 ret = get_physical_address(env, &pa, &prot, address, NULL, 1348 access_type, mmu_idx, true, false, false); 1349 1350 qemu_log_mask(CPU_LOG_MMU, 1351 "%s address=%" VADDR_PRIx " ret %d physical " 1352 HWADDR_FMT_plx " prot %d\n", 1353 __func__, address, ret, pa, prot); 1354 1355 if (ret == TRANSLATE_SUCCESS) { 1356 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1357 size, access_type, mode); 1358 1359 qemu_log_mask(CPU_LOG_MMU, 1360 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1361 " %d tlb_size " TARGET_FMT_lu "\n", 1362 __func__, pa, ret, prot_pmp, tlb_size); 1363 1364 prot &= prot_pmp; 1365 } 1366 } 1367 1368 if (ret == TRANSLATE_PMP_FAIL) { 1369 pmp_violation = true; 1370 } 1371 1372 if (ret == TRANSLATE_SUCCESS) { 1373 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1374 prot, mmu_idx, tlb_size); 1375 return true; 1376 } else if (probe) { 1377 return false; 1378 } else { 1379 raise_mmu_exception(env, address, access_type, pmp_violation, 1380 first_stage_error, 1381 env->virt_enabled || 1382 riscv_cpu_two_stage_lookup(mmu_idx), 1383 two_stage_indirect_error); 1384 cpu_loop_exit_restore(cs, retaddr); 1385 } 1386 1387 return true; 1388 } 1389 1390 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1391 target_ulong insn, 1392 target_ulong taddr) 1393 { 1394 target_ulong xinsn = 0; 1395 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1396 1397 /* 1398 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1399 * be uncompressed. The Quadrant 1 of RVC instruction space need 1400 * not be transformed because these instructions won't generate 1401 * any load/store trap. 1402 */ 1403 1404 if ((insn & 0x3) != 0x3) { 1405 /* Transform 16bit instruction into 32bit instruction */ 1406 switch (GET_C_OP(insn)) { 1407 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1408 switch (GET_C_FUNC(insn)) { 1409 case OPC_RISC_C_FUNC_FLD_LQ: 1410 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1411 xinsn = OPC_RISC_FLD; 1412 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1413 access_rs1 = GET_C_RS1S(insn); 1414 access_imm = GET_C_LD_IMM(insn); 1415 access_size = 8; 1416 } 1417 break; 1418 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1419 xinsn = OPC_RISC_LW; 1420 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1421 access_rs1 = GET_C_RS1S(insn); 1422 access_imm = GET_C_LW_IMM(insn); 1423 access_size = 4; 1424 break; 1425 case OPC_RISC_C_FUNC_FLW_LD: 1426 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1427 xinsn = OPC_RISC_FLW; 1428 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1429 access_rs1 = GET_C_RS1S(insn); 1430 access_imm = GET_C_LW_IMM(insn); 1431 access_size = 4; 1432 } else { /* C.LD (RV64/RV128) */ 1433 xinsn = OPC_RISC_LD; 1434 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1435 access_rs1 = GET_C_RS1S(insn); 1436 access_imm = GET_C_LD_IMM(insn); 1437 access_size = 8; 1438 } 1439 break; 1440 case OPC_RISC_C_FUNC_FSD_SQ: 1441 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1442 xinsn = OPC_RISC_FSD; 1443 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1444 access_rs1 = GET_C_RS1S(insn); 1445 access_imm = GET_C_SD_IMM(insn); 1446 access_size = 8; 1447 } 1448 break; 1449 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1450 xinsn = OPC_RISC_SW; 1451 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1452 access_rs1 = GET_C_RS1S(insn); 1453 access_imm = GET_C_SW_IMM(insn); 1454 access_size = 4; 1455 break; 1456 case OPC_RISC_C_FUNC_FSW_SD: 1457 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1458 xinsn = OPC_RISC_FSW; 1459 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1460 access_rs1 = GET_C_RS1S(insn); 1461 access_imm = GET_C_SW_IMM(insn); 1462 access_size = 4; 1463 } else { /* C.SD (RV64/RV128) */ 1464 xinsn = OPC_RISC_SD; 1465 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1466 access_rs1 = GET_C_RS1S(insn); 1467 access_imm = GET_C_SD_IMM(insn); 1468 access_size = 8; 1469 } 1470 break; 1471 default: 1472 break; 1473 } 1474 break; 1475 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1476 switch (GET_C_FUNC(insn)) { 1477 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1478 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1479 xinsn = OPC_RISC_FLD; 1480 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1481 access_rs1 = 2; 1482 access_imm = GET_C_LDSP_IMM(insn); 1483 access_size = 8; 1484 } 1485 break; 1486 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1487 xinsn = OPC_RISC_LW; 1488 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1489 access_rs1 = 2; 1490 access_imm = GET_C_LWSP_IMM(insn); 1491 access_size = 4; 1492 break; 1493 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1494 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1495 xinsn = OPC_RISC_FLW; 1496 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1497 access_rs1 = 2; 1498 access_imm = GET_C_LWSP_IMM(insn); 1499 access_size = 4; 1500 } else { /* C.LDSP (RV64/RV128) */ 1501 xinsn = OPC_RISC_LD; 1502 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1503 access_rs1 = 2; 1504 access_imm = GET_C_LDSP_IMM(insn); 1505 access_size = 8; 1506 } 1507 break; 1508 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1509 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1510 xinsn = OPC_RISC_FSD; 1511 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1512 access_rs1 = 2; 1513 access_imm = GET_C_SDSP_IMM(insn); 1514 access_size = 8; 1515 } 1516 break; 1517 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1518 xinsn = OPC_RISC_SW; 1519 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1520 access_rs1 = 2; 1521 access_imm = GET_C_SWSP_IMM(insn); 1522 access_size = 4; 1523 break; 1524 case 7: 1525 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1526 xinsn = OPC_RISC_FSW; 1527 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1528 access_rs1 = 2; 1529 access_imm = GET_C_SWSP_IMM(insn); 1530 access_size = 4; 1531 } else { /* C.SDSP (RV64/RV128) */ 1532 xinsn = OPC_RISC_SD; 1533 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1534 access_rs1 = 2; 1535 access_imm = GET_C_SDSP_IMM(insn); 1536 access_size = 8; 1537 } 1538 break; 1539 default: 1540 break; 1541 } 1542 break; 1543 default: 1544 break; 1545 } 1546 1547 /* 1548 * Clear Bit1 of transformed instruction to indicate that 1549 * original insruction was a 16bit instruction 1550 */ 1551 xinsn &= ~((target_ulong)0x2); 1552 } else { 1553 /* Transform 32bit (or wider) instructions */ 1554 switch (MASK_OP_MAJOR(insn)) { 1555 case OPC_RISC_ATOMIC: 1556 xinsn = insn; 1557 access_rs1 = GET_RS1(insn); 1558 access_size = 1 << GET_FUNCT3(insn); 1559 break; 1560 case OPC_RISC_LOAD: 1561 case OPC_RISC_FP_LOAD: 1562 xinsn = SET_I_IMM(insn, 0); 1563 access_rs1 = GET_RS1(insn); 1564 access_imm = GET_IMM(insn); 1565 access_size = 1 << GET_FUNCT3(insn); 1566 break; 1567 case OPC_RISC_STORE: 1568 case OPC_RISC_FP_STORE: 1569 xinsn = SET_S_IMM(insn, 0); 1570 access_rs1 = GET_RS1(insn); 1571 access_imm = GET_STORE_IMM(insn); 1572 access_size = 1 << GET_FUNCT3(insn); 1573 break; 1574 case OPC_RISC_SYSTEM: 1575 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1576 xinsn = insn; 1577 access_rs1 = GET_RS1(insn); 1578 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1579 access_size = 1 << access_size; 1580 } 1581 break; 1582 default: 1583 break; 1584 } 1585 } 1586 1587 if (access_size) { 1588 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1589 (access_size - 1)); 1590 } 1591 1592 return xinsn; 1593 } 1594 #endif /* !CONFIG_USER_ONLY */ 1595 1596 /* 1597 * Handle Traps 1598 * 1599 * Adapted from Spike's processor_t::take_trap. 1600 * 1601 */ 1602 void riscv_cpu_do_interrupt(CPUState *cs) 1603 { 1604 #if !defined(CONFIG_USER_ONLY) 1605 1606 RISCVCPU *cpu = RISCV_CPU(cs); 1607 CPURISCVState *env = &cpu->env; 1608 bool write_gva = false; 1609 uint64_t s; 1610 1611 /* 1612 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1613 * so we mask off the MSB and separate into trap type and cause. 1614 */ 1615 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1616 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1617 uint64_t deleg = async ? env->mideleg : env->medeleg; 1618 target_ulong tval = 0; 1619 target_ulong tinst = 0; 1620 target_ulong htval = 0; 1621 target_ulong mtval2 = 0; 1622 1623 if (cause == RISCV_EXCP_SEMIHOST) { 1624 do_common_semihosting(cs); 1625 env->pc += 4; 1626 return; 1627 } 1628 1629 if (!async) { 1630 /* set tval to badaddr for traps with address information */ 1631 switch (cause) { 1632 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1633 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1634 case RISCV_EXCP_LOAD_ADDR_MIS: 1635 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1636 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1637 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1638 case RISCV_EXCP_LOAD_PAGE_FAULT: 1639 case RISCV_EXCP_STORE_PAGE_FAULT: 1640 write_gva = env->two_stage_lookup; 1641 tval = env->badaddr; 1642 if (env->two_stage_indirect_lookup) { 1643 /* 1644 * special pseudoinstruction for G-stage fault taken while 1645 * doing VS-stage page table walk. 1646 */ 1647 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1648 } else { 1649 /* 1650 * The "Addr. Offset" field in transformed instruction is 1651 * non-zero only for misaligned access. 1652 */ 1653 tinst = riscv_transformed_insn(env, env->bins, tval); 1654 } 1655 break; 1656 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1657 case RISCV_EXCP_INST_ADDR_MIS: 1658 case RISCV_EXCP_INST_ACCESS_FAULT: 1659 case RISCV_EXCP_INST_PAGE_FAULT: 1660 write_gva = env->two_stage_lookup; 1661 tval = env->badaddr; 1662 if (env->two_stage_indirect_lookup) { 1663 /* 1664 * special pseudoinstruction for G-stage fault taken while 1665 * doing VS-stage page table walk. 1666 */ 1667 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1668 } 1669 break; 1670 case RISCV_EXCP_ILLEGAL_INST: 1671 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1672 tval = env->bins; 1673 break; 1674 case RISCV_EXCP_BREAKPOINT: 1675 if (cs->watchpoint_hit) { 1676 tval = cs->watchpoint_hit->hitaddr; 1677 cs->watchpoint_hit = NULL; 1678 } 1679 break; 1680 default: 1681 break; 1682 } 1683 /* ecall is dispatched as one cause so translate based on mode */ 1684 if (cause == RISCV_EXCP_U_ECALL) { 1685 assert(env->priv <= 3); 1686 1687 if (env->priv == PRV_M) { 1688 cause = RISCV_EXCP_M_ECALL; 1689 } else if (env->priv == PRV_S && env->virt_enabled) { 1690 cause = RISCV_EXCP_VS_ECALL; 1691 } else if (env->priv == PRV_S && !env->virt_enabled) { 1692 cause = RISCV_EXCP_S_ECALL; 1693 } else if (env->priv == PRV_U) { 1694 cause = RISCV_EXCP_U_ECALL; 1695 } 1696 } 1697 } 1698 1699 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1700 riscv_cpu_get_trap_name(cause, async)); 1701 1702 qemu_log_mask(CPU_LOG_INT, 1703 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1704 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1705 __func__, env->mhartid, async, cause, env->pc, tval, 1706 riscv_cpu_get_trap_name(cause, async)); 1707 1708 if (env->priv <= PRV_S && 1709 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1710 /* handle the trap in S-mode */ 1711 if (riscv_has_ext(env, RVH)) { 1712 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1713 1714 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1715 /* Trap to VS mode */ 1716 /* 1717 * See if we need to adjust cause. Yes if its VS mode interrupt 1718 * no if hypervisor has delegated one of hs mode's interrupt 1719 */ 1720 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1721 cause == IRQ_VS_EXT) { 1722 cause = cause - 1; 1723 } 1724 write_gva = false; 1725 } else if (env->virt_enabled) { 1726 /* Trap into HS mode, from virt */ 1727 riscv_cpu_swap_hypervisor_regs(env); 1728 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1729 env->priv); 1730 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1731 1732 htval = env->guest_phys_fault_addr; 1733 1734 riscv_cpu_set_virt_enabled(env, 0); 1735 } else { 1736 /* Trap into HS mode */ 1737 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1738 htval = env->guest_phys_fault_addr; 1739 } 1740 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1741 } 1742 1743 s = env->mstatus; 1744 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1745 s = set_field(s, MSTATUS_SPP, env->priv); 1746 s = set_field(s, MSTATUS_SIE, 0); 1747 env->mstatus = s; 1748 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1749 env->sepc = env->pc; 1750 env->stval = tval; 1751 env->htval = htval; 1752 env->htinst = tinst; 1753 env->pc = (env->stvec >> 2 << 2) + 1754 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1755 riscv_cpu_set_mode(env, PRV_S); 1756 } else { 1757 /* handle the trap in M-mode */ 1758 if (riscv_has_ext(env, RVH)) { 1759 if (env->virt_enabled) { 1760 riscv_cpu_swap_hypervisor_regs(env); 1761 } 1762 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1763 env->virt_enabled); 1764 if (env->virt_enabled && tval) { 1765 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1766 } 1767 1768 mtval2 = env->guest_phys_fault_addr; 1769 1770 /* Trapping to M mode, virt is disabled */ 1771 riscv_cpu_set_virt_enabled(env, 0); 1772 } 1773 1774 s = env->mstatus; 1775 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1776 s = set_field(s, MSTATUS_MPP, env->priv); 1777 s = set_field(s, MSTATUS_MIE, 0); 1778 env->mstatus = s; 1779 env->mcause = cause | ~(((target_ulong)-1) >> async); 1780 env->mepc = env->pc; 1781 env->mtval = tval; 1782 env->mtval2 = mtval2; 1783 env->mtinst = tinst; 1784 env->pc = (env->mtvec >> 2 << 2) + 1785 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1786 riscv_cpu_set_mode(env, PRV_M); 1787 } 1788 1789 /* 1790 * NOTE: it is not necessary to yield load reservations here. It is only 1791 * necessary for an SC from "another hart" to cause a load reservation 1792 * to be yielded. Refer to the memory consistency model section of the 1793 * RISC-V ISA Specification. 1794 */ 1795 1796 env->two_stage_lookup = false; 1797 env->two_stage_indirect_lookup = false; 1798 #endif 1799 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1800 } 1801