1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 #include "semihosting/common-semi.h" 28 29 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 30 { 31 #ifdef CONFIG_USER_ONLY 32 return 0; 33 #else 34 return env->priv; 35 #endif 36 } 37 38 #ifndef CONFIG_USER_ONLY 39 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 40 { 41 target_ulong irqs; 42 43 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 44 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 45 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 46 47 target_ulong pending = env->mip & env->mie & 48 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 49 target_ulong vspending = (env->mip & env->mie & 50 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); 51 52 target_ulong mie = env->priv < PRV_M || 53 (env->priv == PRV_M && mstatus_mie); 54 target_ulong sie = env->priv < PRV_S || 55 (env->priv == PRV_S && mstatus_sie); 56 target_ulong hs_sie = env->priv < PRV_S || 57 (env->priv == PRV_S && hs_mstatus_sie); 58 59 if (riscv_cpu_virt_enabled(env)) { 60 target_ulong pending_hs_irq = pending & -hs_sie; 61 62 if (pending_hs_irq) { 63 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 64 return ctz64(pending_hs_irq); 65 } 66 67 pending = vspending; 68 } 69 70 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 71 72 if (irqs) { 73 return ctz64(irqs); /* since non-zero */ 74 } else { 75 return RISCV_EXCP_NONE; /* indicates no pending interrupt */ 76 } 77 } 78 #endif 79 80 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 81 { 82 #if !defined(CONFIG_USER_ONLY) 83 if (interrupt_request & CPU_INTERRUPT_HARD) { 84 RISCVCPU *cpu = RISCV_CPU(cs); 85 CPURISCVState *env = &cpu->env; 86 int interruptno = riscv_cpu_local_irq_pending(env); 87 if (interruptno >= 0) { 88 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 89 riscv_cpu_do_interrupt(cs); 90 return true; 91 } 92 } 93 #endif 94 return false; 95 } 96 97 #if !defined(CONFIG_USER_ONLY) 98 99 /* Return true is floating point support is currently enabled */ 100 bool riscv_cpu_fp_enabled(CPURISCVState *env) 101 { 102 if (env->mstatus & MSTATUS_FS) { 103 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 104 return false; 105 } 106 return true; 107 } 108 109 return false; 110 } 111 112 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 113 { 114 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 115 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 116 MSTATUS64_UXL; 117 bool current_virt = riscv_cpu_virt_enabled(env); 118 119 g_assert(riscv_has_ext(env, RVH)); 120 121 if (current_virt) { 122 /* Current V=1 and we are about to change to V=0 */ 123 env->vsstatus = env->mstatus & mstatus_mask; 124 env->mstatus &= ~mstatus_mask; 125 env->mstatus |= env->mstatus_hs; 126 127 env->vstvec = env->stvec; 128 env->stvec = env->stvec_hs; 129 130 env->vsscratch = env->sscratch; 131 env->sscratch = env->sscratch_hs; 132 133 env->vsepc = env->sepc; 134 env->sepc = env->sepc_hs; 135 136 env->vscause = env->scause; 137 env->scause = env->scause_hs; 138 139 env->vstval = env->stval; 140 env->stval = env->stval_hs; 141 142 env->vsatp = env->satp; 143 env->satp = env->satp_hs; 144 } else { 145 /* Current V=0 and we are about to change to V=1 */ 146 env->mstatus_hs = env->mstatus & mstatus_mask; 147 env->mstatus &= ~mstatus_mask; 148 env->mstatus |= env->vsstatus; 149 150 env->stvec_hs = env->stvec; 151 env->stvec = env->vstvec; 152 153 env->sscratch_hs = env->sscratch; 154 env->sscratch = env->vsscratch; 155 156 env->sepc_hs = env->sepc; 157 env->sepc = env->vsepc; 158 159 env->scause_hs = env->scause; 160 env->scause = env->vscause; 161 162 env->stval_hs = env->stval; 163 env->stval = env->vstval; 164 165 env->satp_hs = env->satp; 166 env->satp = env->vsatp; 167 } 168 } 169 170 bool riscv_cpu_virt_enabled(CPURISCVState *env) 171 { 172 if (!riscv_has_ext(env, RVH)) { 173 return false; 174 } 175 176 return get_field(env->virt, VIRT_ONOFF); 177 } 178 179 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 180 { 181 if (!riscv_has_ext(env, RVH)) { 182 return; 183 } 184 185 /* Flush the TLB on all virt mode changes. */ 186 if (get_field(env->virt, VIRT_ONOFF) != enable) { 187 tlb_flush(env_cpu(env)); 188 } 189 190 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 191 } 192 193 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 194 { 195 if (!riscv_has_ext(env, RVH)) { 196 return false; 197 } 198 199 return get_field(env->virt, FORCE_HS_EXCEP); 200 } 201 202 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 203 { 204 if (!riscv_has_ext(env, RVH)) { 205 return; 206 } 207 208 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 209 } 210 211 bool riscv_cpu_two_stage_lookup(int mmu_idx) 212 { 213 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 214 } 215 216 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 217 { 218 CPURISCVState *env = &cpu->env; 219 if (env->miclaim & interrupts) { 220 return -1; 221 } else { 222 env->miclaim |= interrupts; 223 return 0; 224 } 225 } 226 227 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 228 { 229 CPURISCVState *env = &cpu->env; 230 CPUState *cs = CPU(cpu); 231 uint32_t old = env->mip; 232 bool locked = false; 233 234 if (!qemu_mutex_iothread_locked()) { 235 locked = true; 236 qemu_mutex_lock_iothread(); 237 } 238 239 env->mip = (env->mip & ~mask) | (value & mask); 240 241 if (env->mip) { 242 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 243 } else { 244 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 245 } 246 247 if (locked) { 248 qemu_mutex_unlock_iothread(); 249 } 250 251 return old; 252 } 253 254 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 255 uint32_t arg) 256 { 257 env->rdtime_fn = fn; 258 env->rdtime_fn_arg = arg; 259 } 260 261 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 262 { 263 if (newpriv > PRV_M) { 264 g_assert_not_reached(); 265 } 266 if (newpriv == PRV_H) { 267 newpriv = PRV_U; 268 } 269 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 270 env->priv = newpriv; 271 272 /* 273 * Clear the load reservation - otherwise a reservation placed in one 274 * context/process can be used by another, resulting in an SC succeeding 275 * incorrectly. Version 2.2 of the ISA specification explicitly requires 276 * this behaviour, while later revisions say that the kernel "should" use 277 * an SC instruction to force the yielding of a load reservation on a 278 * preemptive context switch. As a result, do both. 279 */ 280 env->load_res = -1; 281 } 282 283 /* 284 * get_physical_address_pmp - check PMP permission for this physical address 285 * 286 * Match the PMP region and check permission for this physical address and it's 287 * TLB page. Returns 0 if the permission checking was successful 288 * 289 * @env: CPURISCVState 290 * @prot: The returned protection attributes 291 * @tlb_size: TLB page size containing addr. It could be modified after PMP 292 * permission checking. NULL if not set TLB page for addr. 293 * @addr: The physical address to be checked permission 294 * @access_type: The type of MMU access 295 * @mode: Indicates current privilege level. 296 */ 297 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 298 target_ulong *tlb_size, hwaddr addr, 299 int size, MMUAccessType access_type, 300 int mode) 301 { 302 pmp_priv_t pmp_priv; 303 target_ulong tlb_size_pmp = 0; 304 305 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 306 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 307 return TRANSLATE_SUCCESS; 308 } 309 310 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, 311 mode)) { 312 *prot = 0; 313 return TRANSLATE_PMP_FAIL; 314 } 315 316 *prot = pmp_priv_to_page_prot(pmp_priv); 317 if (tlb_size != NULL) { 318 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { 319 *tlb_size = tlb_size_pmp; 320 } 321 } 322 323 return TRANSLATE_SUCCESS; 324 } 325 326 /* get_physical_address - get the physical address for this virtual address 327 * 328 * Do a page table walk to obtain the physical address corresponding to a 329 * virtual address. Returns 0 if the translation was successful 330 * 331 * Adapted from Spike's mmu_t::translate and mmu_t::walk 332 * 333 * @env: CPURISCVState 334 * @physical: This will be set to the calculated physical address 335 * @prot: The returned protection attributes 336 * @addr: The virtual address to be translated 337 * @fault_pte_addr: If not NULL, this will be set to fault pte address 338 * when a error occurs on pte address translation. 339 * This will already be shifted to match htval. 340 * @access_type: The type of MMU access 341 * @mmu_idx: Indicates current privilege level 342 * @first_stage: Are we in first stage translation? 343 * Second stage is used for hypervisor guest translation 344 * @two_stage: Are we going to perform two stage translation 345 * @is_debug: Is this access from a debugger or the monitor? 346 */ 347 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 348 int *prot, target_ulong addr, 349 target_ulong *fault_pte_addr, 350 int access_type, int mmu_idx, 351 bool first_stage, bool two_stage, 352 bool is_debug) 353 { 354 /* NOTE: the env->pc value visible here will not be 355 * correct, but the value visible to the exception handler 356 * (riscv_cpu_do_interrupt) is correct */ 357 MemTxResult res; 358 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 359 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 360 bool use_background = false; 361 362 /* 363 * Check if we should use the background registers for the two 364 * stage translation. We don't need to check if we actually need 365 * two stage translation as that happened before this function 366 * was called. Background registers will be used if the guest has 367 * forced a two stage translation to be on (in HS or M mode). 368 */ 369 if (!riscv_cpu_virt_enabled(env) && two_stage) { 370 use_background = true; 371 } 372 373 /* MPRV does not affect the virtual-machine load/store 374 instructions, HLV, HLVX, and HSV. */ 375 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 376 mode = get_field(env->hstatus, HSTATUS_SPVP); 377 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 378 if (get_field(env->mstatus, MSTATUS_MPRV)) { 379 mode = get_field(env->mstatus, MSTATUS_MPP); 380 } 381 } 382 383 if (first_stage == false) { 384 /* We are in stage 2 translation, this is similar to stage 1. */ 385 /* Stage 2 is always taken as U-mode */ 386 mode = PRV_U; 387 } 388 389 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 390 *physical = addr; 391 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 392 return TRANSLATE_SUCCESS; 393 } 394 395 *prot = 0; 396 397 hwaddr base; 398 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 399 400 if (first_stage == true) { 401 mxr = get_field(env->mstatus, MSTATUS_MXR); 402 } else { 403 mxr = get_field(env->vsstatus, MSTATUS_MXR); 404 } 405 406 if (first_stage == true) { 407 if (use_background) { 408 base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; 409 vm = get_field(env->vsatp, SATP_MODE); 410 } else { 411 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 412 vm = get_field(env->satp, SATP_MODE); 413 } 414 widened = 0; 415 } else { 416 if (riscv_cpu_is_32bit(env)) { 417 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 418 vm = get_field(env->hgatp, SATP32_MODE); 419 } else { 420 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 421 vm = get_field(env->hgatp, SATP64_MODE); 422 } 423 widened = 2; 424 } 425 /* status.SUM will be ignored if execute on background */ 426 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 427 switch (vm) { 428 case VM_1_10_SV32: 429 levels = 2; ptidxbits = 10; ptesize = 4; break; 430 case VM_1_10_SV39: 431 levels = 3; ptidxbits = 9; ptesize = 8; break; 432 case VM_1_10_SV48: 433 levels = 4; ptidxbits = 9; ptesize = 8; break; 434 case VM_1_10_SV57: 435 levels = 5; ptidxbits = 9; ptesize = 8; break; 436 case VM_1_10_MBARE: 437 *physical = addr; 438 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 439 return TRANSLATE_SUCCESS; 440 default: 441 g_assert_not_reached(); 442 } 443 444 CPUState *cs = env_cpu(env); 445 int va_bits = PGSHIFT + levels * ptidxbits + widened; 446 target_ulong mask, masked_msbs; 447 448 if (TARGET_LONG_BITS > (va_bits - 1)) { 449 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 450 } else { 451 mask = 0; 452 } 453 masked_msbs = (addr >> (va_bits - 1)) & mask; 454 455 if (masked_msbs != 0 && masked_msbs != mask) { 456 return TRANSLATE_FAIL; 457 } 458 459 int ptshift = (levels - 1) * ptidxbits; 460 int i; 461 462 #if !TCG_OVERSIZED_GUEST 463 restart: 464 #endif 465 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 466 target_ulong idx; 467 if (i == 0) { 468 idx = (addr >> (PGSHIFT + ptshift)) & 469 ((1 << (ptidxbits + widened)) - 1); 470 } else { 471 idx = (addr >> (PGSHIFT + ptshift)) & 472 ((1 << ptidxbits) - 1); 473 } 474 475 /* check that physical address of PTE is legal */ 476 hwaddr pte_addr; 477 478 if (two_stage && first_stage) { 479 int vbase_prot; 480 hwaddr vbase; 481 482 /* Do the second stage translation on the base PTE address. */ 483 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 484 base, NULL, MMU_DATA_LOAD, 485 mmu_idx, false, true, 486 is_debug); 487 488 if (vbase_ret != TRANSLATE_SUCCESS) { 489 if (fault_pte_addr) { 490 *fault_pte_addr = (base + idx * ptesize) >> 2; 491 } 492 return TRANSLATE_G_STAGE_FAIL; 493 } 494 495 pte_addr = vbase + idx * ptesize; 496 } else { 497 pte_addr = base + idx * ptesize; 498 } 499 500 int pmp_prot; 501 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 502 sizeof(target_ulong), 503 MMU_DATA_LOAD, PRV_S); 504 if (pmp_ret != TRANSLATE_SUCCESS) { 505 return TRANSLATE_PMP_FAIL; 506 } 507 508 target_ulong pte; 509 if (riscv_cpu_is_32bit(env)) { 510 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 511 } else { 512 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 513 } 514 515 if (res != MEMTX_OK) { 516 return TRANSLATE_FAIL; 517 } 518 519 hwaddr ppn = pte >> PTE_PPN_SHIFT; 520 521 if (!(pte & PTE_V)) { 522 /* Invalid PTE */ 523 return TRANSLATE_FAIL; 524 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 525 /* Inner PTE, continue walking */ 526 base = ppn << PGSHIFT; 527 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 528 /* Reserved leaf PTE flags: PTE_W */ 529 return TRANSLATE_FAIL; 530 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 531 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 532 return TRANSLATE_FAIL; 533 } else if ((pte & PTE_U) && ((mode != PRV_U) && 534 (!sum || access_type == MMU_INST_FETCH))) { 535 /* User PTE flags when not U mode and mstatus.SUM is not set, 536 or the access type is an instruction fetch */ 537 return TRANSLATE_FAIL; 538 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 539 /* Supervisor PTE flags when not S mode */ 540 return TRANSLATE_FAIL; 541 } else if (ppn & ((1ULL << ptshift) - 1)) { 542 /* Misaligned PPN */ 543 return TRANSLATE_FAIL; 544 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 545 ((pte & PTE_X) && mxr))) { 546 /* Read access check failed */ 547 return TRANSLATE_FAIL; 548 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 549 /* Write access check failed */ 550 return TRANSLATE_FAIL; 551 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 552 /* Fetch access check failed */ 553 return TRANSLATE_FAIL; 554 } else { 555 /* if necessary, set accessed and dirty bits. */ 556 target_ulong updated_pte = pte | PTE_A | 557 (access_type == MMU_DATA_STORE ? PTE_D : 0); 558 559 /* Page table updates need to be atomic with MTTCG enabled */ 560 if (updated_pte != pte) { 561 /* 562 * - if accessed or dirty bits need updating, and the PTE is 563 * in RAM, then we do so atomically with a compare and swap. 564 * - if the PTE is in IO space or ROM, then it can't be updated 565 * and we return TRANSLATE_FAIL. 566 * - if the PTE changed by the time we went to update it, then 567 * it is no longer valid and we must re-walk the page table. 568 */ 569 MemoryRegion *mr; 570 hwaddr l = sizeof(target_ulong), addr1; 571 mr = address_space_translate(cs->as, pte_addr, 572 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 573 if (memory_region_is_ram(mr)) { 574 target_ulong *pte_pa = 575 qemu_map_ram_ptr(mr->ram_block, addr1); 576 #if TCG_OVERSIZED_GUEST 577 /* MTTCG is not enabled on oversized TCG guests so 578 * page table updates do not need to be atomic */ 579 *pte_pa = pte = updated_pte; 580 #else 581 target_ulong old_pte = 582 qatomic_cmpxchg(pte_pa, pte, updated_pte); 583 if (old_pte != pte) { 584 goto restart; 585 } else { 586 pte = updated_pte; 587 } 588 #endif 589 } else { 590 /* misconfigured PTE in ROM (AD bits are not preset) or 591 * PTE is in IO space and can't be updated atomically */ 592 return TRANSLATE_FAIL; 593 } 594 } 595 596 /* for superpage mappings, make a fake leaf PTE for the TLB's 597 benefit. */ 598 target_ulong vpn = addr >> PGSHIFT; 599 *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | 600 (addr & ~TARGET_PAGE_MASK); 601 602 /* set permissions on the TLB entry */ 603 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 604 *prot |= PAGE_READ; 605 } 606 if ((pte & PTE_X)) { 607 *prot |= PAGE_EXEC; 608 } 609 /* add write permission on stores or if the page is already dirty, 610 so that we TLB miss on later writes to update the dirty bit */ 611 if ((pte & PTE_W) && 612 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 613 *prot |= PAGE_WRITE; 614 } 615 return TRANSLATE_SUCCESS; 616 } 617 } 618 return TRANSLATE_FAIL; 619 } 620 621 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 622 MMUAccessType access_type, bool pmp_violation, 623 bool first_stage, bool two_stage) 624 { 625 CPUState *cs = env_cpu(env); 626 int page_fault_exceptions, vm; 627 628 if (first_stage) { 629 vm = get_field(env->satp, SATP_MODE); 630 } else if (riscv_cpu_is_32bit(env)) { 631 vm = get_field(env->hgatp, SATP32_MODE); 632 } else { 633 vm = get_field(env->hgatp, SATP64_MODE); 634 } 635 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 636 637 switch (access_type) { 638 case MMU_INST_FETCH: 639 if (riscv_cpu_virt_enabled(env) && !first_stage) { 640 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 641 } else { 642 cs->exception_index = page_fault_exceptions ? 643 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 644 } 645 break; 646 case MMU_DATA_LOAD: 647 if (two_stage && !first_stage) { 648 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 649 } else { 650 cs->exception_index = page_fault_exceptions ? 651 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 652 } 653 break; 654 case MMU_DATA_STORE: 655 if (two_stage && !first_stage) { 656 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 657 } else { 658 cs->exception_index = page_fault_exceptions ? 659 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 660 } 661 break; 662 default: 663 g_assert_not_reached(); 664 } 665 env->badaddr = address; 666 env->two_stage_lookup = two_stage; 667 } 668 669 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 670 { 671 RISCVCPU *cpu = RISCV_CPU(cs); 672 CPURISCVState *env = &cpu->env; 673 hwaddr phys_addr; 674 int prot; 675 int mmu_idx = cpu_mmu_index(&cpu->env, false); 676 677 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 678 true, riscv_cpu_virt_enabled(env), true)) { 679 return -1; 680 } 681 682 if (riscv_cpu_virt_enabled(env)) { 683 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 684 0, mmu_idx, false, true, true)) { 685 return -1; 686 } 687 } 688 689 return phys_addr & TARGET_PAGE_MASK; 690 } 691 692 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 693 vaddr addr, unsigned size, 694 MMUAccessType access_type, 695 int mmu_idx, MemTxAttrs attrs, 696 MemTxResult response, uintptr_t retaddr) 697 { 698 RISCVCPU *cpu = RISCV_CPU(cs); 699 CPURISCVState *env = &cpu->env; 700 701 if (access_type == MMU_DATA_STORE) { 702 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 703 } else if (access_type == MMU_DATA_LOAD) { 704 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 705 } else { 706 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 707 } 708 709 env->badaddr = addr; 710 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 711 riscv_cpu_two_stage_lookup(mmu_idx); 712 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 713 } 714 715 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 716 MMUAccessType access_type, int mmu_idx, 717 uintptr_t retaddr) 718 { 719 RISCVCPU *cpu = RISCV_CPU(cs); 720 CPURISCVState *env = &cpu->env; 721 switch (access_type) { 722 case MMU_INST_FETCH: 723 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 724 break; 725 case MMU_DATA_LOAD: 726 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 727 break; 728 case MMU_DATA_STORE: 729 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 730 break; 731 default: 732 g_assert_not_reached(); 733 } 734 env->badaddr = addr; 735 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 736 riscv_cpu_two_stage_lookup(mmu_idx); 737 riscv_raise_exception(env, cs->exception_index, retaddr); 738 } 739 #endif /* !CONFIG_USER_ONLY */ 740 741 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 742 MMUAccessType access_type, int mmu_idx, 743 bool probe, uintptr_t retaddr) 744 { 745 RISCVCPU *cpu = RISCV_CPU(cs); 746 CPURISCVState *env = &cpu->env; 747 #ifndef CONFIG_USER_ONLY 748 vaddr im_address; 749 hwaddr pa = 0; 750 int prot, prot2, prot_pmp; 751 bool pmp_violation = false; 752 bool first_stage_error = true; 753 bool two_stage_lookup = false; 754 int ret = TRANSLATE_FAIL; 755 int mode = mmu_idx; 756 /* default TLB page size */ 757 target_ulong tlb_size = TARGET_PAGE_SIZE; 758 759 env->guest_phys_fault_addr = 0; 760 761 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 762 __func__, address, access_type, mmu_idx); 763 764 /* MPRV does not affect the virtual-machine load/store 765 instructions, HLV, HLVX, and HSV. */ 766 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 767 mode = get_field(env->hstatus, HSTATUS_SPVP); 768 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 769 get_field(env->mstatus, MSTATUS_MPRV)) { 770 mode = get_field(env->mstatus, MSTATUS_MPP); 771 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 772 two_stage_lookup = true; 773 } 774 } 775 776 if (riscv_cpu_virt_enabled(env) || 777 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 778 access_type != MMU_INST_FETCH)) { 779 /* Two stage lookup */ 780 ret = get_physical_address(env, &pa, &prot, address, 781 &env->guest_phys_fault_addr, access_type, 782 mmu_idx, true, true, false); 783 784 /* 785 * A G-stage exception may be triggered during two state lookup. 786 * And the env->guest_phys_fault_addr has already been set in 787 * get_physical_address(). 788 */ 789 if (ret == TRANSLATE_G_STAGE_FAIL) { 790 first_stage_error = false; 791 access_type = MMU_DATA_LOAD; 792 } 793 794 qemu_log_mask(CPU_LOG_MMU, 795 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 796 TARGET_FMT_plx " prot %d\n", 797 __func__, address, ret, pa, prot); 798 799 if (ret == TRANSLATE_SUCCESS) { 800 /* Second stage lookup */ 801 im_address = pa; 802 803 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 804 access_type, mmu_idx, false, true, 805 false); 806 807 qemu_log_mask(CPU_LOG_MMU, 808 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 809 TARGET_FMT_plx " prot %d\n", 810 __func__, im_address, ret, pa, prot2); 811 812 prot &= prot2; 813 814 if (ret == TRANSLATE_SUCCESS) { 815 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 816 size, access_type, mode); 817 818 qemu_log_mask(CPU_LOG_MMU, 819 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 820 " %d tlb_size " TARGET_FMT_lu "\n", 821 __func__, pa, ret, prot_pmp, tlb_size); 822 823 prot &= prot_pmp; 824 } 825 826 if (ret != TRANSLATE_SUCCESS) { 827 /* 828 * Guest physical address translation failed, this is a HS 829 * level exception 830 */ 831 first_stage_error = false; 832 env->guest_phys_fault_addr = (im_address | 833 (address & 834 (TARGET_PAGE_SIZE - 1))) >> 2; 835 } 836 } 837 } else { 838 /* Single stage lookup */ 839 ret = get_physical_address(env, &pa, &prot, address, NULL, 840 access_type, mmu_idx, true, false, false); 841 842 qemu_log_mask(CPU_LOG_MMU, 843 "%s address=%" VADDR_PRIx " ret %d physical " 844 TARGET_FMT_plx " prot %d\n", 845 __func__, address, ret, pa, prot); 846 847 if (ret == TRANSLATE_SUCCESS) { 848 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 849 size, access_type, mode); 850 851 qemu_log_mask(CPU_LOG_MMU, 852 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 853 " %d tlb_size " TARGET_FMT_lu "\n", 854 __func__, pa, ret, prot_pmp, tlb_size); 855 856 prot &= prot_pmp; 857 } 858 } 859 860 if (ret == TRANSLATE_PMP_FAIL) { 861 pmp_violation = true; 862 } 863 864 if (ret == TRANSLATE_SUCCESS) { 865 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 866 prot, mmu_idx, tlb_size); 867 return true; 868 } else if (probe) { 869 return false; 870 } else { 871 raise_mmu_exception(env, address, access_type, pmp_violation, 872 first_stage_error, 873 riscv_cpu_virt_enabled(env) || 874 riscv_cpu_two_stage_lookup(mmu_idx)); 875 riscv_raise_exception(env, cs->exception_index, retaddr); 876 } 877 878 return true; 879 880 #else 881 switch (access_type) { 882 case MMU_INST_FETCH: 883 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 884 break; 885 case MMU_DATA_LOAD: 886 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 887 break; 888 case MMU_DATA_STORE: 889 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 890 break; 891 default: 892 g_assert_not_reached(); 893 } 894 env->badaddr = address; 895 cpu_loop_exit_restore(cs, retaddr); 896 #endif 897 } 898 899 /* 900 * Handle Traps 901 * 902 * Adapted from Spike's processor_t::take_trap. 903 * 904 */ 905 void riscv_cpu_do_interrupt(CPUState *cs) 906 { 907 #if !defined(CONFIG_USER_ONLY) 908 909 RISCVCPU *cpu = RISCV_CPU(cs); 910 CPURISCVState *env = &cpu->env; 911 bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); 912 uint64_t s; 913 914 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 915 * so we mask off the MSB and separate into trap type and cause. 916 */ 917 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 918 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 919 target_ulong deleg = async ? env->mideleg : env->medeleg; 920 bool write_tval = false; 921 target_ulong tval = 0; 922 target_ulong htval = 0; 923 target_ulong mtval2 = 0; 924 925 if (cause == RISCV_EXCP_SEMIHOST) { 926 if (env->priv >= PRV_S) { 927 env->gpr[xA0] = do_common_semihosting(cs); 928 env->pc += 4; 929 return; 930 } 931 cause = RISCV_EXCP_BREAKPOINT; 932 } 933 934 if (!async) { 935 /* set tval to badaddr for traps with address information */ 936 switch (cause) { 937 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 938 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 939 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 940 force_hs_execp = true; 941 /* fallthrough */ 942 case RISCV_EXCP_INST_ADDR_MIS: 943 case RISCV_EXCP_INST_ACCESS_FAULT: 944 case RISCV_EXCP_LOAD_ADDR_MIS: 945 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 946 case RISCV_EXCP_LOAD_ACCESS_FAULT: 947 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 948 case RISCV_EXCP_INST_PAGE_FAULT: 949 case RISCV_EXCP_LOAD_PAGE_FAULT: 950 case RISCV_EXCP_STORE_PAGE_FAULT: 951 write_tval = true; 952 tval = env->badaddr; 953 break; 954 default: 955 break; 956 } 957 /* ecall is dispatched as one cause so translate based on mode */ 958 if (cause == RISCV_EXCP_U_ECALL) { 959 assert(env->priv <= 3); 960 961 if (env->priv == PRV_M) { 962 cause = RISCV_EXCP_M_ECALL; 963 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 964 cause = RISCV_EXCP_VS_ECALL; 965 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 966 cause = RISCV_EXCP_S_ECALL; 967 } else if (env->priv == PRV_U) { 968 cause = RISCV_EXCP_U_ECALL; 969 } 970 } 971 } 972 973 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 974 riscv_cpu_get_trap_name(cause, async)); 975 976 qemu_log_mask(CPU_LOG_INT, 977 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 978 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 979 __func__, env->mhartid, async, cause, env->pc, tval, 980 riscv_cpu_get_trap_name(cause, async)); 981 982 if (env->priv <= PRV_S && 983 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 984 /* handle the trap in S-mode */ 985 if (riscv_has_ext(env, RVH)) { 986 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 987 988 if (env->two_stage_lookup && write_tval) { 989 /* 990 * If we are writing a guest virtual address to stval, set 991 * this to 1. If we are trapping to VS we will set this to 0 992 * later. 993 */ 994 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); 995 } else { 996 /* For other HS-mode traps, we set this to 0. */ 997 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); 998 } 999 1000 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && 1001 !force_hs_execp) { 1002 /* Trap to VS mode */ 1003 /* 1004 * See if we need to adjust cause. Yes if its VS mode interrupt 1005 * no if hypervisor has delegated one of hs mode's interrupt 1006 */ 1007 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1008 cause == IRQ_VS_EXT) { 1009 cause = cause - 1; 1010 } 1011 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); 1012 } else if (riscv_cpu_virt_enabled(env)) { 1013 /* Trap into HS mode, from virt */ 1014 riscv_cpu_swap_hypervisor_regs(env); 1015 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1016 env->priv); 1017 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1018 riscv_cpu_virt_enabled(env)); 1019 1020 htval = env->guest_phys_fault_addr; 1021 1022 riscv_cpu_set_virt_enabled(env, 0); 1023 riscv_cpu_set_force_hs_excep(env, 0); 1024 } else { 1025 /* Trap into HS mode */ 1026 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1027 htval = env->guest_phys_fault_addr; 1028 } 1029 } 1030 1031 s = env->mstatus; 1032 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1033 s = set_field(s, MSTATUS_SPP, env->priv); 1034 s = set_field(s, MSTATUS_SIE, 0); 1035 env->mstatus = s; 1036 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1037 env->sepc = env->pc; 1038 env->stval = tval; 1039 env->htval = htval; 1040 env->pc = (env->stvec >> 2 << 2) + 1041 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1042 riscv_cpu_set_mode(env, PRV_S); 1043 } else { 1044 /* handle the trap in M-mode */ 1045 if (riscv_has_ext(env, RVH)) { 1046 if (riscv_cpu_virt_enabled(env)) { 1047 riscv_cpu_swap_hypervisor_regs(env); 1048 } 1049 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1050 riscv_cpu_virt_enabled(env)); 1051 if (riscv_cpu_virt_enabled(env) && tval) { 1052 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1053 } 1054 1055 mtval2 = env->guest_phys_fault_addr; 1056 1057 /* Trapping to M mode, virt is disabled */ 1058 riscv_cpu_set_virt_enabled(env, 0); 1059 riscv_cpu_set_force_hs_excep(env, 0); 1060 } 1061 1062 s = env->mstatus; 1063 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1064 s = set_field(s, MSTATUS_MPP, env->priv); 1065 s = set_field(s, MSTATUS_MIE, 0); 1066 env->mstatus = s; 1067 env->mcause = cause | ~(((target_ulong)-1) >> async); 1068 env->mepc = env->pc; 1069 env->mtval = tval; 1070 env->mtval2 = mtval2; 1071 env->pc = (env->mtvec >> 2 << 2) + 1072 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1073 riscv_cpu_set_mode(env, PRV_M); 1074 } 1075 1076 /* NOTE: it is not necessary to yield load reservations here. It is only 1077 * necessary for an SC from "another hart" to cause a load reservation 1078 * to be yielded. Refer to the memory consistency model section of the 1079 * RISC-V ISA Specification. 1080 */ 1081 1082 env->two_stage_lookup = false; 1083 #endif 1084 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1085 } 1086