1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 29 { 30 #ifdef CONFIG_USER_ONLY 31 return 0; 32 #else 33 return env->priv; 34 #endif 35 } 36 37 #ifndef CONFIG_USER_ONLY 38 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 39 { 40 target_ulong irqs; 41 42 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 43 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 44 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 45 46 target_ulong pending = env->mip & env->mie & 47 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 48 target_ulong vspending = (env->mip & env->mie & 49 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); 50 51 target_ulong mie = env->priv < PRV_M || 52 (env->priv == PRV_M && mstatus_mie); 53 target_ulong sie = env->priv < PRV_S || 54 (env->priv == PRV_S && mstatus_sie); 55 target_ulong hs_sie = env->priv < PRV_S || 56 (env->priv == PRV_S && hs_mstatus_sie); 57 58 if (riscv_cpu_virt_enabled(env)) { 59 target_ulong pending_hs_irq = pending & -hs_sie; 60 61 if (pending_hs_irq) { 62 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 63 return ctz64(pending_hs_irq); 64 } 65 66 pending = vspending; 67 } 68 69 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 70 71 if (irqs) { 72 return ctz64(irqs); /* since non-zero */ 73 } else { 74 return EXCP_NONE; /* indicates no pending interrupt */ 75 } 76 } 77 #endif 78 79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (interrupt_request & CPU_INTERRUPT_HARD) { 83 RISCVCPU *cpu = RISCV_CPU(cs); 84 CPURISCVState *env = &cpu->env; 85 int interruptno = riscv_cpu_local_irq_pending(env); 86 if (interruptno >= 0) { 87 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 88 riscv_cpu_do_interrupt(cs); 89 return true; 90 } 91 } 92 #endif 93 return false; 94 } 95 96 #if !defined(CONFIG_USER_ONLY) 97 98 /* Return true is floating point support is currently enabled */ 99 bool riscv_cpu_fp_enabled(CPURISCVState *env) 100 { 101 if (env->mstatus & MSTATUS_FS) { 102 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 103 return false; 104 } 105 return true; 106 } 107 108 return false; 109 } 110 111 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 112 { 113 target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 114 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; 115 bool current_virt = riscv_cpu_virt_enabled(env); 116 117 g_assert(riscv_has_ext(env, RVH)); 118 119 #if defined(TARGET_RISCV64) 120 mstatus_mask |= MSTATUS64_UXL; 121 #endif 122 123 if (current_virt) { 124 /* Current V=1 and we are about to change to V=0 */ 125 env->vsstatus = env->mstatus & mstatus_mask; 126 env->mstatus &= ~mstatus_mask; 127 env->mstatus |= env->mstatus_hs; 128 129 #if defined(TARGET_RISCV32) 130 env->vsstatush = env->mstatush; 131 env->mstatush |= env->mstatush_hs; 132 #endif 133 134 env->vstvec = env->stvec; 135 env->stvec = env->stvec_hs; 136 137 env->vsscratch = env->sscratch; 138 env->sscratch = env->sscratch_hs; 139 140 env->vsepc = env->sepc; 141 env->sepc = env->sepc_hs; 142 143 env->vscause = env->scause; 144 env->scause = env->scause_hs; 145 146 env->vstval = env->sbadaddr; 147 env->sbadaddr = env->stval_hs; 148 149 env->vsatp = env->satp; 150 env->satp = env->satp_hs; 151 } else { 152 /* Current V=0 and we are about to change to V=1 */ 153 env->mstatus_hs = env->mstatus & mstatus_mask; 154 env->mstatus &= ~mstatus_mask; 155 env->mstatus |= env->vsstatus; 156 157 #if defined(TARGET_RISCV32) 158 env->mstatush_hs = env->mstatush; 159 env->mstatush |= env->vsstatush; 160 #endif 161 162 env->stvec_hs = env->stvec; 163 env->stvec = env->vstvec; 164 165 env->sscratch_hs = env->sscratch; 166 env->sscratch = env->vsscratch; 167 168 env->sepc_hs = env->sepc; 169 env->sepc = env->vsepc; 170 171 env->scause_hs = env->scause; 172 env->scause = env->vscause; 173 174 env->stval_hs = env->sbadaddr; 175 env->sbadaddr = env->vstval; 176 177 env->satp_hs = env->satp; 178 env->satp = env->vsatp; 179 } 180 } 181 182 bool riscv_cpu_virt_enabled(CPURISCVState *env) 183 { 184 if (!riscv_has_ext(env, RVH)) { 185 return false; 186 } 187 188 return get_field(env->virt, VIRT_ONOFF); 189 } 190 191 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 192 { 193 if (!riscv_has_ext(env, RVH)) { 194 return; 195 } 196 197 /* Flush the TLB on all virt mode changes. */ 198 if (get_field(env->virt, VIRT_ONOFF) != enable) { 199 tlb_flush(env_cpu(env)); 200 } 201 202 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 203 } 204 205 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 206 { 207 if (!riscv_has_ext(env, RVH)) { 208 return false; 209 } 210 211 return get_field(env->virt, FORCE_HS_EXCEP); 212 } 213 214 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 215 { 216 if (!riscv_has_ext(env, RVH)) { 217 return; 218 } 219 220 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 221 } 222 223 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 224 { 225 CPURISCVState *env = &cpu->env; 226 if (env->miclaim & interrupts) { 227 return -1; 228 } else { 229 env->miclaim |= interrupts; 230 return 0; 231 } 232 } 233 234 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 235 { 236 CPURISCVState *env = &cpu->env; 237 CPUState *cs = CPU(cpu); 238 uint32_t old = env->mip; 239 bool locked = false; 240 241 if (!qemu_mutex_iothread_locked()) { 242 locked = true; 243 qemu_mutex_lock_iothread(); 244 } 245 246 env->mip = (env->mip & ~mask) | (value & mask); 247 248 if (env->mip) { 249 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 250 } else { 251 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 252 } 253 254 if (locked) { 255 qemu_mutex_unlock_iothread(); 256 } 257 258 return old; 259 } 260 261 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)) 262 { 263 env->rdtime_fn = fn; 264 } 265 266 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 267 { 268 if (newpriv > PRV_M) { 269 g_assert_not_reached(); 270 } 271 if (newpriv == PRV_H) { 272 newpriv = PRV_U; 273 } 274 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 275 env->priv = newpriv; 276 277 /* 278 * Clear the load reservation - otherwise a reservation placed in one 279 * context/process can be used by another, resulting in an SC succeeding 280 * incorrectly. Version 2.2 of the ISA specification explicitly requires 281 * this behaviour, while later revisions say that the kernel "should" use 282 * an SC instruction to force the yielding of a load reservation on a 283 * preemptive context switch. As a result, do both. 284 */ 285 env->load_res = -1; 286 } 287 288 /* get_physical_address - get the physical address for this virtual address 289 * 290 * Do a page table walk to obtain the physical address corresponding to a 291 * virtual address. Returns 0 if the translation was successful 292 * 293 * Adapted from Spike's mmu_t::translate and mmu_t::walk 294 * 295 * @env: CPURISCVState 296 * @physical: This will be set to the calculated physical address 297 * @prot: The returned protection attributes 298 * @addr: The virtual address to be translated 299 * @access_type: The type of MMU access 300 * @mmu_idx: Indicates current privilege level 301 * @first_stage: Are we in first stage translation? 302 * Second stage is used for hypervisor guest translation 303 * @two_stage: Are we going to perform two stage translation 304 */ 305 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 306 int *prot, target_ulong addr, 307 int access_type, int mmu_idx, 308 bool first_stage, bool two_stage) 309 { 310 /* NOTE: the env->pc value visible here will not be 311 * correct, but the value visible to the exception handler 312 * (riscv_cpu_do_interrupt) is correct */ 313 MemTxResult res; 314 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 315 int mode = mmu_idx; 316 bool use_background = false; 317 318 /* 319 * Check if we should use the background registers for the two 320 * stage translation. We don't need to check if we actually need 321 * two stage translation as that happened before this function 322 * was called. Background registers will be used if the guest has 323 * forced a two stage translation to be on (in HS or M mode). 324 */ 325 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 326 if (get_field(env->mstatus, MSTATUS_MPRV)) { 327 mode = get_field(env->mstatus, MSTATUS_MPP); 328 329 if (riscv_has_ext(env, RVH) && 330 MSTATUS_MPV_ISSET(env)) { 331 use_background = true; 332 } 333 } 334 } 335 336 if (mode == PRV_S && access_type != MMU_INST_FETCH && 337 riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { 338 if (get_field(env->hstatus, HSTATUS_SPRV)) { 339 mode = get_field(env->mstatus, SSTATUS_SPP); 340 use_background = true; 341 } 342 } 343 344 if (first_stage == false) { 345 /* We are in stage 2 translation, this is similar to stage 1. */ 346 /* Stage 2 is always taken as U-mode */ 347 mode = PRV_U; 348 } 349 350 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 351 *physical = addr; 352 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 353 return TRANSLATE_SUCCESS; 354 } 355 356 *prot = 0; 357 358 hwaddr base; 359 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 360 361 if (first_stage == true) { 362 mxr = get_field(env->mstatus, MSTATUS_MXR); 363 } else { 364 mxr = get_field(env->vsstatus, MSTATUS_MXR); 365 } 366 367 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 368 if (first_stage == true) { 369 if (use_background) { 370 base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; 371 vm = get_field(env->vsatp, SATP_MODE); 372 } else { 373 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 374 vm = get_field(env->satp, SATP_MODE); 375 } 376 widened = 0; 377 } else { 378 base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; 379 vm = get_field(env->hgatp, HGATP_MODE); 380 widened = 2; 381 } 382 sum = get_field(env->mstatus, MSTATUS_SUM); 383 switch (vm) { 384 case VM_1_10_SV32: 385 levels = 2; ptidxbits = 10; ptesize = 4; break; 386 case VM_1_10_SV39: 387 levels = 3; ptidxbits = 9; ptesize = 8; break; 388 case VM_1_10_SV48: 389 levels = 4; ptidxbits = 9; ptesize = 8; break; 390 case VM_1_10_SV57: 391 levels = 5; ptidxbits = 9; ptesize = 8; break; 392 case VM_1_10_MBARE: 393 *physical = addr; 394 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 395 return TRANSLATE_SUCCESS; 396 default: 397 g_assert_not_reached(); 398 } 399 } else { 400 widened = 0; 401 base = (hwaddr)(env->sptbr) << PGSHIFT; 402 sum = !get_field(env->mstatus, MSTATUS_PUM); 403 vm = get_field(env->mstatus, MSTATUS_VM); 404 switch (vm) { 405 case VM_1_09_SV32: 406 levels = 2; ptidxbits = 10; ptesize = 4; break; 407 case VM_1_09_SV39: 408 levels = 3; ptidxbits = 9; ptesize = 8; break; 409 case VM_1_09_SV48: 410 levels = 4; ptidxbits = 9; ptesize = 8; break; 411 case VM_1_09_MBARE: 412 *physical = addr; 413 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 414 return TRANSLATE_SUCCESS; 415 default: 416 g_assert_not_reached(); 417 } 418 } 419 420 CPUState *cs = env_cpu(env); 421 int va_bits = PGSHIFT + levels * ptidxbits + widened; 422 target_ulong mask, masked_msbs; 423 424 if (TARGET_LONG_BITS > (va_bits - 1)) { 425 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 426 } else { 427 mask = 0; 428 } 429 masked_msbs = (addr >> (va_bits - 1)) & mask; 430 431 if (masked_msbs != 0 && masked_msbs != mask) { 432 return TRANSLATE_FAIL; 433 } 434 435 int ptshift = (levels - 1) * ptidxbits; 436 int i; 437 438 #if !TCG_OVERSIZED_GUEST 439 restart: 440 #endif 441 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 442 target_ulong idx; 443 if (i == 0) { 444 idx = (addr >> (PGSHIFT + ptshift)) & 445 ((1 << (ptidxbits + widened)) - 1); 446 } else { 447 idx = (addr >> (PGSHIFT + ptshift)) & 448 ((1 << ptidxbits) - 1); 449 } 450 451 /* check that physical address of PTE is legal */ 452 hwaddr pte_addr; 453 454 if (two_stage && first_stage) { 455 int vbase_prot; 456 hwaddr vbase; 457 458 /* Do the second stage translation on the base PTE address. */ 459 get_physical_address(env, &vbase, &vbase_prot, base, access_type, 460 mmu_idx, false, true); 461 462 pte_addr = vbase + idx * ptesize; 463 } else { 464 pte_addr = base + idx * ptesize; 465 } 466 467 if (riscv_feature(env, RISCV_FEATURE_PMP) && 468 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), 469 1 << MMU_DATA_LOAD, PRV_S)) { 470 return TRANSLATE_PMP_FAIL; 471 } 472 473 #if defined(TARGET_RISCV32) 474 target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 475 #elif defined(TARGET_RISCV64) 476 target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 477 #endif 478 if (res != MEMTX_OK) { 479 return TRANSLATE_FAIL; 480 } 481 482 hwaddr ppn = pte >> PTE_PPN_SHIFT; 483 484 if (!(pte & PTE_V)) { 485 /* Invalid PTE */ 486 return TRANSLATE_FAIL; 487 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 488 /* Inner PTE, continue walking */ 489 base = ppn << PGSHIFT; 490 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 491 /* Reserved leaf PTE flags: PTE_W */ 492 return TRANSLATE_FAIL; 493 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 494 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 495 return TRANSLATE_FAIL; 496 } else if ((pte & PTE_U) && ((mode != PRV_U) && 497 (!sum || access_type == MMU_INST_FETCH))) { 498 /* User PTE flags when not U mode and mstatus.SUM is not set, 499 or the access type is an instruction fetch */ 500 return TRANSLATE_FAIL; 501 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 502 /* Supervisor PTE flags when not S mode */ 503 return TRANSLATE_FAIL; 504 } else if (ppn & ((1ULL << ptshift) - 1)) { 505 /* Misaligned PPN */ 506 return TRANSLATE_FAIL; 507 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 508 ((pte & PTE_X) && mxr))) { 509 /* Read access check failed */ 510 return TRANSLATE_FAIL; 511 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 512 /* Write access check failed */ 513 return TRANSLATE_FAIL; 514 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 515 /* Fetch access check failed */ 516 return TRANSLATE_FAIL; 517 } else { 518 /* if necessary, set accessed and dirty bits. */ 519 target_ulong updated_pte = pte | PTE_A | 520 (access_type == MMU_DATA_STORE ? PTE_D : 0); 521 522 /* Page table updates need to be atomic with MTTCG enabled */ 523 if (updated_pte != pte) { 524 /* 525 * - if accessed or dirty bits need updating, and the PTE is 526 * in RAM, then we do so atomically with a compare and swap. 527 * - if the PTE is in IO space or ROM, then it can't be updated 528 * and we return TRANSLATE_FAIL. 529 * - if the PTE changed by the time we went to update it, then 530 * it is no longer valid and we must re-walk the page table. 531 */ 532 MemoryRegion *mr; 533 hwaddr l = sizeof(target_ulong), addr1; 534 mr = address_space_translate(cs->as, pte_addr, 535 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 536 if (memory_region_is_ram(mr)) { 537 target_ulong *pte_pa = 538 qemu_map_ram_ptr(mr->ram_block, addr1); 539 #if TCG_OVERSIZED_GUEST 540 /* MTTCG is not enabled on oversized TCG guests so 541 * page table updates do not need to be atomic */ 542 *pte_pa = pte = updated_pte; 543 #else 544 target_ulong old_pte = 545 atomic_cmpxchg(pte_pa, pte, updated_pte); 546 if (old_pte != pte) { 547 goto restart; 548 } else { 549 pte = updated_pte; 550 } 551 #endif 552 } else { 553 /* misconfigured PTE in ROM (AD bits are not preset) or 554 * PTE is in IO space and can't be updated atomically */ 555 return TRANSLATE_FAIL; 556 } 557 } 558 559 /* for superpage mappings, make a fake leaf PTE for the TLB's 560 benefit. */ 561 target_ulong vpn = addr >> PGSHIFT; 562 if (i == 0) { 563 *physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) << 564 PGSHIFT; 565 } else { 566 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 567 } 568 569 /* set permissions on the TLB entry */ 570 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 571 *prot |= PAGE_READ; 572 } 573 if ((pte & PTE_X)) { 574 *prot |= PAGE_EXEC; 575 } 576 /* add write permission on stores or if the page is already dirty, 577 so that we TLB miss on later writes to update the dirty bit */ 578 if ((pte & PTE_W) && 579 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 580 *prot |= PAGE_WRITE; 581 } 582 return TRANSLATE_SUCCESS; 583 } 584 } 585 return TRANSLATE_FAIL; 586 } 587 588 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 589 MMUAccessType access_type, bool pmp_violation, 590 bool first_stage) 591 { 592 CPUState *cs = env_cpu(env); 593 int page_fault_exceptions; 594 if (first_stage) { 595 page_fault_exceptions = 596 (env->priv_ver >= PRIV_VERSION_1_10_0) && 597 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 598 !pmp_violation; 599 } else { 600 page_fault_exceptions = 601 get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE && 602 !pmp_violation; 603 } 604 switch (access_type) { 605 case MMU_INST_FETCH: 606 if (riscv_cpu_virt_enabled(env) && !first_stage) { 607 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 608 } else { 609 cs->exception_index = page_fault_exceptions ? 610 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 611 } 612 break; 613 case MMU_DATA_LOAD: 614 if (riscv_cpu_virt_enabled(env) && !first_stage) { 615 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 616 } else { 617 cs->exception_index = page_fault_exceptions ? 618 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 619 } 620 break; 621 case MMU_DATA_STORE: 622 if (riscv_cpu_virt_enabled(env) && !first_stage) { 623 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 624 } else { 625 cs->exception_index = page_fault_exceptions ? 626 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 627 } 628 break; 629 default: 630 g_assert_not_reached(); 631 } 632 env->badaddr = address; 633 } 634 635 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 636 { 637 RISCVCPU *cpu = RISCV_CPU(cs); 638 CPURISCVState *env = &cpu->env; 639 hwaddr phys_addr; 640 int prot; 641 int mmu_idx = cpu_mmu_index(&cpu->env, false); 642 643 if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, 644 true, riscv_cpu_virt_enabled(env))) { 645 return -1; 646 } 647 648 if (riscv_cpu_virt_enabled(env)) { 649 if (get_physical_address(env, &phys_addr, &prot, phys_addr, 650 0, mmu_idx, false, true)) { 651 return -1; 652 } 653 } 654 655 return phys_addr; 656 } 657 658 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 659 vaddr addr, unsigned size, 660 MMUAccessType access_type, 661 int mmu_idx, MemTxAttrs attrs, 662 MemTxResult response, uintptr_t retaddr) 663 { 664 RISCVCPU *cpu = RISCV_CPU(cs); 665 CPURISCVState *env = &cpu->env; 666 667 if (access_type == MMU_DATA_STORE) { 668 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 669 } else { 670 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 671 } 672 673 env->badaddr = addr; 674 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 675 } 676 677 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 678 MMUAccessType access_type, int mmu_idx, 679 uintptr_t retaddr) 680 { 681 RISCVCPU *cpu = RISCV_CPU(cs); 682 CPURISCVState *env = &cpu->env; 683 switch (access_type) { 684 case MMU_INST_FETCH: 685 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 686 break; 687 case MMU_DATA_LOAD: 688 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 689 break; 690 case MMU_DATA_STORE: 691 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 692 break; 693 default: 694 g_assert_not_reached(); 695 } 696 env->badaddr = addr; 697 riscv_raise_exception(env, cs->exception_index, retaddr); 698 } 699 #endif 700 701 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 702 MMUAccessType access_type, int mmu_idx, 703 bool probe, uintptr_t retaddr) 704 { 705 RISCVCPU *cpu = RISCV_CPU(cs); 706 CPURISCVState *env = &cpu->env; 707 #ifndef CONFIG_USER_ONLY 708 vaddr im_address; 709 hwaddr pa = 0; 710 int prot, prot2; 711 bool pmp_violation = false; 712 bool m_mode_two_stage = false; 713 bool hs_mode_two_stage = false; 714 bool first_stage_error = true; 715 int ret = TRANSLATE_FAIL; 716 int mode = mmu_idx; 717 718 env->guest_phys_fault_addr = 0; 719 720 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 721 __func__, address, access_type, mmu_idx); 722 723 /* 724 * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is 725 * set and we want to access a virtulisation address. 726 */ 727 if (riscv_has_ext(env, RVH)) { 728 m_mode_two_stage = env->priv == PRV_M && 729 access_type != MMU_INST_FETCH && 730 get_field(env->mstatus, MSTATUS_MPRV) && 731 MSTATUS_MPV_ISSET(env); 732 733 hs_mode_two_stage = env->priv == PRV_S && 734 !riscv_cpu_virt_enabled(env) && 735 access_type != MMU_INST_FETCH && 736 get_field(env->hstatus, HSTATUS_SPRV) && 737 get_field(env->hstatus, HSTATUS_SPV); 738 } 739 740 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 741 if (get_field(env->mstatus, MSTATUS_MPRV)) { 742 mode = get_field(env->mstatus, MSTATUS_MPP); 743 } 744 } 745 746 if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { 747 /* Two stage lookup */ 748 ret = get_physical_address(env, &pa, &prot, address, access_type, 749 mmu_idx, true, true); 750 751 qemu_log_mask(CPU_LOG_MMU, 752 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 753 TARGET_FMT_plx " prot %d\n", 754 __func__, address, ret, pa, prot); 755 756 if (ret != TRANSLATE_FAIL) { 757 /* Second stage lookup */ 758 im_address = pa; 759 760 ret = get_physical_address(env, &pa, &prot2, im_address, 761 access_type, mmu_idx, false, true); 762 763 qemu_log_mask(CPU_LOG_MMU, 764 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 765 TARGET_FMT_plx " prot %d\n", 766 __func__, im_address, ret, pa, prot2); 767 768 prot &= prot2; 769 770 if (riscv_feature(env, RISCV_FEATURE_PMP) && 771 (ret == TRANSLATE_SUCCESS) && 772 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 773 ret = TRANSLATE_PMP_FAIL; 774 } 775 776 if (ret != TRANSLATE_SUCCESS) { 777 /* 778 * Guest physical address translation failed, this is a HS 779 * level exception 780 */ 781 first_stage_error = false; 782 env->guest_phys_fault_addr = (im_address | 783 (address & 784 (TARGET_PAGE_SIZE - 1))) >> 2; 785 } 786 } 787 } else { 788 /* Single stage lookup */ 789 ret = get_physical_address(env, &pa, &prot, address, access_type, 790 mmu_idx, true, false); 791 792 qemu_log_mask(CPU_LOG_MMU, 793 "%s address=%" VADDR_PRIx " ret %d physical " 794 TARGET_FMT_plx " prot %d\n", 795 __func__, address, ret, pa, prot); 796 } 797 798 if (riscv_feature(env, RISCV_FEATURE_PMP) && 799 (ret == TRANSLATE_SUCCESS) && 800 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 801 ret = TRANSLATE_PMP_FAIL; 802 } 803 if (ret == TRANSLATE_PMP_FAIL) { 804 pmp_violation = true; 805 } 806 807 if (ret == TRANSLATE_SUCCESS) { 808 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 809 prot, mmu_idx, TARGET_PAGE_SIZE); 810 return true; 811 } else if (probe) { 812 return false; 813 } else { 814 raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error); 815 riscv_raise_exception(env, cs->exception_index, retaddr); 816 } 817 818 return true; 819 820 #else 821 switch (access_type) { 822 case MMU_INST_FETCH: 823 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 824 break; 825 case MMU_DATA_LOAD: 826 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 827 break; 828 case MMU_DATA_STORE: 829 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 830 break; 831 default: 832 g_assert_not_reached(); 833 } 834 env->badaddr = address; 835 cpu_loop_exit_restore(cs, retaddr); 836 #endif 837 } 838 839 /* 840 * Handle Traps 841 * 842 * Adapted from Spike's processor_t::take_trap. 843 * 844 */ 845 void riscv_cpu_do_interrupt(CPUState *cs) 846 { 847 #if !defined(CONFIG_USER_ONLY) 848 849 RISCVCPU *cpu = RISCV_CPU(cs); 850 CPURISCVState *env = &cpu->env; 851 bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); 852 target_ulong s; 853 854 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 855 * so we mask off the MSB and separate into trap type and cause. 856 */ 857 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 858 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 859 target_ulong deleg = async ? env->mideleg : env->medeleg; 860 target_ulong tval = 0; 861 target_ulong htval = 0; 862 target_ulong mtval2 = 0; 863 864 if (!async) { 865 /* set tval to badaddr for traps with address information */ 866 switch (cause) { 867 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 868 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 869 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 870 force_hs_execp = true; 871 /* fallthrough */ 872 case RISCV_EXCP_INST_ADDR_MIS: 873 case RISCV_EXCP_INST_ACCESS_FAULT: 874 case RISCV_EXCP_LOAD_ADDR_MIS: 875 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 876 case RISCV_EXCP_LOAD_ACCESS_FAULT: 877 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 878 case RISCV_EXCP_INST_PAGE_FAULT: 879 case RISCV_EXCP_LOAD_PAGE_FAULT: 880 case RISCV_EXCP_STORE_PAGE_FAULT: 881 tval = env->badaddr; 882 break; 883 default: 884 break; 885 } 886 /* ecall is dispatched as one cause so translate based on mode */ 887 if (cause == RISCV_EXCP_U_ECALL) { 888 assert(env->priv <= 3); 889 890 if (env->priv == PRV_M) { 891 cause = RISCV_EXCP_M_ECALL; 892 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 893 cause = RISCV_EXCP_VS_ECALL; 894 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 895 cause = RISCV_EXCP_S_ECALL; 896 } else if (env->priv == PRV_U) { 897 cause = RISCV_EXCP_U_ECALL; 898 } 899 } 900 } 901 902 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? 903 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 904 905 if (env->priv <= PRV_S && 906 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 907 /* handle the trap in S-mode */ 908 if (riscv_has_ext(env, RVH)) { 909 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 910 911 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && 912 !force_hs_execp) { 913 /* 914 * See if we need to adjust cause. Yes if its VS mode interrupt 915 * no if hypervisor has delegated one of hs mode's interrupt 916 */ 917 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 918 cause == IRQ_VS_EXT) 919 cause = cause - 1; 920 /* Trap to VS mode */ 921 } else if (riscv_cpu_virt_enabled(env)) { 922 /* Trap into HS mode, from virt */ 923 riscv_cpu_swap_hypervisor_regs(env); 924 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 925 get_field(env->hstatus, HSTATUS_SPV)); 926 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 927 get_field(env->mstatus, SSTATUS_SPP)); 928 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 929 riscv_cpu_virt_enabled(env)); 930 931 htval = env->guest_phys_fault_addr; 932 933 riscv_cpu_set_virt_enabled(env, 0); 934 riscv_cpu_set_force_hs_excep(env, 0); 935 } else { 936 /* Trap into HS mode */ 937 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 938 get_field(env->hstatus, HSTATUS_SPV)); 939 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 940 get_field(env->mstatus, SSTATUS_SPP)); 941 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 942 riscv_cpu_virt_enabled(env)); 943 944 htval = env->guest_phys_fault_addr; 945 } 946 } 947 948 s = env->mstatus; 949 s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 950 get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); 951 s = set_field(s, MSTATUS_SPP, env->priv); 952 s = set_field(s, MSTATUS_SIE, 0); 953 env->mstatus = s; 954 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 955 env->sepc = env->pc; 956 env->sbadaddr = tval; 957 env->htval = htval; 958 env->pc = (env->stvec >> 2 << 2) + 959 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 960 riscv_cpu_set_mode(env, PRV_S); 961 } else { 962 /* handle the trap in M-mode */ 963 if (riscv_has_ext(env, RVH)) { 964 if (riscv_cpu_virt_enabled(env)) { 965 riscv_cpu_swap_hypervisor_regs(env); 966 } 967 #ifdef TARGET_RISCV32 968 env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 969 riscv_cpu_virt_enabled(env)); 970 env->mstatush = set_field(env->mstatush, MSTATUS_MTL, 971 riscv_cpu_force_hs_excep_enabled(env)); 972 #else 973 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 974 riscv_cpu_virt_enabled(env)); 975 env->mstatus = set_field(env->mstatus, MSTATUS_MTL, 976 riscv_cpu_force_hs_excep_enabled(env)); 977 #endif 978 979 mtval2 = env->guest_phys_fault_addr; 980 981 /* Trapping to M mode, virt is disabled */ 982 riscv_cpu_set_virt_enabled(env, 0); 983 riscv_cpu_set_force_hs_excep(env, 0); 984 } 985 986 s = env->mstatus; 987 s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 988 get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); 989 s = set_field(s, MSTATUS_MPP, env->priv); 990 s = set_field(s, MSTATUS_MIE, 0); 991 env->mstatus = s; 992 env->mcause = cause | ~(((target_ulong)-1) >> async); 993 env->mepc = env->pc; 994 env->mbadaddr = tval; 995 env->mtval2 = mtval2; 996 env->pc = (env->mtvec >> 2 << 2) + 997 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 998 riscv_cpu_set_mode(env, PRV_M); 999 } 1000 1001 /* NOTE: it is not necessary to yield load reservations here. It is only 1002 * necessary for an SC from "another hart" to cause a load reservation 1003 * to be yielded. Refer to the memory consistency model section of the 1004 * RISC-V ISA Specification. 1005 */ 1006 1007 #endif 1008 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 1009 } 1010