1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 #include "semihosting/common-semi.h" 28 29 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 30 { 31 #ifdef CONFIG_USER_ONLY 32 return 0; 33 #else 34 return env->priv; 35 #endif 36 } 37 38 static RISCVMXL cpu_get_xl(CPURISCVState *env) 39 { 40 #if defined(TARGET_RISCV32) 41 return MXL_RV32; 42 #elif defined(CONFIG_USER_ONLY) 43 return MXL_RV64; 44 #else 45 RISCVMXL xl = riscv_cpu_mxl(env); 46 47 /* 48 * When emulating a 32-bit-only cpu, use RV32. 49 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 50 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 51 * back to RV64 for lower privs. 52 */ 53 if (xl != MXL_RV32) { 54 switch (env->priv) { 55 case PRV_M: 56 break; 57 case PRV_U: 58 xl = get_field(env->mstatus, MSTATUS64_UXL); 59 break; 60 default: /* PRV_S | PRV_H */ 61 xl = get_field(env->mstatus, MSTATUS64_SXL); 62 break; 63 } 64 } 65 return xl; 66 #endif 67 } 68 69 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 70 target_ulong *cs_base, uint32_t *pflags) 71 { 72 uint32_t flags = 0; 73 74 *pc = env->pc; 75 *cs_base = 0; 76 77 if (riscv_has_ext(env, RVV)) { 78 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 79 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 80 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 81 FIELD_EX64(env->vtype, VTYPE, VILL)); 82 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 83 FIELD_EX64(env->vtype, VTYPE, VSEW)); 84 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 85 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 86 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 87 } else { 88 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 89 } 90 91 #ifdef CONFIG_USER_ONLY 92 flags |= TB_FLAGS_MSTATUS_FS; 93 flags |= TB_FLAGS_MSTATUS_VS; 94 #else 95 flags |= cpu_mmu_index(env, 0); 96 if (riscv_cpu_fp_enabled(env)) { 97 flags |= env->mstatus & MSTATUS_FS; 98 } 99 100 if (riscv_cpu_vector_enabled(env)) { 101 flags |= env->mstatus & MSTATUS_VS; 102 } 103 104 if (riscv_has_ext(env, RVH)) { 105 if (env->priv == PRV_M || 106 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 107 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 108 get_field(env->hstatus, HSTATUS_HU))) { 109 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 110 } 111 112 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 113 get_field(env->mstatus_hs, MSTATUS_FS)); 114 115 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 116 get_field(env->mstatus_hs, MSTATUS_VS)); 117 } 118 if (riscv_has_ext(env, RVJ)) { 119 int priv = flags & TB_FLAGS_PRIV_MMU_MASK; 120 bool pm_enabled = false; 121 switch (priv) { 122 case PRV_U: 123 pm_enabled = env->mmte & U_PM_ENABLE; 124 break; 125 case PRV_S: 126 pm_enabled = env->mmte & S_PM_ENABLE; 127 break; 128 case PRV_M: 129 pm_enabled = env->mmte & M_PM_ENABLE; 130 break; 131 default: 132 g_assert_not_reached(); 133 } 134 flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); 135 } 136 #endif 137 138 flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); 139 140 *pflags = flags; 141 } 142 143 #ifndef CONFIG_USER_ONLY 144 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 145 { 146 target_ulong virt_enabled = riscv_cpu_virt_enabled(env); 147 148 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 149 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 150 151 target_ulong pending = env->mip & env->mie; 152 153 target_ulong mie = env->priv < PRV_M || 154 (env->priv == PRV_M && mstatus_mie); 155 target_ulong sie = env->priv < PRV_S || 156 (env->priv == PRV_S && mstatus_sie); 157 target_ulong hsie = virt_enabled || sie; 158 target_ulong vsie = virt_enabled && sie; 159 160 target_ulong irqs = 161 (pending & ~env->mideleg & -mie) | 162 (pending & env->mideleg & ~env->hideleg & -hsie) | 163 (pending & env->mideleg & env->hideleg & -vsie); 164 165 if (irqs) { 166 return ctz64(irqs); /* since non-zero */ 167 } else { 168 return RISCV_EXCP_NONE; /* indicates no pending interrupt */ 169 } 170 } 171 172 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 173 { 174 if (interrupt_request & CPU_INTERRUPT_HARD) { 175 RISCVCPU *cpu = RISCV_CPU(cs); 176 CPURISCVState *env = &cpu->env; 177 int interruptno = riscv_cpu_local_irq_pending(env); 178 if (interruptno >= 0) { 179 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 180 riscv_cpu_do_interrupt(cs); 181 return true; 182 } 183 } 184 return false; 185 } 186 187 /* Return true is floating point support is currently enabled */ 188 bool riscv_cpu_fp_enabled(CPURISCVState *env) 189 { 190 if (env->mstatus & MSTATUS_FS) { 191 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 192 return false; 193 } 194 return true; 195 } 196 197 return false; 198 } 199 200 /* Return true is vector support is currently enabled */ 201 bool riscv_cpu_vector_enabled(CPURISCVState *env) 202 { 203 if (env->mstatus & MSTATUS_VS) { 204 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 205 return false; 206 } 207 return true; 208 } 209 210 return false; 211 } 212 213 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 214 { 215 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 216 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 217 MSTATUS64_UXL | MSTATUS_VS; 218 bool current_virt = riscv_cpu_virt_enabled(env); 219 220 g_assert(riscv_has_ext(env, RVH)); 221 222 if (current_virt) { 223 /* Current V=1 and we are about to change to V=0 */ 224 env->vsstatus = env->mstatus & mstatus_mask; 225 env->mstatus &= ~mstatus_mask; 226 env->mstatus |= env->mstatus_hs; 227 228 env->vstvec = env->stvec; 229 env->stvec = env->stvec_hs; 230 231 env->vsscratch = env->sscratch; 232 env->sscratch = env->sscratch_hs; 233 234 env->vsepc = env->sepc; 235 env->sepc = env->sepc_hs; 236 237 env->vscause = env->scause; 238 env->scause = env->scause_hs; 239 240 env->vstval = env->stval; 241 env->stval = env->stval_hs; 242 243 env->vsatp = env->satp; 244 env->satp = env->satp_hs; 245 } else { 246 /* Current V=0 and we are about to change to V=1 */ 247 env->mstatus_hs = env->mstatus & mstatus_mask; 248 env->mstatus &= ~mstatus_mask; 249 env->mstatus |= env->vsstatus; 250 251 env->stvec_hs = env->stvec; 252 env->stvec = env->vstvec; 253 254 env->sscratch_hs = env->sscratch; 255 env->sscratch = env->vsscratch; 256 257 env->sepc_hs = env->sepc; 258 env->sepc = env->vsepc; 259 260 env->scause_hs = env->scause; 261 env->scause = env->vscause; 262 263 env->stval_hs = env->stval; 264 env->stval = env->vstval; 265 266 env->satp_hs = env->satp; 267 env->satp = env->vsatp; 268 } 269 } 270 271 bool riscv_cpu_virt_enabled(CPURISCVState *env) 272 { 273 if (!riscv_has_ext(env, RVH)) { 274 return false; 275 } 276 277 return get_field(env->virt, VIRT_ONOFF); 278 } 279 280 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 281 { 282 if (!riscv_has_ext(env, RVH)) { 283 return; 284 } 285 286 /* Flush the TLB on all virt mode changes. */ 287 if (get_field(env->virt, VIRT_ONOFF) != enable) { 288 tlb_flush(env_cpu(env)); 289 } 290 291 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 292 } 293 294 bool riscv_cpu_two_stage_lookup(int mmu_idx) 295 { 296 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 297 } 298 299 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 300 { 301 CPURISCVState *env = &cpu->env; 302 if (env->miclaim & interrupts) { 303 return -1; 304 } else { 305 env->miclaim |= interrupts; 306 return 0; 307 } 308 } 309 310 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 311 { 312 CPURISCVState *env = &cpu->env; 313 CPUState *cs = CPU(cpu); 314 uint32_t old = env->mip; 315 bool locked = false; 316 317 if (!qemu_mutex_iothread_locked()) { 318 locked = true; 319 qemu_mutex_lock_iothread(); 320 } 321 322 env->mip = (env->mip & ~mask) | (value & mask); 323 324 if (env->mip) { 325 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 326 } else { 327 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 328 } 329 330 if (locked) { 331 qemu_mutex_unlock_iothread(); 332 } 333 334 return old; 335 } 336 337 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 338 uint32_t arg) 339 { 340 env->rdtime_fn = fn; 341 env->rdtime_fn_arg = arg; 342 } 343 344 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 345 { 346 if (newpriv > PRV_M) { 347 g_assert_not_reached(); 348 } 349 if (newpriv == PRV_H) { 350 newpriv = PRV_U; 351 } 352 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 353 env->priv = newpriv; 354 355 /* 356 * Clear the load reservation - otherwise a reservation placed in one 357 * context/process can be used by another, resulting in an SC succeeding 358 * incorrectly. Version 2.2 of the ISA specification explicitly requires 359 * this behaviour, while later revisions say that the kernel "should" use 360 * an SC instruction to force the yielding of a load reservation on a 361 * preemptive context switch. As a result, do both. 362 */ 363 env->load_res = -1; 364 } 365 366 /* 367 * get_physical_address_pmp - check PMP permission for this physical address 368 * 369 * Match the PMP region and check permission for this physical address and it's 370 * TLB page. Returns 0 if the permission checking was successful 371 * 372 * @env: CPURISCVState 373 * @prot: The returned protection attributes 374 * @tlb_size: TLB page size containing addr. It could be modified after PMP 375 * permission checking. NULL if not set TLB page for addr. 376 * @addr: The physical address to be checked permission 377 * @access_type: The type of MMU access 378 * @mode: Indicates current privilege level. 379 */ 380 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 381 target_ulong *tlb_size, hwaddr addr, 382 int size, MMUAccessType access_type, 383 int mode) 384 { 385 pmp_priv_t pmp_priv; 386 target_ulong tlb_size_pmp = 0; 387 388 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 389 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 390 return TRANSLATE_SUCCESS; 391 } 392 393 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, 394 mode)) { 395 *prot = 0; 396 return TRANSLATE_PMP_FAIL; 397 } 398 399 *prot = pmp_priv_to_page_prot(pmp_priv); 400 if (tlb_size != NULL) { 401 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { 402 *tlb_size = tlb_size_pmp; 403 } 404 } 405 406 return TRANSLATE_SUCCESS; 407 } 408 409 /* get_physical_address - get the physical address for this virtual address 410 * 411 * Do a page table walk to obtain the physical address corresponding to a 412 * virtual address. Returns 0 if the translation was successful 413 * 414 * Adapted from Spike's mmu_t::translate and mmu_t::walk 415 * 416 * @env: CPURISCVState 417 * @physical: This will be set to the calculated physical address 418 * @prot: The returned protection attributes 419 * @addr: The virtual address to be translated 420 * @fault_pte_addr: If not NULL, this will be set to fault pte address 421 * when a error occurs on pte address translation. 422 * This will already be shifted to match htval. 423 * @access_type: The type of MMU access 424 * @mmu_idx: Indicates current privilege level 425 * @first_stage: Are we in first stage translation? 426 * Second stage is used for hypervisor guest translation 427 * @two_stage: Are we going to perform two stage translation 428 * @is_debug: Is this access from a debugger or the monitor? 429 */ 430 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 431 int *prot, target_ulong addr, 432 target_ulong *fault_pte_addr, 433 int access_type, int mmu_idx, 434 bool first_stage, bool two_stage, 435 bool is_debug) 436 { 437 /* NOTE: the env->pc value visible here will not be 438 * correct, but the value visible to the exception handler 439 * (riscv_cpu_do_interrupt) is correct */ 440 MemTxResult res; 441 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 442 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 443 bool use_background = false; 444 445 /* 446 * Check if we should use the background registers for the two 447 * stage translation. We don't need to check if we actually need 448 * two stage translation as that happened before this function 449 * was called. Background registers will be used if the guest has 450 * forced a two stage translation to be on (in HS or M mode). 451 */ 452 if (!riscv_cpu_virt_enabled(env) && two_stage) { 453 use_background = true; 454 } 455 456 /* MPRV does not affect the virtual-machine load/store 457 instructions, HLV, HLVX, and HSV. */ 458 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 459 mode = get_field(env->hstatus, HSTATUS_SPVP); 460 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 461 if (get_field(env->mstatus, MSTATUS_MPRV)) { 462 mode = get_field(env->mstatus, MSTATUS_MPP); 463 } 464 } 465 466 if (first_stage == false) { 467 /* We are in stage 2 translation, this is similar to stage 1. */ 468 /* Stage 2 is always taken as U-mode */ 469 mode = PRV_U; 470 } 471 472 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 473 *physical = addr; 474 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 475 return TRANSLATE_SUCCESS; 476 } 477 478 *prot = 0; 479 480 hwaddr base; 481 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 482 483 if (first_stage == true) { 484 mxr = get_field(env->mstatus, MSTATUS_MXR); 485 } else { 486 mxr = get_field(env->vsstatus, MSTATUS_MXR); 487 } 488 489 if (first_stage == true) { 490 if (use_background) { 491 if (riscv_cpu_mxl(env) == MXL_RV32) { 492 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 493 vm = get_field(env->vsatp, SATP32_MODE); 494 } else { 495 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 496 vm = get_field(env->vsatp, SATP64_MODE); 497 } 498 } else { 499 if (riscv_cpu_mxl(env) == MXL_RV32) { 500 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 501 vm = get_field(env->satp, SATP32_MODE); 502 } else { 503 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 504 vm = get_field(env->satp, SATP64_MODE); 505 } 506 } 507 widened = 0; 508 } else { 509 if (riscv_cpu_mxl(env) == MXL_RV32) { 510 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 511 vm = get_field(env->hgatp, SATP32_MODE); 512 } else { 513 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 514 vm = get_field(env->hgatp, SATP64_MODE); 515 } 516 widened = 2; 517 } 518 /* status.SUM will be ignored if execute on background */ 519 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 520 switch (vm) { 521 case VM_1_10_SV32: 522 levels = 2; ptidxbits = 10; ptesize = 4; break; 523 case VM_1_10_SV39: 524 levels = 3; ptidxbits = 9; ptesize = 8; break; 525 case VM_1_10_SV48: 526 levels = 4; ptidxbits = 9; ptesize = 8; break; 527 case VM_1_10_SV57: 528 levels = 5; ptidxbits = 9; ptesize = 8; break; 529 case VM_1_10_MBARE: 530 *physical = addr; 531 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 532 return TRANSLATE_SUCCESS; 533 default: 534 g_assert_not_reached(); 535 } 536 537 CPUState *cs = env_cpu(env); 538 int va_bits = PGSHIFT + levels * ptidxbits + widened; 539 target_ulong mask, masked_msbs; 540 541 if (TARGET_LONG_BITS > (va_bits - 1)) { 542 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 543 } else { 544 mask = 0; 545 } 546 masked_msbs = (addr >> (va_bits - 1)) & mask; 547 548 if (masked_msbs != 0 && masked_msbs != mask) { 549 return TRANSLATE_FAIL; 550 } 551 552 int ptshift = (levels - 1) * ptidxbits; 553 int i; 554 555 #if !TCG_OVERSIZED_GUEST 556 restart: 557 #endif 558 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 559 target_ulong idx; 560 if (i == 0) { 561 idx = (addr >> (PGSHIFT + ptshift)) & 562 ((1 << (ptidxbits + widened)) - 1); 563 } else { 564 idx = (addr >> (PGSHIFT + ptshift)) & 565 ((1 << ptidxbits) - 1); 566 } 567 568 /* check that physical address of PTE is legal */ 569 hwaddr pte_addr; 570 571 if (two_stage && first_stage) { 572 int vbase_prot; 573 hwaddr vbase; 574 575 /* Do the second stage translation on the base PTE address. */ 576 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 577 base, NULL, MMU_DATA_LOAD, 578 mmu_idx, false, true, 579 is_debug); 580 581 if (vbase_ret != TRANSLATE_SUCCESS) { 582 if (fault_pte_addr) { 583 *fault_pte_addr = (base + idx * ptesize) >> 2; 584 } 585 return TRANSLATE_G_STAGE_FAIL; 586 } 587 588 pte_addr = vbase + idx * ptesize; 589 } else { 590 pte_addr = base + idx * ptesize; 591 } 592 593 int pmp_prot; 594 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 595 sizeof(target_ulong), 596 MMU_DATA_LOAD, PRV_S); 597 if (pmp_ret != TRANSLATE_SUCCESS) { 598 return TRANSLATE_PMP_FAIL; 599 } 600 601 target_ulong pte; 602 if (riscv_cpu_mxl(env) == MXL_RV32) { 603 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 604 } else { 605 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 606 } 607 608 if (res != MEMTX_OK) { 609 return TRANSLATE_FAIL; 610 } 611 612 hwaddr ppn = pte >> PTE_PPN_SHIFT; 613 614 if (!(pte & PTE_V)) { 615 /* Invalid PTE */ 616 return TRANSLATE_FAIL; 617 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 618 /* Inner PTE, continue walking */ 619 base = ppn << PGSHIFT; 620 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 621 /* Reserved leaf PTE flags: PTE_W */ 622 return TRANSLATE_FAIL; 623 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 624 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 625 return TRANSLATE_FAIL; 626 } else if ((pte & PTE_U) && ((mode != PRV_U) && 627 (!sum || access_type == MMU_INST_FETCH))) { 628 /* User PTE flags when not U mode and mstatus.SUM is not set, 629 or the access type is an instruction fetch */ 630 return TRANSLATE_FAIL; 631 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 632 /* Supervisor PTE flags when not S mode */ 633 return TRANSLATE_FAIL; 634 } else if (ppn & ((1ULL << ptshift) - 1)) { 635 /* Misaligned PPN */ 636 return TRANSLATE_FAIL; 637 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 638 ((pte & PTE_X) && mxr))) { 639 /* Read access check failed */ 640 return TRANSLATE_FAIL; 641 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 642 /* Write access check failed */ 643 return TRANSLATE_FAIL; 644 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 645 /* Fetch access check failed */ 646 return TRANSLATE_FAIL; 647 } else { 648 /* if necessary, set accessed and dirty bits. */ 649 target_ulong updated_pte = pte | PTE_A | 650 (access_type == MMU_DATA_STORE ? PTE_D : 0); 651 652 /* Page table updates need to be atomic with MTTCG enabled */ 653 if (updated_pte != pte) { 654 /* 655 * - if accessed or dirty bits need updating, and the PTE is 656 * in RAM, then we do so atomically with a compare and swap. 657 * - if the PTE is in IO space or ROM, then it can't be updated 658 * and we return TRANSLATE_FAIL. 659 * - if the PTE changed by the time we went to update it, then 660 * it is no longer valid and we must re-walk the page table. 661 */ 662 MemoryRegion *mr; 663 hwaddr l = sizeof(target_ulong), addr1; 664 mr = address_space_translate(cs->as, pte_addr, 665 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 666 if (memory_region_is_ram(mr)) { 667 target_ulong *pte_pa = 668 qemu_map_ram_ptr(mr->ram_block, addr1); 669 #if TCG_OVERSIZED_GUEST 670 /* MTTCG is not enabled on oversized TCG guests so 671 * page table updates do not need to be atomic */ 672 *pte_pa = pte = updated_pte; 673 #else 674 target_ulong old_pte = 675 qatomic_cmpxchg(pte_pa, pte, updated_pte); 676 if (old_pte != pte) { 677 goto restart; 678 } else { 679 pte = updated_pte; 680 } 681 #endif 682 } else { 683 /* misconfigured PTE in ROM (AD bits are not preset) or 684 * PTE is in IO space and can't be updated atomically */ 685 return TRANSLATE_FAIL; 686 } 687 } 688 689 /* for superpage mappings, make a fake leaf PTE for the TLB's 690 benefit. */ 691 target_ulong vpn = addr >> PGSHIFT; 692 *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | 693 (addr & ~TARGET_PAGE_MASK); 694 695 /* set permissions on the TLB entry */ 696 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 697 *prot |= PAGE_READ; 698 } 699 if ((pte & PTE_X)) { 700 *prot |= PAGE_EXEC; 701 } 702 /* add write permission on stores or if the page is already dirty, 703 so that we TLB miss on later writes to update the dirty bit */ 704 if ((pte & PTE_W) && 705 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 706 *prot |= PAGE_WRITE; 707 } 708 return TRANSLATE_SUCCESS; 709 } 710 } 711 return TRANSLATE_FAIL; 712 } 713 714 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 715 MMUAccessType access_type, bool pmp_violation, 716 bool first_stage, bool two_stage) 717 { 718 CPUState *cs = env_cpu(env); 719 int page_fault_exceptions, vm; 720 uint64_t stap_mode; 721 722 if (riscv_cpu_mxl(env) == MXL_RV32) { 723 stap_mode = SATP32_MODE; 724 } else { 725 stap_mode = SATP64_MODE; 726 } 727 728 if (first_stage) { 729 vm = get_field(env->satp, stap_mode); 730 } else { 731 vm = get_field(env->hgatp, stap_mode); 732 } 733 734 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 735 736 switch (access_type) { 737 case MMU_INST_FETCH: 738 if (riscv_cpu_virt_enabled(env) && !first_stage) { 739 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 740 } else { 741 cs->exception_index = page_fault_exceptions ? 742 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 743 } 744 break; 745 case MMU_DATA_LOAD: 746 if (two_stage && !first_stage) { 747 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 748 } else { 749 cs->exception_index = page_fault_exceptions ? 750 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 751 } 752 break; 753 case MMU_DATA_STORE: 754 if (two_stage && !first_stage) { 755 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 756 } else { 757 cs->exception_index = page_fault_exceptions ? 758 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 759 } 760 break; 761 default: 762 g_assert_not_reached(); 763 } 764 env->badaddr = address; 765 env->two_stage_lookup = two_stage; 766 } 767 768 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 769 { 770 RISCVCPU *cpu = RISCV_CPU(cs); 771 CPURISCVState *env = &cpu->env; 772 hwaddr phys_addr; 773 int prot; 774 int mmu_idx = cpu_mmu_index(&cpu->env, false); 775 776 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 777 true, riscv_cpu_virt_enabled(env), true)) { 778 return -1; 779 } 780 781 if (riscv_cpu_virt_enabled(env)) { 782 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 783 0, mmu_idx, false, true, true)) { 784 return -1; 785 } 786 } 787 788 return phys_addr & TARGET_PAGE_MASK; 789 } 790 791 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 792 vaddr addr, unsigned size, 793 MMUAccessType access_type, 794 int mmu_idx, MemTxAttrs attrs, 795 MemTxResult response, uintptr_t retaddr) 796 { 797 RISCVCPU *cpu = RISCV_CPU(cs); 798 CPURISCVState *env = &cpu->env; 799 800 if (access_type == MMU_DATA_STORE) { 801 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 802 } else if (access_type == MMU_DATA_LOAD) { 803 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 804 } else { 805 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 806 } 807 808 env->badaddr = addr; 809 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 810 riscv_cpu_two_stage_lookup(mmu_idx); 811 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 812 } 813 814 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 815 MMUAccessType access_type, int mmu_idx, 816 uintptr_t retaddr) 817 { 818 RISCVCPU *cpu = RISCV_CPU(cs); 819 CPURISCVState *env = &cpu->env; 820 switch (access_type) { 821 case MMU_INST_FETCH: 822 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 823 break; 824 case MMU_DATA_LOAD: 825 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 826 break; 827 case MMU_DATA_STORE: 828 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 829 break; 830 default: 831 g_assert_not_reached(); 832 } 833 env->badaddr = addr; 834 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 835 riscv_cpu_two_stage_lookup(mmu_idx); 836 riscv_raise_exception(env, cs->exception_index, retaddr); 837 } 838 839 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 840 MMUAccessType access_type, int mmu_idx, 841 bool probe, uintptr_t retaddr) 842 { 843 RISCVCPU *cpu = RISCV_CPU(cs); 844 CPURISCVState *env = &cpu->env; 845 vaddr im_address; 846 hwaddr pa = 0; 847 int prot, prot2, prot_pmp; 848 bool pmp_violation = false; 849 bool first_stage_error = true; 850 bool two_stage_lookup = false; 851 int ret = TRANSLATE_FAIL; 852 int mode = mmu_idx; 853 /* default TLB page size */ 854 target_ulong tlb_size = TARGET_PAGE_SIZE; 855 856 env->guest_phys_fault_addr = 0; 857 858 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 859 __func__, address, access_type, mmu_idx); 860 861 /* MPRV does not affect the virtual-machine load/store 862 instructions, HLV, HLVX, and HSV. */ 863 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 864 mode = get_field(env->hstatus, HSTATUS_SPVP); 865 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 866 get_field(env->mstatus, MSTATUS_MPRV)) { 867 mode = get_field(env->mstatus, MSTATUS_MPP); 868 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 869 two_stage_lookup = true; 870 } 871 } 872 873 if (riscv_cpu_virt_enabled(env) || 874 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 875 access_type != MMU_INST_FETCH)) { 876 /* Two stage lookup */ 877 ret = get_physical_address(env, &pa, &prot, address, 878 &env->guest_phys_fault_addr, access_type, 879 mmu_idx, true, true, false); 880 881 /* 882 * A G-stage exception may be triggered during two state lookup. 883 * And the env->guest_phys_fault_addr has already been set in 884 * get_physical_address(). 885 */ 886 if (ret == TRANSLATE_G_STAGE_FAIL) { 887 first_stage_error = false; 888 access_type = MMU_DATA_LOAD; 889 } 890 891 qemu_log_mask(CPU_LOG_MMU, 892 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 893 TARGET_FMT_plx " prot %d\n", 894 __func__, address, ret, pa, prot); 895 896 if (ret == TRANSLATE_SUCCESS) { 897 /* Second stage lookup */ 898 im_address = pa; 899 900 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 901 access_type, mmu_idx, false, true, 902 false); 903 904 qemu_log_mask(CPU_LOG_MMU, 905 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 906 TARGET_FMT_plx " prot %d\n", 907 __func__, im_address, ret, pa, prot2); 908 909 prot &= prot2; 910 911 if (ret == TRANSLATE_SUCCESS) { 912 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 913 size, access_type, mode); 914 915 qemu_log_mask(CPU_LOG_MMU, 916 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 917 " %d tlb_size " TARGET_FMT_lu "\n", 918 __func__, pa, ret, prot_pmp, tlb_size); 919 920 prot &= prot_pmp; 921 } 922 923 if (ret != TRANSLATE_SUCCESS) { 924 /* 925 * Guest physical address translation failed, this is a HS 926 * level exception 927 */ 928 first_stage_error = false; 929 env->guest_phys_fault_addr = (im_address | 930 (address & 931 (TARGET_PAGE_SIZE - 1))) >> 2; 932 } 933 } 934 } else { 935 /* Single stage lookup */ 936 ret = get_physical_address(env, &pa, &prot, address, NULL, 937 access_type, mmu_idx, true, false, false); 938 939 qemu_log_mask(CPU_LOG_MMU, 940 "%s address=%" VADDR_PRIx " ret %d physical " 941 TARGET_FMT_plx " prot %d\n", 942 __func__, address, ret, pa, prot); 943 944 if (ret == TRANSLATE_SUCCESS) { 945 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 946 size, access_type, mode); 947 948 qemu_log_mask(CPU_LOG_MMU, 949 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 950 " %d tlb_size " TARGET_FMT_lu "\n", 951 __func__, pa, ret, prot_pmp, tlb_size); 952 953 prot &= prot_pmp; 954 } 955 } 956 957 if (ret == TRANSLATE_PMP_FAIL) { 958 pmp_violation = true; 959 } 960 961 if (ret == TRANSLATE_SUCCESS) { 962 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 963 prot, mmu_idx, tlb_size); 964 return true; 965 } else if (probe) { 966 return false; 967 } else { 968 raise_mmu_exception(env, address, access_type, pmp_violation, 969 first_stage_error, 970 riscv_cpu_virt_enabled(env) || 971 riscv_cpu_two_stage_lookup(mmu_idx)); 972 riscv_raise_exception(env, cs->exception_index, retaddr); 973 } 974 975 return true; 976 } 977 #endif /* !CONFIG_USER_ONLY */ 978 979 /* 980 * Handle Traps 981 * 982 * Adapted from Spike's processor_t::take_trap. 983 * 984 */ 985 void riscv_cpu_do_interrupt(CPUState *cs) 986 { 987 #if !defined(CONFIG_USER_ONLY) 988 989 RISCVCPU *cpu = RISCV_CPU(cs); 990 CPURISCVState *env = &cpu->env; 991 uint64_t s; 992 993 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 994 * so we mask off the MSB and separate into trap type and cause. 995 */ 996 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 997 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 998 target_ulong deleg = async ? env->mideleg : env->medeleg; 999 bool write_tval = false; 1000 target_ulong tval = 0; 1001 target_ulong htval = 0; 1002 target_ulong mtval2 = 0; 1003 1004 if (cause == RISCV_EXCP_SEMIHOST) { 1005 if (env->priv >= PRV_S) { 1006 env->gpr[xA0] = do_common_semihosting(cs); 1007 env->pc += 4; 1008 return; 1009 } 1010 cause = RISCV_EXCP_BREAKPOINT; 1011 } 1012 1013 if (!async) { 1014 /* set tval to badaddr for traps with address information */ 1015 switch (cause) { 1016 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1017 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1018 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1019 case RISCV_EXCP_INST_ADDR_MIS: 1020 case RISCV_EXCP_INST_ACCESS_FAULT: 1021 case RISCV_EXCP_LOAD_ADDR_MIS: 1022 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1023 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1024 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1025 case RISCV_EXCP_INST_PAGE_FAULT: 1026 case RISCV_EXCP_LOAD_PAGE_FAULT: 1027 case RISCV_EXCP_STORE_PAGE_FAULT: 1028 write_tval = true; 1029 tval = env->badaddr; 1030 break; 1031 default: 1032 break; 1033 } 1034 /* ecall is dispatched as one cause so translate based on mode */ 1035 if (cause == RISCV_EXCP_U_ECALL) { 1036 assert(env->priv <= 3); 1037 1038 if (env->priv == PRV_M) { 1039 cause = RISCV_EXCP_M_ECALL; 1040 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1041 cause = RISCV_EXCP_VS_ECALL; 1042 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1043 cause = RISCV_EXCP_S_ECALL; 1044 } else if (env->priv == PRV_U) { 1045 cause = RISCV_EXCP_U_ECALL; 1046 } 1047 } 1048 } 1049 1050 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1051 riscv_cpu_get_trap_name(cause, async)); 1052 1053 qemu_log_mask(CPU_LOG_INT, 1054 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1055 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1056 __func__, env->mhartid, async, cause, env->pc, tval, 1057 riscv_cpu_get_trap_name(cause, async)); 1058 1059 if (env->priv <= PRV_S && 1060 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1061 /* handle the trap in S-mode */ 1062 if (riscv_has_ext(env, RVH)) { 1063 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 1064 1065 if (env->two_stage_lookup && write_tval) { 1066 /* 1067 * If we are writing a guest virtual address to stval, set 1068 * this to 1. If we are trapping to VS we will set this to 0 1069 * later. 1070 */ 1071 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); 1072 } else { 1073 /* For other HS-mode traps, we set this to 0. */ 1074 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); 1075 } 1076 1077 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1078 /* Trap to VS mode */ 1079 /* 1080 * See if we need to adjust cause. Yes if its VS mode interrupt 1081 * no if hypervisor has delegated one of hs mode's interrupt 1082 */ 1083 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1084 cause == IRQ_VS_EXT) { 1085 cause = cause - 1; 1086 } 1087 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); 1088 } else if (riscv_cpu_virt_enabled(env)) { 1089 /* Trap into HS mode, from virt */ 1090 riscv_cpu_swap_hypervisor_regs(env); 1091 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1092 env->priv); 1093 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1094 riscv_cpu_virt_enabled(env)); 1095 1096 htval = env->guest_phys_fault_addr; 1097 1098 riscv_cpu_set_virt_enabled(env, 0); 1099 } else { 1100 /* Trap into HS mode */ 1101 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1102 htval = env->guest_phys_fault_addr; 1103 } 1104 } 1105 1106 s = env->mstatus; 1107 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1108 s = set_field(s, MSTATUS_SPP, env->priv); 1109 s = set_field(s, MSTATUS_SIE, 0); 1110 env->mstatus = s; 1111 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1112 env->sepc = env->pc; 1113 env->stval = tval; 1114 env->htval = htval; 1115 env->pc = (env->stvec >> 2 << 2) + 1116 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1117 riscv_cpu_set_mode(env, PRV_S); 1118 } else { 1119 /* handle the trap in M-mode */ 1120 if (riscv_has_ext(env, RVH)) { 1121 if (riscv_cpu_virt_enabled(env)) { 1122 riscv_cpu_swap_hypervisor_regs(env); 1123 } 1124 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1125 riscv_cpu_virt_enabled(env)); 1126 if (riscv_cpu_virt_enabled(env) && tval) { 1127 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1128 } 1129 1130 mtval2 = env->guest_phys_fault_addr; 1131 1132 /* Trapping to M mode, virt is disabled */ 1133 riscv_cpu_set_virt_enabled(env, 0); 1134 } 1135 1136 s = env->mstatus; 1137 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1138 s = set_field(s, MSTATUS_MPP, env->priv); 1139 s = set_field(s, MSTATUS_MIE, 0); 1140 env->mstatus = s; 1141 env->mcause = cause | ~(((target_ulong)-1) >> async); 1142 env->mepc = env->pc; 1143 env->mtval = tval; 1144 env->mtval2 = mtval2; 1145 env->pc = (env->mtvec >> 2 << 2) + 1146 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1147 riscv_cpu_set_mode(env, PRV_M); 1148 } 1149 1150 /* NOTE: it is not necessary to yield load reservations here. It is only 1151 * necessary for an SC from "another hart" to cause a load reservation 1152 * to be yielded. Refer to the memory consistency model section of the 1153 * RISC-V ISA Specification. 1154 */ 1155 1156 env->two_stage_lookup = false; 1157 #endif 1158 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1159 } 1160