1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 29 { 30 #ifdef CONFIG_USER_ONLY 31 return 0; 32 #else 33 return env->priv; 34 #endif 35 } 36 37 #ifndef CONFIG_USER_ONLY 38 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 39 { 40 target_ulong irqs; 41 42 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 43 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 44 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 45 46 target_ulong pending = env->mip & env->mie & 47 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 48 target_ulong vspending = (env->mip & env->mie & 49 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); 50 51 target_ulong mie = env->priv < PRV_M || 52 (env->priv == PRV_M && mstatus_mie); 53 target_ulong sie = env->priv < PRV_S || 54 (env->priv == PRV_S && mstatus_sie); 55 target_ulong hs_sie = env->priv < PRV_S || 56 (env->priv == PRV_S && hs_mstatus_sie); 57 58 if (riscv_cpu_virt_enabled(env)) { 59 target_ulong pending_hs_irq = pending & -hs_sie; 60 61 if (pending_hs_irq) { 62 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 63 return ctz64(pending_hs_irq); 64 } 65 66 pending = vspending; 67 } 68 69 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 70 71 if (irqs) { 72 return ctz64(irqs); /* since non-zero */ 73 } else { 74 return EXCP_NONE; /* indicates no pending interrupt */ 75 } 76 } 77 #endif 78 79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (interrupt_request & CPU_INTERRUPT_HARD) { 83 RISCVCPU *cpu = RISCV_CPU(cs); 84 CPURISCVState *env = &cpu->env; 85 int interruptno = riscv_cpu_local_irq_pending(env); 86 if (interruptno >= 0) { 87 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 88 riscv_cpu_do_interrupt(cs); 89 return true; 90 } 91 } 92 #endif 93 return false; 94 } 95 96 #if !defined(CONFIG_USER_ONLY) 97 98 /* Return true is floating point support is currently enabled */ 99 bool riscv_cpu_fp_enabled(CPURISCVState *env) 100 { 101 if (env->mstatus & MSTATUS_FS) { 102 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 103 return false; 104 } 105 return true; 106 } 107 108 return false; 109 } 110 111 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 112 { 113 target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 114 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; 115 bool current_virt = riscv_cpu_virt_enabled(env); 116 117 g_assert(riscv_has_ext(env, RVH)); 118 119 #if defined(TARGET_RISCV64) 120 mstatus_mask |= MSTATUS64_UXL; 121 #endif 122 123 if (current_virt) { 124 /* Current V=1 and we are about to change to V=0 */ 125 env->vsstatus = env->mstatus & mstatus_mask; 126 env->mstatus &= ~mstatus_mask; 127 env->mstatus |= env->mstatus_hs; 128 129 #if defined(TARGET_RISCV32) 130 env->vsstatush = env->mstatush; 131 env->mstatush |= env->mstatush_hs; 132 #endif 133 134 env->vstvec = env->stvec; 135 env->stvec = env->stvec_hs; 136 137 env->vsscratch = env->sscratch; 138 env->sscratch = env->sscratch_hs; 139 140 env->vsepc = env->sepc; 141 env->sepc = env->sepc_hs; 142 143 env->vscause = env->scause; 144 env->scause = env->scause_hs; 145 146 env->vstval = env->sbadaddr; 147 env->sbadaddr = env->stval_hs; 148 149 env->vsatp = env->satp; 150 env->satp = env->satp_hs; 151 } else { 152 /* Current V=0 and we are about to change to V=1 */ 153 env->mstatus_hs = env->mstatus & mstatus_mask; 154 env->mstatus &= ~mstatus_mask; 155 env->mstatus |= env->vsstatus; 156 157 #if defined(TARGET_RISCV32) 158 env->mstatush_hs = env->mstatush; 159 env->mstatush |= env->vsstatush; 160 #endif 161 162 env->stvec_hs = env->stvec; 163 env->stvec = env->vstvec; 164 165 env->sscratch_hs = env->sscratch; 166 env->sscratch = env->vsscratch; 167 168 env->sepc_hs = env->sepc; 169 env->sepc = env->vsepc; 170 171 env->scause_hs = env->scause; 172 env->scause = env->vscause; 173 174 env->stval_hs = env->sbadaddr; 175 env->sbadaddr = env->vstval; 176 177 env->satp_hs = env->satp; 178 env->satp = env->vsatp; 179 } 180 } 181 182 bool riscv_cpu_virt_enabled(CPURISCVState *env) 183 { 184 if (!riscv_has_ext(env, RVH)) { 185 return false; 186 } 187 188 return get_field(env->virt, VIRT_ONOFF); 189 } 190 191 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 192 { 193 if (!riscv_has_ext(env, RVH)) { 194 return; 195 } 196 197 /* Flush the TLB on all virt mode changes. */ 198 if (get_field(env->virt, VIRT_ONOFF) != enable) { 199 tlb_flush(env_cpu(env)); 200 } 201 202 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 203 } 204 205 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 206 { 207 if (!riscv_has_ext(env, RVH)) { 208 return false; 209 } 210 211 return get_field(env->virt, FORCE_HS_EXCEP); 212 } 213 214 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 215 { 216 if (!riscv_has_ext(env, RVH)) { 217 return; 218 } 219 220 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 221 } 222 223 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 224 { 225 CPURISCVState *env = &cpu->env; 226 if (env->miclaim & interrupts) { 227 return -1; 228 } else { 229 env->miclaim |= interrupts; 230 return 0; 231 } 232 } 233 234 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 235 { 236 CPURISCVState *env = &cpu->env; 237 CPUState *cs = CPU(cpu); 238 uint32_t old = env->mip; 239 bool locked = false; 240 241 if (!qemu_mutex_iothread_locked()) { 242 locked = true; 243 qemu_mutex_lock_iothread(); 244 } 245 246 env->mip = (env->mip & ~mask) | (value & mask); 247 248 if (env->mip) { 249 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 250 } else { 251 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 252 } 253 254 if (locked) { 255 qemu_mutex_unlock_iothread(); 256 } 257 258 return old; 259 } 260 261 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)) 262 { 263 env->rdtime_fn = fn; 264 } 265 266 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 267 { 268 if (newpriv > PRV_M) { 269 g_assert_not_reached(); 270 } 271 if (newpriv == PRV_H) { 272 newpriv = PRV_U; 273 } 274 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 275 env->priv = newpriv; 276 277 /* 278 * Clear the load reservation - otherwise a reservation placed in one 279 * context/process can be used by another, resulting in an SC succeeding 280 * incorrectly. Version 2.2 of the ISA specification explicitly requires 281 * this behaviour, while later revisions say that the kernel "should" use 282 * an SC instruction to force the yielding of a load reservation on a 283 * preemptive context switch. As a result, do both. 284 */ 285 env->load_res = -1; 286 } 287 288 /* get_physical_address - get the physical address for this virtual address 289 * 290 * Do a page table walk to obtain the physical address corresponding to a 291 * virtual address. Returns 0 if the translation was successful 292 * 293 * Adapted from Spike's mmu_t::translate and mmu_t::walk 294 * 295 * @env: CPURISCVState 296 * @physical: This will be set to the calculated physical address 297 * @prot: The returned protection attributes 298 * @addr: The virtual address to be translated 299 * @access_type: The type of MMU access 300 * @mmu_idx: Indicates current privilege level 301 * @first_stage: Are we in first stage translation? 302 * Second stage is used for hypervisor guest translation 303 * @two_stage: Are we going to perform two stage translation 304 */ 305 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 306 int *prot, target_ulong addr, 307 int access_type, int mmu_idx, 308 bool first_stage, bool two_stage) 309 { 310 /* NOTE: the env->pc value visible here will not be 311 * correct, but the value visible to the exception handler 312 * (riscv_cpu_do_interrupt) is correct */ 313 MemTxResult res; 314 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 315 int mode = mmu_idx; 316 bool use_background = false; 317 318 /* 319 * Check if we should use the background registers for the two 320 * stage translation. We don't need to check if we actually need 321 * two stage translation as that happened before this function 322 * was called. Background registers will be used if the guest has 323 * forced a two stage translation to be on (in HS or M mode). 324 */ 325 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 326 if (get_field(env->mstatus, MSTATUS_MPRV)) { 327 mode = get_field(env->mstatus, MSTATUS_MPP); 328 329 if (riscv_has_ext(env, RVH) && 330 MSTATUS_MPV_ISSET(env)) { 331 use_background = true; 332 } 333 } 334 } 335 336 if (mode == PRV_S && access_type != MMU_INST_FETCH && 337 riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { 338 if (get_field(env->hstatus, HSTATUS_SPRV)) { 339 mode = get_field(env->mstatus, SSTATUS_SPP); 340 use_background = true; 341 } 342 } 343 344 if (first_stage == false) { 345 /* We are in stage 2 translation, this is similar to stage 1. */ 346 /* Stage 2 is always taken as U-mode */ 347 mode = PRV_U; 348 } 349 350 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 351 *physical = addr; 352 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 353 return TRANSLATE_SUCCESS; 354 } 355 356 *prot = 0; 357 358 hwaddr base; 359 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 360 361 if (first_stage == true) { 362 mxr = get_field(env->mstatus, MSTATUS_MXR); 363 } else { 364 mxr = get_field(env->vsstatus, MSTATUS_MXR); 365 } 366 367 if (first_stage == true) { 368 if (use_background) { 369 base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; 370 vm = get_field(env->vsatp, SATP_MODE); 371 } else { 372 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 373 vm = get_field(env->satp, SATP_MODE); 374 } 375 widened = 0; 376 } else { 377 base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; 378 vm = get_field(env->hgatp, HGATP_MODE); 379 widened = 2; 380 } 381 sum = get_field(env->mstatus, MSTATUS_SUM); 382 switch (vm) { 383 case VM_1_10_SV32: 384 levels = 2; ptidxbits = 10; ptesize = 4; break; 385 case VM_1_10_SV39: 386 levels = 3; ptidxbits = 9; ptesize = 8; break; 387 case VM_1_10_SV48: 388 levels = 4; ptidxbits = 9; ptesize = 8; break; 389 case VM_1_10_SV57: 390 levels = 5; ptidxbits = 9; ptesize = 8; break; 391 case VM_1_10_MBARE: 392 *physical = addr; 393 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 394 return TRANSLATE_SUCCESS; 395 default: 396 g_assert_not_reached(); 397 } 398 399 CPUState *cs = env_cpu(env); 400 int va_bits = PGSHIFT + levels * ptidxbits + widened; 401 target_ulong mask, masked_msbs; 402 403 if (TARGET_LONG_BITS > (va_bits - 1)) { 404 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 405 } else { 406 mask = 0; 407 } 408 masked_msbs = (addr >> (va_bits - 1)) & mask; 409 410 if (masked_msbs != 0 && masked_msbs != mask) { 411 return TRANSLATE_FAIL; 412 } 413 414 int ptshift = (levels - 1) * ptidxbits; 415 int i; 416 417 #if !TCG_OVERSIZED_GUEST 418 restart: 419 #endif 420 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 421 target_ulong idx; 422 if (i == 0) { 423 idx = (addr >> (PGSHIFT + ptshift)) & 424 ((1 << (ptidxbits + widened)) - 1); 425 } else { 426 idx = (addr >> (PGSHIFT + ptshift)) & 427 ((1 << ptidxbits) - 1); 428 } 429 430 /* check that physical address of PTE is legal */ 431 hwaddr pte_addr; 432 433 if (two_stage && first_stage) { 434 int vbase_prot; 435 hwaddr vbase; 436 437 /* Do the second stage translation on the base PTE address. */ 438 get_physical_address(env, &vbase, &vbase_prot, base, access_type, 439 mmu_idx, false, true); 440 441 pte_addr = vbase + idx * ptesize; 442 } else { 443 pte_addr = base + idx * ptesize; 444 } 445 446 if (riscv_feature(env, RISCV_FEATURE_PMP) && 447 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), 448 1 << MMU_DATA_LOAD, PRV_S)) { 449 return TRANSLATE_PMP_FAIL; 450 } 451 452 #if defined(TARGET_RISCV32) 453 target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 454 #elif defined(TARGET_RISCV64) 455 target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 456 #endif 457 if (res != MEMTX_OK) { 458 return TRANSLATE_FAIL; 459 } 460 461 hwaddr ppn = pte >> PTE_PPN_SHIFT; 462 463 if (!(pte & PTE_V)) { 464 /* Invalid PTE */ 465 return TRANSLATE_FAIL; 466 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 467 /* Inner PTE, continue walking */ 468 base = ppn << PGSHIFT; 469 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 470 /* Reserved leaf PTE flags: PTE_W */ 471 return TRANSLATE_FAIL; 472 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 473 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 474 return TRANSLATE_FAIL; 475 } else if ((pte & PTE_U) && ((mode != PRV_U) && 476 (!sum || access_type == MMU_INST_FETCH))) { 477 /* User PTE flags when not U mode and mstatus.SUM is not set, 478 or the access type is an instruction fetch */ 479 return TRANSLATE_FAIL; 480 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 481 /* Supervisor PTE flags when not S mode */ 482 return TRANSLATE_FAIL; 483 } else if (ppn & ((1ULL << ptshift) - 1)) { 484 /* Misaligned PPN */ 485 return TRANSLATE_FAIL; 486 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 487 ((pte & PTE_X) && mxr))) { 488 /* Read access check failed */ 489 return TRANSLATE_FAIL; 490 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 491 /* Write access check failed */ 492 return TRANSLATE_FAIL; 493 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 494 /* Fetch access check failed */ 495 return TRANSLATE_FAIL; 496 } else { 497 /* if necessary, set accessed and dirty bits. */ 498 target_ulong updated_pte = pte | PTE_A | 499 (access_type == MMU_DATA_STORE ? PTE_D : 0); 500 501 /* Page table updates need to be atomic with MTTCG enabled */ 502 if (updated_pte != pte) { 503 /* 504 * - if accessed or dirty bits need updating, and the PTE is 505 * in RAM, then we do so atomically with a compare and swap. 506 * - if the PTE is in IO space or ROM, then it can't be updated 507 * and we return TRANSLATE_FAIL. 508 * - if the PTE changed by the time we went to update it, then 509 * it is no longer valid and we must re-walk the page table. 510 */ 511 MemoryRegion *mr; 512 hwaddr l = sizeof(target_ulong), addr1; 513 mr = address_space_translate(cs->as, pte_addr, 514 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 515 if (memory_region_is_ram(mr)) { 516 target_ulong *pte_pa = 517 qemu_map_ram_ptr(mr->ram_block, addr1); 518 #if TCG_OVERSIZED_GUEST 519 /* MTTCG is not enabled on oversized TCG guests so 520 * page table updates do not need to be atomic */ 521 *pte_pa = pte = updated_pte; 522 #else 523 target_ulong old_pte = 524 atomic_cmpxchg(pte_pa, pte, updated_pte); 525 if (old_pte != pte) { 526 goto restart; 527 } else { 528 pte = updated_pte; 529 } 530 #endif 531 } else { 532 /* misconfigured PTE in ROM (AD bits are not preset) or 533 * PTE is in IO space and can't be updated atomically */ 534 return TRANSLATE_FAIL; 535 } 536 } 537 538 /* for superpage mappings, make a fake leaf PTE for the TLB's 539 benefit. */ 540 target_ulong vpn = addr >> PGSHIFT; 541 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 542 543 /* set permissions on the TLB entry */ 544 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 545 *prot |= PAGE_READ; 546 } 547 if ((pte & PTE_X)) { 548 *prot |= PAGE_EXEC; 549 } 550 /* add write permission on stores or if the page is already dirty, 551 so that we TLB miss on later writes to update the dirty bit */ 552 if ((pte & PTE_W) && 553 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 554 *prot |= PAGE_WRITE; 555 } 556 return TRANSLATE_SUCCESS; 557 } 558 } 559 return TRANSLATE_FAIL; 560 } 561 562 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 563 MMUAccessType access_type, bool pmp_violation, 564 bool first_stage) 565 { 566 CPUState *cs = env_cpu(env); 567 int page_fault_exceptions; 568 if (first_stage) { 569 page_fault_exceptions = 570 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 571 !pmp_violation; 572 } else { 573 page_fault_exceptions = 574 get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE && 575 !pmp_violation; 576 } 577 switch (access_type) { 578 case MMU_INST_FETCH: 579 if (riscv_cpu_virt_enabled(env) && !first_stage) { 580 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 581 } else { 582 cs->exception_index = page_fault_exceptions ? 583 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 584 } 585 break; 586 case MMU_DATA_LOAD: 587 if (riscv_cpu_virt_enabled(env) && !first_stage) { 588 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 589 } else { 590 cs->exception_index = page_fault_exceptions ? 591 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 592 } 593 break; 594 case MMU_DATA_STORE: 595 if (riscv_cpu_virt_enabled(env) && !first_stage) { 596 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 597 } else { 598 cs->exception_index = page_fault_exceptions ? 599 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 600 } 601 break; 602 default: 603 g_assert_not_reached(); 604 } 605 env->badaddr = address; 606 } 607 608 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 609 { 610 RISCVCPU *cpu = RISCV_CPU(cs); 611 CPURISCVState *env = &cpu->env; 612 hwaddr phys_addr; 613 int prot; 614 int mmu_idx = cpu_mmu_index(&cpu->env, false); 615 616 if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, 617 true, riscv_cpu_virt_enabled(env))) { 618 return -1; 619 } 620 621 if (riscv_cpu_virt_enabled(env)) { 622 if (get_physical_address(env, &phys_addr, &prot, phys_addr, 623 0, mmu_idx, false, true)) { 624 return -1; 625 } 626 } 627 628 return phys_addr; 629 } 630 631 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 632 vaddr addr, unsigned size, 633 MMUAccessType access_type, 634 int mmu_idx, MemTxAttrs attrs, 635 MemTxResult response, uintptr_t retaddr) 636 { 637 RISCVCPU *cpu = RISCV_CPU(cs); 638 CPURISCVState *env = &cpu->env; 639 640 if (access_type == MMU_DATA_STORE) { 641 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 642 } else { 643 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 644 } 645 646 env->badaddr = addr; 647 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 648 } 649 650 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 651 MMUAccessType access_type, int mmu_idx, 652 uintptr_t retaddr) 653 { 654 RISCVCPU *cpu = RISCV_CPU(cs); 655 CPURISCVState *env = &cpu->env; 656 switch (access_type) { 657 case MMU_INST_FETCH: 658 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 659 break; 660 case MMU_DATA_LOAD: 661 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 662 break; 663 case MMU_DATA_STORE: 664 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 665 break; 666 default: 667 g_assert_not_reached(); 668 } 669 env->badaddr = addr; 670 riscv_raise_exception(env, cs->exception_index, retaddr); 671 } 672 #endif 673 674 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 675 MMUAccessType access_type, int mmu_idx, 676 bool probe, uintptr_t retaddr) 677 { 678 RISCVCPU *cpu = RISCV_CPU(cs); 679 CPURISCVState *env = &cpu->env; 680 #ifndef CONFIG_USER_ONLY 681 vaddr im_address; 682 hwaddr pa = 0; 683 int prot, prot2; 684 bool pmp_violation = false; 685 bool m_mode_two_stage = false; 686 bool hs_mode_two_stage = false; 687 bool first_stage_error = true; 688 int ret = TRANSLATE_FAIL; 689 int mode = mmu_idx; 690 691 env->guest_phys_fault_addr = 0; 692 693 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 694 __func__, address, access_type, mmu_idx); 695 696 /* 697 * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is 698 * set and we want to access a virtulisation address. 699 */ 700 if (riscv_has_ext(env, RVH)) { 701 m_mode_two_stage = env->priv == PRV_M && 702 access_type != MMU_INST_FETCH && 703 get_field(env->mstatus, MSTATUS_MPRV) && 704 MSTATUS_MPV_ISSET(env); 705 706 hs_mode_two_stage = env->priv == PRV_S && 707 !riscv_cpu_virt_enabled(env) && 708 access_type != MMU_INST_FETCH && 709 get_field(env->hstatus, HSTATUS_SPRV) && 710 get_field(env->hstatus, HSTATUS_SPV); 711 } 712 713 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 714 if (get_field(env->mstatus, MSTATUS_MPRV)) { 715 mode = get_field(env->mstatus, MSTATUS_MPP); 716 } 717 } 718 719 if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { 720 /* Two stage lookup */ 721 ret = get_physical_address(env, &pa, &prot, address, access_type, 722 mmu_idx, true, true); 723 724 qemu_log_mask(CPU_LOG_MMU, 725 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 726 TARGET_FMT_plx " prot %d\n", 727 __func__, address, ret, pa, prot); 728 729 if (ret != TRANSLATE_FAIL) { 730 /* Second stage lookup */ 731 im_address = pa; 732 733 ret = get_physical_address(env, &pa, &prot2, im_address, 734 access_type, mmu_idx, false, true); 735 736 qemu_log_mask(CPU_LOG_MMU, 737 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 738 TARGET_FMT_plx " prot %d\n", 739 __func__, im_address, ret, pa, prot2); 740 741 prot &= prot2; 742 743 if (riscv_feature(env, RISCV_FEATURE_PMP) && 744 (ret == TRANSLATE_SUCCESS) && 745 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 746 ret = TRANSLATE_PMP_FAIL; 747 } 748 749 if (ret != TRANSLATE_SUCCESS) { 750 /* 751 * Guest physical address translation failed, this is a HS 752 * level exception 753 */ 754 first_stage_error = false; 755 env->guest_phys_fault_addr = (im_address | 756 (address & 757 (TARGET_PAGE_SIZE - 1))) >> 2; 758 } 759 } 760 } else { 761 /* Single stage lookup */ 762 ret = get_physical_address(env, &pa, &prot, address, access_type, 763 mmu_idx, true, false); 764 765 qemu_log_mask(CPU_LOG_MMU, 766 "%s address=%" VADDR_PRIx " ret %d physical " 767 TARGET_FMT_plx " prot %d\n", 768 __func__, address, ret, pa, prot); 769 } 770 771 if (riscv_feature(env, RISCV_FEATURE_PMP) && 772 (ret == TRANSLATE_SUCCESS) && 773 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 774 ret = TRANSLATE_PMP_FAIL; 775 } 776 if (ret == TRANSLATE_PMP_FAIL) { 777 pmp_violation = true; 778 } 779 780 if (ret == TRANSLATE_SUCCESS) { 781 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 782 prot, mmu_idx, TARGET_PAGE_SIZE); 783 return true; 784 } else if (probe) { 785 return false; 786 } else { 787 raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error); 788 riscv_raise_exception(env, cs->exception_index, retaddr); 789 } 790 791 return true; 792 793 #else 794 switch (access_type) { 795 case MMU_INST_FETCH: 796 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 797 break; 798 case MMU_DATA_LOAD: 799 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 800 break; 801 case MMU_DATA_STORE: 802 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 803 break; 804 default: 805 g_assert_not_reached(); 806 } 807 env->badaddr = address; 808 cpu_loop_exit_restore(cs, retaddr); 809 #endif 810 } 811 812 /* 813 * Handle Traps 814 * 815 * Adapted from Spike's processor_t::take_trap. 816 * 817 */ 818 void riscv_cpu_do_interrupt(CPUState *cs) 819 { 820 #if !defined(CONFIG_USER_ONLY) 821 822 RISCVCPU *cpu = RISCV_CPU(cs); 823 CPURISCVState *env = &cpu->env; 824 bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); 825 target_ulong s; 826 827 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 828 * so we mask off the MSB and separate into trap type and cause. 829 */ 830 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 831 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 832 target_ulong deleg = async ? env->mideleg : env->medeleg; 833 target_ulong tval = 0; 834 target_ulong htval = 0; 835 target_ulong mtval2 = 0; 836 837 if (!async) { 838 /* set tval to badaddr for traps with address information */ 839 switch (cause) { 840 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 841 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 842 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 843 force_hs_execp = true; 844 /* fallthrough */ 845 case RISCV_EXCP_INST_ADDR_MIS: 846 case RISCV_EXCP_INST_ACCESS_FAULT: 847 case RISCV_EXCP_LOAD_ADDR_MIS: 848 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 849 case RISCV_EXCP_LOAD_ACCESS_FAULT: 850 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 851 case RISCV_EXCP_INST_PAGE_FAULT: 852 case RISCV_EXCP_LOAD_PAGE_FAULT: 853 case RISCV_EXCP_STORE_PAGE_FAULT: 854 tval = env->badaddr; 855 break; 856 default: 857 break; 858 } 859 /* ecall is dispatched as one cause so translate based on mode */ 860 if (cause == RISCV_EXCP_U_ECALL) { 861 assert(env->priv <= 3); 862 863 if (env->priv == PRV_M) { 864 cause = RISCV_EXCP_M_ECALL; 865 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 866 cause = RISCV_EXCP_VS_ECALL; 867 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 868 cause = RISCV_EXCP_S_ECALL; 869 } else if (env->priv == PRV_U) { 870 cause = RISCV_EXCP_U_ECALL; 871 } 872 } 873 } 874 875 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? 876 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 877 878 if (env->priv <= PRV_S && 879 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 880 /* handle the trap in S-mode */ 881 if (riscv_has_ext(env, RVH)) { 882 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 883 884 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && 885 !force_hs_execp) { 886 /* 887 * See if we need to adjust cause. Yes if its VS mode interrupt 888 * no if hypervisor has delegated one of hs mode's interrupt 889 */ 890 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 891 cause == IRQ_VS_EXT) 892 cause = cause - 1; 893 /* Trap to VS mode */ 894 } else if (riscv_cpu_virt_enabled(env)) { 895 /* Trap into HS mode, from virt */ 896 riscv_cpu_swap_hypervisor_regs(env); 897 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 898 get_field(env->hstatus, HSTATUS_SPV)); 899 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 900 get_field(env->mstatus, SSTATUS_SPP)); 901 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 902 riscv_cpu_virt_enabled(env)); 903 904 htval = env->guest_phys_fault_addr; 905 906 riscv_cpu_set_virt_enabled(env, 0); 907 riscv_cpu_set_force_hs_excep(env, 0); 908 } else { 909 /* Trap into HS mode */ 910 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 911 get_field(env->hstatus, HSTATUS_SPV)); 912 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 913 get_field(env->mstatus, SSTATUS_SPP)); 914 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 915 riscv_cpu_virt_enabled(env)); 916 917 htval = env->guest_phys_fault_addr; 918 } 919 } 920 921 s = env->mstatus; 922 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 923 s = set_field(s, MSTATUS_SPP, env->priv); 924 s = set_field(s, MSTATUS_SIE, 0); 925 env->mstatus = s; 926 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 927 env->sepc = env->pc; 928 env->sbadaddr = tval; 929 env->htval = htval; 930 env->pc = (env->stvec >> 2 << 2) + 931 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 932 riscv_cpu_set_mode(env, PRV_S); 933 } else { 934 /* handle the trap in M-mode */ 935 if (riscv_has_ext(env, RVH)) { 936 if (riscv_cpu_virt_enabled(env)) { 937 riscv_cpu_swap_hypervisor_regs(env); 938 } 939 #ifdef TARGET_RISCV32 940 env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 941 riscv_cpu_virt_enabled(env)); 942 env->mstatush = set_field(env->mstatush, MSTATUS_MTL, 943 riscv_cpu_force_hs_excep_enabled(env)); 944 #else 945 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 946 riscv_cpu_virt_enabled(env)); 947 env->mstatus = set_field(env->mstatus, MSTATUS_MTL, 948 riscv_cpu_force_hs_excep_enabled(env)); 949 #endif 950 951 mtval2 = env->guest_phys_fault_addr; 952 953 /* Trapping to M mode, virt is disabled */ 954 riscv_cpu_set_virt_enabled(env, 0); 955 riscv_cpu_set_force_hs_excep(env, 0); 956 } 957 958 s = env->mstatus; 959 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 960 s = set_field(s, MSTATUS_MPP, env->priv); 961 s = set_field(s, MSTATUS_MIE, 0); 962 env->mstatus = s; 963 env->mcause = cause | ~(((target_ulong)-1) >> async); 964 env->mepc = env->pc; 965 env->mbadaddr = tval; 966 env->mtval2 = mtval2; 967 env->pc = (env->mtvec >> 2 << 2) + 968 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 969 riscv_cpu_set_mode(env, PRV_M); 970 } 971 972 /* NOTE: it is not necessary to yield load reservations here. It is only 973 * necessary for an SC from "another hart" to cause a load reservation 974 * to be yielded. Refer to the memory consistency model section of the 975 * RISC-V ISA Specification. 976 */ 977 978 #endif 979 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 980 } 981