1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "internals.h" 25 #include "pmu.h" 26 #include "exec/exec-all.h" 27 #include "instmap.h" 28 #include "tcg/tcg-op.h" 29 #include "trace.h" 30 #include "semihosting/common-semi.h" 31 #include "sysemu/cpu-timers.h" 32 #include "cpu_bits.h" 33 #include "debug.h" 34 #include "tcg/oversized-guest.h" 35 36 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 37 { 38 #ifdef CONFIG_USER_ONLY 39 return 0; 40 #else 41 bool virt = env->virt_enabled; 42 int mode = env->priv; 43 44 /* All priv -> mmu_idx mapping are here */ 45 if (!ifetch) { 46 uint64_t status = env->mstatus; 47 48 if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { 49 mode = get_field(env->mstatus, MSTATUS_MPP); 50 virt = get_field(env->mstatus, MSTATUS_MPV); 51 if (virt) { 52 status = env->vsstatus; 53 } 54 } 55 if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { 56 mode = MMUIdx_S_SUM; 57 } 58 } 59 60 return mode | (virt ? MMU_2STAGE_BIT : 0); 61 #endif 62 } 63 64 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 65 target_ulong *cs_base, uint32_t *pflags) 66 { 67 CPUState *cs = env_cpu(env); 68 RISCVCPU *cpu = RISCV_CPU(cs); 69 RISCVExtStatus fs, vs; 70 uint32_t flags = 0; 71 72 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 73 *cs_base = 0; 74 75 if (cpu->cfg.ext_zve32f) { 76 /* 77 * If env->vl equals to VLMAX, we can use generic vector operation 78 * expanders (GVEC) to accerlate the vector operations. 79 * However, as LMUL could be a fractional number. The maximum 80 * vector size can be operated might be less than 8 bytes, 81 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 82 * only when maxsz >= 8 bytes. 83 */ 84 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 85 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 86 uint32_t maxsz = vlmax << sew; 87 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 88 (maxsz >= 8); 89 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 90 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 91 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 92 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 93 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 94 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 95 FIELD_EX64(env->vtype, VTYPE, VTA)); 96 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 97 FIELD_EX64(env->vtype, VTYPE, VMA)); 98 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); 99 } else { 100 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 101 } 102 103 #ifdef CONFIG_USER_ONLY 104 fs = EXT_STATUS_DIRTY; 105 vs = EXT_STATUS_DIRTY; 106 #else 107 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); 108 109 flags |= cpu_mmu_index(env, 0); 110 fs = get_field(env->mstatus, MSTATUS_FS); 111 vs = get_field(env->mstatus, MSTATUS_VS); 112 113 if (env->virt_enabled) { 114 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); 115 /* 116 * Merge DISABLED and !DIRTY states using MIN. 117 * We will set both fields when dirtying. 118 */ 119 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); 120 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); 121 } 122 123 if (cpu->cfg.debug && !icount_enabled()) { 124 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 125 } 126 #endif 127 128 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); 129 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); 130 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 131 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 132 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 133 } 134 if (env->cur_pmbase != 0) { 135 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 136 } 137 138 *pflags = flags; 139 } 140 141 void riscv_cpu_update_mask(CPURISCVState *env) 142 { 143 target_ulong mask = -1, base = 0; 144 /* 145 * TODO: Current RVJ spec does not specify 146 * how the extension interacts with XLEN. 147 */ 148 #ifndef CONFIG_USER_ONLY 149 if (riscv_has_ext(env, RVJ)) { 150 switch (env->priv) { 151 case PRV_M: 152 if (env->mmte & M_PM_ENABLE) { 153 mask = env->mpmmask; 154 base = env->mpmbase; 155 } 156 break; 157 case PRV_S: 158 if (env->mmte & S_PM_ENABLE) { 159 mask = env->spmmask; 160 base = env->spmbase; 161 } 162 break; 163 case PRV_U: 164 if (env->mmte & U_PM_ENABLE) { 165 mask = env->upmmask; 166 base = env->upmbase; 167 } 168 break; 169 default: 170 g_assert_not_reached(); 171 } 172 } 173 #endif 174 if (env->xl == MXL_RV32) { 175 env->cur_pmmask = mask & UINT32_MAX; 176 env->cur_pmbase = base & UINT32_MAX; 177 } else { 178 env->cur_pmmask = mask; 179 env->cur_pmbase = base; 180 } 181 } 182 183 #ifndef CONFIG_USER_ONLY 184 185 /* 186 * The HS-mode is allowed to configure priority only for the 187 * following VS-mode local interrupts: 188 * 189 * 0 (Reserved interrupt, reads as zero) 190 * 1 Supervisor software interrupt 191 * 4 (Reserved interrupt, reads as zero) 192 * 5 Supervisor timer interrupt 193 * 8 (Reserved interrupt, reads as zero) 194 * 13 (Reserved interrupt) 195 * 14 " 196 * 15 " 197 * 16 " 198 * 17 " 199 * 18 " 200 * 19 " 201 * 20 " 202 * 21 " 203 * 22 " 204 * 23 " 205 */ 206 207 static const int hviprio_index2irq[] = { 208 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 209 static const int hviprio_index2rdzero[] = { 210 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 211 212 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 213 { 214 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 215 return -EINVAL; 216 } 217 218 if (out_irq) { 219 *out_irq = hviprio_index2irq[index]; 220 } 221 222 if (out_rdzero) { 223 *out_rdzero = hviprio_index2rdzero[index]; 224 } 225 226 return 0; 227 } 228 229 /* 230 * Default priorities of local interrupts are defined in the 231 * RISC-V Advanced Interrupt Architecture specification. 232 * 233 * ---------------------------------------------------------------- 234 * Default | 235 * Priority | Major Interrupt Numbers 236 * ---------------------------------------------------------------- 237 * Highest | 47, 23, 46, 45, 22, 44, 238 * | 43, 21, 42, 41, 20, 40 239 * | 240 * | 11 (0b), 3 (03), 7 (07) 241 * | 9 (09), 1 (01), 5 (05) 242 * | 12 (0c) 243 * | 10 (0a), 2 (02), 6 (06) 244 * | 245 * | 39, 19, 38, 37, 18, 36, 246 * Lowest | 35, 17, 34, 33, 16, 32 247 * ---------------------------------------------------------------- 248 */ 249 static const uint8_t default_iprio[64] = { 250 /* Custom interrupts 48 to 63 */ 251 [63] = IPRIO_MMAXIPRIO, 252 [62] = IPRIO_MMAXIPRIO, 253 [61] = IPRIO_MMAXIPRIO, 254 [60] = IPRIO_MMAXIPRIO, 255 [59] = IPRIO_MMAXIPRIO, 256 [58] = IPRIO_MMAXIPRIO, 257 [57] = IPRIO_MMAXIPRIO, 258 [56] = IPRIO_MMAXIPRIO, 259 [55] = IPRIO_MMAXIPRIO, 260 [54] = IPRIO_MMAXIPRIO, 261 [53] = IPRIO_MMAXIPRIO, 262 [52] = IPRIO_MMAXIPRIO, 263 [51] = IPRIO_MMAXIPRIO, 264 [50] = IPRIO_MMAXIPRIO, 265 [49] = IPRIO_MMAXIPRIO, 266 [48] = IPRIO_MMAXIPRIO, 267 268 /* Custom interrupts 24 to 31 */ 269 [31] = IPRIO_MMAXIPRIO, 270 [30] = IPRIO_MMAXIPRIO, 271 [29] = IPRIO_MMAXIPRIO, 272 [28] = IPRIO_MMAXIPRIO, 273 [27] = IPRIO_MMAXIPRIO, 274 [26] = IPRIO_MMAXIPRIO, 275 [25] = IPRIO_MMAXIPRIO, 276 [24] = IPRIO_MMAXIPRIO, 277 278 [47] = IPRIO_DEFAULT_UPPER, 279 [23] = IPRIO_DEFAULT_UPPER + 1, 280 [46] = IPRIO_DEFAULT_UPPER + 2, 281 [45] = IPRIO_DEFAULT_UPPER + 3, 282 [22] = IPRIO_DEFAULT_UPPER + 4, 283 [44] = IPRIO_DEFAULT_UPPER + 5, 284 285 [43] = IPRIO_DEFAULT_UPPER + 6, 286 [21] = IPRIO_DEFAULT_UPPER + 7, 287 [42] = IPRIO_DEFAULT_UPPER + 8, 288 [41] = IPRIO_DEFAULT_UPPER + 9, 289 [20] = IPRIO_DEFAULT_UPPER + 10, 290 [40] = IPRIO_DEFAULT_UPPER + 11, 291 292 [11] = IPRIO_DEFAULT_M, 293 [3] = IPRIO_DEFAULT_M + 1, 294 [7] = IPRIO_DEFAULT_M + 2, 295 296 [9] = IPRIO_DEFAULT_S, 297 [1] = IPRIO_DEFAULT_S + 1, 298 [5] = IPRIO_DEFAULT_S + 2, 299 300 [12] = IPRIO_DEFAULT_SGEXT, 301 302 [10] = IPRIO_DEFAULT_VS, 303 [2] = IPRIO_DEFAULT_VS + 1, 304 [6] = IPRIO_DEFAULT_VS + 2, 305 306 [39] = IPRIO_DEFAULT_LOWER, 307 [19] = IPRIO_DEFAULT_LOWER + 1, 308 [38] = IPRIO_DEFAULT_LOWER + 2, 309 [37] = IPRIO_DEFAULT_LOWER + 3, 310 [18] = IPRIO_DEFAULT_LOWER + 4, 311 [36] = IPRIO_DEFAULT_LOWER + 5, 312 313 [35] = IPRIO_DEFAULT_LOWER + 6, 314 [17] = IPRIO_DEFAULT_LOWER + 7, 315 [34] = IPRIO_DEFAULT_LOWER + 8, 316 [33] = IPRIO_DEFAULT_LOWER + 9, 317 [16] = IPRIO_DEFAULT_LOWER + 10, 318 [32] = IPRIO_DEFAULT_LOWER + 11, 319 }; 320 321 uint8_t riscv_cpu_default_priority(int irq) 322 { 323 if (irq < 0 || irq > 63) { 324 return IPRIO_MMAXIPRIO; 325 } 326 327 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 328 }; 329 330 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 331 int extirq, unsigned int extirq_def_prio, 332 uint64_t pending, uint8_t *iprio) 333 { 334 int irq, best_irq = RISCV_EXCP_NONE; 335 unsigned int prio, best_prio = UINT_MAX; 336 337 if (!pending) { 338 return RISCV_EXCP_NONE; 339 } 340 341 irq = ctz64(pending); 342 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 343 riscv_cpu_cfg(env)->ext_ssaia)) { 344 return irq; 345 } 346 347 pending = pending >> irq; 348 while (pending) { 349 prio = iprio[irq]; 350 if (!prio) { 351 if (irq == extirq) { 352 prio = extirq_def_prio; 353 } else { 354 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 355 1 : IPRIO_MMAXIPRIO; 356 } 357 } 358 if ((pending & 0x1) && (prio <= best_prio)) { 359 best_irq = irq; 360 best_prio = prio; 361 } 362 irq++; 363 pending = pending >> 1; 364 } 365 366 return best_irq; 367 } 368 369 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 370 { 371 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 372 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 373 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 374 375 return (env->mip | vsgein | vstip) & env->mie; 376 } 377 378 int riscv_cpu_mirq_pending(CPURISCVState *env) 379 { 380 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 381 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 382 383 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 384 irqs, env->miprio); 385 } 386 387 int riscv_cpu_sirq_pending(CPURISCVState *env) 388 { 389 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 390 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 391 392 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 393 irqs, env->siprio); 394 } 395 396 int riscv_cpu_vsirq_pending(CPURISCVState *env) 397 { 398 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 399 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 400 401 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 402 irqs >> 1, env->hviprio); 403 } 404 405 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 406 { 407 int virq; 408 uint64_t irqs, pending, mie, hsie, vsie; 409 410 /* Determine interrupt enable state of all privilege modes */ 411 if (env->virt_enabled) { 412 mie = 1; 413 hsie = 1; 414 vsie = (env->priv < PRV_S) || 415 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 416 } else { 417 mie = (env->priv < PRV_M) || 418 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 419 hsie = (env->priv < PRV_S) || 420 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 421 vsie = 0; 422 } 423 424 /* Determine all pending interrupts */ 425 pending = riscv_cpu_all_pending(env); 426 427 /* Check M-mode interrupts */ 428 irqs = pending & ~env->mideleg & -mie; 429 if (irqs) { 430 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 431 irqs, env->miprio); 432 } 433 434 /* Check HS-mode interrupts */ 435 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 436 if (irqs) { 437 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 438 irqs, env->siprio); 439 } 440 441 /* Check VS-mode interrupts */ 442 irqs = pending & env->mideleg & env->hideleg & -vsie; 443 if (irqs) { 444 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 445 irqs >> 1, env->hviprio); 446 return (virq <= 0) ? virq : virq + 1; 447 } 448 449 /* Indicate no pending interrupt */ 450 return RISCV_EXCP_NONE; 451 } 452 453 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 454 { 455 if (interrupt_request & CPU_INTERRUPT_HARD) { 456 RISCVCPU *cpu = RISCV_CPU(cs); 457 CPURISCVState *env = &cpu->env; 458 int interruptno = riscv_cpu_local_irq_pending(env); 459 if (interruptno >= 0) { 460 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 461 riscv_cpu_do_interrupt(cs); 462 return true; 463 } 464 } 465 return false; 466 } 467 468 /* Return true is floating point support is currently enabled */ 469 bool riscv_cpu_fp_enabled(CPURISCVState *env) 470 { 471 if (env->mstatus & MSTATUS_FS) { 472 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 473 return false; 474 } 475 return true; 476 } 477 478 return false; 479 } 480 481 /* Return true is vector support is currently enabled */ 482 bool riscv_cpu_vector_enabled(CPURISCVState *env) 483 { 484 if (env->mstatus & MSTATUS_VS) { 485 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 486 return false; 487 } 488 return true; 489 } 490 491 return false; 492 } 493 494 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 495 { 496 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 497 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 498 MSTATUS64_UXL | MSTATUS_VS; 499 500 if (riscv_has_ext(env, RVF)) { 501 mstatus_mask |= MSTATUS_FS; 502 } 503 bool current_virt = env->virt_enabled; 504 505 g_assert(riscv_has_ext(env, RVH)); 506 507 if (current_virt) { 508 /* Current V=1 and we are about to change to V=0 */ 509 env->vsstatus = env->mstatus & mstatus_mask; 510 env->mstatus &= ~mstatus_mask; 511 env->mstatus |= env->mstatus_hs; 512 513 env->vstvec = env->stvec; 514 env->stvec = env->stvec_hs; 515 516 env->vsscratch = env->sscratch; 517 env->sscratch = env->sscratch_hs; 518 519 env->vsepc = env->sepc; 520 env->sepc = env->sepc_hs; 521 522 env->vscause = env->scause; 523 env->scause = env->scause_hs; 524 525 env->vstval = env->stval; 526 env->stval = env->stval_hs; 527 528 env->vsatp = env->satp; 529 env->satp = env->satp_hs; 530 } else { 531 /* Current V=0 and we are about to change to V=1 */ 532 env->mstatus_hs = env->mstatus & mstatus_mask; 533 env->mstatus &= ~mstatus_mask; 534 env->mstatus |= env->vsstatus; 535 536 env->stvec_hs = env->stvec; 537 env->stvec = env->vstvec; 538 539 env->sscratch_hs = env->sscratch; 540 env->sscratch = env->vsscratch; 541 542 env->sepc_hs = env->sepc; 543 env->sepc = env->vsepc; 544 545 env->scause_hs = env->scause; 546 env->scause = env->vscause; 547 548 env->stval_hs = env->stval; 549 env->stval = env->vstval; 550 551 env->satp_hs = env->satp; 552 env->satp = env->vsatp; 553 } 554 } 555 556 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 557 { 558 if (!riscv_has_ext(env, RVH)) { 559 return 0; 560 } 561 562 return env->geilen; 563 } 564 565 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 566 { 567 if (!riscv_has_ext(env, RVH)) { 568 return; 569 } 570 571 if (geilen > (TARGET_LONG_BITS - 1)) { 572 return; 573 } 574 575 env->geilen = geilen; 576 } 577 578 /* This function can only be called to set virt when RVH is enabled */ 579 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 580 { 581 /* Flush the TLB on all virt mode changes. */ 582 if (env->virt_enabled != enable) { 583 tlb_flush(env_cpu(env)); 584 } 585 586 env->virt_enabled = enable; 587 588 if (enable) { 589 /* 590 * The guest external interrupts from an interrupt controller are 591 * delivered only when the Guest/VM is running (i.e. V=1). This means 592 * any guest external interrupt which is triggered while the Guest/VM 593 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 594 * with sluggish response to serial console input and other I/O events. 595 * 596 * To solve this, we check and inject interrupt after setting V=1. 597 */ 598 riscv_cpu_update_mip(env, 0, 0); 599 } 600 } 601 602 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 603 { 604 CPURISCVState *env = &cpu->env; 605 if (env->miclaim & interrupts) { 606 return -1; 607 } else { 608 env->miclaim |= interrupts; 609 return 0; 610 } 611 } 612 613 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 614 uint64_t value) 615 { 616 CPUState *cs = env_cpu(env); 617 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 618 619 if (env->virt_enabled) { 620 gein = get_field(env->hstatus, HSTATUS_VGEIN); 621 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 622 } 623 624 vstip = env->vstime_irq ? MIP_VSTIP : 0; 625 626 QEMU_IOTHREAD_LOCK_GUARD(); 627 628 env->mip = (env->mip & ~mask) | (value & mask); 629 630 if (env->mip | vsgein | vstip) { 631 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 632 } else { 633 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 634 } 635 636 return old; 637 } 638 639 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 640 void *arg) 641 { 642 env->rdtime_fn = fn; 643 env->rdtime_fn_arg = arg; 644 } 645 646 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 647 int (*rmw_fn)(void *arg, 648 target_ulong reg, 649 target_ulong *val, 650 target_ulong new_val, 651 target_ulong write_mask), 652 void *rmw_fn_arg) 653 { 654 if (priv <= PRV_M) { 655 env->aia_ireg_rmw_fn[priv] = rmw_fn; 656 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 657 } 658 } 659 660 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 661 { 662 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); 663 664 if (icount_enabled() && newpriv != env->priv) { 665 riscv_itrigger_update_priv(env); 666 } 667 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 668 env->priv = newpriv; 669 env->xl = cpu_recompute_xl(env); 670 riscv_cpu_update_mask(env); 671 672 /* 673 * Clear the load reservation - otherwise a reservation placed in one 674 * context/process can be used by another, resulting in an SC succeeding 675 * incorrectly. Version 2.2 of the ISA specification explicitly requires 676 * this behaviour, while later revisions say that the kernel "should" use 677 * an SC instruction to force the yielding of a load reservation on a 678 * preemptive context switch. As a result, do both. 679 */ 680 env->load_res = -1; 681 } 682 683 /* 684 * get_physical_address_pmp - check PMP permission for this physical address 685 * 686 * Match the PMP region and check permission for this physical address and it's 687 * TLB page. Returns 0 if the permission checking was successful 688 * 689 * @env: CPURISCVState 690 * @prot: The returned protection attributes 691 * @tlb_size: TLB page size containing addr. It could be modified after PMP 692 * permission checking. NULL if not set TLB page for addr. 693 * @addr: The physical address to be checked permission 694 * @access_type: The type of MMU access 695 * @mode: Indicates current privilege level. 696 */ 697 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 698 target_ulong *tlb_size, hwaddr addr, 699 int size, MMUAccessType access_type, 700 int mode) 701 { 702 pmp_priv_t pmp_priv; 703 int pmp_index = -1; 704 705 if (!riscv_cpu_cfg(env)->pmp) { 706 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 707 return TRANSLATE_SUCCESS; 708 } 709 710 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 711 &pmp_priv, mode); 712 if (pmp_index < 0) { 713 *prot = 0; 714 return TRANSLATE_PMP_FAIL; 715 } 716 717 *prot = pmp_priv_to_page_prot(pmp_priv); 718 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 719 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 720 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 721 722 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 723 } 724 725 return TRANSLATE_SUCCESS; 726 } 727 728 /* 729 * get_physical_address - get the physical address for this virtual address 730 * 731 * Do a page table walk to obtain the physical address corresponding to a 732 * virtual address. Returns 0 if the translation was successful 733 * 734 * Adapted from Spike's mmu_t::translate and mmu_t::walk 735 * 736 * @env: CPURISCVState 737 * @physical: This will be set to the calculated physical address 738 * @prot: The returned protection attributes 739 * @addr: The virtual address or guest physical address to be translated 740 * @fault_pte_addr: If not NULL, this will be set to fault pte address 741 * when a error occurs on pte address translation. 742 * This will already be shifted to match htval. 743 * @access_type: The type of MMU access 744 * @mmu_idx: Indicates current privilege level 745 * @first_stage: Are we in first stage translation? 746 * Second stage is used for hypervisor guest translation 747 * @two_stage: Are we going to perform two stage translation 748 * @is_debug: Is this access from a debugger or the monitor? 749 */ 750 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 751 int *ret_prot, vaddr addr, 752 target_ulong *fault_pte_addr, 753 int access_type, int mmu_idx, 754 bool first_stage, bool two_stage, 755 bool is_debug) 756 { 757 /* 758 * NOTE: the env->pc value visible here will not be 759 * correct, but the value visible to the exception handler 760 * (riscv_cpu_do_interrupt) is correct 761 */ 762 MemTxResult res; 763 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 764 int mode = mmuidx_priv(mmu_idx); 765 bool use_background = false; 766 hwaddr ppn; 767 int napot_bits = 0; 768 target_ulong napot_mask; 769 770 /* 771 * Check if we should use the background registers for the two 772 * stage translation. We don't need to check if we actually need 773 * two stage translation as that happened before this function 774 * was called. Background registers will be used if the guest has 775 * forced a two stage translation to be on (in HS or M mode). 776 */ 777 if (!env->virt_enabled && two_stage) { 778 use_background = true; 779 } 780 781 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 782 *physical = addr; 783 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 784 return TRANSLATE_SUCCESS; 785 } 786 787 *ret_prot = 0; 788 789 hwaddr base; 790 int levels, ptidxbits, ptesize, vm, widened; 791 792 if (first_stage == true) { 793 if (use_background) { 794 if (riscv_cpu_mxl(env) == MXL_RV32) { 795 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 796 vm = get_field(env->vsatp, SATP32_MODE); 797 } else { 798 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 799 vm = get_field(env->vsatp, SATP64_MODE); 800 } 801 } else { 802 if (riscv_cpu_mxl(env) == MXL_RV32) { 803 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 804 vm = get_field(env->satp, SATP32_MODE); 805 } else { 806 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 807 vm = get_field(env->satp, SATP64_MODE); 808 } 809 } 810 widened = 0; 811 } else { 812 if (riscv_cpu_mxl(env) == MXL_RV32) { 813 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 814 vm = get_field(env->hgatp, SATP32_MODE); 815 } else { 816 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 817 vm = get_field(env->hgatp, SATP64_MODE); 818 } 819 widened = 2; 820 } 821 822 switch (vm) { 823 case VM_1_10_SV32: 824 levels = 2; ptidxbits = 10; ptesize = 4; break; 825 case VM_1_10_SV39: 826 levels = 3; ptidxbits = 9; ptesize = 8; break; 827 case VM_1_10_SV48: 828 levels = 4; ptidxbits = 9; ptesize = 8; break; 829 case VM_1_10_SV57: 830 levels = 5; ptidxbits = 9; ptesize = 8; break; 831 case VM_1_10_MBARE: 832 *physical = addr; 833 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 834 return TRANSLATE_SUCCESS; 835 default: 836 g_assert_not_reached(); 837 } 838 839 CPUState *cs = env_cpu(env); 840 int va_bits = PGSHIFT + levels * ptidxbits + widened; 841 842 if (first_stage == true) { 843 target_ulong mask, masked_msbs; 844 845 if (TARGET_LONG_BITS > (va_bits - 1)) { 846 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 847 } else { 848 mask = 0; 849 } 850 masked_msbs = (addr >> (va_bits - 1)) & mask; 851 852 if (masked_msbs != 0 && masked_msbs != mask) { 853 return TRANSLATE_FAIL; 854 } 855 } else { 856 if (vm != VM_1_10_SV32 && addr >> va_bits != 0) { 857 return TRANSLATE_FAIL; 858 } 859 } 860 861 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 862 bool hade = env->menvcfg & MENVCFG_HADE; 863 864 if (first_stage && two_stage && env->virt_enabled) { 865 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 866 hade = hade && (env->henvcfg & HENVCFG_HADE); 867 } 868 869 int ptshift = (levels - 1) * ptidxbits; 870 target_ulong pte; 871 hwaddr pte_addr; 872 int i; 873 874 #if !TCG_OVERSIZED_GUEST 875 restart: 876 #endif 877 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 878 target_ulong idx; 879 if (i == 0) { 880 idx = (addr >> (PGSHIFT + ptshift)) & 881 ((1 << (ptidxbits + widened)) - 1); 882 } else { 883 idx = (addr >> (PGSHIFT + ptshift)) & 884 ((1 << ptidxbits) - 1); 885 } 886 887 /* check that physical address of PTE is legal */ 888 889 if (two_stage && first_stage) { 890 int vbase_prot; 891 hwaddr vbase; 892 893 /* Do the second stage translation on the base PTE address. */ 894 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 895 base, NULL, MMU_DATA_LOAD, 896 MMUIdx_U, false, true, 897 is_debug); 898 899 if (vbase_ret != TRANSLATE_SUCCESS) { 900 if (fault_pte_addr) { 901 *fault_pte_addr = (base + idx * ptesize) >> 2; 902 } 903 return TRANSLATE_G_STAGE_FAIL; 904 } 905 906 pte_addr = vbase + idx * ptesize; 907 } else { 908 pte_addr = base + idx * ptesize; 909 } 910 911 int pmp_prot; 912 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 913 sizeof(target_ulong), 914 MMU_DATA_LOAD, PRV_S); 915 if (pmp_ret != TRANSLATE_SUCCESS) { 916 return TRANSLATE_PMP_FAIL; 917 } 918 919 if (riscv_cpu_mxl(env) == MXL_RV32) { 920 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 921 } else { 922 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 923 } 924 925 if (res != MEMTX_OK) { 926 return TRANSLATE_FAIL; 927 } 928 929 if (riscv_cpu_sxl(env) == MXL_RV32) { 930 ppn = pte >> PTE_PPN_SHIFT; 931 } else { 932 if (pte & PTE_RESERVED) { 933 return TRANSLATE_FAIL; 934 } 935 936 if (!pbmte && (pte & PTE_PBMT)) { 937 return TRANSLATE_FAIL; 938 } 939 940 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 941 return TRANSLATE_FAIL; 942 } 943 944 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 945 } 946 947 if (!(pte & PTE_V)) { 948 /* Invalid PTE */ 949 return TRANSLATE_FAIL; 950 } 951 if (pte & (PTE_R | PTE_W | PTE_X)) { 952 goto leaf; 953 } 954 955 /* Inner PTE, continue walking */ 956 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 957 return TRANSLATE_FAIL; 958 } 959 base = ppn << PGSHIFT; 960 } 961 962 /* No leaf pte at any translation level. */ 963 return TRANSLATE_FAIL; 964 965 leaf: 966 if (ppn & ((1ULL << ptshift) - 1)) { 967 /* Misaligned PPN */ 968 return TRANSLATE_FAIL; 969 } 970 if (!pbmte && (pte & PTE_PBMT)) { 971 /* Reserved without Svpbmt. */ 972 return TRANSLATE_FAIL; 973 } 974 975 /* Check for reserved combinations of RWX flags. */ 976 switch (pte & (PTE_R | PTE_W | PTE_X)) { 977 case PTE_W: 978 case PTE_W | PTE_X: 979 return TRANSLATE_FAIL; 980 } 981 982 int prot = 0; 983 if (pte & PTE_R) { 984 prot |= PAGE_READ; 985 } 986 if (pte & PTE_W) { 987 prot |= PAGE_WRITE; 988 } 989 if (pte & PTE_X) { 990 bool mxr; 991 992 if (first_stage == true) { 993 mxr = get_field(env->mstatus, MSTATUS_MXR); 994 } else { 995 mxr = get_field(env->vsstatus, MSTATUS_MXR); 996 } 997 if (mxr) { 998 prot |= PAGE_READ; 999 } 1000 prot |= PAGE_EXEC; 1001 } 1002 1003 if (pte & PTE_U) { 1004 if (mode != PRV_U) { 1005 if (!mmuidx_sum(mmu_idx)) { 1006 return TRANSLATE_FAIL; 1007 } 1008 /* SUM allows only read+write, not execute. */ 1009 prot &= PAGE_READ | PAGE_WRITE; 1010 } 1011 } else if (mode != PRV_S) { 1012 /* Supervisor PTE flags when not S mode */ 1013 return TRANSLATE_FAIL; 1014 } 1015 1016 if (!((prot >> access_type) & 1)) { 1017 /* Access check failed */ 1018 return TRANSLATE_FAIL; 1019 } 1020 1021 /* If necessary, set accessed and dirty bits. */ 1022 target_ulong updated_pte = pte | PTE_A | 1023 (access_type == MMU_DATA_STORE ? PTE_D : 0); 1024 1025 /* Page table updates need to be atomic with MTTCG enabled */ 1026 if (updated_pte != pte && !is_debug) { 1027 if (!hade) { 1028 return TRANSLATE_FAIL; 1029 } 1030 1031 /* 1032 * - if accessed or dirty bits need updating, and the PTE is 1033 * in RAM, then we do so atomically with a compare and swap. 1034 * - if the PTE is in IO space or ROM, then it can't be updated 1035 * and we return TRANSLATE_FAIL. 1036 * - if the PTE changed by the time we went to update it, then 1037 * it is no longer valid and we must re-walk the page table. 1038 */ 1039 MemoryRegion *mr; 1040 hwaddr l = sizeof(target_ulong), addr1; 1041 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1042 false, MEMTXATTRS_UNSPECIFIED); 1043 if (memory_region_is_ram(mr)) { 1044 target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); 1045 #if TCG_OVERSIZED_GUEST 1046 /* 1047 * MTTCG is not enabled on oversized TCG guests so 1048 * page table updates do not need to be atomic 1049 */ 1050 *pte_pa = pte = updated_pte; 1051 #else 1052 target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); 1053 if (old_pte != pte) { 1054 goto restart; 1055 } 1056 pte = updated_pte; 1057 #endif 1058 } else { 1059 /* 1060 * Misconfigured PTE in ROM (AD bits are not preset) or 1061 * PTE is in IO space and can't be updated atomically. 1062 */ 1063 return TRANSLATE_FAIL; 1064 } 1065 } 1066 1067 /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */ 1068 target_ulong vpn = addr >> PGSHIFT; 1069 1070 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1071 napot_bits = ctzl(ppn) + 1; 1072 if ((i != (levels - 1)) || (napot_bits != 4)) { 1073 return TRANSLATE_FAIL; 1074 } 1075 } 1076 1077 napot_mask = (1 << napot_bits) - 1; 1078 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1079 (vpn & (((target_ulong)1 << ptshift) - 1)) 1080 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1081 1082 /* 1083 * Remove write permission unless this is a store, or the page is 1084 * already dirty, so that we TLB miss on later writes to update 1085 * the dirty bit. 1086 */ 1087 if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { 1088 prot &= ~PAGE_WRITE; 1089 } 1090 *ret_prot = prot; 1091 1092 return TRANSLATE_SUCCESS; 1093 } 1094 1095 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1096 MMUAccessType access_type, bool pmp_violation, 1097 bool first_stage, bool two_stage, 1098 bool two_stage_indirect) 1099 { 1100 CPUState *cs = env_cpu(env); 1101 int page_fault_exceptions, vm; 1102 uint64_t stap_mode; 1103 1104 if (riscv_cpu_mxl(env) == MXL_RV32) { 1105 stap_mode = SATP32_MODE; 1106 } else { 1107 stap_mode = SATP64_MODE; 1108 } 1109 1110 if (first_stage) { 1111 vm = get_field(env->satp, stap_mode); 1112 } else { 1113 vm = get_field(env->hgatp, stap_mode); 1114 } 1115 1116 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1117 1118 switch (access_type) { 1119 case MMU_INST_FETCH: 1120 if (env->virt_enabled && !first_stage) { 1121 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1122 } else { 1123 cs->exception_index = page_fault_exceptions ? 1124 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1125 } 1126 break; 1127 case MMU_DATA_LOAD: 1128 if (two_stage && !first_stage) { 1129 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1130 } else { 1131 cs->exception_index = page_fault_exceptions ? 1132 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1133 } 1134 break; 1135 case MMU_DATA_STORE: 1136 if (two_stage && !first_stage) { 1137 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1138 } else { 1139 cs->exception_index = page_fault_exceptions ? 1140 RISCV_EXCP_STORE_PAGE_FAULT : 1141 RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1142 } 1143 break; 1144 default: 1145 g_assert_not_reached(); 1146 } 1147 env->badaddr = address; 1148 env->two_stage_lookup = two_stage; 1149 env->two_stage_indirect_lookup = two_stage_indirect; 1150 } 1151 1152 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1153 { 1154 RISCVCPU *cpu = RISCV_CPU(cs); 1155 CPURISCVState *env = &cpu->env; 1156 hwaddr phys_addr; 1157 int prot; 1158 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1159 1160 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1161 true, env->virt_enabled, true)) { 1162 return -1; 1163 } 1164 1165 if (env->virt_enabled) { 1166 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1167 0, mmu_idx, false, true, true)) { 1168 return -1; 1169 } 1170 } 1171 1172 return phys_addr & TARGET_PAGE_MASK; 1173 } 1174 1175 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1176 vaddr addr, unsigned size, 1177 MMUAccessType access_type, 1178 int mmu_idx, MemTxAttrs attrs, 1179 MemTxResult response, uintptr_t retaddr) 1180 { 1181 RISCVCPU *cpu = RISCV_CPU(cs); 1182 CPURISCVState *env = &cpu->env; 1183 1184 if (access_type == MMU_DATA_STORE) { 1185 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1186 } else if (access_type == MMU_DATA_LOAD) { 1187 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1188 } else { 1189 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1190 } 1191 1192 env->badaddr = addr; 1193 env->two_stage_lookup = mmuidx_2stage(mmu_idx); 1194 env->two_stage_indirect_lookup = false; 1195 cpu_loop_exit_restore(cs, retaddr); 1196 } 1197 1198 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1199 MMUAccessType access_type, int mmu_idx, 1200 uintptr_t retaddr) 1201 { 1202 RISCVCPU *cpu = RISCV_CPU(cs); 1203 CPURISCVState *env = &cpu->env; 1204 switch (access_type) { 1205 case MMU_INST_FETCH: 1206 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1207 break; 1208 case MMU_DATA_LOAD: 1209 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1210 break; 1211 case MMU_DATA_STORE: 1212 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1213 break; 1214 default: 1215 g_assert_not_reached(); 1216 } 1217 env->badaddr = addr; 1218 env->two_stage_lookup = mmuidx_2stage(mmu_idx); 1219 env->two_stage_indirect_lookup = false; 1220 cpu_loop_exit_restore(cs, retaddr); 1221 } 1222 1223 1224 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1225 { 1226 enum riscv_pmu_event_idx pmu_event_type; 1227 1228 switch (access_type) { 1229 case MMU_INST_FETCH: 1230 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1231 break; 1232 case MMU_DATA_LOAD: 1233 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1234 break; 1235 case MMU_DATA_STORE: 1236 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1237 break; 1238 default: 1239 return; 1240 } 1241 1242 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1243 } 1244 1245 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1246 MMUAccessType access_type, int mmu_idx, 1247 bool probe, uintptr_t retaddr) 1248 { 1249 RISCVCPU *cpu = RISCV_CPU(cs); 1250 CPURISCVState *env = &cpu->env; 1251 vaddr im_address; 1252 hwaddr pa = 0; 1253 int prot, prot2, prot_pmp; 1254 bool pmp_violation = false; 1255 bool first_stage_error = true; 1256 bool two_stage_lookup = mmuidx_2stage(mmu_idx); 1257 bool two_stage_indirect_error = false; 1258 int ret = TRANSLATE_FAIL; 1259 int mode = mmu_idx; 1260 /* default TLB page size */ 1261 target_ulong tlb_size = TARGET_PAGE_SIZE; 1262 1263 env->guest_phys_fault_addr = 0; 1264 1265 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1266 __func__, address, access_type, mmu_idx); 1267 1268 pmu_tlb_fill_incr_ctr(cpu, access_type); 1269 if (two_stage_lookup) { 1270 /* Two stage lookup */ 1271 ret = get_physical_address(env, &pa, &prot, address, 1272 &env->guest_phys_fault_addr, access_type, 1273 mmu_idx, true, true, false); 1274 1275 /* 1276 * A G-stage exception may be triggered during two state lookup. 1277 * And the env->guest_phys_fault_addr has already been set in 1278 * get_physical_address(). 1279 */ 1280 if (ret == TRANSLATE_G_STAGE_FAIL) { 1281 first_stage_error = false; 1282 two_stage_indirect_error = true; 1283 access_type = MMU_DATA_LOAD; 1284 } 1285 1286 qemu_log_mask(CPU_LOG_MMU, 1287 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1288 HWADDR_FMT_plx " prot %d\n", 1289 __func__, address, ret, pa, prot); 1290 1291 if (ret == TRANSLATE_SUCCESS) { 1292 /* Second stage lookup */ 1293 im_address = pa; 1294 1295 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1296 access_type, MMUIdx_U, false, true, 1297 false); 1298 1299 qemu_log_mask(CPU_LOG_MMU, 1300 "%s 2nd-stage address=%" VADDR_PRIx 1301 " ret %d physical " 1302 HWADDR_FMT_plx " prot %d\n", 1303 __func__, im_address, ret, pa, prot2); 1304 1305 prot &= prot2; 1306 1307 if (ret == TRANSLATE_SUCCESS) { 1308 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1309 size, access_type, mode); 1310 1311 qemu_log_mask(CPU_LOG_MMU, 1312 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1313 " %d tlb_size " TARGET_FMT_lu "\n", 1314 __func__, pa, ret, prot_pmp, tlb_size); 1315 1316 prot &= prot_pmp; 1317 } 1318 1319 if (ret != TRANSLATE_SUCCESS) { 1320 /* 1321 * Guest physical address translation failed, this is a HS 1322 * level exception 1323 */ 1324 first_stage_error = false; 1325 env->guest_phys_fault_addr = (im_address | 1326 (address & 1327 (TARGET_PAGE_SIZE - 1))) >> 2; 1328 } 1329 } 1330 } else { 1331 /* Single stage lookup */ 1332 ret = get_physical_address(env, &pa, &prot, address, NULL, 1333 access_type, mmu_idx, true, false, false); 1334 1335 qemu_log_mask(CPU_LOG_MMU, 1336 "%s address=%" VADDR_PRIx " ret %d physical " 1337 HWADDR_FMT_plx " prot %d\n", 1338 __func__, address, ret, pa, prot); 1339 1340 if (ret == TRANSLATE_SUCCESS) { 1341 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1342 size, access_type, mode); 1343 1344 qemu_log_mask(CPU_LOG_MMU, 1345 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1346 " %d tlb_size " TARGET_FMT_lu "\n", 1347 __func__, pa, ret, prot_pmp, tlb_size); 1348 1349 prot &= prot_pmp; 1350 } 1351 } 1352 1353 if (ret == TRANSLATE_PMP_FAIL) { 1354 pmp_violation = true; 1355 } 1356 1357 if (ret == TRANSLATE_SUCCESS) { 1358 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1359 prot, mmu_idx, tlb_size); 1360 return true; 1361 } else if (probe) { 1362 return false; 1363 } else { 1364 raise_mmu_exception(env, address, access_type, pmp_violation, 1365 first_stage_error, two_stage_lookup, 1366 two_stage_indirect_error); 1367 cpu_loop_exit_restore(cs, retaddr); 1368 } 1369 1370 return true; 1371 } 1372 1373 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1374 target_ulong insn, 1375 target_ulong taddr) 1376 { 1377 target_ulong xinsn = 0; 1378 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1379 1380 /* 1381 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1382 * be uncompressed. The Quadrant 1 of RVC instruction space need 1383 * not be transformed because these instructions won't generate 1384 * any load/store trap. 1385 */ 1386 1387 if ((insn & 0x3) != 0x3) { 1388 /* Transform 16bit instruction into 32bit instruction */ 1389 switch (GET_C_OP(insn)) { 1390 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1391 switch (GET_C_FUNC(insn)) { 1392 case OPC_RISC_C_FUNC_FLD_LQ: 1393 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1394 xinsn = OPC_RISC_FLD; 1395 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1396 access_rs1 = GET_C_RS1S(insn); 1397 access_imm = GET_C_LD_IMM(insn); 1398 access_size = 8; 1399 } 1400 break; 1401 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1402 xinsn = OPC_RISC_LW; 1403 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1404 access_rs1 = GET_C_RS1S(insn); 1405 access_imm = GET_C_LW_IMM(insn); 1406 access_size = 4; 1407 break; 1408 case OPC_RISC_C_FUNC_FLW_LD: 1409 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1410 xinsn = OPC_RISC_FLW; 1411 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1412 access_rs1 = GET_C_RS1S(insn); 1413 access_imm = GET_C_LW_IMM(insn); 1414 access_size = 4; 1415 } else { /* C.LD (RV64/RV128) */ 1416 xinsn = OPC_RISC_LD; 1417 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1418 access_rs1 = GET_C_RS1S(insn); 1419 access_imm = GET_C_LD_IMM(insn); 1420 access_size = 8; 1421 } 1422 break; 1423 case OPC_RISC_C_FUNC_FSD_SQ: 1424 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1425 xinsn = OPC_RISC_FSD; 1426 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1427 access_rs1 = GET_C_RS1S(insn); 1428 access_imm = GET_C_SD_IMM(insn); 1429 access_size = 8; 1430 } 1431 break; 1432 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1433 xinsn = OPC_RISC_SW; 1434 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1435 access_rs1 = GET_C_RS1S(insn); 1436 access_imm = GET_C_SW_IMM(insn); 1437 access_size = 4; 1438 break; 1439 case OPC_RISC_C_FUNC_FSW_SD: 1440 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1441 xinsn = OPC_RISC_FSW; 1442 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1443 access_rs1 = GET_C_RS1S(insn); 1444 access_imm = GET_C_SW_IMM(insn); 1445 access_size = 4; 1446 } else { /* C.SD (RV64/RV128) */ 1447 xinsn = OPC_RISC_SD; 1448 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1449 access_rs1 = GET_C_RS1S(insn); 1450 access_imm = GET_C_SD_IMM(insn); 1451 access_size = 8; 1452 } 1453 break; 1454 default: 1455 break; 1456 } 1457 break; 1458 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1459 switch (GET_C_FUNC(insn)) { 1460 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1461 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1462 xinsn = OPC_RISC_FLD; 1463 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1464 access_rs1 = 2; 1465 access_imm = GET_C_LDSP_IMM(insn); 1466 access_size = 8; 1467 } 1468 break; 1469 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1470 xinsn = OPC_RISC_LW; 1471 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1472 access_rs1 = 2; 1473 access_imm = GET_C_LWSP_IMM(insn); 1474 access_size = 4; 1475 break; 1476 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1477 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1478 xinsn = OPC_RISC_FLW; 1479 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1480 access_rs1 = 2; 1481 access_imm = GET_C_LWSP_IMM(insn); 1482 access_size = 4; 1483 } else { /* C.LDSP (RV64/RV128) */ 1484 xinsn = OPC_RISC_LD; 1485 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1486 access_rs1 = 2; 1487 access_imm = GET_C_LDSP_IMM(insn); 1488 access_size = 8; 1489 } 1490 break; 1491 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1492 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1493 xinsn = OPC_RISC_FSD; 1494 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1495 access_rs1 = 2; 1496 access_imm = GET_C_SDSP_IMM(insn); 1497 access_size = 8; 1498 } 1499 break; 1500 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1501 xinsn = OPC_RISC_SW; 1502 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1503 access_rs1 = 2; 1504 access_imm = GET_C_SWSP_IMM(insn); 1505 access_size = 4; 1506 break; 1507 case 7: 1508 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1509 xinsn = OPC_RISC_FSW; 1510 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1511 access_rs1 = 2; 1512 access_imm = GET_C_SWSP_IMM(insn); 1513 access_size = 4; 1514 } else { /* C.SDSP (RV64/RV128) */ 1515 xinsn = OPC_RISC_SD; 1516 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1517 access_rs1 = 2; 1518 access_imm = GET_C_SDSP_IMM(insn); 1519 access_size = 8; 1520 } 1521 break; 1522 default: 1523 break; 1524 } 1525 break; 1526 default: 1527 break; 1528 } 1529 1530 /* 1531 * Clear Bit1 of transformed instruction to indicate that 1532 * original insruction was a 16bit instruction 1533 */ 1534 xinsn &= ~((target_ulong)0x2); 1535 } else { 1536 /* Transform 32bit (or wider) instructions */ 1537 switch (MASK_OP_MAJOR(insn)) { 1538 case OPC_RISC_ATOMIC: 1539 xinsn = insn; 1540 access_rs1 = GET_RS1(insn); 1541 access_size = 1 << GET_FUNCT3(insn); 1542 break; 1543 case OPC_RISC_LOAD: 1544 case OPC_RISC_FP_LOAD: 1545 xinsn = SET_I_IMM(insn, 0); 1546 access_rs1 = GET_RS1(insn); 1547 access_imm = GET_IMM(insn); 1548 access_size = 1 << GET_FUNCT3(insn); 1549 break; 1550 case OPC_RISC_STORE: 1551 case OPC_RISC_FP_STORE: 1552 xinsn = SET_S_IMM(insn, 0); 1553 access_rs1 = GET_RS1(insn); 1554 access_imm = GET_STORE_IMM(insn); 1555 access_size = 1 << GET_FUNCT3(insn); 1556 break; 1557 case OPC_RISC_SYSTEM: 1558 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1559 xinsn = insn; 1560 access_rs1 = GET_RS1(insn); 1561 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1562 access_size = 1 << access_size; 1563 } 1564 break; 1565 default: 1566 break; 1567 } 1568 } 1569 1570 if (access_size) { 1571 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1572 (access_size - 1)); 1573 } 1574 1575 return xinsn; 1576 } 1577 #endif /* !CONFIG_USER_ONLY */ 1578 1579 /* 1580 * Handle Traps 1581 * 1582 * Adapted from Spike's processor_t::take_trap. 1583 * 1584 */ 1585 void riscv_cpu_do_interrupt(CPUState *cs) 1586 { 1587 #if !defined(CONFIG_USER_ONLY) 1588 1589 RISCVCPU *cpu = RISCV_CPU(cs); 1590 CPURISCVState *env = &cpu->env; 1591 bool write_gva = false; 1592 uint64_t s; 1593 1594 /* 1595 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1596 * so we mask off the MSB and separate into trap type and cause. 1597 */ 1598 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1599 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1600 uint64_t deleg = async ? env->mideleg : env->medeleg; 1601 target_ulong tval = 0; 1602 target_ulong tinst = 0; 1603 target_ulong htval = 0; 1604 target_ulong mtval2 = 0; 1605 1606 if (cause == RISCV_EXCP_SEMIHOST) { 1607 do_common_semihosting(cs); 1608 env->pc += 4; 1609 return; 1610 } 1611 1612 if (!async) { 1613 /* set tval to badaddr for traps with address information */ 1614 switch (cause) { 1615 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1616 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1617 case RISCV_EXCP_LOAD_ADDR_MIS: 1618 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1619 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1620 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1621 case RISCV_EXCP_LOAD_PAGE_FAULT: 1622 case RISCV_EXCP_STORE_PAGE_FAULT: 1623 write_gva = env->two_stage_lookup; 1624 tval = env->badaddr; 1625 if (env->two_stage_indirect_lookup) { 1626 /* 1627 * special pseudoinstruction for G-stage fault taken while 1628 * doing VS-stage page table walk. 1629 */ 1630 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1631 } else { 1632 /* 1633 * The "Addr. Offset" field in transformed instruction is 1634 * non-zero only for misaligned access. 1635 */ 1636 tinst = riscv_transformed_insn(env, env->bins, tval); 1637 } 1638 break; 1639 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1640 case RISCV_EXCP_INST_ADDR_MIS: 1641 case RISCV_EXCP_INST_ACCESS_FAULT: 1642 case RISCV_EXCP_INST_PAGE_FAULT: 1643 write_gva = env->two_stage_lookup; 1644 tval = env->badaddr; 1645 if (env->two_stage_indirect_lookup) { 1646 /* 1647 * special pseudoinstruction for G-stage fault taken while 1648 * doing VS-stage page table walk. 1649 */ 1650 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1651 } 1652 break; 1653 case RISCV_EXCP_ILLEGAL_INST: 1654 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1655 tval = env->bins; 1656 break; 1657 case RISCV_EXCP_BREAKPOINT: 1658 if (cs->watchpoint_hit) { 1659 tval = cs->watchpoint_hit->hitaddr; 1660 cs->watchpoint_hit = NULL; 1661 } 1662 break; 1663 default: 1664 break; 1665 } 1666 /* ecall is dispatched as one cause so translate based on mode */ 1667 if (cause == RISCV_EXCP_U_ECALL) { 1668 assert(env->priv <= 3); 1669 1670 if (env->priv == PRV_M) { 1671 cause = RISCV_EXCP_M_ECALL; 1672 } else if (env->priv == PRV_S && env->virt_enabled) { 1673 cause = RISCV_EXCP_VS_ECALL; 1674 } else if (env->priv == PRV_S && !env->virt_enabled) { 1675 cause = RISCV_EXCP_S_ECALL; 1676 } else if (env->priv == PRV_U) { 1677 cause = RISCV_EXCP_U_ECALL; 1678 } 1679 } 1680 } 1681 1682 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1683 riscv_cpu_get_trap_name(cause, async)); 1684 1685 qemu_log_mask(CPU_LOG_INT, 1686 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1687 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1688 __func__, env->mhartid, async, cause, env->pc, tval, 1689 riscv_cpu_get_trap_name(cause, async)); 1690 1691 if (env->priv <= PRV_S && 1692 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1693 /* handle the trap in S-mode */ 1694 if (riscv_has_ext(env, RVH)) { 1695 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1696 1697 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1698 /* Trap to VS mode */ 1699 /* 1700 * See if we need to adjust cause. Yes if its VS mode interrupt 1701 * no if hypervisor has delegated one of hs mode's interrupt 1702 */ 1703 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1704 cause == IRQ_VS_EXT) { 1705 cause = cause - 1; 1706 } 1707 write_gva = false; 1708 } else if (env->virt_enabled) { 1709 /* Trap into HS mode, from virt */ 1710 riscv_cpu_swap_hypervisor_regs(env); 1711 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1712 env->priv); 1713 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1714 1715 htval = env->guest_phys_fault_addr; 1716 1717 riscv_cpu_set_virt_enabled(env, 0); 1718 } else { 1719 /* Trap into HS mode */ 1720 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1721 htval = env->guest_phys_fault_addr; 1722 } 1723 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1724 } 1725 1726 s = env->mstatus; 1727 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1728 s = set_field(s, MSTATUS_SPP, env->priv); 1729 s = set_field(s, MSTATUS_SIE, 0); 1730 env->mstatus = s; 1731 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1732 env->sepc = env->pc; 1733 env->stval = tval; 1734 env->htval = htval; 1735 env->htinst = tinst; 1736 env->pc = (env->stvec >> 2 << 2) + 1737 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1738 riscv_cpu_set_mode(env, PRV_S); 1739 } else { 1740 /* handle the trap in M-mode */ 1741 if (riscv_has_ext(env, RVH)) { 1742 if (env->virt_enabled) { 1743 riscv_cpu_swap_hypervisor_regs(env); 1744 } 1745 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1746 env->virt_enabled); 1747 if (env->virt_enabled && tval) { 1748 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1749 } 1750 1751 mtval2 = env->guest_phys_fault_addr; 1752 1753 /* Trapping to M mode, virt is disabled */ 1754 riscv_cpu_set_virt_enabled(env, 0); 1755 } 1756 1757 s = env->mstatus; 1758 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1759 s = set_field(s, MSTATUS_MPP, env->priv); 1760 s = set_field(s, MSTATUS_MIE, 0); 1761 env->mstatus = s; 1762 env->mcause = cause | ~(((target_ulong)-1) >> async); 1763 env->mepc = env->pc; 1764 env->mtval = tval; 1765 env->mtval2 = mtval2; 1766 env->mtinst = tinst; 1767 env->pc = (env->mtvec >> 2 << 2) + 1768 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1769 riscv_cpu_set_mode(env, PRV_M); 1770 } 1771 1772 /* 1773 * NOTE: it is not necessary to yield load reservations here. It is only 1774 * necessary for an SC from "another hart" to cause a load reservation 1775 * to be yielded. Refer to the memory consistency model section of the 1776 * RISC-V ISA Specification. 1777 */ 1778 1779 env->two_stage_lookup = false; 1780 env->two_stage_indirect_lookup = false; 1781 #endif 1782 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1783 } 1784