1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 #include "semihosting/common-semi.h" 28 29 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 30 { 31 #ifdef CONFIG_USER_ONLY 32 return 0; 33 #else 34 return env->priv; 35 #endif 36 } 37 38 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 39 target_ulong *cs_base, uint32_t *pflags) 40 { 41 CPUState *cs = env_cpu(env); 42 RISCVCPU *cpu = RISCV_CPU(cs); 43 44 uint32_t flags = 0; 45 46 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 47 *cs_base = 0; 48 49 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 50 /* 51 * If env->vl equals to VLMAX, we can use generic vector operation 52 * expanders (GVEC) to accerlate the vector operations. 53 * However, as LMUL could be a fractional number. The maximum 54 * vector size can be operated might be less than 8 bytes, 55 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 56 * only when maxsz >= 8 bytes. 57 */ 58 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 59 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 60 uint32_t maxsz = vlmax << sew; 61 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 62 (maxsz >= 8); 63 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 64 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 65 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 66 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 67 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 68 } else { 69 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 70 } 71 72 #ifdef CONFIG_USER_ONLY 73 flags |= TB_FLAGS_MSTATUS_FS; 74 flags |= TB_FLAGS_MSTATUS_VS; 75 #else 76 flags |= cpu_mmu_index(env, 0); 77 if (riscv_cpu_fp_enabled(env)) { 78 flags |= env->mstatus & MSTATUS_FS; 79 } 80 81 if (riscv_cpu_vector_enabled(env)) { 82 flags |= env->mstatus & MSTATUS_VS; 83 } 84 85 if (riscv_has_ext(env, RVH)) { 86 if (env->priv == PRV_M || 87 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 88 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 89 get_field(env->hstatus, HSTATUS_HU))) { 90 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 91 } 92 93 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 94 get_field(env->mstatus_hs, MSTATUS_FS)); 95 96 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 97 get_field(env->mstatus_hs, MSTATUS_VS)); 98 } 99 #endif 100 101 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 102 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 103 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 104 } 105 if (env->cur_pmbase != 0) { 106 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 107 } 108 109 *pflags = flags; 110 } 111 112 void riscv_cpu_update_mask(CPURISCVState *env) 113 { 114 target_ulong mask = -1, base = 0; 115 /* 116 * TODO: Current RVJ spec does not specify 117 * how the extension interacts with XLEN. 118 */ 119 #ifndef CONFIG_USER_ONLY 120 if (riscv_has_ext(env, RVJ)) { 121 switch (env->priv) { 122 case PRV_M: 123 if (env->mmte & M_PM_ENABLE) { 124 mask = env->mpmmask; 125 base = env->mpmbase; 126 } 127 break; 128 case PRV_S: 129 if (env->mmte & S_PM_ENABLE) { 130 mask = env->spmmask; 131 base = env->spmbase; 132 } 133 break; 134 case PRV_U: 135 if (env->mmte & U_PM_ENABLE) { 136 mask = env->upmmask; 137 base = env->upmbase; 138 } 139 break; 140 default: 141 g_assert_not_reached(); 142 } 143 } 144 #endif 145 if (env->xl == MXL_RV32) { 146 env->cur_pmmask = mask & UINT32_MAX; 147 env->cur_pmbase = base & UINT32_MAX; 148 } else { 149 env->cur_pmmask = mask; 150 env->cur_pmbase = base; 151 } 152 } 153 154 #ifndef CONFIG_USER_ONLY 155 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 156 { 157 target_ulong virt_enabled = riscv_cpu_virt_enabled(env); 158 159 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 160 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 161 162 target_ulong vsgemask = 163 (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN); 164 target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0; 165 166 target_ulong pending = (env->mip | vsgein) & env->mie; 167 168 target_ulong mie = env->priv < PRV_M || 169 (env->priv == PRV_M && mstatus_mie); 170 target_ulong sie = env->priv < PRV_S || 171 (env->priv == PRV_S && mstatus_sie); 172 target_ulong hsie = virt_enabled || sie; 173 target_ulong vsie = virt_enabled && sie; 174 175 target_ulong irqs = 176 (pending & ~env->mideleg & -mie) | 177 (pending & env->mideleg & ~env->hideleg & -hsie) | 178 (pending & env->mideleg & env->hideleg & -vsie); 179 180 if (irqs) { 181 return ctz64(irqs); /* since non-zero */ 182 } else { 183 return RISCV_EXCP_NONE; /* indicates no pending interrupt */ 184 } 185 } 186 187 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 188 { 189 if (interrupt_request & CPU_INTERRUPT_HARD) { 190 RISCVCPU *cpu = RISCV_CPU(cs); 191 CPURISCVState *env = &cpu->env; 192 int interruptno = riscv_cpu_local_irq_pending(env); 193 if (interruptno >= 0) { 194 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 195 riscv_cpu_do_interrupt(cs); 196 return true; 197 } 198 } 199 return false; 200 } 201 202 /* Return true is floating point support is currently enabled */ 203 bool riscv_cpu_fp_enabled(CPURISCVState *env) 204 { 205 if (env->mstatus & MSTATUS_FS) { 206 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 207 return false; 208 } 209 return true; 210 } 211 212 return false; 213 } 214 215 /* Return true is vector support is currently enabled */ 216 bool riscv_cpu_vector_enabled(CPURISCVState *env) 217 { 218 if (env->mstatus & MSTATUS_VS) { 219 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 220 return false; 221 } 222 return true; 223 } 224 225 return false; 226 } 227 228 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 229 { 230 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 231 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 232 MSTATUS64_UXL | MSTATUS_VS; 233 bool current_virt = riscv_cpu_virt_enabled(env); 234 235 g_assert(riscv_has_ext(env, RVH)); 236 237 if (current_virt) { 238 /* Current V=1 and we are about to change to V=0 */ 239 env->vsstatus = env->mstatus & mstatus_mask; 240 env->mstatus &= ~mstatus_mask; 241 env->mstatus |= env->mstatus_hs; 242 243 env->vstvec = env->stvec; 244 env->stvec = env->stvec_hs; 245 246 env->vsscratch = env->sscratch; 247 env->sscratch = env->sscratch_hs; 248 249 env->vsepc = env->sepc; 250 env->sepc = env->sepc_hs; 251 252 env->vscause = env->scause; 253 env->scause = env->scause_hs; 254 255 env->vstval = env->stval; 256 env->stval = env->stval_hs; 257 258 env->vsatp = env->satp; 259 env->satp = env->satp_hs; 260 } else { 261 /* Current V=0 and we are about to change to V=1 */ 262 env->mstatus_hs = env->mstatus & mstatus_mask; 263 env->mstatus &= ~mstatus_mask; 264 env->mstatus |= env->vsstatus; 265 266 env->stvec_hs = env->stvec; 267 env->stvec = env->vstvec; 268 269 env->sscratch_hs = env->sscratch; 270 env->sscratch = env->vsscratch; 271 272 env->sepc_hs = env->sepc; 273 env->sepc = env->vsepc; 274 275 env->scause_hs = env->scause; 276 env->scause = env->vscause; 277 278 env->stval_hs = env->stval; 279 env->stval = env->vstval; 280 281 env->satp_hs = env->satp; 282 env->satp = env->vsatp; 283 } 284 } 285 286 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 287 { 288 if (!riscv_has_ext(env, RVH)) { 289 return 0; 290 } 291 292 return env->geilen; 293 } 294 295 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 296 { 297 if (!riscv_has_ext(env, RVH)) { 298 return; 299 } 300 301 if (geilen > (TARGET_LONG_BITS - 1)) { 302 return; 303 } 304 305 env->geilen = geilen; 306 } 307 308 bool riscv_cpu_virt_enabled(CPURISCVState *env) 309 { 310 if (!riscv_has_ext(env, RVH)) { 311 return false; 312 } 313 314 return get_field(env->virt, VIRT_ONOFF); 315 } 316 317 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 318 { 319 if (!riscv_has_ext(env, RVH)) { 320 return; 321 } 322 323 /* Flush the TLB on all virt mode changes. */ 324 if (get_field(env->virt, VIRT_ONOFF) != enable) { 325 tlb_flush(env_cpu(env)); 326 } 327 328 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 329 330 if (enable) { 331 /* 332 * The guest external interrupts from an interrupt controller are 333 * delivered only when the Guest/VM is running (i.e. V=1). This means 334 * any guest external interrupt which is triggered while the Guest/VM 335 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 336 * with sluggish response to serial console input and other I/O events. 337 * 338 * To solve this, we check and inject interrupt after setting V=1. 339 */ 340 riscv_cpu_update_mip(env_archcpu(env), 0, 0); 341 } 342 } 343 344 bool riscv_cpu_two_stage_lookup(int mmu_idx) 345 { 346 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 347 } 348 349 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 350 { 351 CPURISCVState *env = &cpu->env; 352 if (env->miclaim & interrupts) { 353 return -1; 354 } else { 355 env->miclaim |= interrupts; 356 return 0; 357 } 358 } 359 360 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 361 { 362 CPURISCVState *env = &cpu->env; 363 CPUState *cs = CPU(cpu); 364 uint32_t gein, vsgein = 0, old = env->mip; 365 bool locked = false; 366 367 if (riscv_cpu_virt_enabled(env)) { 368 gein = get_field(env->hstatus, HSTATUS_VGEIN); 369 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 370 } 371 372 if (!qemu_mutex_iothread_locked()) { 373 locked = true; 374 qemu_mutex_lock_iothread(); 375 } 376 377 env->mip = (env->mip & ~mask) | (value & mask); 378 379 if (env->mip | vsgein) { 380 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 381 } else { 382 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 383 } 384 385 if (locked) { 386 qemu_mutex_unlock_iothread(); 387 } 388 389 return old; 390 } 391 392 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 393 uint32_t arg) 394 { 395 env->rdtime_fn = fn; 396 env->rdtime_fn_arg = arg; 397 } 398 399 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 400 int (*rmw_fn)(void *arg, 401 target_ulong reg, 402 target_ulong *val, 403 target_ulong new_val, 404 target_ulong write_mask), 405 void *rmw_fn_arg) 406 { 407 if (priv <= PRV_M) { 408 env->aia_ireg_rmw_fn[priv] = rmw_fn; 409 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 410 } 411 } 412 413 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 414 { 415 if (newpriv > PRV_M) { 416 g_assert_not_reached(); 417 } 418 if (newpriv == PRV_H) { 419 newpriv = PRV_U; 420 } 421 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 422 env->priv = newpriv; 423 env->xl = cpu_recompute_xl(env); 424 riscv_cpu_update_mask(env); 425 426 /* 427 * Clear the load reservation - otherwise a reservation placed in one 428 * context/process can be used by another, resulting in an SC succeeding 429 * incorrectly. Version 2.2 of the ISA specification explicitly requires 430 * this behaviour, while later revisions say that the kernel "should" use 431 * an SC instruction to force the yielding of a load reservation on a 432 * preemptive context switch. As a result, do both. 433 */ 434 env->load_res = -1; 435 } 436 437 /* 438 * get_physical_address_pmp - check PMP permission for this physical address 439 * 440 * Match the PMP region and check permission for this physical address and it's 441 * TLB page. Returns 0 if the permission checking was successful 442 * 443 * @env: CPURISCVState 444 * @prot: The returned protection attributes 445 * @tlb_size: TLB page size containing addr. It could be modified after PMP 446 * permission checking. NULL if not set TLB page for addr. 447 * @addr: The physical address to be checked permission 448 * @access_type: The type of MMU access 449 * @mode: Indicates current privilege level. 450 */ 451 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 452 target_ulong *tlb_size, hwaddr addr, 453 int size, MMUAccessType access_type, 454 int mode) 455 { 456 pmp_priv_t pmp_priv; 457 target_ulong tlb_size_pmp = 0; 458 459 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 460 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 461 return TRANSLATE_SUCCESS; 462 } 463 464 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, 465 mode)) { 466 *prot = 0; 467 return TRANSLATE_PMP_FAIL; 468 } 469 470 *prot = pmp_priv_to_page_prot(pmp_priv); 471 if (tlb_size != NULL) { 472 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { 473 *tlb_size = tlb_size_pmp; 474 } 475 } 476 477 return TRANSLATE_SUCCESS; 478 } 479 480 /* get_physical_address - get the physical address for this virtual address 481 * 482 * Do a page table walk to obtain the physical address corresponding to a 483 * virtual address. Returns 0 if the translation was successful 484 * 485 * Adapted from Spike's mmu_t::translate and mmu_t::walk 486 * 487 * @env: CPURISCVState 488 * @physical: This will be set to the calculated physical address 489 * @prot: The returned protection attributes 490 * @addr: The virtual address to be translated 491 * @fault_pte_addr: If not NULL, this will be set to fault pte address 492 * when a error occurs on pte address translation. 493 * This will already be shifted to match htval. 494 * @access_type: The type of MMU access 495 * @mmu_idx: Indicates current privilege level 496 * @first_stage: Are we in first stage translation? 497 * Second stage is used for hypervisor guest translation 498 * @two_stage: Are we going to perform two stage translation 499 * @is_debug: Is this access from a debugger or the monitor? 500 */ 501 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 502 int *prot, target_ulong addr, 503 target_ulong *fault_pte_addr, 504 int access_type, int mmu_idx, 505 bool first_stage, bool two_stage, 506 bool is_debug) 507 { 508 /* NOTE: the env->pc value visible here will not be 509 * correct, but the value visible to the exception handler 510 * (riscv_cpu_do_interrupt) is correct */ 511 MemTxResult res; 512 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 513 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 514 bool use_background = false; 515 516 /* 517 * Check if we should use the background registers for the two 518 * stage translation. We don't need to check if we actually need 519 * two stage translation as that happened before this function 520 * was called. Background registers will be used if the guest has 521 * forced a two stage translation to be on (in HS or M mode). 522 */ 523 if (!riscv_cpu_virt_enabled(env) && two_stage) { 524 use_background = true; 525 } 526 527 /* MPRV does not affect the virtual-machine load/store 528 instructions, HLV, HLVX, and HSV. */ 529 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 530 mode = get_field(env->hstatus, HSTATUS_SPVP); 531 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 532 if (get_field(env->mstatus, MSTATUS_MPRV)) { 533 mode = get_field(env->mstatus, MSTATUS_MPP); 534 } 535 } 536 537 if (first_stage == false) { 538 /* We are in stage 2 translation, this is similar to stage 1. */ 539 /* Stage 2 is always taken as U-mode */ 540 mode = PRV_U; 541 } 542 543 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 544 *physical = addr; 545 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 546 return TRANSLATE_SUCCESS; 547 } 548 549 *prot = 0; 550 551 hwaddr base; 552 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 553 554 if (first_stage == true) { 555 mxr = get_field(env->mstatus, MSTATUS_MXR); 556 } else { 557 mxr = get_field(env->vsstatus, MSTATUS_MXR); 558 } 559 560 if (first_stage == true) { 561 if (use_background) { 562 if (riscv_cpu_mxl(env) == MXL_RV32) { 563 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 564 vm = get_field(env->vsatp, SATP32_MODE); 565 } else { 566 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 567 vm = get_field(env->vsatp, SATP64_MODE); 568 } 569 } else { 570 if (riscv_cpu_mxl(env) == MXL_RV32) { 571 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 572 vm = get_field(env->satp, SATP32_MODE); 573 } else { 574 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 575 vm = get_field(env->satp, SATP64_MODE); 576 } 577 } 578 widened = 0; 579 } else { 580 if (riscv_cpu_mxl(env) == MXL_RV32) { 581 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 582 vm = get_field(env->hgatp, SATP32_MODE); 583 } else { 584 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 585 vm = get_field(env->hgatp, SATP64_MODE); 586 } 587 widened = 2; 588 } 589 /* status.SUM will be ignored if execute on background */ 590 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 591 switch (vm) { 592 case VM_1_10_SV32: 593 levels = 2; ptidxbits = 10; ptesize = 4; break; 594 case VM_1_10_SV39: 595 levels = 3; ptidxbits = 9; ptesize = 8; break; 596 case VM_1_10_SV48: 597 levels = 4; ptidxbits = 9; ptesize = 8; break; 598 case VM_1_10_SV57: 599 levels = 5; ptidxbits = 9; ptesize = 8; break; 600 case VM_1_10_MBARE: 601 *physical = addr; 602 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 603 return TRANSLATE_SUCCESS; 604 default: 605 g_assert_not_reached(); 606 } 607 608 CPUState *cs = env_cpu(env); 609 int va_bits = PGSHIFT + levels * ptidxbits + widened; 610 target_ulong mask, masked_msbs; 611 612 if (TARGET_LONG_BITS > (va_bits - 1)) { 613 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 614 } else { 615 mask = 0; 616 } 617 masked_msbs = (addr >> (va_bits - 1)) & mask; 618 619 if (masked_msbs != 0 && masked_msbs != mask) { 620 return TRANSLATE_FAIL; 621 } 622 623 int ptshift = (levels - 1) * ptidxbits; 624 int i; 625 626 #if !TCG_OVERSIZED_GUEST 627 restart: 628 #endif 629 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 630 target_ulong idx; 631 if (i == 0) { 632 idx = (addr >> (PGSHIFT + ptshift)) & 633 ((1 << (ptidxbits + widened)) - 1); 634 } else { 635 idx = (addr >> (PGSHIFT + ptshift)) & 636 ((1 << ptidxbits) - 1); 637 } 638 639 /* check that physical address of PTE is legal */ 640 hwaddr pte_addr; 641 642 if (two_stage && first_stage) { 643 int vbase_prot; 644 hwaddr vbase; 645 646 /* Do the second stage translation on the base PTE address. */ 647 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 648 base, NULL, MMU_DATA_LOAD, 649 mmu_idx, false, true, 650 is_debug); 651 652 if (vbase_ret != TRANSLATE_SUCCESS) { 653 if (fault_pte_addr) { 654 *fault_pte_addr = (base + idx * ptesize) >> 2; 655 } 656 return TRANSLATE_G_STAGE_FAIL; 657 } 658 659 pte_addr = vbase + idx * ptesize; 660 } else { 661 pte_addr = base + idx * ptesize; 662 } 663 664 int pmp_prot; 665 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 666 sizeof(target_ulong), 667 MMU_DATA_LOAD, PRV_S); 668 if (pmp_ret != TRANSLATE_SUCCESS) { 669 return TRANSLATE_PMP_FAIL; 670 } 671 672 target_ulong pte; 673 if (riscv_cpu_mxl(env) == MXL_RV32) { 674 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 675 } else { 676 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 677 } 678 679 if (res != MEMTX_OK) { 680 return TRANSLATE_FAIL; 681 } 682 683 hwaddr ppn = pte >> PTE_PPN_SHIFT; 684 685 if (!(pte & PTE_V)) { 686 /* Invalid PTE */ 687 return TRANSLATE_FAIL; 688 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 689 /* Inner PTE, continue walking */ 690 base = ppn << PGSHIFT; 691 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 692 /* Reserved leaf PTE flags: PTE_W */ 693 return TRANSLATE_FAIL; 694 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 695 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 696 return TRANSLATE_FAIL; 697 } else if ((pte & PTE_U) && ((mode != PRV_U) && 698 (!sum || access_type == MMU_INST_FETCH))) { 699 /* User PTE flags when not U mode and mstatus.SUM is not set, 700 or the access type is an instruction fetch */ 701 return TRANSLATE_FAIL; 702 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 703 /* Supervisor PTE flags when not S mode */ 704 return TRANSLATE_FAIL; 705 } else if (ppn & ((1ULL << ptshift) - 1)) { 706 /* Misaligned PPN */ 707 return TRANSLATE_FAIL; 708 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 709 ((pte & PTE_X) && mxr))) { 710 /* Read access check failed */ 711 return TRANSLATE_FAIL; 712 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 713 /* Write access check failed */ 714 return TRANSLATE_FAIL; 715 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 716 /* Fetch access check failed */ 717 return TRANSLATE_FAIL; 718 } else { 719 /* if necessary, set accessed and dirty bits. */ 720 target_ulong updated_pte = pte | PTE_A | 721 (access_type == MMU_DATA_STORE ? PTE_D : 0); 722 723 /* Page table updates need to be atomic with MTTCG enabled */ 724 if (updated_pte != pte) { 725 /* 726 * - if accessed or dirty bits need updating, and the PTE is 727 * in RAM, then we do so atomically with a compare and swap. 728 * - if the PTE is in IO space or ROM, then it can't be updated 729 * and we return TRANSLATE_FAIL. 730 * - if the PTE changed by the time we went to update it, then 731 * it is no longer valid and we must re-walk the page table. 732 */ 733 MemoryRegion *mr; 734 hwaddr l = sizeof(target_ulong), addr1; 735 mr = address_space_translate(cs->as, pte_addr, 736 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 737 if (memory_region_is_ram(mr)) { 738 target_ulong *pte_pa = 739 qemu_map_ram_ptr(mr->ram_block, addr1); 740 #if TCG_OVERSIZED_GUEST 741 /* MTTCG is not enabled on oversized TCG guests so 742 * page table updates do not need to be atomic */ 743 *pte_pa = pte = updated_pte; 744 #else 745 target_ulong old_pte = 746 qatomic_cmpxchg(pte_pa, pte, updated_pte); 747 if (old_pte != pte) { 748 goto restart; 749 } else { 750 pte = updated_pte; 751 } 752 #endif 753 } else { 754 /* misconfigured PTE in ROM (AD bits are not preset) or 755 * PTE is in IO space and can't be updated atomically */ 756 return TRANSLATE_FAIL; 757 } 758 } 759 760 /* for superpage mappings, make a fake leaf PTE for the TLB's 761 benefit. */ 762 target_ulong vpn = addr >> PGSHIFT; 763 *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | 764 (addr & ~TARGET_PAGE_MASK); 765 766 /* set permissions on the TLB entry */ 767 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 768 *prot |= PAGE_READ; 769 } 770 if ((pte & PTE_X)) { 771 *prot |= PAGE_EXEC; 772 } 773 /* add write permission on stores or if the page is already dirty, 774 so that we TLB miss on later writes to update the dirty bit */ 775 if ((pte & PTE_W) && 776 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 777 *prot |= PAGE_WRITE; 778 } 779 return TRANSLATE_SUCCESS; 780 } 781 } 782 return TRANSLATE_FAIL; 783 } 784 785 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 786 MMUAccessType access_type, bool pmp_violation, 787 bool first_stage, bool two_stage) 788 { 789 CPUState *cs = env_cpu(env); 790 int page_fault_exceptions, vm; 791 uint64_t stap_mode; 792 793 if (riscv_cpu_mxl(env) == MXL_RV32) { 794 stap_mode = SATP32_MODE; 795 } else { 796 stap_mode = SATP64_MODE; 797 } 798 799 if (first_stage) { 800 vm = get_field(env->satp, stap_mode); 801 } else { 802 vm = get_field(env->hgatp, stap_mode); 803 } 804 805 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 806 807 switch (access_type) { 808 case MMU_INST_FETCH: 809 if (riscv_cpu_virt_enabled(env) && !first_stage) { 810 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 811 } else { 812 cs->exception_index = page_fault_exceptions ? 813 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 814 } 815 break; 816 case MMU_DATA_LOAD: 817 if (two_stage && !first_stage) { 818 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 819 } else { 820 cs->exception_index = page_fault_exceptions ? 821 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 822 } 823 break; 824 case MMU_DATA_STORE: 825 if (two_stage && !first_stage) { 826 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 827 } else { 828 cs->exception_index = page_fault_exceptions ? 829 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 830 } 831 break; 832 default: 833 g_assert_not_reached(); 834 } 835 env->badaddr = address; 836 env->two_stage_lookup = two_stage; 837 } 838 839 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 840 { 841 RISCVCPU *cpu = RISCV_CPU(cs); 842 CPURISCVState *env = &cpu->env; 843 hwaddr phys_addr; 844 int prot; 845 int mmu_idx = cpu_mmu_index(&cpu->env, false); 846 847 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 848 true, riscv_cpu_virt_enabled(env), true)) { 849 return -1; 850 } 851 852 if (riscv_cpu_virt_enabled(env)) { 853 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 854 0, mmu_idx, false, true, true)) { 855 return -1; 856 } 857 } 858 859 return phys_addr & TARGET_PAGE_MASK; 860 } 861 862 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 863 vaddr addr, unsigned size, 864 MMUAccessType access_type, 865 int mmu_idx, MemTxAttrs attrs, 866 MemTxResult response, uintptr_t retaddr) 867 { 868 RISCVCPU *cpu = RISCV_CPU(cs); 869 CPURISCVState *env = &cpu->env; 870 871 if (access_type == MMU_DATA_STORE) { 872 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 873 } else if (access_type == MMU_DATA_LOAD) { 874 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 875 } else { 876 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 877 } 878 879 env->badaddr = addr; 880 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 881 riscv_cpu_two_stage_lookup(mmu_idx); 882 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 883 } 884 885 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 886 MMUAccessType access_type, int mmu_idx, 887 uintptr_t retaddr) 888 { 889 RISCVCPU *cpu = RISCV_CPU(cs); 890 CPURISCVState *env = &cpu->env; 891 switch (access_type) { 892 case MMU_INST_FETCH: 893 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 894 break; 895 case MMU_DATA_LOAD: 896 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 897 break; 898 case MMU_DATA_STORE: 899 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 900 break; 901 default: 902 g_assert_not_reached(); 903 } 904 env->badaddr = addr; 905 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 906 riscv_cpu_two_stage_lookup(mmu_idx); 907 riscv_raise_exception(env, cs->exception_index, retaddr); 908 } 909 910 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 911 MMUAccessType access_type, int mmu_idx, 912 bool probe, uintptr_t retaddr) 913 { 914 RISCVCPU *cpu = RISCV_CPU(cs); 915 CPURISCVState *env = &cpu->env; 916 vaddr im_address; 917 hwaddr pa = 0; 918 int prot, prot2, prot_pmp; 919 bool pmp_violation = false; 920 bool first_stage_error = true; 921 bool two_stage_lookup = false; 922 int ret = TRANSLATE_FAIL; 923 int mode = mmu_idx; 924 /* default TLB page size */ 925 target_ulong tlb_size = TARGET_PAGE_SIZE; 926 927 env->guest_phys_fault_addr = 0; 928 929 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 930 __func__, address, access_type, mmu_idx); 931 932 /* MPRV does not affect the virtual-machine load/store 933 instructions, HLV, HLVX, and HSV. */ 934 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 935 mode = get_field(env->hstatus, HSTATUS_SPVP); 936 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 937 get_field(env->mstatus, MSTATUS_MPRV)) { 938 mode = get_field(env->mstatus, MSTATUS_MPP); 939 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 940 two_stage_lookup = true; 941 } 942 } 943 944 if (riscv_cpu_virt_enabled(env) || 945 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 946 access_type != MMU_INST_FETCH)) { 947 /* Two stage lookup */ 948 ret = get_physical_address(env, &pa, &prot, address, 949 &env->guest_phys_fault_addr, access_type, 950 mmu_idx, true, true, false); 951 952 /* 953 * A G-stage exception may be triggered during two state lookup. 954 * And the env->guest_phys_fault_addr has already been set in 955 * get_physical_address(). 956 */ 957 if (ret == TRANSLATE_G_STAGE_FAIL) { 958 first_stage_error = false; 959 access_type = MMU_DATA_LOAD; 960 } 961 962 qemu_log_mask(CPU_LOG_MMU, 963 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 964 TARGET_FMT_plx " prot %d\n", 965 __func__, address, ret, pa, prot); 966 967 if (ret == TRANSLATE_SUCCESS) { 968 /* Second stage lookup */ 969 im_address = pa; 970 971 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 972 access_type, mmu_idx, false, true, 973 false); 974 975 qemu_log_mask(CPU_LOG_MMU, 976 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 977 TARGET_FMT_plx " prot %d\n", 978 __func__, im_address, ret, pa, prot2); 979 980 prot &= prot2; 981 982 if (ret == TRANSLATE_SUCCESS) { 983 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 984 size, access_type, mode); 985 986 qemu_log_mask(CPU_LOG_MMU, 987 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 988 " %d tlb_size " TARGET_FMT_lu "\n", 989 __func__, pa, ret, prot_pmp, tlb_size); 990 991 prot &= prot_pmp; 992 } 993 994 if (ret != TRANSLATE_SUCCESS) { 995 /* 996 * Guest physical address translation failed, this is a HS 997 * level exception 998 */ 999 first_stage_error = false; 1000 env->guest_phys_fault_addr = (im_address | 1001 (address & 1002 (TARGET_PAGE_SIZE - 1))) >> 2; 1003 } 1004 } 1005 } else { 1006 /* Single stage lookup */ 1007 ret = get_physical_address(env, &pa, &prot, address, NULL, 1008 access_type, mmu_idx, true, false, false); 1009 1010 qemu_log_mask(CPU_LOG_MMU, 1011 "%s address=%" VADDR_PRIx " ret %d physical " 1012 TARGET_FMT_plx " prot %d\n", 1013 __func__, address, ret, pa, prot); 1014 1015 if (ret == TRANSLATE_SUCCESS) { 1016 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1017 size, access_type, mode); 1018 1019 qemu_log_mask(CPU_LOG_MMU, 1020 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1021 " %d tlb_size " TARGET_FMT_lu "\n", 1022 __func__, pa, ret, prot_pmp, tlb_size); 1023 1024 prot &= prot_pmp; 1025 } 1026 } 1027 1028 if (ret == TRANSLATE_PMP_FAIL) { 1029 pmp_violation = true; 1030 } 1031 1032 if (ret == TRANSLATE_SUCCESS) { 1033 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1034 prot, mmu_idx, tlb_size); 1035 return true; 1036 } else if (probe) { 1037 return false; 1038 } else { 1039 raise_mmu_exception(env, address, access_type, pmp_violation, 1040 first_stage_error, 1041 riscv_cpu_virt_enabled(env) || 1042 riscv_cpu_two_stage_lookup(mmu_idx)); 1043 riscv_raise_exception(env, cs->exception_index, retaddr); 1044 } 1045 1046 return true; 1047 } 1048 #endif /* !CONFIG_USER_ONLY */ 1049 1050 /* 1051 * Handle Traps 1052 * 1053 * Adapted from Spike's processor_t::take_trap. 1054 * 1055 */ 1056 void riscv_cpu_do_interrupt(CPUState *cs) 1057 { 1058 #if !defined(CONFIG_USER_ONLY) 1059 1060 RISCVCPU *cpu = RISCV_CPU(cs); 1061 CPURISCVState *env = &cpu->env; 1062 bool write_gva = false; 1063 uint64_t s; 1064 1065 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1066 * so we mask off the MSB and separate into trap type and cause. 1067 */ 1068 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1069 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1070 target_ulong deleg = async ? env->mideleg : env->medeleg; 1071 target_ulong tval = 0; 1072 target_ulong htval = 0; 1073 target_ulong mtval2 = 0; 1074 1075 if (cause == RISCV_EXCP_SEMIHOST) { 1076 if (env->priv >= PRV_S) { 1077 env->gpr[xA0] = do_common_semihosting(cs); 1078 env->pc += 4; 1079 return; 1080 } 1081 cause = RISCV_EXCP_BREAKPOINT; 1082 } 1083 1084 if (!async) { 1085 /* set tval to badaddr for traps with address information */ 1086 switch (cause) { 1087 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1088 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1089 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1090 case RISCV_EXCP_INST_ADDR_MIS: 1091 case RISCV_EXCP_INST_ACCESS_FAULT: 1092 case RISCV_EXCP_LOAD_ADDR_MIS: 1093 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1094 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1095 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1096 case RISCV_EXCP_INST_PAGE_FAULT: 1097 case RISCV_EXCP_LOAD_PAGE_FAULT: 1098 case RISCV_EXCP_STORE_PAGE_FAULT: 1099 write_gva = true; 1100 tval = env->badaddr; 1101 break; 1102 case RISCV_EXCP_ILLEGAL_INST: 1103 tval = env->bins; 1104 break; 1105 default: 1106 break; 1107 } 1108 /* ecall is dispatched as one cause so translate based on mode */ 1109 if (cause == RISCV_EXCP_U_ECALL) { 1110 assert(env->priv <= 3); 1111 1112 if (env->priv == PRV_M) { 1113 cause = RISCV_EXCP_M_ECALL; 1114 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1115 cause = RISCV_EXCP_VS_ECALL; 1116 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1117 cause = RISCV_EXCP_S_ECALL; 1118 } else if (env->priv == PRV_U) { 1119 cause = RISCV_EXCP_U_ECALL; 1120 } 1121 } 1122 } 1123 1124 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1125 riscv_cpu_get_trap_name(cause, async)); 1126 1127 qemu_log_mask(CPU_LOG_INT, 1128 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1129 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1130 __func__, env->mhartid, async, cause, env->pc, tval, 1131 riscv_cpu_get_trap_name(cause, async)); 1132 1133 if (env->priv <= PRV_S && 1134 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1135 /* handle the trap in S-mode */ 1136 if (riscv_has_ext(env, RVH)) { 1137 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 1138 1139 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1140 /* Trap to VS mode */ 1141 /* 1142 * See if we need to adjust cause. Yes if its VS mode interrupt 1143 * no if hypervisor has delegated one of hs mode's interrupt 1144 */ 1145 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1146 cause == IRQ_VS_EXT) { 1147 cause = cause - 1; 1148 } 1149 write_gva = false; 1150 } else if (riscv_cpu_virt_enabled(env)) { 1151 /* Trap into HS mode, from virt */ 1152 riscv_cpu_swap_hypervisor_regs(env); 1153 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1154 env->priv); 1155 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1156 riscv_cpu_virt_enabled(env)); 1157 1158 1159 htval = env->guest_phys_fault_addr; 1160 1161 riscv_cpu_set_virt_enabled(env, 0); 1162 } else { 1163 /* Trap into HS mode */ 1164 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1165 htval = env->guest_phys_fault_addr; 1166 write_gva = false; 1167 } 1168 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1169 } 1170 1171 s = env->mstatus; 1172 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1173 s = set_field(s, MSTATUS_SPP, env->priv); 1174 s = set_field(s, MSTATUS_SIE, 0); 1175 env->mstatus = s; 1176 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1177 env->sepc = env->pc; 1178 env->stval = tval; 1179 env->htval = htval; 1180 env->pc = (env->stvec >> 2 << 2) + 1181 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1182 riscv_cpu_set_mode(env, PRV_S); 1183 } else { 1184 /* handle the trap in M-mode */ 1185 if (riscv_has_ext(env, RVH)) { 1186 if (riscv_cpu_virt_enabled(env)) { 1187 riscv_cpu_swap_hypervisor_regs(env); 1188 } 1189 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1190 riscv_cpu_virt_enabled(env)); 1191 if (riscv_cpu_virt_enabled(env) && tval) { 1192 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1193 } 1194 1195 mtval2 = env->guest_phys_fault_addr; 1196 1197 /* Trapping to M mode, virt is disabled */ 1198 riscv_cpu_set_virt_enabled(env, 0); 1199 } 1200 1201 s = env->mstatus; 1202 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1203 s = set_field(s, MSTATUS_MPP, env->priv); 1204 s = set_field(s, MSTATUS_MIE, 0); 1205 env->mstatus = s; 1206 env->mcause = cause | ~(((target_ulong)-1) >> async); 1207 env->mepc = env->pc; 1208 env->mtval = tval; 1209 env->mtval2 = mtval2; 1210 env->pc = (env->mtvec >> 2 << 2) + 1211 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1212 riscv_cpu_set_mode(env, PRV_M); 1213 } 1214 1215 /* NOTE: it is not necessary to yield load reservations here. It is only 1216 * necessary for an SC from "another hart" to cause a load reservation 1217 * to be yielded. Refer to the memory consistency model section of the 1218 * RISC-V ISA Specification. 1219 */ 1220 1221 env->two_stage_lookup = false; 1222 #endif 1223 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1224 } 1225