1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 } else { 78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 79 } 80 81 #ifdef CONFIG_USER_ONLY 82 flags |= TB_FLAGS_MSTATUS_FS; 83 flags |= TB_FLAGS_MSTATUS_VS; 84 #else 85 flags |= cpu_mmu_index(env, 0); 86 if (riscv_cpu_fp_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_FS; 88 } 89 90 if (riscv_cpu_vector_enabled(env)) { 91 flags |= env->mstatus & MSTATUS_VS; 92 } 93 94 if (riscv_has_ext(env, RVH)) { 95 if (env->priv == PRV_M || 96 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 97 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 98 get_field(env->hstatus, HSTATUS_HU))) { 99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 100 } 101 102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 103 get_field(env->mstatus_hs, MSTATUS_FS)); 104 105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 106 get_field(env->mstatus_hs, MSTATUS_VS)); 107 } 108 if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, 110 riscv_itrigger_enabled(env)); 111 } 112 #endif 113 114 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 115 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 116 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 117 } 118 if (env->cur_pmbase != 0) { 119 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 120 } 121 122 *pflags = flags; 123 } 124 125 void riscv_cpu_update_mask(CPURISCVState *env) 126 { 127 target_ulong mask = -1, base = 0; 128 /* 129 * TODO: Current RVJ spec does not specify 130 * how the extension interacts with XLEN. 131 */ 132 #ifndef CONFIG_USER_ONLY 133 if (riscv_has_ext(env, RVJ)) { 134 switch (env->priv) { 135 case PRV_M: 136 if (env->mmte & M_PM_ENABLE) { 137 mask = env->mpmmask; 138 base = env->mpmbase; 139 } 140 break; 141 case PRV_S: 142 if (env->mmte & S_PM_ENABLE) { 143 mask = env->spmmask; 144 base = env->spmbase; 145 } 146 break; 147 case PRV_U: 148 if (env->mmte & U_PM_ENABLE) { 149 mask = env->upmmask; 150 base = env->upmbase; 151 } 152 break; 153 default: 154 g_assert_not_reached(); 155 } 156 } 157 #endif 158 if (env->xl == MXL_RV32) { 159 env->cur_pmmask = mask & UINT32_MAX; 160 env->cur_pmbase = base & UINT32_MAX; 161 } else { 162 env->cur_pmmask = mask; 163 env->cur_pmbase = base; 164 } 165 } 166 167 #ifndef CONFIG_USER_ONLY 168 169 /* 170 * The HS-mode is allowed to configure priority only for the 171 * following VS-mode local interrupts: 172 * 173 * 0 (Reserved interrupt, reads as zero) 174 * 1 Supervisor software interrupt 175 * 4 (Reserved interrupt, reads as zero) 176 * 5 Supervisor timer interrupt 177 * 8 (Reserved interrupt, reads as zero) 178 * 13 (Reserved interrupt) 179 * 14 " 180 * 15 " 181 * 16 " 182 * 17 " 183 * 18 " 184 * 19 " 185 * 20 " 186 * 21 " 187 * 22 " 188 * 23 " 189 */ 190 191 static const int hviprio_index2irq[] = { 192 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 193 static const int hviprio_index2rdzero[] = { 194 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 195 196 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 197 { 198 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 199 return -EINVAL; 200 } 201 202 if (out_irq) { 203 *out_irq = hviprio_index2irq[index]; 204 } 205 206 if (out_rdzero) { 207 *out_rdzero = hviprio_index2rdzero[index]; 208 } 209 210 return 0; 211 } 212 213 /* 214 * Default priorities of local interrupts are defined in the 215 * RISC-V Advanced Interrupt Architecture specification. 216 * 217 * ---------------------------------------------------------------- 218 * Default | 219 * Priority | Major Interrupt Numbers 220 * ---------------------------------------------------------------- 221 * Highest | 47, 23, 46, 45, 22, 44, 222 * | 43, 21, 42, 41, 20, 40 223 * | 224 * | 11 (0b), 3 (03), 7 (07) 225 * | 9 (09), 1 (01), 5 (05) 226 * | 12 (0c) 227 * | 10 (0a), 2 (02), 6 (06) 228 * | 229 * | 39, 19, 38, 37, 18, 36, 230 * Lowest | 35, 17, 34, 33, 16, 32 231 * ---------------------------------------------------------------- 232 */ 233 static const uint8_t default_iprio[64] = { 234 /* Custom interrupts 48 to 63 */ 235 [63] = IPRIO_MMAXIPRIO, 236 [62] = IPRIO_MMAXIPRIO, 237 [61] = IPRIO_MMAXIPRIO, 238 [60] = IPRIO_MMAXIPRIO, 239 [59] = IPRIO_MMAXIPRIO, 240 [58] = IPRIO_MMAXIPRIO, 241 [57] = IPRIO_MMAXIPRIO, 242 [56] = IPRIO_MMAXIPRIO, 243 [55] = IPRIO_MMAXIPRIO, 244 [54] = IPRIO_MMAXIPRIO, 245 [53] = IPRIO_MMAXIPRIO, 246 [52] = IPRIO_MMAXIPRIO, 247 [51] = IPRIO_MMAXIPRIO, 248 [50] = IPRIO_MMAXIPRIO, 249 [49] = IPRIO_MMAXIPRIO, 250 [48] = IPRIO_MMAXIPRIO, 251 252 /* Custom interrupts 24 to 31 */ 253 [31] = IPRIO_MMAXIPRIO, 254 [30] = IPRIO_MMAXIPRIO, 255 [29] = IPRIO_MMAXIPRIO, 256 [28] = IPRIO_MMAXIPRIO, 257 [27] = IPRIO_MMAXIPRIO, 258 [26] = IPRIO_MMAXIPRIO, 259 [25] = IPRIO_MMAXIPRIO, 260 [24] = IPRIO_MMAXIPRIO, 261 262 [47] = IPRIO_DEFAULT_UPPER, 263 [23] = IPRIO_DEFAULT_UPPER + 1, 264 [46] = IPRIO_DEFAULT_UPPER + 2, 265 [45] = IPRIO_DEFAULT_UPPER + 3, 266 [22] = IPRIO_DEFAULT_UPPER + 4, 267 [44] = IPRIO_DEFAULT_UPPER + 5, 268 269 [43] = IPRIO_DEFAULT_UPPER + 6, 270 [21] = IPRIO_DEFAULT_UPPER + 7, 271 [42] = IPRIO_DEFAULT_UPPER + 8, 272 [41] = IPRIO_DEFAULT_UPPER + 9, 273 [20] = IPRIO_DEFAULT_UPPER + 10, 274 [40] = IPRIO_DEFAULT_UPPER + 11, 275 276 [11] = IPRIO_DEFAULT_M, 277 [3] = IPRIO_DEFAULT_M + 1, 278 [7] = IPRIO_DEFAULT_M + 2, 279 280 [9] = IPRIO_DEFAULT_S, 281 [1] = IPRIO_DEFAULT_S + 1, 282 [5] = IPRIO_DEFAULT_S + 2, 283 284 [12] = IPRIO_DEFAULT_SGEXT, 285 286 [10] = IPRIO_DEFAULT_VS, 287 [2] = IPRIO_DEFAULT_VS + 1, 288 [6] = IPRIO_DEFAULT_VS + 2, 289 290 [39] = IPRIO_DEFAULT_LOWER, 291 [19] = IPRIO_DEFAULT_LOWER + 1, 292 [38] = IPRIO_DEFAULT_LOWER + 2, 293 [37] = IPRIO_DEFAULT_LOWER + 3, 294 [18] = IPRIO_DEFAULT_LOWER + 4, 295 [36] = IPRIO_DEFAULT_LOWER + 5, 296 297 [35] = IPRIO_DEFAULT_LOWER + 6, 298 [17] = IPRIO_DEFAULT_LOWER + 7, 299 [34] = IPRIO_DEFAULT_LOWER + 8, 300 [33] = IPRIO_DEFAULT_LOWER + 9, 301 [16] = IPRIO_DEFAULT_LOWER + 10, 302 [32] = IPRIO_DEFAULT_LOWER + 11, 303 }; 304 305 uint8_t riscv_cpu_default_priority(int irq) 306 { 307 if (irq < 0 || irq > 63) { 308 return IPRIO_MMAXIPRIO; 309 } 310 311 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 312 }; 313 314 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 315 int extirq, unsigned int extirq_def_prio, 316 uint64_t pending, uint8_t *iprio) 317 { 318 RISCVCPU *cpu = env_archcpu(env); 319 int irq, best_irq = RISCV_EXCP_NONE; 320 unsigned int prio, best_prio = UINT_MAX; 321 322 if (!pending) { 323 return RISCV_EXCP_NONE; 324 } 325 326 irq = ctz64(pending); 327 if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) { 328 return irq; 329 } 330 331 pending = pending >> irq; 332 while (pending) { 333 prio = iprio[irq]; 334 if (!prio) { 335 if (irq == extirq) { 336 prio = extirq_def_prio; 337 } else { 338 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 339 1 : IPRIO_MMAXIPRIO; 340 } 341 } 342 if ((pending & 0x1) && (prio <= best_prio)) { 343 best_irq = irq; 344 best_prio = prio; 345 } 346 irq++; 347 pending = pending >> 1; 348 } 349 350 return best_irq; 351 } 352 353 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 354 { 355 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 356 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 357 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 358 359 return (env->mip | vsgein | vstip) & env->mie; 360 } 361 362 int riscv_cpu_mirq_pending(CPURISCVState *env) 363 { 364 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 365 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 366 367 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 368 irqs, env->miprio); 369 } 370 371 int riscv_cpu_sirq_pending(CPURISCVState *env) 372 { 373 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 374 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 375 376 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 377 irqs, env->siprio); 378 } 379 380 int riscv_cpu_vsirq_pending(CPURISCVState *env) 381 { 382 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 383 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 384 385 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 386 irqs >> 1, env->hviprio); 387 } 388 389 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 390 { 391 int virq; 392 uint64_t irqs, pending, mie, hsie, vsie; 393 394 /* Determine interrupt enable state of all privilege modes */ 395 if (riscv_cpu_virt_enabled(env)) { 396 mie = 1; 397 hsie = 1; 398 vsie = (env->priv < PRV_S) || 399 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 400 } else { 401 mie = (env->priv < PRV_M) || 402 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 403 hsie = (env->priv < PRV_S) || 404 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 405 vsie = 0; 406 } 407 408 /* Determine all pending interrupts */ 409 pending = riscv_cpu_all_pending(env); 410 411 /* Check M-mode interrupts */ 412 irqs = pending & ~env->mideleg & -mie; 413 if (irqs) { 414 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 415 irqs, env->miprio); 416 } 417 418 /* Check HS-mode interrupts */ 419 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 420 if (irqs) { 421 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 422 irqs, env->siprio); 423 } 424 425 /* Check VS-mode interrupts */ 426 irqs = pending & env->mideleg & env->hideleg & -vsie; 427 if (irqs) { 428 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 429 irqs >> 1, env->hviprio); 430 return (virq <= 0) ? virq : virq + 1; 431 } 432 433 /* Indicate no pending interrupt */ 434 return RISCV_EXCP_NONE; 435 } 436 437 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 438 { 439 if (interrupt_request & CPU_INTERRUPT_HARD) { 440 RISCVCPU *cpu = RISCV_CPU(cs); 441 CPURISCVState *env = &cpu->env; 442 int interruptno = riscv_cpu_local_irq_pending(env); 443 if (interruptno >= 0) { 444 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 445 riscv_cpu_do_interrupt(cs); 446 return true; 447 } 448 } 449 return false; 450 } 451 452 /* Return true is floating point support is currently enabled */ 453 bool riscv_cpu_fp_enabled(CPURISCVState *env) 454 { 455 if (env->mstatus & MSTATUS_FS) { 456 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 457 return false; 458 } 459 return true; 460 } 461 462 return false; 463 } 464 465 /* Return true is vector support is currently enabled */ 466 bool riscv_cpu_vector_enabled(CPURISCVState *env) 467 { 468 if (env->mstatus & MSTATUS_VS) { 469 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 470 return false; 471 } 472 return true; 473 } 474 475 return false; 476 } 477 478 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 479 { 480 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 481 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 482 MSTATUS64_UXL | MSTATUS_VS; 483 484 if (riscv_has_ext(env, RVF)) { 485 mstatus_mask |= MSTATUS_FS; 486 } 487 bool current_virt = riscv_cpu_virt_enabled(env); 488 489 g_assert(riscv_has_ext(env, RVH)); 490 491 if (current_virt) { 492 /* Current V=1 and we are about to change to V=0 */ 493 env->vsstatus = env->mstatus & mstatus_mask; 494 env->mstatus &= ~mstatus_mask; 495 env->mstatus |= env->mstatus_hs; 496 497 env->vstvec = env->stvec; 498 env->stvec = env->stvec_hs; 499 500 env->vsscratch = env->sscratch; 501 env->sscratch = env->sscratch_hs; 502 503 env->vsepc = env->sepc; 504 env->sepc = env->sepc_hs; 505 506 env->vscause = env->scause; 507 env->scause = env->scause_hs; 508 509 env->vstval = env->stval; 510 env->stval = env->stval_hs; 511 512 env->vsatp = env->satp; 513 env->satp = env->satp_hs; 514 } else { 515 /* Current V=0 and we are about to change to V=1 */ 516 env->mstatus_hs = env->mstatus & mstatus_mask; 517 env->mstatus &= ~mstatus_mask; 518 env->mstatus |= env->vsstatus; 519 520 env->stvec_hs = env->stvec; 521 env->stvec = env->vstvec; 522 523 env->sscratch_hs = env->sscratch; 524 env->sscratch = env->vsscratch; 525 526 env->sepc_hs = env->sepc; 527 env->sepc = env->vsepc; 528 529 env->scause_hs = env->scause; 530 env->scause = env->vscause; 531 532 env->stval_hs = env->stval; 533 env->stval = env->vstval; 534 535 env->satp_hs = env->satp; 536 env->satp = env->vsatp; 537 } 538 } 539 540 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 541 { 542 if (!riscv_has_ext(env, RVH)) { 543 return 0; 544 } 545 546 return env->geilen; 547 } 548 549 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 550 { 551 if (!riscv_has_ext(env, RVH)) { 552 return; 553 } 554 555 if (geilen > (TARGET_LONG_BITS - 1)) { 556 return; 557 } 558 559 env->geilen = geilen; 560 } 561 562 bool riscv_cpu_virt_enabled(CPURISCVState *env) 563 { 564 if (!riscv_has_ext(env, RVH)) { 565 return false; 566 } 567 568 return get_field(env->virt, VIRT_ONOFF); 569 } 570 571 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 572 { 573 if (!riscv_has_ext(env, RVH)) { 574 return; 575 } 576 577 /* Flush the TLB on all virt mode changes. */ 578 if (get_field(env->virt, VIRT_ONOFF) != enable) { 579 tlb_flush(env_cpu(env)); 580 } 581 582 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 583 584 if (enable) { 585 /* 586 * The guest external interrupts from an interrupt controller are 587 * delivered only when the Guest/VM is running (i.e. V=1). This means 588 * any guest external interrupt which is triggered while the Guest/VM 589 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 590 * with sluggish response to serial console input and other I/O events. 591 * 592 * To solve this, we check and inject interrupt after setting V=1. 593 */ 594 riscv_cpu_update_mip(env_archcpu(env), 0, 0); 595 } 596 } 597 598 bool riscv_cpu_two_stage_lookup(int mmu_idx) 599 { 600 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 601 } 602 603 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 604 { 605 CPURISCVState *env = &cpu->env; 606 if (env->miclaim & interrupts) { 607 return -1; 608 } else { 609 env->miclaim |= interrupts; 610 return 0; 611 } 612 } 613 614 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) 615 { 616 CPURISCVState *env = &cpu->env; 617 CPUState *cs = CPU(cpu); 618 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 619 bool locked = false; 620 621 if (riscv_cpu_virt_enabled(env)) { 622 gein = get_field(env->hstatus, HSTATUS_VGEIN); 623 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 624 } 625 626 /* No need to update mip for VSTIP */ 627 mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; 628 vstip = env->vstime_irq ? MIP_VSTIP : 0; 629 630 if (!qemu_mutex_iothread_locked()) { 631 locked = true; 632 qemu_mutex_lock_iothread(); 633 } 634 635 env->mip = (env->mip & ~mask) | (value & mask); 636 637 if (env->mip | vsgein | vstip) { 638 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 639 } else { 640 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 641 } 642 643 if (locked) { 644 qemu_mutex_unlock_iothread(); 645 } 646 647 return old; 648 } 649 650 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 651 void *arg) 652 { 653 env->rdtime_fn = fn; 654 env->rdtime_fn_arg = arg; 655 } 656 657 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 658 int (*rmw_fn)(void *arg, 659 target_ulong reg, 660 target_ulong *val, 661 target_ulong new_val, 662 target_ulong write_mask), 663 void *rmw_fn_arg) 664 { 665 if (priv <= PRV_M) { 666 env->aia_ireg_rmw_fn[priv] = rmw_fn; 667 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 668 } 669 } 670 671 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 672 { 673 if (newpriv > PRV_M) { 674 g_assert_not_reached(); 675 } 676 if (newpriv == PRV_H) { 677 newpriv = PRV_U; 678 } 679 if (icount_enabled() && newpriv != env->priv) { 680 riscv_itrigger_update_priv(env); 681 } 682 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 683 env->priv = newpriv; 684 env->xl = cpu_recompute_xl(env); 685 riscv_cpu_update_mask(env); 686 687 /* 688 * Clear the load reservation - otherwise a reservation placed in one 689 * context/process can be used by another, resulting in an SC succeeding 690 * incorrectly. Version 2.2 of the ISA specification explicitly requires 691 * this behaviour, while later revisions say that the kernel "should" use 692 * an SC instruction to force the yielding of a load reservation on a 693 * preemptive context switch. As a result, do both. 694 */ 695 env->load_res = -1; 696 } 697 698 /* 699 * get_physical_address_pmp - check PMP permission for this physical address 700 * 701 * Match the PMP region and check permission for this physical address and it's 702 * TLB page. Returns 0 if the permission checking was successful 703 * 704 * @env: CPURISCVState 705 * @prot: The returned protection attributes 706 * @tlb_size: TLB page size containing addr. It could be modified after PMP 707 * permission checking. NULL if not set TLB page for addr. 708 * @addr: The physical address to be checked permission 709 * @access_type: The type of MMU access 710 * @mode: Indicates current privilege level. 711 */ 712 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 713 target_ulong *tlb_size, hwaddr addr, 714 int size, MMUAccessType access_type, 715 int mode) 716 { 717 pmp_priv_t pmp_priv; 718 int pmp_index = -1; 719 720 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 721 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 722 return TRANSLATE_SUCCESS; 723 } 724 725 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 726 &pmp_priv, mode); 727 if (pmp_index < 0) { 728 *prot = 0; 729 return TRANSLATE_PMP_FAIL; 730 } 731 732 *prot = pmp_priv_to_page_prot(pmp_priv); 733 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 734 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 735 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 736 737 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 738 } 739 740 return TRANSLATE_SUCCESS; 741 } 742 743 /* get_physical_address - get the physical address for this virtual address 744 * 745 * Do a page table walk to obtain the physical address corresponding to a 746 * virtual address. Returns 0 if the translation was successful 747 * 748 * Adapted from Spike's mmu_t::translate and mmu_t::walk 749 * 750 * @env: CPURISCVState 751 * @physical: This will be set to the calculated physical address 752 * @prot: The returned protection attributes 753 * @addr: The virtual address to be translated 754 * @fault_pte_addr: If not NULL, this will be set to fault pte address 755 * when a error occurs on pte address translation. 756 * This will already be shifted to match htval. 757 * @access_type: The type of MMU access 758 * @mmu_idx: Indicates current privilege level 759 * @first_stage: Are we in first stage translation? 760 * Second stage is used for hypervisor guest translation 761 * @two_stage: Are we going to perform two stage translation 762 * @is_debug: Is this access from a debugger or the monitor? 763 */ 764 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 765 int *prot, target_ulong addr, 766 target_ulong *fault_pte_addr, 767 int access_type, int mmu_idx, 768 bool first_stage, bool two_stage, 769 bool is_debug) 770 { 771 /* NOTE: the env->pc value visible here will not be 772 * correct, but the value visible to the exception handler 773 * (riscv_cpu_do_interrupt) is correct */ 774 MemTxResult res; 775 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 776 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 777 bool use_background = false; 778 hwaddr ppn; 779 RISCVCPU *cpu = env_archcpu(env); 780 int napot_bits = 0; 781 target_ulong napot_mask; 782 783 /* 784 * Check if we should use the background registers for the two 785 * stage translation. We don't need to check if we actually need 786 * two stage translation as that happened before this function 787 * was called. Background registers will be used if the guest has 788 * forced a two stage translation to be on (in HS or M mode). 789 */ 790 if (!riscv_cpu_virt_enabled(env) && two_stage) { 791 use_background = true; 792 } 793 794 /* MPRV does not affect the virtual-machine load/store 795 instructions, HLV, HLVX, and HSV. */ 796 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 797 mode = get_field(env->hstatus, HSTATUS_SPVP); 798 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 799 if (get_field(env->mstatus, MSTATUS_MPRV)) { 800 mode = get_field(env->mstatus, MSTATUS_MPP); 801 } 802 } 803 804 if (first_stage == false) { 805 /* We are in stage 2 translation, this is similar to stage 1. */ 806 /* Stage 2 is always taken as U-mode */ 807 mode = PRV_U; 808 } 809 810 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 811 *physical = addr; 812 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 813 return TRANSLATE_SUCCESS; 814 } 815 816 *prot = 0; 817 818 hwaddr base; 819 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 820 821 if (first_stage == true) { 822 mxr = get_field(env->mstatus, MSTATUS_MXR); 823 } else { 824 mxr = get_field(env->vsstatus, MSTATUS_MXR); 825 } 826 827 if (first_stage == true) { 828 if (use_background) { 829 if (riscv_cpu_mxl(env) == MXL_RV32) { 830 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 831 vm = get_field(env->vsatp, SATP32_MODE); 832 } else { 833 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 834 vm = get_field(env->vsatp, SATP64_MODE); 835 } 836 } else { 837 if (riscv_cpu_mxl(env) == MXL_RV32) { 838 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 839 vm = get_field(env->satp, SATP32_MODE); 840 } else { 841 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 842 vm = get_field(env->satp, SATP64_MODE); 843 } 844 } 845 widened = 0; 846 } else { 847 if (riscv_cpu_mxl(env) == MXL_RV32) { 848 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 849 vm = get_field(env->hgatp, SATP32_MODE); 850 } else { 851 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 852 vm = get_field(env->hgatp, SATP64_MODE); 853 } 854 widened = 2; 855 } 856 /* status.SUM will be ignored if execute on background */ 857 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 858 switch (vm) { 859 case VM_1_10_SV32: 860 levels = 2; ptidxbits = 10; ptesize = 4; break; 861 case VM_1_10_SV39: 862 levels = 3; ptidxbits = 9; ptesize = 8; break; 863 case VM_1_10_SV48: 864 levels = 4; ptidxbits = 9; ptesize = 8; break; 865 case VM_1_10_SV57: 866 levels = 5; ptidxbits = 9; ptesize = 8; break; 867 case VM_1_10_MBARE: 868 *physical = addr; 869 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 870 return TRANSLATE_SUCCESS; 871 default: 872 g_assert_not_reached(); 873 } 874 875 CPUState *cs = env_cpu(env); 876 int va_bits = PGSHIFT + levels * ptidxbits + widened; 877 target_ulong mask, masked_msbs; 878 879 if (TARGET_LONG_BITS > (va_bits - 1)) { 880 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 881 } else { 882 mask = 0; 883 } 884 masked_msbs = (addr >> (va_bits - 1)) & mask; 885 886 if (masked_msbs != 0 && masked_msbs != mask) { 887 return TRANSLATE_FAIL; 888 } 889 890 int ptshift = (levels - 1) * ptidxbits; 891 int i; 892 893 #if !TCG_OVERSIZED_GUEST 894 restart: 895 #endif 896 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 897 target_ulong idx; 898 if (i == 0) { 899 idx = (addr >> (PGSHIFT + ptshift)) & 900 ((1 << (ptidxbits + widened)) - 1); 901 } else { 902 idx = (addr >> (PGSHIFT + ptshift)) & 903 ((1 << ptidxbits) - 1); 904 } 905 906 /* check that physical address of PTE is legal */ 907 hwaddr pte_addr; 908 909 if (two_stage && first_stage) { 910 int vbase_prot; 911 hwaddr vbase; 912 913 /* Do the second stage translation on the base PTE address. */ 914 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 915 base, NULL, MMU_DATA_LOAD, 916 mmu_idx, false, true, 917 is_debug); 918 919 if (vbase_ret != TRANSLATE_SUCCESS) { 920 if (fault_pte_addr) { 921 *fault_pte_addr = (base + idx * ptesize) >> 2; 922 } 923 return TRANSLATE_G_STAGE_FAIL; 924 } 925 926 pte_addr = vbase + idx * ptesize; 927 } else { 928 pte_addr = base + idx * ptesize; 929 } 930 931 int pmp_prot; 932 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 933 sizeof(target_ulong), 934 MMU_DATA_LOAD, PRV_S); 935 if (pmp_ret != TRANSLATE_SUCCESS) { 936 return TRANSLATE_PMP_FAIL; 937 } 938 939 target_ulong pte; 940 if (riscv_cpu_mxl(env) == MXL_RV32) { 941 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 942 } else { 943 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 944 } 945 946 if (res != MEMTX_OK) { 947 return TRANSLATE_FAIL; 948 } 949 950 if (riscv_cpu_sxl(env) == MXL_RV32) { 951 ppn = pte >> PTE_PPN_SHIFT; 952 } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { 953 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 954 } else { 955 ppn = pte >> PTE_PPN_SHIFT; 956 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 957 return TRANSLATE_FAIL; 958 } 959 } 960 961 if (!(pte & PTE_V)) { 962 /* Invalid PTE */ 963 return TRANSLATE_FAIL; 964 } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { 965 return TRANSLATE_FAIL; 966 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 967 /* Inner PTE, continue walking */ 968 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 969 return TRANSLATE_FAIL; 970 } 971 base = ppn << PGSHIFT; 972 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 973 /* Reserved leaf PTE flags: PTE_W */ 974 return TRANSLATE_FAIL; 975 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 976 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 977 return TRANSLATE_FAIL; 978 } else if ((pte & PTE_U) && ((mode != PRV_U) && 979 (!sum || access_type == MMU_INST_FETCH))) { 980 /* User PTE flags when not U mode and mstatus.SUM is not set, 981 or the access type is an instruction fetch */ 982 return TRANSLATE_FAIL; 983 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 984 /* Supervisor PTE flags when not S mode */ 985 return TRANSLATE_FAIL; 986 } else if (ppn & ((1ULL << ptshift) - 1)) { 987 /* Misaligned PPN */ 988 return TRANSLATE_FAIL; 989 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 990 ((pte & PTE_X) && mxr))) { 991 /* Read access check failed */ 992 return TRANSLATE_FAIL; 993 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 994 /* Write access check failed */ 995 return TRANSLATE_FAIL; 996 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 997 /* Fetch access check failed */ 998 return TRANSLATE_FAIL; 999 } else { 1000 /* if necessary, set accessed and dirty bits. */ 1001 target_ulong updated_pte = pte | PTE_A | 1002 (access_type == MMU_DATA_STORE ? PTE_D : 0); 1003 1004 /* Page table updates need to be atomic with MTTCG enabled */ 1005 if (updated_pte != pte) { 1006 /* 1007 * - if accessed or dirty bits need updating, and the PTE is 1008 * in RAM, then we do so atomically with a compare and swap. 1009 * - if the PTE is in IO space or ROM, then it can't be updated 1010 * and we return TRANSLATE_FAIL. 1011 * - if the PTE changed by the time we went to update it, then 1012 * it is no longer valid and we must re-walk the page table. 1013 */ 1014 MemoryRegion *mr; 1015 hwaddr l = sizeof(target_ulong), addr1; 1016 mr = address_space_translate(cs->as, pte_addr, 1017 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 1018 if (memory_region_is_ram(mr)) { 1019 target_ulong *pte_pa = 1020 qemu_map_ram_ptr(mr->ram_block, addr1); 1021 #if TCG_OVERSIZED_GUEST 1022 /* MTTCG is not enabled on oversized TCG guests so 1023 * page table updates do not need to be atomic */ 1024 *pte_pa = pte = updated_pte; 1025 #else 1026 target_ulong old_pte = 1027 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1028 if (old_pte != pte) { 1029 goto restart; 1030 } else { 1031 pte = updated_pte; 1032 } 1033 #endif 1034 } else { 1035 /* misconfigured PTE in ROM (AD bits are not preset) or 1036 * PTE is in IO space and can't be updated atomically */ 1037 return TRANSLATE_FAIL; 1038 } 1039 } 1040 1041 /* for superpage mappings, make a fake leaf PTE for the TLB's 1042 benefit. */ 1043 target_ulong vpn = addr >> PGSHIFT; 1044 1045 if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { 1046 napot_bits = ctzl(ppn) + 1; 1047 if ((i != (levels - 1)) || (napot_bits != 4)) { 1048 return TRANSLATE_FAIL; 1049 } 1050 } 1051 1052 napot_mask = (1 << napot_bits) - 1; 1053 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1054 (vpn & (((target_ulong)1 << ptshift) - 1)) 1055 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1056 1057 /* set permissions on the TLB entry */ 1058 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1059 *prot |= PAGE_READ; 1060 } 1061 if ((pte & PTE_X)) { 1062 *prot |= PAGE_EXEC; 1063 } 1064 /* add write permission on stores or if the page is already dirty, 1065 so that we TLB miss on later writes to update the dirty bit */ 1066 if ((pte & PTE_W) && 1067 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1068 *prot |= PAGE_WRITE; 1069 } 1070 return TRANSLATE_SUCCESS; 1071 } 1072 } 1073 return TRANSLATE_FAIL; 1074 } 1075 1076 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1077 MMUAccessType access_type, bool pmp_violation, 1078 bool first_stage, bool two_stage, 1079 bool two_stage_indirect) 1080 { 1081 CPUState *cs = env_cpu(env); 1082 int page_fault_exceptions, vm; 1083 uint64_t stap_mode; 1084 1085 if (riscv_cpu_mxl(env) == MXL_RV32) { 1086 stap_mode = SATP32_MODE; 1087 } else { 1088 stap_mode = SATP64_MODE; 1089 } 1090 1091 if (first_stage) { 1092 vm = get_field(env->satp, stap_mode); 1093 } else { 1094 vm = get_field(env->hgatp, stap_mode); 1095 } 1096 1097 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1098 1099 switch (access_type) { 1100 case MMU_INST_FETCH: 1101 if (riscv_cpu_virt_enabled(env) && !first_stage) { 1102 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1103 } else { 1104 cs->exception_index = page_fault_exceptions ? 1105 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1106 } 1107 break; 1108 case MMU_DATA_LOAD: 1109 if (two_stage && !first_stage) { 1110 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1111 } else { 1112 cs->exception_index = page_fault_exceptions ? 1113 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1114 } 1115 break; 1116 case MMU_DATA_STORE: 1117 if (two_stage && !first_stage) { 1118 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1119 } else { 1120 cs->exception_index = page_fault_exceptions ? 1121 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1122 } 1123 break; 1124 default: 1125 g_assert_not_reached(); 1126 } 1127 env->badaddr = address; 1128 env->two_stage_lookup = two_stage; 1129 env->two_stage_indirect_lookup = two_stage_indirect; 1130 } 1131 1132 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1133 { 1134 RISCVCPU *cpu = RISCV_CPU(cs); 1135 CPURISCVState *env = &cpu->env; 1136 hwaddr phys_addr; 1137 int prot; 1138 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1139 1140 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1141 true, riscv_cpu_virt_enabled(env), true)) { 1142 return -1; 1143 } 1144 1145 if (riscv_cpu_virt_enabled(env)) { 1146 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1147 0, mmu_idx, false, true, true)) { 1148 return -1; 1149 } 1150 } 1151 1152 return phys_addr & TARGET_PAGE_MASK; 1153 } 1154 1155 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1156 vaddr addr, unsigned size, 1157 MMUAccessType access_type, 1158 int mmu_idx, MemTxAttrs attrs, 1159 MemTxResult response, uintptr_t retaddr) 1160 { 1161 RISCVCPU *cpu = RISCV_CPU(cs); 1162 CPURISCVState *env = &cpu->env; 1163 1164 if (access_type == MMU_DATA_STORE) { 1165 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1166 } else if (access_type == MMU_DATA_LOAD) { 1167 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1168 } else { 1169 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1170 } 1171 1172 env->badaddr = addr; 1173 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1174 riscv_cpu_two_stage_lookup(mmu_idx); 1175 env->two_stage_indirect_lookup = false; 1176 cpu_loop_exit_restore(cs, retaddr); 1177 } 1178 1179 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1180 MMUAccessType access_type, int mmu_idx, 1181 uintptr_t retaddr) 1182 { 1183 RISCVCPU *cpu = RISCV_CPU(cs); 1184 CPURISCVState *env = &cpu->env; 1185 switch (access_type) { 1186 case MMU_INST_FETCH: 1187 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1188 break; 1189 case MMU_DATA_LOAD: 1190 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1191 break; 1192 case MMU_DATA_STORE: 1193 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1194 break; 1195 default: 1196 g_assert_not_reached(); 1197 } 1198 env->badaddr = addr; 1199 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1200 riscv_cpu_two_stage_lookup(mmu_idx); 1201 env->two_stage_indirect_lookup = false; 1202 cpu_loop_exit_restore(cs, retaddr); 1203 } 1204 1205 1206 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1207 { 1208 enum riscv_pmu_event_idx pmu_event_type; 1209 1210 switch (access_type) { 1211 case MMU_INST_FETCH: 1212 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1213 break; 1214 case MMU_DATA_LOAD: 1215 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1216 break; 1217 case MMU_DATA_STORE: 1218 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1219 break; 1220 default: 1221 return; 1222 } 1223 1224 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1225 } 1226 1227 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1228 MMUAccessType access_type, int mmu_idx, 1229 bool probe, uintptr_t retaddr) 1230 { 1231 RISCVCPU *cpu = RISCV_CPU(cs); 1232 CPURISCVState *env = &cpu->env; 1233 vaddr im_address; 1234 hwaddr pa = 0; 1235 int prot, prot2, prot_pmp; 1236 bool pmp_violation = false; 1237 bool first_stage_error = true; 1238 bool two_stage_lookup = false; 1239 bool two_stage_indirect_error = false; 1240 int ret = TRANSLATE_FAIL; 1241 int mode = mmu_idx; 1242 /* default TLB page size */ 1243 target_ulong tlb_size = TARGET_PAGE_SIZE; 1244 1245 env->guest_phys_fault_addr = 0; 1246 1247 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1248 __func__, address, access_type, mmu_idx); 1249 1250 /* MPRV does not affect the virtual-machine load/store 1251 instructions, HLV, HLVX, and HSV. */ 1252 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1253 mode = get_field(env->hstatus, HSTATUS_SPVP); 1254 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1255 get_field(env->mstatus, MSTATUS_MPRV)) { 1256 mode = get_field(env->mstatus, MSTATUS_MPP); 1257 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1258 two_stage_lookup = true; 1259 } 1260 } 1261 1262 if (riscv_cpu_virt_enabled(env) || 1263 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1264 access_type != MMU_INST_FETCH)) { 1265 /* Two stage lookup */ 1266 ret = get_physical_address(env, &pa, &prot, address, 1267 &env->guest_phys_fault_addr, access_type, 1268 mmu_idx, true, true, false); 1269 1270 /* 1271 * A G-stage exception may be triggered during two state lookup. 1272 * And the env->guest_phys_fault_addr has already been set in 1273 * get_physical_address(). 1274 */ 1275 if (ret == TRANSLATE_G_STAGE_FAIL) { 1276 first_stage_error = false; 1277 two_stage_indirect_error = true; 1278 access_type = MMU_DATA_LOAD; 1279 } 1280 1281 qemu_log_mask(CPU_LOG_MMU, 1282 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1283 TARGET_FMT_plx " prot %d\n", 1284 __func__, address, ret, pa, prot); 1285 1286 if (ret == TRANSLATE_SUCCESS) { 1287 /* Second stage lookup */ 1288 im_address = pa; 1289 1290 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1291 access_type, mmu_idx, false, true, 1292 false); 1293 1294 qemu_log_mask(CPU_LOG_MMU, 1295 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 1296 TARGET_FMT_plx " prot %d\n", 1297 __func__, im_address, ret, pa, prot2); 1298 1299 prot &= prot2; 1300 1301 if (ret == TRANSLATE_SUCCESS) { 1302 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1303 size, access_type, mode); 1304 1305 qemu_log_mask(CPU_LOG_MMU, 1306 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1307 " %d tlb_size " TARGET_FMT_lu "\n", 1308 __func__, pa, ret, prot_pmp, tlb_size); 1309 1310 prot &= prot_pmp; 1311 } 1312 1313 if (ret != TRANSLATE_SUCCESS) { 1314 /* 1315 * Guest physical address translation failed, this is a HS 1316 * level exception 1317 */ 1318 first_stage_error = false; 1319 env->guest_phys_fault_addr = (im_address | 1320 (address & 1321 (TARGET_PAGE_SIZE - 1))) >> 2; 1322 } 1323 } 1324 } else { 1325 pmu_tlb_fill_incr_ctr(cpu, access_type); 1326 /* Single stage lookup */ 1327 ret = get_physical_address(env, &pa, &prot, address, NULL, 1328 access_type, mmu_idx, true, false, false); 1329 1330 qemu_log_mask(CPU_LOG_MMU, 1331 "%s address=%" VADDR_PRIx " ret %d physical " 1332 TARGET_FMT_plx " prot %d\n", 1333 __func__, address, ret, pa, prot); 1334 1335 if (ret == TRANSLATE_SUCCESS) { 1336 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1337 size, access_type, mode); 1338 1339 qemu_log_mask(CPU_LOG_MMU, 1340 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1341 " %d tlb_size " TARGET_FMT_lu "\n", 1342 __func__, pa, ret, prot_pmp, tlb_size); 1343 1344 prot &= prot_pmp; 1345 } 1346 } 1347 1348 if (ret == TRANSLATE_PMP_FAIL) { 1349 pmp_violation = true; 1350 } 1351 1352 if (ret == TRANSLATE_SUCCESS) { 1353 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1354 prot, mmu_idx, tlb_size); 1355 return true; 1356 } else if (probe) { 1357 return false; 1358 } else { 1359 raise_mmu_exception(env, address, access_type, pmp_violation, 1360 first_stage_error, 1361 riscv_cpu_virt_enabled(env) || 1362 riscv_cpu_two_stage_lookup(mmu_idx), 1363 two_stage_indirect_error); 1364 cpu_loop_exit_restore(cs, retaddr); 1365 } 1366 1367 return true; 1368 } 1369 1370 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1371 target_ulong insn, 1372 target_ulong taddr) 1373 { 1374 target_ulong xinsn = 0; 1375 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1376 1377 /* 1378 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1379 * be uncompressed. The Quadrant 1 of RVC instruction space need 1380 * not be transformed because these instructions won't generate 1381 * any load/store trap. 1382 */ 1383 1384 if ((insn & 0x3) != 0x3) { 1385 /* Transform 16bit instruction into 32bit instruction */ 1386 switch (GET_C_OP(insn)) { 1387 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1388 switch (GET_C_FUNC(insn)) { 1389 case OPC_RISC_C_FUNC_FLD_LQ: 1390 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1391 xinsn = OPC_RISC_FLD; 1392 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1393 access_rs1 = GET_C_RS1S(insn); 1394 access_imm = GET_C_LD_IMM(insn); 1395 access_size = 8; 1396 } 1397 break; 1398 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1399 xinsn = OPC_RISC_LW; 1400 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1401 access_rs1 = GET_C_RS1S(insn); 1402 access_imm = GET_C_LW_IMM(insn); 1403 access_size = 4; 1404 break; 1405 case OPC_RISC_C_FUNC_FLW_LD: 1406 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1407 xinsn = OPC_RISC_FLW; 1408 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1409 access_rs1 = GET_C_RS1S(insn); 1410 access_imm = GET_C_LW_IMM(insn); 1411 access_size = 4; 1412 } else { /* C.LD (RV64/RV128) */ 1413 xinsn = OPC_RISC_LD; 1414 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1415 access_rs1 = GET_C_RS1S(insn); 1416 access_imm = GET_C_LD_IMM(insn); 1417 access_size = 8; 1418 } 1419 break; 1420 case OPC_RISC_C_FUNC_FSD_SQ: 1421 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1422 xinsn = OPC_RISC_FSD; 1423 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1424 access_rs1 = GET_C_RS1S(insn); 1425 access_imm = GET_C_SD_IMM(insn); 1426 access_size = 8; 1427 } 1428 break; 1429 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1430 xinsn = OPC_RISC_SW; 1431 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1432 access_rs1 = GET_C_RS1S(insn); 1433 access_imm = GET_C_SW_IMM(insn); 1434 access_size = 4; 1435 break; 1436 case OPC_RISC_C_FUNC_FSW_SD: 1437 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1438 xinsn = OPC_RISC_FSW; 1439 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1440 access_rs1 = GET_C_RS1S(insn); 1441 access_imm = GET_C_SW_IMM(insn); 1442 access_size = 4; 1443 } else { /* C.SD (RV64/RV128) */ 1444 xinsn = OPC_RISC_SD; 1445 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1446 access_rs1 = GET_C_RS1S(insn); 1447 access_imm = GET_C_SD_IMM(insn); 1448 access_size = 8; 1449 } 1450 break; 1451 default: 1452 break; 1453 } 1454 break; 1455 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1456 switch (GET_C_FUNC(insn)) { 1457 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1458 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1459 xinsn = OPC_RISC_FLD; 1460 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1461 access_rs1 = 2; 1462 access_imm = GET_C_LDSP_IMM(insn); 1463 access_size = 8; 1464 } 1465 break; 1466 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1467 xinsn = OPC_RISC_LW; 1468 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1469 access_rs1 = 2; 1470 access_imm = GET_C_LWSP_IMM(insn); 1471 access_size = 4; 1472 break; 1473 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1474 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1475 xinsn = OPC_RISC_FLW; 1476 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1477 access_rs1 = 2; 1478 access_imm = GET_C_LWSP_IMM(insn); 1479 access_size = 4; 1480 } else { /* C.LDSP (RV64/RV128) */ 1481 xinsn = OPC_RISC_LD; 1482 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1483 access_rs1 = 2; 1484 access_imm = GET_C_LDSP_IMM(insn); 1485 access_size = 8; 1486 } 1487 break; 1488 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1489 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1490 xinsn = OPC_RISC_FSD; 1491 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1492 access_rs1 = 2; 1493 access_imm = GET_C_SDSP_IMM(insn); 1494 access_size = 8; 1495 } 1496 break; 1497 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1498 xinsn = OPC_RISC_SW; 1499 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1500 access_rs1 = 2; 1501 access_imm = GET_C_SWSP_IMM(insn); 1502 access_size = 4; 1503 break; 1504 case 7: 1505 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1506 xinsn = OPC_RISC_FSW; 1507 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1508 access_rs1 = 2; 1509 access_imm = GET_C_SWSP_IMM(insn); 1510 access_size = 4; 1511 } else { /* C.SDSP (RV64/RV128) */ 1512 xinsn = OPC_RISC_SD; 1513 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1514 access_rs1 = 2; 1515 access_imm = GET_C_SDSP_IMM(insn); 1516 access_size = 8; 1517 } 1518 break; 1519 default: 1520 break; 1521 } 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 /* 1528 * Clear Bit1 of transformed instruction to indicate that 1529 * original insruction was a 16bit instruction 1530 */ 1531 xinsn &= ~((target_ulong)0x2); 1532 } else { 1533 /* Transform 32bit (or wider) instructions */ 1534 switch (MASK_OP_MAJOR(insn)) { 1535 case OPC_RISC_ATOMIC: 1536 xinsn = insn; 1537 access_rs1 = GET_RS1(insn); 1538 access_size = 1 << GET_FUNCT3(insn); 1539 break; 1540 case OPC_RISC_LOAD: 1541 case OPC_RISC_FP_LOAD: 1542 xinsn = SET_I_IMM(insn, 0); 1543 access_rs1 = GET_RS1(insn); 1544 access_imm = GET_IMM(insn); 1545 access_size = 1 << GET_FUNCT3(insn); 1546 break; 1547 case OPC_RISC_STORE: 1548 case OPC_RISC_FP_STORE: 1549 xinsn = SET_S_IMM(insn, 0); 1550 access_rs1 = GET_RS1(insn); 1551 access_imm = GET_STORE_IMM(insn); 1552 access_size = 1 << GET_FUNCT3(insn); 1553 break; 1554 case OPC_RISC_SYSTEM: 1555 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1556 xinsn = insn; 1557 access_rs1 = GET_RS1(insn); 1558 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1559 access_size = 1 << access_size; 1560 } 1561 break; 1562 default: 1563 break; 1564 } 1565 } 1566 1567 if (access_size) { 1568 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1569 (access_size - 1)); 1570 } 1571 1572 return xinsn; 1573 } 1574 #endif /* !CONFIG_USER_ONLY */ 1575 1576 /* 1577 * Handle Traps 1578 * 1579 * Adapted from Spike's processor_t::take_trap. 1580 * 1581 */ 1582 void riscv_cpu_do_interrupt(CPUState *cs) 1583 { 1584 #if !defined(CONFIG_USER_ONLY) 1585 1586 RISCVCPU *cpu = RISCV_CPU(cs); 1587 CPURISCVState *env = &cpu->env; 1588 bool write_gva = false; 1589 uint64_t s; 1590 1591 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1592 * so we mask off the MSB and separate into trap type and cause. 1593 */ 1594 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1595 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1596 uint64_t deleg = async ? env->mideleg : env->medeleg; 1597 target_ulong tval = 0; 1598 target_ulong tinst = 0; 1599 target_ulong htval = 0; 1600 target_ulong mtval2 = 0; 1601 1602 if (cause == RISCV_EXCP_SEMIHOST) { 1603 do_common_semihosting(cs); 1604 env->pc += 4; 1605 return; 1606 } 1607 1608 if (!async) { 1609 /* set tval to badaddr for traps with address information */ 1610 switch (cause) { 1611 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1612 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1613 case RISCV_EXCP_LOAD_ADDR_MIS: 1614 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1615 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1616 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1617 case RISCV_EXCP_LOAD_PAGE_FAULT: 1618 case RISCV_EXCP_STORE_PAGE_FAULT: 1619 write_gva = env->two_stage_lookup; 1620 tval = env->badaddr; 1621 if (env->two_stage_indirect_lookup) { 1622 /* 1623 * special pseudoinstruction for G-stage fault taken while 1624 * doing VS-stage page table walk. 1625 */ 1626 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1627 } else { 1628 /* 1629 * The "Addr. Offset" field in transformed instruction is 1630 * non-zero only for misaligned access. 1631 */ 1632 tinst = riscv_transformed_insn(env, env->bins, tval); 1633 } 1634 break; 1635 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1636 case RISCV_EXCP_INST_ADDR_MIS: 1637 case RISCV_EXCP_INST_ACCESS_FAULT: 1638 case RISCV_EXCP_INST_PAGE_FAULT: 1639 write_gva = env->two_stage_lookup; 1640 tval = env->badaddr; 1641 if (env->two_stage_indirect_lookup) { 1642 /* 1643 * special pseudoinstruction for G-stage fault taken while 1644 * doing VS-stage page table walk. 1645 */ 1646 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1647 } 1648 break; 1649 case RISCV_EXCP_ILLEGAL_INST: 1650 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1651 tval = env->bins; 1652 break; 1653 default: 1654 break; 1655 } 1656 /* ecall is dispatched as one cause so translate based on mode */ 1657 if (cause == RISCV_EXCP_U_ECALL) { 1658 assert(env->priv <= 3); 1659 1660 if (env->priv == PRV_M) { 1661 cause = RISCV_EXCP_M_ECALL; 1662 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1663 cause = RISCV_EXCP_VS_ECALL; 1664 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1665 cause = RISCV_EXCP_S_ECALL; 1666 } else if (env->priv == PRV_U) { 1667 cause = RISCV_EXCP_U_ECALL; 1668 } 1669 } 1670 } 1671 1672 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1673 riscv_cpu_get_trap_name(cause, async)); 1674 1675 qemu_log_mask(CPU_LOG_INT, 1676 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1677 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1678 __func__, env->mhartid, async, cause, env->pc, tval, 1679 riscv_cpu_get_trap_name(cause, async)); 1680 1681 if (env->priv <= PRV_S && 1682 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1683 /* handle the trap in S-mode */ 1684 if (riscv_has_ext(env, RVH)) { 1685 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1686 1687 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1688 /* Trap to VS mode */ 1689 /* 1690 * See if we need to adjust cause. Yes if its VS mode interrupt 1691 * no if hypervisor has delegated one of hs mode's interrupt 1692 */ 1693 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1694 cause == IRQ_VS_EXT) { 1695 cause = cause - 1; 1696 } 1697 write_gva = false; 1698 } else if (riscv_cpu_virt_enabled(env)) { 1699 /* Trap into HS mode, from virt */ 1700 riscv_cpu_swap_hypervisor_regs(env); 1701 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1702 env->priv); 1703 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1704 riscv_cpu_virt_enabled(env)); 1705 1706 1707 htval = env->guest_phys_fault_addr; 1708 1709 riscv_cpu_set_virt_enabled(env, 0); 1710 } else { 1711 /* Trap into HS mode */ 1712 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1713 htval = env->guest_phys_fault_addr; 1714 } 1715 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1716 } 1717 1718 s = env->mstatus; 1719 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1720 s = set_field(s, MSTATUS_SPP, env->priv); 1721 s = set_field(s, MSTATUS_SIE, 0); 1722 env->mstatus = s; 1723 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1724 env->sepc = env->pc; 1725 env->stval = tval; 1726 env->htval = htval; 1727 env->htinst = tinst; 1728 env->pc = (env->stvec >> 2 << 2) + 1729 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1730 riscv_cpu_set_mode(env, PRV_S); 1731 } else { 1732 /* handle the trap in M-mode */ 1733 if (riscv_has_ext(env, RVH)) { 1734 if (riscv_cpu_virt_enabled(env)) { 1735 riscv_cpu_swap_hypervisor_regs(env); 1736 } 1737 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1738 riscv_cpu_virt_enabled(env)); 1739 if (riscv_cpu_virt_enabled(env) && tval) { 1740 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1741 } 1742 1743 mtval2 = env->guest_phys_fault_addr; 1744 1745 /* Trapping to M mode, virt is disabled */ 1746 riscv_cpu_set_virt_enabled(env, 0); 1747 } 1748 1749 s = env->mstatus; 1750 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1751 s = set_field(s, MSTATUS_MPP, env->priv); 1752 s = set_field(s, MSTATUS_MIE, 0); 1753 env->mstatus = s; 1754 env->mcause = cause | ~(((target_ulong)-1) >> async); 1755 env->mepc = env->pc; 1756 env->mtval = tval; 1757 env->mtval2 = mtval2; 1758 env->mtinst = tinst; 1759 env->pc = (env->mtvec >> 2 << 2) + 1760 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1761 riscv_cpu_set_mode(env, PRV_M); 1762 } 1763 1764 /* NOTE: it is not necessary to yield load reservations here. It is only 1765 * necessary for an SC from "another hart" to cause a load reservation 1766 * to be yielded. Refer to the memory consistency model section of the 1767 * RISC-V ISA Specification. 1768 */ 1769 1770 env->two_stage_lookup = false; 1771 env->two_stage_indirect_lookup = false; 1772 #endif 1773 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1774 } 1775