1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 RISCVExtStatus fs, vs; 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (cpu->cfg.ext_zve32f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); 78 } else { 79 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 80 } 81 82 #ifdef CONFIG_USER_ONLY 83 fs = EXT_STATUS_DIRTY; 84 vs = EXT_STATUS_DIRTY; 85 #else 86 flags |= cpu_mmu_index(env, 0); 87 fs = get_field(env->mstatus, MSTATUS_FS); 88 vs = get_field(env->mstatus, MSTATUS_VS); 89 90 if (riscv_has_ext(env, RVH)) { 91 if (env->priv == PRV_M || 92 (env->priv == PRV_S && !env->virt_enabled) || 93 (env->priv == PRV_U && !env->virt_enabled && 94 get_field(env->hstatus, HSTATUS_HU))) { 95 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 96 } 97 98 if (env->virt_enabled) { 99 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); 100 /* 101 * Merge DISABLED and !DIRTY states using MIN. 102 * We will set both fields when dirtying. 103 */ 104 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); 105 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); 106 } 107 } 108 if (cpu->cfg.debug && !icount_enabled()) { 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 110 } 111 #endif 112 113 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); 114 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); 115 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 116 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 117 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 118 } 119 if (env->cur_pmbase != 0) { 120 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 121 } 122 123 *pflags = flags; 124 } 125 126 void riscv_cpu_update_mask(CPURISCVState *env) 127 { 128 target_ulong mask = -1, base = 0; 129 /* 130 * TODO: Current RVJ spec does not specify 131 * how the extension interacts with XLEN. 132 */ 133 #ifndef CONFIG_USER_ONLY 134 if (riscv_has_ext(env, RVJ)) { 135 switch (env->priv) { 136 case PRV_M: 137 if (env->mmte & M_PM_ENABLE) { 138 mask = env->mpmmask; 139 base = env->mpmbase; 140 } 141 break; 142 case PRV_S: 143 if (env->mmte & S_PM_ENABLE) { 144 mask = env->spmmask; 145 base = env->spmbase; 146 } 147 break; 148 case PRV_U: 149 if (env->mmte & U_PM_ENABLE) { 150 mask = env->upmmask; 151 base = env->upmbase; 152 } 153 break; 154 default: 155 g_assert_not_reached(); 156 } 157 } 158 #endif 159 if (env->xl == MXL_RV32) { 160 env->cur_pmmask = mask & UINT32_MAX; 161 env->cur_pmbase = base & UINT32_MAX; 162 } else { 163 env->cur_pmmask = mask; 164 env->cur_pmbase = base; 165 } 166 } 167 168 #ifndef CONFIG_USER_ONLY 169 170 /* 171 * The HS-mode is allowed to configure priority only for the 172 * following VS-mode local interrupts: 173 * 174 * 0 (Reserved interrupt, reads as zero) 175 * 1 Supervisor software interrupt 176 * 4 (Reserved interrupt, reads as zero) 177 * 5 Supervisor timer interrupt 178 * 8 (Reserved interrupt, reads as zero) 179 * 13 (Reserved interrupt) 180 * 14 " 181 * 15 " 182 * 16 " 183 * 17 " 184 * 18 " 185 * 19 " 186 * 20 " 187 * 21 " 188 * 22 " 189 * 23 " 190 */ 191 192 static const int hviprio_index2irq[] = { 193 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 194 static const int hviprio_index2rdzero[] = { 195 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 196 197 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 198 { 199 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 200 return -EINVAL; 201 } 202 203 if (out_irq) { 204 *out_irq = hviprio_index2irq[index]; 205 } 206 207 if (out_rdzero) { 208 *out_rdzero = hviprio_index2rdzero[index]; 209 } 210 211 return 0; 212 } 213 214 /* 215 * Default priorities of local interrupts are defined in the 216 * RISC-V Advanced Interrupt Architecture specification. 217 * 218 * ---------------------------------------------------------------- 219 * Default | 220 * Priority | Major Interrupt Numbers 221 * ---------------------------------------------------------------- 222 * Highest | 47, 23, 46, 45, 22, 44, 223 * | 43, 21, 42, 41, 20, 40 224 * | 225 * | 11 (0b), 3 (03), 7 (07) 226 * | 9 (09), 1 (01), 5 (05) 227 * | 12 (0c) 228 * | 10 (0a), 2 (02), 6 (06) 229 * | 230 * | 39, 19, 38, 37, 18, 36, 231 * Lowest | 35, 17, 34, 33, 16, 32 232 * ---------------------------------------------------------------- 233 */ 234 static const uint8_t default_iprio[64] = { 235 /* Custom interrupts 48 to 63 */ 236 [63] = IPRIO_MMAXIPRIO, 237 [62] = IPRIO_MMAXIPRIO, 238 [61] = IPRIO_MMAXIPRIO, 239 [60] = IPRIO_MMAXIPRIO, 240 [59] = IPRIO_MMAXIPRIO, 241 [58] = IPRIO_MMAXIPRIO, 242 [57] = IPRIO_MMAXIPRIO, 243 [56] = IPRIO_MMAXIPRIO, 244 [55] = IPRIO_MMAXIPRIO, 245 [54] = IPRIO_MMAXIPRIO, 246 [53] = IPRIO_MMAXIPRIO, 247 [52] = IPRIO_MMAXIPRIO, 248 [51] = IPRIO_MMAXIPRIO, 249 [50] = IPRIO_MMAXIPRIO, 250 [49] = IPRIO_MMAXIPRIO, 251 [48] = IPRIO_MMAXIPRIO, 252 253 /* Custom interrupts 24 to 31 */ 254 [31] = IPRIO_MMAXIPRIO, 255 [30] = IPRIO_MMAXIPRIO, 256 [29] = IPRIO_MMAXIPRIO, 257 [28] = IPRIO_MMAXIPRIO, 258 [27] = IPRIO_MMAXIPRIO, 259 [26] = IPRIO_MMAXIPRIO, 260 [25] = IPRIO_MMAXIPRIO, 261 [24] = IPRIO_MMAXIPRIO, 262 263 [47] = IPRIO_DEFAULT_UPPER, 264 [23] = IPRIO_DEFAULT_UPPER + 1, 265 [46] = IPRIO_DEFAULT_UPPER + 2, 266 [45] = IPRIO_DEFAULT_UPPER + 3, 267 [22] = IPRIO_DEFAULT_UPPER + 4, 268 [44] = IPRIO_DEFAULT_UPPER + 5, 269 270 [43] = IPRIO_DEFAULT_UPPER + 6, 271 [21] = IPRIO_DEFAULT_UPPER + 7, 272 [42] = IPRIO_DEFAULT_UPPER + 8, 273 [41] = IPRIO_DEFAULT_UPPER + 9, 274 [20] = IPRIO_DEFAULT_UPPER + 10, 275 [40] = IPRIO_DEFAULT_UPPER + 11, 276 277 [11] = IPRIO_DEFAULT_M, 278 [3] = IPRIO_DEFAULT_M + 1, 279 [7] = IPRIO_DEFAULT_M + 2, 280 281 [9] = IPRIO_DEFAULT_S, 282 [1] = IPRIO_DEFAULT_S + 1, 283 [5] = IPRIO_DEFAULT_S + 2, 284 285 [12] = IPRIO_DEFAULT_SGEXT, 286 287 [10] = IPRIO_DEFAULT_VS, 288 [2] = IPRIO_DEFAULT_VS + 1, 289 [6] = IPRIO_DEFAULT_VS + 2, 290 291 [39] = IPRIO_DEFAULT_LOWER, 292 [19] = IPRIO_DEFAULT_LOWER + 1, 293 [38] = IPRIO_DEFAULT_LOWER + 2, 294 [37] = IPRIO_DEFAULT_LOWER + 3, 295 [18] = IPRIO_DEFAULT_LOWER + 4, 296 [36] = IPRIO_DEFAULT_LOWER + 5, 297 298 [35] = IPRIO_DEFAULT_LOWER + 6, 299 [17] = IPRIO_DEFAULT_LOWER + 7, 300 [34] = IPRIO_DEFAULT_LOWER + 8, 301 [33] = IPRIO_DEFAULT_LOWER + 9, 302 [16] = IPRIO_DEFAULT_LOWER + 10, 303 [32] = IPRIO_DEFAULT_LOWER + 11, 304 }; 305 306 uint8_t riscv_cpu_default_priority(int irq) 307 { 308 if (irq < 0 || irq > 63) { 309 return IPRIO_MMAXIPRIO; 310 } 311 312 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 313 }; 314 315 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 316 int extirq, unsigned int extirq_def_prio, 317 uint64_t pending, uint8_t *iprio) 318 { 319 int irq, best_irq = RISCV_EXCP_NONE; 320 unsigned int prio, best_prio = UINT_MAX; 321 322 if (!pending) { 323 return RISCV_EXCP_NONE; 324 } 325 326 irq = ctz64(pending); 327 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 328 riscv_cpu_cfg(env)->ext_ssaia)) { 329 return irq; 330 } 331 332 pending = pending >> irq; 333 while (pending) { 334 prio = iprio[irq]; 335 if (!prio) { 336 if (irq == extirq) { 337 prio = extirq_def_prio; 338 } else { 339 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 340 1 : IPRIO_MMAXIPRIO; 341 } 342 } 343 if ((pending & 0x1) && (prio <= best_prio)) { 344 best_irq = irq; 345 best_prio = prio; 346 } 347 irq++; 348 pending = pending >> 1; 349 } 350 351 return best_irq; 352 } 353 354 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 355 { 356 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 357 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 358 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 359 360 return (env->mip | vsgein | vstip) & env->mie; 361 } 362 363 int riscv_cpu_mirq_pending(CPURISCVState *env) 364 { 365 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 366 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 367 368 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 369 irqs, env->miprio); 370 } 371 372 int riscv_cpu_sirq_pending(CPURISCVState *env) 373 { 374 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 375 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 376 377 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 378 irqs, env->siprio); 379 } 380 381 int riscv_cpu_vsirq_pending(CPURISCVState *env) 382 { 383 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 384 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 385 386 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 387 irqs >> 1, env->hviprio); 388 } 389 390 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 391 { 392 int virq; 393 uint64_t irqs, pending, mie, hsie, vsie; 394 395 /* Determine interrupt enable state of all privilege modes */ 396 if (env->virt_enabled) { 397 mie = 1; 398 hsie = 1; 399 vsie = (env->priv < PRV_S) || 400 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 401 } else { 402 mie = (env->priv < PRV_M) || 403 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 404 hsie = (env->priv < PRV_S) || 405 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 406 vsie = 0; 407 } 408 409 /* Determine all pending interrupts */ 410 pending = riscv_cpu_all_pending(env); 411 412 /* Check M-mode interrupts */ 413 irqs = pending & ~env->mideleg & -mie; 414 if (irqs) { 415 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 416 irqs, env->miprio); 417 } 418 419 /* Check HS-mode interrupts */ 420 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 421 if (irqs) { 422 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 423 irqs, env->siprio); 424 } 425 426 /* Check VS-mode interrupts */ 427 irqs = pending & env->mideleg & env->hideleg & -vsie; 428 if (irqs) { 429 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 430 irqs >> 1, env->hviprio); 431 return (virq <= 0) ? virq : virq + 1; 432 } 433 434 /* Indicate no pending interrupt */ 435 return RISCV_EXCP_NONE; 436 } 437 438 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 439 { 440 if (interrupt_request & CPU_INTERRUPT_HARD) { 441 RISCVCPU *cpu = RISCV_CPU(cs); 442 CPURISCVState *env = &cpu->env; 443 int interruptno = riscv_cpu_local_irq_pending(env); 444 if (interruptno >= 0) { 445 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 446 riscv_cpu_do_interrupt(cs); 447 return true; 448 } 449 } 450 return false; 451 } 452 453 /* Return true is floating point support is currently enabled */ 454 bool riscv_cpu_fp_enabled(CPURISCVState *env) 455 { 456 if (env->mstatus & MSTATUS_FS) { 457 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 458 return false; 459 } 460 return true; 461 } 462 463 return false; 464 } 465 466 /* Return true is vector support is currently enabled */ 467 bool riscv_cpu_vector_enabled(CPURISCVState *env) 468 { 469 if (env->mstatus & MSTATUS_VS) { 470 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 471 return false; 472 } 473 return true; 474 } 475 476 return false; 477 } 478 479 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 480 { 481 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 482 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 483 MSTATUS64_UXL | MSTATUS_VS; 484 485 if (riscv_has_ext(env, RVF)) { 486 mstatus_mask |= MSTATUS_FS; 487 } 488 bool current_virt = env->virt_enabled; 489 490 g_assert(riscv_has_ext(env, RVH)); 491 492 if (current_virt) { 493 /* Current V=1 and we are about to change to V=0 */ 494 env->vsstatus = env->mstatus & mstatus_mask; 495 env->mstatus &= ~mstatus_mask; 496 env->mstatus |= env->mstatus_hs; 497 498 env->vstvec = env->stvec; 499 env->stvec = env->stvec_hs; 500 501 env->vsscratch = env->sscratch; 502 env->sscratch = env->sscratch_hs; 503 504 env->vsepc = env->sepc; 505 env->sepc = env->sepc_hs; 506 507 env->vscause = env->scause; 508 env->scause = env->scause_hs; 509 510 env->vstval = env->stval; 511 env->stval = env->stval_hs; 512 513 env->vsatp = env->satp; 514 env->satp = env->satp_hs; 515 } else { 516 /* Current V=0 and we are about to change to V=1 */ 517 env->mstatus_hs = env->mstatus & mstatus_mask; 518 env->mstatus &= ~mstatus_mask; 519 env->mstatus |= env->vsstatus; 520 521 env->stvec_hs = env->stvec; 522 env->stvec = env->vstvec; 523 524 env->sscratch_hs = env->sscratch; 525 env->sscratch = env->vsscratch; 526 527 env->sepc_hs = env->sepc; 528 env->sepc = env->vsepc; 529 530 env->scause_hs = env->scause; 531 env->scause = env->vscause; 532 533 env->stval_hs = env->stval; 534 env->stval = env->vstval; 535 536 env->satp_hs = env->satp; 537 env->satp = env->vsatp; 538 } 539 } 540 541 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 542 { 543 if (!riscv_has_ext(env, RVH)) { 544 return 0; 545 } 546 547 return env->geilen; 548 } 549 550 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 551 { 552 if (!riscv_has_ext(env, RVH)) { 553 return; 554 } 555 556 if (geilen > (TARGET_LONG_BITS - 1)) { 557 return; 558 } 559 560 env->geilen = geilen; 561 } 562 563 /* This function can only be called to set virt when RVH is enabled */ 564 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 565 { 566 /* Flush the TLB on all virt mode changes. */ 567 if (env->virt_enabled != enable) { 568 tlb_flush(env_cpu(env)); 569 } 570 571 env->virt_enabled = enable; 572 573 if (enable) { 574 /* 575 * The guest external interrupts from an interrupt controller are 576 * delivered only when the Guest/VM is running (i.e. V=1). This means 577 * any guest external interrupt which is triggered while the Guest/VM 578 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 579 * with sluggish response to serial console input and other I/O events. 580 * 581 * To solve this, we check and inject interrupt after setting V=1. 582 */ 583 riscv_cpu_update_mip(env, 0, 0); 584 } 585 } 586 587 bool riscv_cpu_two_stage_lookup(int mmu_idx) 588 { 589 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 590 } 591 592 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 593 { 594 CPURISCVState *env = &cpu->env; 595 if (env->miclaim & interrupts) { 596 return -1; 597 } else { 598 env->miclaim |= interrupts; 599 return 0; 600 } 601 } 602 603 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 604 uint64_t value) 605 { 606 CPUState *cs = env_cpu(env); 607 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 608 609 if (env->virt_enabled) { 610 gein = get_field(env->hstatus, HSTATUS_VGEIN); 611 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 612 } 613 614 vstip = env->vstime_irq ? MIP_VSTIP : 0; 615 616 QEMU_IOTHREAD_LOCK_GUARD(); 617 618 env->mip = (env->mip & ~mask) | (value & mask); 619 620 if (env->mip | vsgein | vstip) { 621 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 622 } else { 623 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 624 } 625 626 return old; 627 } 628 629 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 630 void *arg) 631 { 632 env->rdtime_fn = fn; 633 env->rdtime_fn_arg = arg; 634 } 635 636 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 637 int (*rmw_fn)(void *arg, 638 target_ulong reg, 639 target_ulong *val, 640 target_ulong new_val, 641 target_ulong write_mask), 642 void *rmw_fn_arg) 643 { 644 if (priv <= PRV_M) { 645 env->aia_ireg_rmw_fn[priv] = rmw_fn; 646 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 647 } 648 } 649 650 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 651 { 652 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); 653 654 if (icount_enabled() && newpriv != env->priv) { 655 riscv_itrigger_update_priv(env); 656 } 657 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 658 env->priv = newpriv; 659 env->xl = cpu_recompute_xl(env); 660 riscv_cpu_update_mask(env); 661 662 /* 663 * Clear the load reservation - otherwise a reservation placed in one 664 * context/process can be used by another, resulting in an SC succeeding 665 * incorrectly. Version 2.2 of the ISA specification explicitly requires 666 * this behaviour, while later revisions say that the kernel "should" use 667 * an SC instruction to force the yielding of a load reservation on a 668 * preemptive context switch. As a result, do both. 669 */ 670 env->load_res = -1; 671 } 672 673 /* 674 * get_physical_address_pmp - check PMP permission for this physical address 675 * 676 * Match the PMP region and check permission for this physical address and it's 677 * TLB page. Returns 0 if the permission checking was successful 678 * 679 * @env: CPURISCVState 680 * @prot: The returned protection attributes 681 * @tlb_size: TLB page size containing addr. It could be modified after PMP 682 * permission checking. NULL if not set TLB page for addr. 683 * @addr: The physical address to be checked permission 684 * @access_type: The type of MMU access 685 * @mode: Indicates current privilege level. 686 */ 687 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 688 target_ulong *tlb_size, hwaddr addr, 689 int size, MMUAccessType access_type, 690 int mode) 691 { 692 pmp_priv_t pmp_priv; 693 int pmp_index = -1; 694 695 if (!riscv_cpu_cfg(env)->pmp) { 696 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 697 return TRANSLATE_SUCCESS; 698 } 699 700 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 701 &pmp_priv, mode); 702 if (pmp_index < 0) { 703 *prot = 0; 704 return TRANSLATE_PMP_FAIL; 705 } 706 707 *prot = pmp_priv_to_page_prot(pmp_priv); 708 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 709 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 710 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 711 712 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 713 } 714 715 return TRANSLATE_SUCCESS; 716 } 717 718 /* 719 * get_physical_address - get the physical address for this virtual address 720 * 721 * Do a page table walk to obtain the physical address corresponding to a 722 * virtual address. Returns 0 if the translation was successful 723 * 724 * Adapted from Spike's mmu_t::translate and mmu_t::walk 725 * 726 * @env: CPURISCVState 727 * @physical: This will be set to the calculated physical address 728 * @prot: The returned protection attributes 729 * @addr: The virtual address or guest physical address to be translated 730 * @fault_pte_addr: If not NULL, this will be set to fault pte address 731 * when a error occurs on pte address translation. 732 * This will already be shifted to match htval. 733 * @access_type: The type of MMU access 734 * @mmu_idx: Indicates current privilege level 735 * @first_stage: Are we in first stage translation? 736 * Second stage is used for hypervisor guest translation 737 * @two_stage: Are we going to perform two stage translation 738 * @is_debug: Is this access from a debugger or the monitor? 739 */ 740 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 741 int *prot, vaddr addr, 742 target_ulong *fault_pte_addr, 743 int access_type, int mmu_idx, 744 bool first_stage, bool two_stage, 745 bool is_debug) 746 { 747 /* 748 * NOTE: the env->pc value visible here will not be 749 * correct, but the value visible to the exception handler 750 * (riscv_cpu_do_interrupt) is correct 751 */ 752 MemTxResult res; 753 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 754 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 755 bool use_background = false; 756 hwaddr ppn; 757 int napot_bits = 0; 758 target_ulong napot_mask; 759 760 /* 761 * Check if we should use the background registers for the two 762 * stage translation. We don't need to check if we actually need 763 * two stage translation as that happened before this function 764 * was called. Background registers will be used if the guest has 765 * forced a two stage translation to be on (in HS or M mode). 766 */ 767 if (!env->virt_enabled && two_stage) { 768 use_background = true; 769 } 770 771 /* 772 * MPRV does not affect the virtual-machine load/store 773 * instructions, HLV, HLVX, and HSV. 774 */ 775 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 776 mode = get_field(env->hstatus, HSTATUS_SPVP); 777 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 778 if (get_field(env->mstatus, MSTATUS_MPRV)) { 779 mode = get_field(env->mstatus, MSTATUS_MPP); 780 } 781 } 782 783 if (first_stage == false) { 784 /* 785 * We are in stage 2 translation, this is similar to stage 1. 786 * Stage 2 is always taken as U-mode 787 */ 788 mode = PRV_U; 789 } 790 791 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 792 *physical = addr; 793 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 794 return TRANSLATE_SUCCESS; 795 } 796 797 *prot = 0; 798 799 hwaddr base; 800 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 801 802 if (first_stage == true) { 803 mxr = get_field(env->mstatus, MSTATUS_MXR); 804 } else { 805 mxr = get_field(env->vsstatus, MSTATUS_MXR); 806 } 807 808 if (first_stage == true) { 809 if (use_background) { 810 if (riscv_cpu_mxl(env) == MXL_RV32) { 811 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 812 vm = get_field(env->vsatp, SATP32_MODE); 813 } else { 814 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 815 vm = get_field(env->vsatp, SATP64_MODE); 816 } 817 } else { 818 if (riscv_cpu_mxl(env) == MXL_RV32) { 819 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 820 vm = get_field(env->satp, SATP32_MODE); 821 } else { 822 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 823 vm = get_field(env->satp, SATP64_MODE); 824 } 825 } 826 widened = 0; 827 } else { 828 if (riscv_cpu_mxl(env) == MXL_RV32) { 829 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 830 vm = get_field(env->hgatp, SATP32_MODE); 831 } else { 832 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 833 vm = get_field(env->hgatp, SATP64_MODE); 834 } 835 widened = 2; 836 } 837 /* status.SUM will be ignored if execute on background */ 838 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 839 switch (vm) { 840 case VM_1_10_SV32: 841 levels = 2; ptidxbits = 10; ptesize = 4; break; 842 case VM_1_10_SV39: 843 levels = 3; ptidxbits = 9; ptesize = 8; break; 844 case VM_1_10_SV48: 845 levels = 4; ptidxbits = 9; ptesize = 8; break; 846 case VM_1_10_SV57: 847 levels = 5; ptidxbits = 9; ptesize = 8; break; 848 case VM_1_10_MBARE: 849 *physical = addr; 850 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 851 return TRANSLATE_SUCCESS; 852 default: 853 g_assert_not_reached(); 854 } 855 856 CPUState *cs = env_cpu(env); 857 int va_bits = PGSHIFT + levels * ptidxbits + widened; 858 target_ulong mask, masked_msbs; 859 860 if (TARGET_LONG_BITS > (va_bits - 1)) { 861 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 862 } else { 863 mask = 0; 864 } 865 masked_msbs = (addr >> (va_bits - 1)) & mask; 866 867 if (masked_msbs != 0 && masked_msbs != mask) { 868 return TRANSLATE_FAIL; 869 } 870 871 int ptshift = (levels - 1) * ptidxbits; 872 int i; 873 874 #if !TCG_OVERSIZED_GUEST 875 restart: 876 #endif 877 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 878 target_ulong idx; 879 if (i == 0) { 880 idx = (addr >> (PGSHIFT + ptshift)) & 881 ((1 << (ptidxbits + widened)) - 1); 882 } else { 883 idx = (addr >> (PGSHIFT + ptshift)) & 884 ((1 << ptidxbits) - 1); 885 } 886 887 /* check that physical address of PTE is legal */ 888 hwaddr pte_addr; 889 890 if (two_stage && first_stage) { 891 int vbase_prot; 892 hwaddr vbase; 893 894 /* Do the second stage translation on the base PTE address. */ 895 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 896 base, NULL, MMU_DATA_LOAD, 897 mmu_idx, false, true, 898 is_debug); 899 900 if (vbase_ret != TRANSLATE_SUCCESS) { 901 if (fault_pte_addr) { 902 *fault_pte_addr = (base + idx * ptesize) >> 2; 903 } 904 return TRANSLATE_G_STAGE_FAIL; 905 } 906 907 pte_addr = vbase + idx * ptesize; 908 } else { 909 pte_addr = base + idx * ptesize; 910 } 911 912 int pmp_prot; 913 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 914 sizeof(target_ulong), 915 MMU_DATA_LOAD, PRV_S); 916 if (pmp_ret != TRANSLATE_SUCCESS) { 917 return TRANSLATE_PMP_FAIL; 918 } 919 920 target_ulong pte; 921 if (riscv_cpu_mxl(env) == MXL_RV32) { 922 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 923 } else { 924 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 925 } 926 927 if (res != MEMTX_OK) { 928 return TRANSLATE_FAIL; 929 } 930 931 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 932 bool hade = env->menvcfg & MENVCFG_HADE; 933 934 if (first_stage && two_stage && env->virt_enabled) { 935 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 936 hade = hade && (env->henvcfg & HENVCFG_HADE); 937 } 938 939 if (riscv_cpu_sxl(env) == MXL_RV32) { 940 ppn = pte >> PTE_PPN_SHIFT; 941 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 942 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 943 } else { 944 ppn = pte >> PTE_PPN_SHIFT; 945 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 946 return TRANSLATE_FAIL; 947 } 948 } 949 950 if (!(pte & PTE_V)) { 951 /* Invalid PTE */ 952 return TRANSLATE_FAIL; 953 } else if (!pbmte && (pte & PTE_PBMT)) { 954 return TRANSLATE_FAIL; 955 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 956 /* Inner PTE, continue walking */ 957 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 958 return TRANSLATE_FAIL; 959 } 960 base = ppn << PGSHIFT; 961 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 962 /* Reserved leaf PTE flags: PTE_W */ 963 return TRANSLATE_FAIL; 964 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 965 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 966 return TRANSLATE_FAIL; 967 } else if ((pte & PTE_U) && ((mode != PRV_U) && 968 (!sum || access_type == MMU_INST_FETCH))) { 969 /* User PTE flags when not U mode and mstatus.SUM is not set, 970 or the access type is an instruction fetch */ 971 return TRANSLATE_FAIL; 972 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 973 /* Supervisor PTE flags when not S mode */ 974 return TRANSLATE_FAIL; 975 } else if (ppn & ((1ULL << ptshift) - 1)) { 976 /* Misaligned PPN */ 977 return TRANSLATE_FAIL; 978 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 979 ((pte & PTE_X) && mxr))) { 980 /* Read access check failed */ 981 return TRANSLATE_FAIL; 982 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 983 /* Write access check failed */ 984 return TRANSLATE_FAIL; 985 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 986 /* Fetch access check failed */ 987 return TRANSLATE_FAIL; 988 } else { 989 /* if necessary, set accessed and dirty bits. */ 990 target_ulong updated_pte = pte | PTE_A | 991 (access_type == MMU_DATA_STORE ? PTE_D : 0); 992 993 /* Page table updates need to be atomic with MTTCG enabled */ 994 if (updated_pte != pte) { 995 if (!hade) { 996 return TRANSLATE_FAIL; 997 } 998 999 /* 1000 * - if accessed or dirty bits need updating, and the PTE is 1001 * in RAM, then we do so atomically with a compare and swap. 1002 * - if the PTE is in IO space or ROM, then it can't be updated 1003 * and we return TRANSLATE_FAIL. 1004 * - if the PTE changed by the time we went to update it, then 1005 * it is no longer valid and we must re-walk the page table. 1006 */ 1007 MemoryRegion *mr; 1008 hwaddr l = sizeof(target_ulong), addr1; 1009 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1010 false, MEMTXATTRS_UNSPECIFIED); 1011 if (memory_region_is_ram(mr)) { 1012 target_ulong *pte_pa = 1013 qemu_map_ram_ptr(mr->ram_block, addr1); 1014 #if TCG_OVERSIZED_GUEST 1015 /* 1016 * MTTCG is not enabled on oversized TCG guests so 1017 * page table updates do not need to be atomic 1018 */ 1019 *pte_pa = pte = updated_pte; 1020 #else 1021 target_ulong old_pte = 1022 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1023 if (old_pte != pte) { 1024 goto restart; 1025 } else { 1026 pte = updated_pte; 1027 } 1028 #endif 1029 } else { 1030 /* 1031 * misconfigured PTE in ROM (AD bits are not preset) or 1032 * PTE is in IO space and can't be updated atomically 1033 */ 1034 return TRANSLATE_FAIL; 1035 } 1036 } 1037 1038 /* 1039 * for superpage mappings, make a fake leaf PTE for the TLB's 1040 * benefit. 1041 */ 1042 target_ulong vpn = addr >> PGSHIFT; 1043 1044 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1045 napot_bits = ctzl(ppn) + 1; 1046 if ((i != (levels - 1)) || (napot_bits != 4)) { 1047 return TRANSLATE_FAIL; 1048 } 1049 } 1050 1051 napot_mask = (1 << napot_bits) - 1; 1052 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1053 (vpn & (((target_ulong)1 << ptshift) - 1)) 1054 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1055 1056 /* set permissions on the TLB entry */ 1057 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1058 *prot |= PAGE_READ; 1059 } 1060 if (pte & PTE_X) { 1061 *prot |= PAGE_EXEC; 1062 } 1063 /* 1064 * add write permission on stores or if the page is already dirty, 1065 * so that we TLB miss on later writes to update the dirty bit 1066 */ 1067 if ((pte & PTE_W) && 1068 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1069 *prot |= PAGE_WRITE; 1070 } 1071 return TRANSLATE_SUCCESS; 1072 } 1073 } 1074 return TRANSLATE_FAIL; 1075 } 1076 1077 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1078 MMUAccessType access_type, bool pmp_violation, 1079 bool first_stage, bool two_stage, 1080 bool two_stage_indirect) 1081 { 1082 CPUState *cs = env_cpu(env); 1083 int page_fault_exceptions, vm; 1084 uint64_t stap_mode; 1085 1086 if (riscv_cpu_mxl(env) == MXL_RV32) { 1087 stap_mode = SATP32_MODE; 1088 } else { 1089 stap_mode = SATP64_MODE; 1090 } 1091 1092 if (first_stage) { 1093 vm = get_field(env->satp, stap_mode); 1094 } else { 1095 vm = get_field(env->hgatp, stap_mode); 1096 } 1097 1098 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1099 1100 switch (access_type) { 1101 case MMU_INST_FETCH: 1102 if (env->virt_enabled && !first_stage) { 1103 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1104 } else { 1105 cs->exception_index = page_fault_exceptions ? 1106 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1107 } 1108 break; 1109 case MMU_DATA_LOAD: 1110 if (two_stage && !first_stage) { 1111 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1112 } else { 1113 cs->exception_index = page_fault_exceptions ? 1114 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1115 } 1116 break; 1117 case MMU_DATA_STORE: 1118 if (two_stage && !first_stage) { 1119 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1120 } else { 1121 cs->exception_index = page_fault_exceptions ? 1122 RISCV_EXCP_STORE_PAGE_FAULT : 1123 RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1124 } 1125 break; 1126 default: 1127 g_assert_not_reached(); 1128 } 1129 env->badaddr = address; 1130 env->two_stage_lookup = two_stage; 1131 env->two_stage_indirect_lookup = two_stage_indirect; 1132 } 1133 1134 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1135 { 1136 RISCVCPU *cpu = RISCV_CPU(cs); 1137 CPURISCVState *env = &cpu->env; 1138 hwaddr phys_addr; 1139 int prot; 1140 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1141 1142 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1143 true, env->virt_enabled, true)) { 1144 return -1; 1145 } 1146 1147 if (env->virt_enabled) { 1148 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1149 0, mmu_idx, false, true, true)) { 1150 return -1; 1151 } 1152 } 1153 1154 return phys_addr & TARGET_PAGE_MASK; 1155 } 1156 1157 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1158 vaddr addr, unsigned size, 1159 MMUAccessType access_type, 1160 int mmu_idx, MemTxAttrs attrs, 1161 MemTxResult response, uintptr_t retaddr) 1162 { 1163 RISCVCPU *cpu = RISCV_CPU(cs); 1164 CPURISCVState *env = &cpu->env; 1165 1166 if (access_type == MMU_DATA_STORE) { 1167 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1168 } else if (access_type == MMU_DATA_LOAD) { 1169 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1170 } else { 1171 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1172 } 1173 1174 env->badaddr = addr; 1175 env->two_stage_lookup = env->virt_enabled || 1176 riscv_cpu_two_stage_lookup(mmu_idx); 1177 env->two_stage_indirect_lookup = false; 1178 cpu_loop_exit_restore(cs, retaddr); 1179 } 1180 1181 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1182 MMUAccessType access_type, int mmu_idx, 1183 uintptr_t retaddr) 1184 { 1185 RISCVCPU *cpu = RISCV_CPU(cs); 1186 CPURISCVState *env = &cpu->env; 1187 switch (access_type) { 1188 case MMU_INST_FETCH: 1189 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1190 break; 1191 case MMU_DATA_LOAD: 1192 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1193 break; 1194 case MMU_DATA_STORE: 1195 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1196 break; 1197 default: 1198 g_assert_not_reached(); 1199 } 1200 env->badaddr = addr; 1201 env->two_stage_lookup = env->virt_enabled || 1202 riscv_cpu_two_stage_lookup(mmu_idx); 1203 env->two_stage_indirect_lookup = false; 1204 cpu_loop_exit_restore(cs, retaddr); 1205 } 1206 1207 1208 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1209 { 1210 enum riscv_pmu_event_idx pmu_event_type; 1211 1212 switch (access_type) { 1213 case MMU_INST_FETCH: 1214 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1215 break; 1216 case MMU_DATA_LOAD: 1217 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1218 break; 1219 case MMU_DATA_STORE: 1220 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1221 break; 1222 default: 1223 return; 1224 } 1225 1226 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1227 } 1228 1229 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1230 MMUAccessType access_type, int mmu_idx, 1231 bool probe, uintptr_t retaddr) 1232 { 1233 RISCVCPU *cpu = RISCV_CPU(cs); 1234 CPURISCVState *env = &cpu->env; 1235 vaddr im_address; 1236 hwaddr pa = 0; 1237 int prot, prot2, prot_pmp; 1238 bool pmp_violation = false; 1239 bool first_stage_error = true; 1240 bool two_stage_lookup = false; 1241 bool two_stage_indirect_error = false; 1242 int ret = TRANSLATE_FAIL; 1243 int mode = mmu_idx; 1244 /* default TLB page size */ 1245 target_ulong tlb_size = TARGET_PAGE_SIZE; 1246 1247 env->guest_phys_fault_addr = 0; 1248 1249 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1250 __func__, address, access_type, mmu_idx); 1251 1252 /* 1253 * MPRV does not affect the virtual-machine load/store 1254 * instructions, HLV, HLVX, and HSV. 1255 */ 1256 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1257 mode = get_field(env->hstatus, HSTATUS_SPVP); 1258 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1259 get_field(env->mstatus, MSTATUS_MPRV)) { 1260 mode = get_field(env->mstatus, MSTATUS_MPP); 1261 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1262 two_stage_lookup = true; 1263 } 1264 } 1265 1266 pmu_tlb_fill_incr_ctr(cpu, access_type); 1267 if (env->virt_enabled || 1268 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1269 access_type != MMU_INST_FETCH)) { 1270 /* Two stage lookup */ 1271 ret = get_physical_address(env, &pa, &prot, address, 1272 &env->guest_phys_fault_addr, access_type, 1273 mmu_idx, true, true, false); 1274 1275 /* 1276 * A G-stage exception may be triggered during two state lookup. 1277 * And the env->guest_phys_fault_addr has already been set in 1278 * get_physical_address(). 1279 */ 1280 if (ret == TRANSLATE_G_STAGE_FAIL) { 1281 first_stage_error = false; 1282 two_stage_indirect_error = true; 1283 access_type = MMU_DATA_LOAD; 1284 } 1285 1286 qemu_log_mask(CPU_LOG_MMU, 1287 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1288 HWADDR_FMT_plx " prot %d\n", 1289 __func__, address, ret, pa, prot); 1290 1291 if (ret == TRANSLATE_SUCCESS) { 1292 /* Second stage lookup */ 1293 im_address = pa; 1294 1295 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1296 access_type, mmu_idx, false, true, 1297 false); 1298 1299 qemu_log_mask(CPU_LOG_MMU, 1300 "%s 2nd-stage address=%" VADDR_PRIx 1301 " ret %d physical " 1302 HWADDR_FMT_plx " prot %d\n", 1303 __func__, im_address, ret, pa, prot2); 1304 1305 prot &= prot2; 1306 1307 if (ret == TRANSLATE_SUCCESS) { 1308 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1309 size, access_type, mode); 1310 1311 qemu_log_mask(CPU_LOG_MMU, 1312 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1313 " %d tlb_size " TARGET_FMT_lu "\n", 1314 __func__, pa, ret, prot_pmp, tlb_size); 1315 1316 prot &= prot_pmp; 1317 } 1318 1319 if (ret != TRANSLATE_SUCCESS) { 1320 /* 1321 * Guest physical address translation failed, this is a HS 1322 * level exception 1323 */ 1324 first_stage_error = false; 1325 env->guest_phys_fault_addr = (im_address | 1326 (address & 1327 (TARGET_PAGE_SIZE - 1))) >> 2; 1328 } 1329 } 1330 } else { 1331 /* Single stage lookup */ 1332 ret = get_physical_address(env, &pa, &prot, address, NULL, 1333 access_type, mmu_idx, true, false, false); 1334 1335 qemu_log_mask(CPU_LOG_MMU, 1336 "%s address=%" VADDR_PRIx " ret %d physical " 1337 HWADDR_FMT_plx " prot %d\n", 1338 __func__, address, ret, pa, prot); 1339 1340 if (ret == TRANSLATE_SUCCESS) { 1341 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1342 size, access_type, mode); 1343 1344 qemu_log_mask(CPU_LOG_MMU, 1345 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1346 " %d tlb_size " TARGET_FMT_lu "\n", 1347 __func__, pa, ret, prot_pmp, tlb_size); 1348 1349 prot &= prot_pmp; 1350 } 1351 } 1352 1353 if (ret == TRANSLATE_PMP_FAIL) { 1354 pmp_violation = true; 1355 } 1356 1357 if (ret == TRANSLATE_SUCCESS) { 1358 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1359 prot, mmu_idx, tlb_size); 1360 return true; 1361 } else if (probe) { 1362 return false; 1363 } else { 1364 raise_mmu_exception(env, address, access_type, pmp_violation, 1365 first_stage_error, 1366 env->virt_enabled || 1367 riscv_cpu_two_stage_lookup(mmu_idx), 1368 two_stage_indirect_error); 1369 cpu_loop_exit_restore(cs, retaddr); 1370 } 1371 1372 return true; 1373 } 1374 1375 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1376 target_ulong insn, 1377 target_ulong taddr) 1378 { 1379 target_ulong xinsn = 0; 1380 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1381 1382 /* 1383 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1384 * be uncompressed. The Quadrant 1 of RVC instruction space need 1385 * not be transformed because these instructions won't generate 1386 * any load/store trap. 1387 */ 1388 1389 if ((insn & 0x3) != 0x3) { 1390 /* Transform 16bit instruction into 32bit instruction */ 1391 switch (GET_C_OP(insn)) { 1392 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1393 switch (GET_C_FUNC(insn)) { 1394 case OPC_RISC_C_FUNC_FLD_LQ: 1395 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1396 xinsn = OPC_RISC_FLD; 1397 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1398 access_rs1 = GET_C_RS1S(insn); 1399 access_imm = GET_C_LD_IMM(insn); 1400 access_size = 8; 1401 } 1402 break; 1403 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1404 xinsn = OPC_RISC_LW; 1405 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1406 access_rs1 = GET_C_RS1S(insn); 1407 access_imm = GET_C_LW_IMM(insn); 1408 access_size = 4; 1409 break; 1410 case OPC_RISC_C_FUNC_FLW_LD: 1411 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1412 xinsn = OPC_RISC_FLW; 1413 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1414 access_rs1 = GET_C_RS1S(insn); 1415 access_imm = GET_C_LW_IMM(insn); 1416 access_size = 4; 1417 } else { /* C.LD (RV64/RV128) */ 1418 xinsn = OPC_RISC_LD; 1419 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1420 access_rs1 = GET_C_RS1S(insn); 1421 access_imm = GET_C_LD_IMM(insn); 1422 access_size = 8; 1423 } 1424 break; 1425 case OPC_RISC_C_FUNC_FSD_SQ: 1426 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1427 xinsn = OPC_RISC_FSD; 1428 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1429 access_rs1 = GET_C_RS1S(insn); 1430 access_imm = GET_C_SD_IMM(insn); 1431 access_size = 8; 1432 } 1433 break; 1434 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1435 xinsn = OPC_RISC_SW; 1436 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1437 access_rs1 = GET_C_RS1S(insn); 1438 access_imm = GET_C_SW_IMM(insn); 1439 access_size = 4; 1440 break; 1441 case OPC_RISC_C_FUNC_FSW_SD: 1442 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1443 xinsn = OPC_RISC_FSW; 1444 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1445 access_rs1 = GET_C_RS1S(insn); 1446 access_imm = GET_C_SW_IMM(insn); 1447 access_size = 4; 1448 } else { /* C.SD (RV64/RV128) */ 1449 xinsn = OPC_RISC_SD; 1450 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1451 access_rs1 = GET_C_RS1S(insn); 1452 access_imm = GET_C_SD_IMM(insn); 1453 access_size = 8; 1454 } 1455 break; 1456 default: 1457 break; 1458 } 1459 break; 1460 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1461 switch (GET_C_FUNC(insn)) { 1462 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1463 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1464 xinsn = OPC_RISC_FLD; 1465 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1466 access_rs1 = 2; 1467 access_imm = GET_C_LDSP_IMM(insn); 1468 access_size = 8; 1469 } 1470 break; 1471 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1472 xinsn = OPC_RISC_LW; 1473 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1474 access_rs1 = 2; 1475 access_imm = GET_C_LWSP_IMM(insn); 1476 access_size = 4; 1477 break; 1478 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1479 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1480 xinsn = OPC_RISC_FLW; 1481 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1482 access_rs1 = 2; 1483 access_imm = GET_C_LWSP_IMM(insn); 1484 access_size = 4; 1485 } else { /* C.LDSP (RV64/RV128) */ 1486 xinsn = OPC_RISC_LD; 1487 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1488 access_rs1 = 2; 1489 access_imm = GET_C_LDSP_IMM(insn); 1490 access_size = 8; 1491 } 1492 break; 1493 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1494 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1495 xinsn = OPC_RISC_FSD; 1496 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1497 access_rs1 = 2; 1498 access_imm = GET_C_SDSP_IMM(insn); 1499 access_size = 8; 1500 } 1501 break; 1502 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1503 xinsn = OPC_RISC_SW; 1504 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1505 access_rs1 = 2; 1506 access_imm = GET_C_SWSP_IMM(insn); 1507 access_size = 4; 1508 break; 1509 case 7: 1510 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1511 xinsn = OPC_RISC_FSW; 1512 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1513 access_rs1 = 2; 1514 access_imm = GET_C_SWSP_IMM(insn); 1515 access_size = 4; 1516 } else { /* C.SDSP (RV64/RV128) */ 1517 xinsn = OPC_RISC_SD; 1518 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1519 access_rs1 = 2; 1520 access_imm = GET_C_SDSP_IMM(insn); 1521 access_size = 8; 1522 } 1523 break; 1524 default: 1525 break; 1526 } 1527 break; 1528 default: 1529 break; 1530 } 1531 1532 /* 1533 * Clear Bit1 of transformed instruction to indicate that 1534 * original insruction was a 16bit instruction 1535 */ 1536 xinsn &= ~((target_ulong)0x2); 1537 } else { 1538 /* Transform 32bit (or wider) instructions */ 1539 switch (MASK_OP_MAJOR(insn)) { 1540 case OPC_RISC_ATOMIC: 1541 xinsn = insn; 1542 access_rs1 = GET_RS1(insn); 1543 access_size = 1 << GET_FUNCT3(insn); 1544 break; 1545 case OPC_RISC_LOAD: 1546 case OPC_RISC_FP_LOAD: 1547 xinsn = SET_I_IMM(insn, 0); 1548 access_rs1 = GET_RS1(insn); 1549 access_imm = GET_IMM(insn); 1550 access_size = 1 << GET_FUNCT3(insn); 1551 break; 1552 case OPC_RISC_STORE: 1553 case OPC_RISC_FP_STORE: 1554 xinsn = SET_S_IMM(insn, 0); 1555 access_rs1 = GET_RS1(insn); 1556 access_imm = GET_STORE_IMM(insn); 1557 access_size = 1 << GET_FUNCT3(insn); 1558 break; 1559 case OPC_RISC_SYSTEM: 1560 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1561 xinsn = insn; 1562 access_rs1 = GET_RS1(insn); 1563 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1564 access_size = 1 << access_size; 1565 } 1566 break; 1567 default: 1568 break; 1569 } 1570 } 1571 1572 if (access_size) { 1573 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1574 (access_size - 1)); 1575 } 1576 1577 return xinsn; 1578 } 1579 #endif /* !CONFIG_USER_ONLY */ 1580 1581 /* 1582 * Handle Traps 1583 * 1584 * Adapted from Spike's processor_t::take_trap. 1585 * 1586 */ 1587 void riscv_cpu_do_interrupt(CPUState *cs) 1588 { 1589 #if !defined(CONFIG_USER_ONLY) 1590 1591 RISCVCPU *cpu = RISCV_CPU(cs); 1592 CPURISCVState *env = &cpu->env; 1593 bool write_gva = false; 1594 uint64_t s; 1595 1596 /* 1597 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1598 * so we mask off the MSB and separate into trap type and cause. 1599 */ 1600 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1601 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1602 uint64_t deleg = async ? env->mideleg : env->medeleg; 1603 target_ulong tval = 0; 1604 target_ulong tinst = 0; 1605 target_ulong htval = 0; 1606 target_ulong mtval2 = 0; 1607 1608 if (cause == RISCV_EXCP_SEMIHOST) { 1609 do_common_semihosting(cs); 1610 env->pc += 4; 1611 return; 1612 } 1613 1614 if (!async) { 1615 /* set tval to badaddr for traps with address information */ 1616 switch (cause) { 1617 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1618 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1619 case RISCV_EXCP_LOAD_ADDR_MIS: 1620 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1621 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1622 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1623 case RISCV_EXCP_LOAD_PAGE_FAULT: 1624 case RISCV_EXCP_STORE_PAGE_FAULT: 1625 write_gva = env->two_stage_lookup; 1626 tval = env->badaddr; 1627 if (env->two_stage_indirect_lookup) { 1628 /* 1629 * special pseudoinstruction for G-stage fault taken while 1630 * doing VS-stage page table walk. 1631 */ 1632 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1633 } else { 1634 /* 1635 * The "Addr. Offset" field in transformed instruction is 1636 * non-zero only for misaligned access. 1637 */ 1638 tinst = riscv_transformed_insn(env, env->bins, tval); 1639 } 1640 break; 1641 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1642 case RISCV_EXCP_INST_ADDR_MIS: 1643 case RISCV_EXCP_INST_ACCESS_FAULT: 1644 case RISCV_EXCP_INST_PAGE_FAULT: 1645 write_gva = env->two_stage_lookup; 1646 tval = env->badaddr; 1647 if (env->two_stage_indirect_lookup) { 1648 /* 1649 * special pseudoinstruction for G-stage fault taken while 1650 * doing VS-stage page table walk. 1651 */ 1652 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1653 } 1654 break; 1655 case RISCV_EXCP_ILLEGAL_INST: 1656 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1657 tval = env->bins; 1658 break; 1659 case RISCV_EXCP_BREAKPOINT: 1660 if (cs->watchpoint_hit) { 1661 tval = cs->watchpoint_hit->hitaddr; 1662 cs->watchpoint_hit = NULL; 1663 } 1664 break; 1665 default: 1666 break; 1667 } 1668 /* ecall is dispatched as one cause so translate based on mode */ 1669 if (cause == RISCV_EXCP_U_ECALL) { 1670 assert(env->priv <= 3); 1671 1672 if (env->priv == PRV_M) { 1673 cause = RISCV_EXCP_M_ECALL; 1674 } else if (env->priv == PRV_S && env->virt_enabled) { 1675 cause = RISCV_EXCP_VS_ECALL; 1676 } else if (env->priv == PRV_S && !env->virt_enabled) { 1677 cause = RISCV_EXCP_S_ECALL; 1678 } else if (env->priv == PRV_U) { 1679 cause = RISCV_EXCP_U_ECALL; 1680 } 1681 } 1682 } 1683 1684 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1685 riscv_cpu_get_trap_name(cause, async)); 1686 1687 qemu_log_mask(CPU_LOG_INT, 1688 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1689 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1690 __func__, env->mhartid, async, cause, env->pc, tval, 1691 riscv_cpu_get_trap_name(cause, async)); 1692 1693 if (env->priv <= PRV_S && 1694 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1695 /* handle the trap in S-mode */ 1696 if (riscv_has_ext(env, RVH)) { 1697 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1698 1699 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1700 /* Trap to VS mode */ 1701 /* 1702 * See if we need to adjust cause. Yes if its VS mode interrupt 1703 * no if hypervisor has delegated one of hs mode's interrupt 1704 */ 1705 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1706 cause == IRQ_VS_EXT) { 1707 cause = cause - 1; 1708 } 1709 write_gva = false; 1710 } else if (env->virt_enabled) { 1711 /* Trap into HS mode, from virt */ 1712 riscv_cpu_swap_hypervisor_regs(env); 1713 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1714 env->priv); 1715 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1716 1717 htval = env->guest_phys_fault_addr; 1718 1719 riscv_cpu_set_virt_enabled(env, 0); 1720 } else { 1721 /* Trap into HS mode */ 1722 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1723 htval = env->guest_phys_fault_addr; 1724 } 1725 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1726 } 1727 1728 s = env->mstatus; 1729 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1730 s = set_field(s, MSTATUS_SPP, env->priv); 1731 s = set_field(s, MSTATUS_SIE, 0); 1732 env->mstatus = s; 1733 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1734 env->sepc = env->pc; 1735 env->stval = tval; 1736 env->htval = htval; 1737 env->htinst = tinst; 1738 env->pc = (env->stvec >> 2 << 2) + 1739 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1740 riscv_cpu_set_mode(env, PRV_S); 1741 } else { 1742 /* handle the trap in M-mode */ 1743 if (riscv_has_ext(env, RVH)) { 1744 if (env->virt_enabled) { 1745 riscv_cpu_swap_hypervisor_regs(env); 1746 } 1747 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1748 env->virt_enabled); 1749 if (env->virt_enabled && tval) { 1750 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1751 } 1752 1753 mtval2 = env->guest_phys_fault_addr; 1754 1755 /* Trapping to M mode, virt is disabled */ 1756 riscv_cpu_set_virt_enabled(env, 0); 1757 } 1758 1759 s = env->mstatus; 1760 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1761 s = set_field(s, MSTATUS_MPP, env->priv); 1762 s = set_field(s, MSTATUS_MIE, 0); 1763 env->mstatus = s; 1764 env->mcause = cause | ~(((target_ulong)-1) >> async); 1765 env->mepc = env->pc; 1766 env->mtval = tval; 1767 env->mtval2 = mtval2; 1768 env->mtinst = tinst; 1769 env->pc = (env->mtvec >> 2 << 2) + 1770 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1771 riscv_cpu_set_mode(env, PRV_M); 1772 } 1773 1774 /* 1775 * NOTE: it is not necessary to yield load reservations here. It is only 1776 * necessary for an SC from "another hart" to cause a load reservation 1777 * to be yielded. Refer to the memory consistency model section of the 1778 * RISC-V ISA Specification. 1779 */ 1780 1781 env->two_stage_lookup = false; 1782 env->two_stage_indirect_lookup = false; 1783 #endif 1784 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1785 } 1786