1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 29 { 30 #ifdef CONFIG_USER_ONLY 31 return 0; 32 #else 33 return env->priv; 34 #endif 35 } 36 37 #ifndef CONFIG_USER_ONLY 38 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 39 { 40 target_ulong irqs; 41 42 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 43 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 44 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 45 46 target_ulong pending = env->mip & env->mie & 47 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 48 target_ulong vspending = (env->mip & env->mie & 49 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; 50 51 target_ulong mie = env->priv < PRV_M || 52 (env->priv == PRV_M && mstatus_mie); 53 target_ulong sie = env->priv < PRV_S || 54 (env->priv == PRV_S && mstatus_sie); 55 target_ulong hs_sie = env->priv < PRV_S || 56 (env->priv == PRV_S && hs_mstatus_sie); 57 58 if (riscv_cpu_virt_enabled(env)) { 59 target_ulong pending_hs_irq = pending & -hs_sie; 60 61 if (pending_hs_irq) { 62 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 63 return ctz64(pending_hs_irq); 64 } 65 66 pending = vspending; 67 } 68 69 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 70 71 if (irqs) { 72 return ctz64(irqs); /* since non-zero */ 73 } else { 74 return EXCP_NONE; /* indicates no pending interrupt */ 75 } 76 } 77 #endif 78 79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (interrupt_request & CPU_INTERRUPT_HARD) { 83 RISCVCPU *cpu = RISCV_CPU(cs); 84 CPURISCVState *env = &cpu->env; 85 int interruptno = riscv_cpu_local_irq_pending(env); 86 if (interruptno >= 0) { 87 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 88 riscv_cpu_do_interrupt(cs); 89 return true; 90 } 91 } 92 #endif 93 return false; 94 } 95 96 #if !defined(CONFIG_USER_ONLY) 97 98 /* Return true is floating point support is currently enabled */ 99 bool riscv_cpu_fp_enabled(CPURISCVState *env) 100 { 101 if (env->mstatus & MSTATUS_FS) { 102 return true; 103 } 104 105 return false; 106 } 107 108 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 109 { 110 target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 111 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; 112 bool current_virt = riscv_cpu_virt_enabled(env); 113 114 g_assert(riscv_has_ext(env, RVH)); 115 116 #if defined(TARGET_RISCV64) 117 mstatus_mask |= MSTATUS64_UXL; 118 #endif 119 120 if (current_virt) { 121 /* Current V=1 and we are about to change to V=0 */ 122 env->vsstatus = env->mstatus & mstatus_mask; 123 env->mstatus &= ~mstatus_mask; 124 env->mstatus |= env->mstatus_hs; 125 126 env->vstvec = env->stvec; 127 env->stvec = env->stvec_hs; 128 129 env->vsscratch = env->sscratch; 130 env->sscratch = env->sscratch_hs; 131 132 env->vsepc = env->sepc; 133 env->sepc = env->sepc_hs; 134 135 env->vscause = env->scause; 136 env->scause = env->scause_hs; 137 138 env->vstval = env->sbadaddr; 139 env->sbadaddr = env->stval_hs; 140 141 env->vsatp = env->satp; 142 env->satp = env->satp_hs; 143 } else { 144 /* Current V=0 and we are about to change to V=1 */ 145 env->mstatus_hs = env->mstatus & mstatus_mask; 146 env->mstatus &= ~mstatus_mask; 147 env->mstatus |= env->vsstatus; 148 149 env->stvec_hs = env->stvec; 150 env->stvec = env->vstvec; 151 152 env->sscratch_hs = env->sscratch; 153 env->sscratch = env->vsscratch; 154 155 env->sepc_hs = env->sepc; 156 env->sepc = env->vsepc; 157 158 env->scause_hs = env->scause; 159 env->scause = env->vscause; 160 161 env->stval_hs = env->sbadaddr; 162 env->sbadaddr = env->vstval; 163 164 env->satp_hs = env->satp; 165 env->satp = env->vsatp; 166 } 167 } 168 169 bool riscv_cpu_virt_enabled(CPURISCVState *env) 170 { 171 if (!riscv_has_ext(env, RVH)) { 172 return false; 173 } 174 175 return get_field(env->virt, VIRT_ONOFF); 176 } 177 178 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 179 { 180 if (!riscv_has_ext(env, RVH)) { 181 return; 182 } 183 184 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 185 } 186 187 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 188 { 189 if (!riscv_has_ext(env, RVH)) { 190 return false; 191 } 192 193 return get_field(env->virt, FORCE_HS_EXCEP); 194 } 195 196 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 197 { 198 if (!riscv_has_ext(env, RVH)) { 199 return; 200 } 201 202 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 203 } 204 205 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 206 { 207 CPURISCVState *env = &cpu->env; 208 if (env->miclaim & interrupts) { 209 return -1; 210 } else { 211 env->miclaim |= interrupts; 212 return 0; 213 } 214 } 215 216 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 217 { 218 CPURISCVState *env = &cpu->env; 219 CPUState *cs = CPU(cpu); 220 uint32_t old = env->mip; 221 bool locked = false; 222 223 if (!qemu_mutex_iothread_locked()) { 224 locked = true; 225 qemu_mutex_lock_iothread(); 226 } 227 228 env->mip = (env->mip & ~mask) | (value & mask); 229 230 if (env->mip) { 231 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 232 } else { 233 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 234 } 235 236 if (locked) { 237 qemu_mutex_unlock_iothread(); 238 } 239 240 return old; 241 } 242 243 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 244 { 245 if (newpriv > PRV_M) { 246 g_assert_not_reached(); 247 } 248 if (newpriv == PRV_H) { 249 newpriv = PRV_U; 250 } 251 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 252 env->priv = newpriv; 253 254 /* 255 * Clear the load reservation - otherwise a reservation placed in one 256 * context/process can be used by another, resulting in an SC succeeding 257 * incorrectly. Version 2.2 of the ISA specification explicitly requires 258 * this behaviour, while later revisions say that the kernel "should" use 259 * an SC instruction to force the yielding of a load reservation on a 260 * preemptive context switch. As a result, do both. 261 */ 262 env->load_res = -1; 263 } 264 265 /* get_physical_address - get the physical address for this virtual address 266 * 267 * Do a page table walk to obtain the physical address corresponding to a 268 * virtual address. Returns 0 if the translation was successful 269 * 270 * Adapted from Spike's mmu_t::translate and mmu_t::walk 271 * 272 */ 273 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 274 int *prot, target_ulong addr, 275 int access_type, int mmu_idx) 276 { 277 /* NOTE: the env->pc value visible here will not be 278 * correct, but the value visible to the exception handler 279 * (riscv_cpu_do_interrupt) is correct */ 280 MemTxResult res; 281 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 282 int mode = mmu_idx; 283 284 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 285 if (get_field(env->mstatus, MSTATUS_MPRV)) { 286 mode = get_field(env->mstatus, MSTATUS_MPP); 287 } 288 } 289 290 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 291 *physical = addr; 292 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 293 return TRANSLATE_SUCCESS; 294 } 295 296 *prot = 0; 297 298 hwaddr base; 299 int levels, ptidxbits, ptesize, vm, sum; 300 int mxr = get_field(env->mstatus, MSTATUS_MXR); 301 302 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 303 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 304 sum = get_field(env->mstatus, MSTATUS_SUM); 305 vm = get_field(env->satp, SATP_MODE); 306 switch (vm) { 307 case VM_1_10_SV32: 308 levels = 2; ptidxbits = 10; ptesize = 4; break; 309 case VM_1_10_SV39: 310 levels = 3; ptidxbits = 9; ptesize = 8; break; 311 case VM_1_10_SV48: 312 levels = 4; ptidxbits = 9; ptesize = 8; break; 313 case VM_1_10_SV57: 314 levels = 5; ptidxbits = 9; ptesize = 8; break; 315 case VM_1_10_MBARE: 316 *physical = addr; 317 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 318 return TRANSLATE_SUCCESS; 319 default: 320 g_assert_not_reached(); 321 } 322 } else { 323 base = (hwaddr)(env->sptbr) << PGSHIFT; 324 sum = !get_field(env->mstatus, MSTATUS_PUM); 325 vm = get_field(env->mstatus, MSTATUS_VM); 326 switch (vm) { 327 case VM_1_09_SV32: 328 levels = 2; ptidxbits = 10; ptesize = 4; break; 329 case VM_1_09_SV39: 330 levels = 3; ptidxbits = 9; ptesize = 8; break; 331 case VM_1_09_SV48: 332 levels = 4; ptidxbits = 9; ptesize = 8; break; 333 case VM_1_09_MBARE: 334 *physical = addr; 335 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 336 return TRANSLATE_SUCCESS; 337 default: 338 g_assert_not_reached(); 339 } 340 } 341 342 CPUState *cs = env_cpu(env); 343 int va_bits = PGSHIFT + levels * ptidxbits; 344 target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 345 target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; 346 if (masked_msbs != 0 && masked_msbs != mask) { 347 return TRANSLATE_FAIL; 348 } 349 350 int ptshift = (levels - 1) * ptidxbits; 351 int i; 352 353 #if !TCG_OVERSIZED_GUEST 354 restart: 355 #endif 356 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 357 target_ulong idx = (addr >> (PGSHIFT + ptshift)) & 358 ((1 << ptidxbits) - 1); 359 360 /* check that physical address of PTE is legal */ 361 hwaddr pte_addr = base + idx * ptesize; 362 363 if (riscv_feature(env, RISCV_FEATURE_PMP) && 364 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), 365 1 << MMU_DATA_LOAD, PRV_S)) { 366 return TRANSLATE_PMP_FAIL; 367 } 368 369 #if defined(TARGET_RISCV32) 370 target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 371 #elif defined(TARGET_RISCV64) 372 target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 373 #endif 374 if (res != MEMTX_OK) { 375 return TRANSLATE_FAIL; 376 } 377 378 hwaddr ppn = pte >> PTE_PPN_SHIFT; 379 380 if (!(pte & PTE_V)) { 381 /* Invalid PTE */ 382 return TRANSLATE_FAIL; 383 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 384 /* Inner PTE, continue walking */ 385 base = ppn << PGSHIFT; 386 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 387 /* Reserved leaf PTE flags: PTE_W */ 388 return TRANSLATE_FAIL; 389 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 390 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 391 return TRANSLATE_FAIL; 392 } else if ((pte & PTE_U) && ((mode != PRV_U) && 393 (!sum || access_type == MMU_INST_FETCH))) { 394 /* User PTE flags when not U mode and mstatus.SUM is not set, 395 or the access type is an instruction fetch */ 396 return TRANSLATE_FAIL; 397 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 398 /* Supervisor PTE flags when not S mode */ 399 return TRANSLATE_FAIL; 400 } else if (ppn & ((1ULL << ptshift) - 1)) { 401 /* Misaligned PPN */ 402 return TRANSLATE_FAIL; 403 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 404 ((pte & PTE_X) && mxr))) { 405 /* Read access check failed */ 406 return TRANSLATE_FAIL; 407 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 408 /* Write access check failed */ 409 return TRANSLATE_FAIL; 410 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 411 /* Fetch access check failed */ 412 return TRANSLATE_FAIL; 413 } else { 414 /* if necessary, set accessed and dirty bits. */ 415 target_ulong updated_pte = pte | PTE_A | 416 (access_type == MMU_DATA_STORE ? PTE_D : 0); 417 418 /* Page table updates need to be atomic with MTTCG enabled */ 419 if (updated_pte != pte) { 420 /* 421 * - if accessed or dirty bits need updating, and the PTE is 422 * in RAM, then we do so atomically with a compare and swap. 423 * - if the PTE is in IO space or ROM, then it can't be updated 424 * and we return TRANSLATE_FAIL. 425 * - if the PTE changed by the time we went to update it, then 426 * it is no longer valid and we must re-walk the page table. 427 */ 428 MemoryRegion *mr; 429 hwaddr l = sizeof(target_ulong), addr1; 430 mr = address_space_translate(cs->as, pte_addr, 431 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 432 if (memory_region_is_ram(mr)) { 433 target_ulong *pte_pa = 434 qemu_map_ram_ptr(mr->ram_block, addr1); 435 #if TCG_OVERSIZED_GUEST 436 /* MTTCG is not enabled on oversized TCG guests so 437 * page table updates do not need to be atomic */ 438 *pte_pa = pte = updated_pte; 439 #else 440 target_ulong old_pte = 441 atomic_cmpxchg(pte_pa, pte, updated_pte); 442 if (old_pte != pte) { 443 goto restart; 444 } else { 445 pte = updated_pte; 446 } 447 #endif 448 } else { 449 /* misconfigured PTE in ROM (AD bits are not preset) or 450 * PTE is in IO space and can't be updated atomically */ 451 return TRANSLATE_FAIL; 452 } 453 } 454 455 /* for superpage mappings, make a fake leaf PTE for the TLB's 456 benefit. */ 457 target_ulong vpn = addr >> PGSHIFT; 458 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 459 460 /* set permissions on the TLB entry */ 461 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 462 *prot |= PAGE_READ; 463 } 464 if ((pte & PTE_X)) { 465 *prot |= PAGE_EXEC; 466 } 467 /* add write permission on stores or if the page is already dirty, 468 so that we TLB miss on later writes to update the dirty bit */ 469 if ((pte & PTE_W) && 470 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 471 *prot |= PAGE_WRITE; 472 } 473 return TRANSLATE_SUCCESS; 474 } 475 } 476 return TRANSLATE_FAIL; 477 } 478 479 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 480 MMUAccessType access_type, bool pmp_violation) 481 { 482 CPUState *cs = env_cpu(env); 483 int page_fault_exceptions = 484 (env->priv_ver >= PRIV_VERSION_1_10_0) && 485 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 486 !pmp_violation; 487 switch (access_type) { 488 case MMU_INST_FETCH: 489 cs->exception_index = page_fault_exceptions ? 490 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 491 break; 492 case MMU_DATA_LOAD: 493 cs->exception_index = page_fault_exceptions ? 494 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 495 break; 496 case MMU_DATA_STORE: 497 cs->exception_index = page_fault_exceptions ? 498 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 499 break; 500 default: 501 g_assert_not_reached(); 502 } 503 env->badaddr = address; 504 } 505 506 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 507 { 508 RISCVCPU *cpu = RISCV_CPU(cs); 509 hwaddr phys_addr; 510 int prot; 511 int mmu_idx = cpu_mmu_index(&cpu->env, false); 512 513 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { 514 return -1; 515 } 516 return phys_addr; 517 } 518 519 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 520 vaddr addr, unsigned size, 521 MMUAccessType access_type, 522 int mmu_idx, MemTxAttrs attrs, 523 MemTxResult response, uintptr_t retaddr) 524 { 525 RISCVCPU *cpu = RISCV_CPU(cs); 526 CPURISCVState *env = &cpu->env; 527 528 if (access_type == MMU_DATA_STORE) { 529 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 530 } else { 531 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 532 } 533 534 env->badaddr = addr; 535 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 536 } 537 538 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 539 MMUAccessType access_type, int mmu_idx, 540 uintptr_t retaddr) 541 { 542 RISCVCPU *cpu = RISCV_CPU(cs); 543 CPURISCVState *env = &cpu->env; 544 switch (access_type) { 545 case MMU_INST_FETCH: 546 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 547 break; 548 case MMU_DATA_LOAD: 549 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 550 break; 551 case MMU_DATA_STORE: 552 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 553 break; 554 default: 555 g_assert_not_reached(); 556 } 557 env->badaddr = addr; 558 riscv_raise_exception(env, cs->exception_index, retaddr); 559 } 560 #endif 561 562 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 563 MMUAccessType access_type, int mmu_idx, 564 bool probe, uintptr_t retaddr) 565 { 566 RISCVCPU *cpu = RISCV_CPU(cs); 567 CPURISCVState *env = &cpu->env; 568 #ifndef CONFIG_USER_ONLY 569 hwaddr pa = 0; 570 int prot; 571 bool pmp_violation = false; 572 int ret = TRANSLATE_FAIL; 573 int mode = mmu_idx; 574 575 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 576 __func__, address, access_type, mmu_idx); 577 578 ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); 579 580 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 581 if (get_field(env->mstatus, MSTATUS_MPRV)) { 582 mode = get_field(env->mstatus, MSTATUS_MPP); 583 } 584 } 585 586 qemu_log_mask(CPU_LOG_MMU, 587 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx 588 " prot %d\n", __func__, address, ret, pa, prot); 589 590 if (riscv_feature(env, RISCV_FEATURE_PMP) && 591 (ret == TRANSLATE_SUCCESS) && 592 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 593 ret = TRANSLATE_PMP_FAIL; 594 } 595 if (ret == TRANSLATE_PMP_FAIL) { 596 pmp_violation = true; 597 } 598 if (ret == TRANSLATE_SUCCESS) { 599 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 600 prot, mmu_idx, TARGET_PAGE_SIZE); 601 return true; 602 } else if (probe) { 603 return false; 604 } else { 605 raise_mmu_exception(env, address, access_type, pmp_violation); 606 riscv_raise_exception(env, cs->exception_index, retaddr); 607 } 608 #else 609 switch (access_type) { 610 case MMU_INST_FETCH: 611 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 612 break; 613 case MMU_DATA_LOAD: 614 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 615 break; 616 case MMU_DATA_STORE: 617 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 618 break; 619 default: 620 g_assert_not_reached(); 621 } 622 env->badaddr = address; 623 cpu_loop_exit_restore(cs, retaddr); 624 #endif 625 } 626 627 /* 628 * Handle Traps 629 * 630 * Adapted from Spike's processor_t::take_trap. 631 * 632 */ 633 void riscv_cpu_do_interrupt(CPUState *cs) 634 { 635 #if !defined(CONFIG_USER_ONLY) 636 637 RISCVCPU *cpu = RISCV_CPU(cs); 638 CPURISCVState *env = &cpu->env; 639 640 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 641 * so we mask off the MSB and separate into trap type and cause. 642 */ 643 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 644 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 645 target_ulong deleg = async ? env->mideleg : env->medeleg; 646 target_ulong tval = 0; 647 648 static const int ecall_cause_map[] = { 649 [PRV_U] = RISCV_EXCP_U_ECALL, 650 [PRV_S] = RISCV_EXCP_S_ECALL, 651 [PRV_H] = RISCV_EXCP_VS_ECALL, 652 [PRV_M] = RISCV_EXCP_M_ECALL 653 }; 654 655 if (!async) { 656 /* set tval to badaddr for traps with address information */ 657 switch (cause) { 658 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 659 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 660 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 661 case RISCV_EXCP_INST_ADDR_MIS: 662 case RISCV_EXCP_INST_ACCESS_FAULT: 663 case RISCV_EXCP_LOAD_ADDR_MIS: 664 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 665 case RISCV_EXCP_LOAD_ACCESS_FAULT: 666 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 667 case RISCV_EXCP_INST_PAGE_FAULT: 668 case RISCV_EXCP_LOAD_PAGE_FAULT: 669 case RISCV_EXCP_STORE_PAGE_FAULT: 670 tval = env->badaddr; 671 break; 672 default: 673 break; 674 } 675 /* ecall is dispatched as one cause so translate based on mode */ 676 if (cause == RISCV_EXCP_U_ECALL) { 677 assert(env->priv <= 3); 678 cause = ecall_cause_map[env->priv]; 679 } 680 } 681 682 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? 683 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 684 685 if (env->priv <= PRV_S && 686 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 687 /* handle the trap in S-mode */ 688 target_ulong s = env->mstatus; 689 s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 690 get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); 691 s = set_field(s, MSTATUS_SPP, env->priv); 692 s = set_field(s, MSTATUS_SIE, 0); 693 env->mstatus = s; 694 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 695 env->sepc = env->pc; 696 env->sbadaddr = tval; 697 env->pc = (env->stvec >> 2 << 2) + 698 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 699 riscv_cpu_set_mode(env, PRV_S); 700 } else { 701 /* handle the trap in M-mode */ 702 target_ulong s = env->mstatus; 703 s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 704 get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); 705 s = set_field(s, MSTATUS_MPP, env->priv); 706 s = set_field(s, MSTATUS_MIE, 0); 707 env->mstatus = s; 708 env->mcause = cause | ~(((target_ulong)-1) >> async); 709 env->mepc = env->pc; 710 env->mbadaddr = tval; 711 env->pc = (env->mtvec >> 2 << 2) + 712 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 713 riscv_cpu_set_mode(env, PRV_M); 714 } 715 716 /* NOTE: it is not necessary to yield load reservations here. It is only 717 * necessary for an SC from "another hart" to cause a load reservation 718 * to be yielded. Refer to the memory consistency model section of the 719 * RISC-V ISA Specification. 720 */ 721 722 #endif 723 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 724 } 725