1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (cpu->cfg.ext_zve32f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 } else { 78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 79 } 80 81 #ifdef CONFIG_USER_ONLY 82 flags |= TB_FLAGS_MSTATUS_FS; 83 flags |= TB_FLAGS_MSTATUS_VS; 84 #else 85 flags |= cpu_mmu_index(env, 0); 86 if (riscv_cpu_fp_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_FS; 88 } 89 90 if (riscv_cpu_vector_enabled(env)) { 91 flags |= env->mstatus & MSTATUS_VS; 92 } 93 94 if (riscv_has_ext(env, RVH)) { 95 if (env->priv == PRV_M || 96 (env->priv == PRV_S && !env->virt_enabled) || 97 (env->priv == PRV_U && !env->virt_enabled && 98 get_field(env->hstatus, HSTATUS_HU))) { 99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 100 } 101 102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 103 get_field(env->mstatus_hs, MSTATUS_FS)); 104 105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 106 get_field(env->mstatus_hs, MSTATUS_VS)); 107 } 108 if (cpu->cfg.debug && !icount_enabled()) { 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 110 } 111 #endif 112 113 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 114 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 115 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 116 } 117 if (env->cur_pmbase != 0) { 118 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 119 } 120 121 *pflags = flags; 122 } 123 124 void riscv_cpu_update_mask(CPURISCVState *env) 125 { 126 target_ulong mask = -1, base = 0; 127 /* 128 * TODO: Current RVJ spec does not specify 129 * how the extension interacts with XLEN. 130 */ 131 #ifndef CONFIG_USER_ONLY 132 if (riscv_has_ext(env, RVJ)) { 133 switch (env->priv) { 134 case PRV_M: 135 if (env->mmte & M_PM_ENABLE) { 136 mask = env->mpmmask; 137 base = env->mpmbase; 138 } 139 break; 140 case PRV_S: 141 if (env->mmte & S_PM_ENABLE) { 142 mask = env->spmmask; 143 base = env->spmbase; 144 } 145 break; 146 case PRV_U: 147 if (env->mmte & U_PM_ENABLE) { 148 mask = env->upmmask; 149 base = env->upmbase; 150 } 151 break; 152 default: 153 g_assert_not_reached(); 154 } 155 } 156 #endif 157 if (env->xl == MXL_RV32) { 158 env->cur_pmmask = mask & UINT32_MAX; 159 env->cur_pmbase = base & UINT32_MAX; 160 } else { 161 env->cur_pmmask = mask; 162 env->cur_pmbase = base; 163 } 164 } 165 166 #ifndef CONFIG_USER_ONLY 167 168 /* 169 * The HS-mode is allowed to configure priority only for the 170 * following VS-mode local interrupts: 171 * 172 * 0 (Reserved interrupt, reads as zero) 173 * 1 Supervisor software interrupt 174 * 4 (Reserved interrupt, reads as zero) 175 * 5 Supervisor timer interrupt 176 * 8 (Reserved interrupt, reads as zero) 177 * 13 (Reserved interrupt) 178 * 14 " 179 * 15 " 180 * 16 " 181 * 17 " 182 * 18 " 183 * 19 " 184 * 20 " 185 * 21 " 186 * 22 " 187 * 23 " 188 */ 189 190 static const int hviprio_index2irq[] = { 191 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 192 static const int hviprio_index2rdzero[] = { 193 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 194 195 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 196 { 197 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 198 return -EINVAL; 199 } 200 201 if (out_irq) { 202 *out_irq = hviprio_index2irq[index]; 203 } 204 205 if (out_rdzero) { 206 *out_rdzero = hviprio_index2rdzero[index]; 207 } 208 209 return 0; 210 } 211 212 /* 213 * Default priorities of local interrupts are defined in the 214 * RISC-V Advanced Interrupt Architecture specification. 215 * 216 * ---------------------------------------------------------------- 217 * Default | 218 * Priority | Major Interrupt Numbers 219 * ---------------------------------------------------------------- 220 * Highest | 47, 23, 46, 45, 22, 44, 221 * | 43, 21, 42, 41, 20, 40 222 * | 223 * | 11 (0b), 3 (03), 7 (07) 224 * | 9 (09), 1 (01), 5 (05) 225 * | 12 (0c) 226 * | 10 (0a), 2 (02), 6 (06) 227 * | 228 * | 39, 19, 38, 37, 18, 36, 229 * Lowest | 35, 17, 34, 33, 16, 32 230 * ---------------------------------------------------------------- 231 */ 232 static const uint8_t default_iprio[64] = { 233 /* Custom interrupts 48 to 63 */ 234 [63] = IPRIO_MMAXIPRIO, 235 [62] = IPRIO_MMAXIPRIO, 236 [61] = IPRIO_MMAXIPRIO, 237 [60] = IPRIO_MMAXIPRIO, 238 [59] = IPRIO_MMAXIPRIO, 239 [58] = IPRIO_MMAXIPRIO, 240 [57] = IPRIO_MMAXIPRIO, 241 [56] = IPRIO_MMAXIPRIO, 242 [55] = IPRIO_MMAXIPRIO, 243 [54] = IPRIO_MMAXIPRIO, 244 [53] = IPRIO_MMAXIPRIO, 245 [52] = IPRIO_MMAXIPRIO, 246 [51] = IPRIO_MMAXIPRIO, 247 [50] = IPRIO_MMAXIPRIO, 248 [49] = IPRIO_MMAXIPRIO, 249 [48] = IPRIO_MMAXIPRIO, 250 251 /* Custom interrupts 24 to 31 */ 252 [31] = IPRIO_MMAXIPRIO, 253 [30] = IPRIO_MMAXIPRIO, 254 [29] = IPRIO_MMAXIPRIO, 255 [28] = IPRIO_MMAXIPRIO, 256 [27] = IPRIO_MMAXIPRIO, 257 [26] = IPRIO_MMAXIPRIO, 258 [25] = IPRIO_MMAXIPRIO, 259 [24] = IPRIO_MMAXIPRIO, 260 261 [47] = IPRIO_DEFAULT_UPPER, 262 [23] = IPRIO_DEFAULT_UPPER + 1, 263 [46] = IPRIO_DEFAULT_UPPER + 2, 264 [45] = IPRIO_DEFAULT_UPPER + 3, 265 [22] = IPRIO_DEFAULT_UPPER + 4, 266 [44] = IPRIO_DEFAULT_UPPER + 5, 267 268 [43] = IPRIO_DEFAULT_UPPER + 6, 269 [21] = IPRIO_DEFAULT_UPPER + 7, 270 [42] = IPRIO_DEFAULT_UPPER + 8, 271 [41] = IPRIO_DEFAULT_UPPER + 9, 272 [20] = IPRIO_DEFAULT_UPPER + 10, 273 [40] = IPRIO_DEFAULT_UPPER + 11, 274 275 [11] = IPRIO_DEFAULT_M, 276 [3] = IPRIO_DEFAULT_M + 1, 277 [7] = IPRIO_DEFAULT_M + 2, 278 279 [9] = IPRIO_DEFAULT_S, 280 [1] = IPRIO_DEFAULT_S + 1, 281 [5] = IPRIO_DEFAULT_S + 2, 282 283 [12] = IPRIO_DEFAULT_SGEXT, 284 285 [10] = IPRIO_DEFAULT_VS, 286 [2] = IPRIO_DEFAULT_VS + 1, 287 [6] = IPRIO_DEFAULT_VS + 2, 288 289 [39] = IPRIO_DEFAULT_LOWER, 290 [19] = IPRIO_DEFAULT_LOWER + 1, 291 [38] = IPRIO_DEFAULT_LOWER + 2, 292 [37] = IPRIO_DEFAULT_LOWER + 3, 293 [18] = IPRIO_DEFAULT_LOWER + 4, 294 [36] = IPRIO_DEFAULT_LOWER + 5, 295 296 [35] = IPRIO_DEFAULT_LOWER + 6, 297 [17] = IPRIO_DEFAULT_LOWER + 7, 298 [34] = IPRIO_DEFAULT_LOWER + 8, 299 [33] = IPRIO_DEFAULT_LOWER + 9, 300 [16] = IPRIO_DEFAULT_LOWER + 10, 301 [32] = IPRIO_DEFAULT_LOWER + 11, 302 }; 303 304 uint8_t riscv_cpu_default_priority(int irq) 305 { 306 if (irq < 0 || irq > 63) { 307 return IPRIO_MMAXIPRIO; 308 } 309 310 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 311 }; 312 313 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 314 int extirq, unsigned int extirq_def_prio, 315 uint64_t pending, uint8_t *iprio) 316 { 317 int irq, best_irq = RISCV_EXCP_NONE; 318 unsigned int prio, best_prio = UINT_MAX; 319 320 if (!pending) { 321 return RISCV_EXCP_NONE; 322 } 323 324 irq = ctz64(pending); 325 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 326 riscv_cpu_cfg(env)->ext_ssaia)) { 327 return irq; 328 } 329 330 pending = pending >> irq; 331 while (pending) { 332 prio = iprio[irq]; 333 if (!prio) { 334 if (irq == extirq) { 335 prio = extirq_def_prio; 336 } else { 337 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 338 1 : IPRIO_MMAXIPRIO; 339 } 340 } 341 if ((pending & 0x1) && (prio <= best_prio)) { 342 best_irq = irq; 343 best_prio = prio; 344 } 345 irq++; 346 pending = pending >> 1; 347 } 348 349 return best_irq; 350 } 351 352 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 353 { 354 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 355 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 356 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 357 358 return (env->mip | vsgein | vstip) & env->mie; 359 } 360 361 int riscv_cpu_mirq_pending(CPURISCVState *env) 362 { 363 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 364 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 365 366 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 367 irqs, env->miprio); 368 } 369 370 int riscv_cpu_sirq_pending(CPURISCVState *env) 371 { 372 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 373 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 374 375 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 376 irqs, env->siprio); 377 } 378 379 int riscv_cpu_vsirq_pending(CPURISCVState *env) 380 { 381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 382 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 383 384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 385 irqs >> 1, env->hviprio); 386 } 387 388 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 389 { 390 int virq; 391 uint64_t irqs, pending, mie, hsie, vsie; 392 393 /* Determine interrupt enable state of all privilege modes */ 394 if (env->virt_enabled) { 395 mie = 1; 396 hsie = 1; 397 vsie = (env->priv < PRV_S) || 398 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 399 } else { 400 mie = (env->priv < PRV_M) || 401 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 402 hsie = (env->priv < PRV_S) || 403 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 404 vsie = 0; 405 } 406 407 /* Determine all pending interrupts */ 408 pending = riscv_cpu_all_pending(env); 409 410 /* Check M-mode interrupts */ 411 irqs = pending & ~env->mideleg & -mie; 412 if (irqs) { 413 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 414 irqs, env->miprio); 415 } 416 417 /* Check HS-mode interrupts */ 418 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 419 if (irqs) { 420 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 421 irqs, env->siprio); 422 } 423 424 /* Check VS-mode interrupts */ 425 irqs = pending & env->mideleg & env->hideleg & -vsie; 426 if (irqs) { 427 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 428 irqs >> 1, env->hviprio); 429 return (virq <= 0) ? virq : virq + 1; 430 } 431 432 /* Indicate no pending interrupt */ 433 return RISCV_EXCP_NONE; 434 } 435 436 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 437 { 438 if (interrupt_request & CPU_INTERRUPT_HARD) { 439 RISCVCPU *cpu = RISCV_CPU(cs); 440 CPURISCVState *env = &cpu->env; 441 int interruptno = riscv_cpu_local_irq_pending(env); 442 if (interruptno >= 0) { 443 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 444 riscv_cpu_do_interrupt(cs); 445 return true; 446 } 447 } 448 return false; 449 } 450 451 /* Return true is floating point support is currently enabled */ 452 bool riscv_cpu_fp_enabled(CPURISCVState *env) 453 { 454 if (env->mstatus & MSTATUS_FS) { 455 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 456 return false; 457 } 458 return true; 459 } 460 461 return false; 462 } 463 464 /* Return true is vector support is currently enabled */ 465 bool riscv_cpu_vector_enabled(CPURISCVState *env) 466 { 467 if (env->mstatus & MSTATUS_VS) { 468 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 469 return false; 470 } 471 return true; 472 } 473 474 return false; 475 } 476 477 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 478 { 479 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 480 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 481 MSTATUS64_UXL | MSTATUS_VS; 482 483 if (riscv_has_ext(env, RVF)) { 484 mstatus_mask |= MSTATUS_FS; 485 } 486 bool current_virt = env->virt_enabled; 487 488 g_assert(riscv_has_ext(env, RVH)); 489 490 if (current_virt) { 491 /* Current V=1 and we are about to change to V=0 */ 492 env->vsstatus = env->mstatus & mstatus_mask; 493 env->mstatus &= ~mstatus_mask; 494 env->mstatus |= env->mstatus_hs; 495 496 env->vstvec = env->stvec; 497 env->stvec = env->stvec_hs; 498 499 env->vsscratch = env->sscratch; 500 env->sscratch = env->sscratch_hs; 501 502 env->vsepc = env->sepc; 503 env->sepc = env->sepc_hs; 504 505 env->vscause = env->scause; 506 env->scause = env->scause_hs; 507 508 env->vstval = env->stval; 509 env->stval = env->stval_hs; 510 511 env->vsatp = env->satp; 512 env->satp = env->satp_hs; 513 } else { 514 /* Current V=0 and we are about to change to V=1 */ 515 env->mstatus_hs = env->mstatus & mstatus_mask; 516 env->mstatus &= ~mstatus_mask; 517 env->mstatus |= env->vsstatus; 518 519 env->stvec_hs = env->stvec; 520 env->stvec = env->vstvec; 521 522 env->sscratch_hs = env->sscratch; 523 env->sscratch = env->vsscratch; 524 525 env->sepc_hs = env->sepc; 526 env->sepc = env->vsepc; 527 528 env->scause_hs = env->scause; 529 env->scause = env->vscause; 530 531 env->stval_hs = env->stval; 532 env->stval = env->vstval; 533 534 env->satp_hs = env->satp; 535 env->satp = env->vsatp; 536 } 537 } 538 539 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 540 { 541 if (!riscv_has_ext(env, RVH)) { 542 return 0; 543 } 544 545 return env->geilen; 546 } 547 548 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 549 { 550 if (!riscv_has_ext(env, RVH)) { 551 return; 552 } 553 554 if (geilen > (TARGET_LONG_BITS - 1)) { 555 return; 556 } 557 558 env->geilen = geilen; 559 } 560 561 /* This function can only be called to set virt when RVH is enabled */ 562 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 563 { 564 /* Flush the TLB on all virt mode changes. */ 565 if (env->virt_enabled != enable) { 566 tlb_flush(env_cpu(env)); 567 } 568 569 env->virt_enabled = enable; 570 571 if (enable) { 572 /* 573 * The guest external interrupts from an interrupt controller are 574 * delivered only when the Guest/VM is running (i.e. V=1). This means 575 * any guest external interrupt which is triggered while the Guest/VM 576 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 577 * with sluggish response to serial console input and other I/O events. 578 * 579 * To solve this, we check and inject interrupt after setting V=1. 580 */ 581 riscv_cpu_update_mip(env, 0, 0); 582 } 583 } 584 585 bool riscv_cpu_two_stage_lookup(int mmu_idx) 586 { 587 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 588 } 589 590 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 591 { 592 CPURISCVState *env = &cpu->env; 593 if (env->miclaim & interrupts) { 594 return -1; 595 } else { 596 env->miclaim |= interrupts; 597 return 0; 598 } 599 } 600 601 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 602 uint64_t value) 603 { 604 CPUState *cs = env_cpu(env); 605 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 606 607 if (env->virt_enabled) { 608 gein = get_field(env->hstatus, HSTATUS_VGEIN); 609 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 610 } 611 612 vstip = env->vstime_irq ? MIP_VSTIP : 0; 613 614 QEMU_IOTHREAD_LOCK_GUARD(); 615 616 env->mip = (env->mip & ~mask) | (value & mask); 617 618 if (env->mip | vsgein | vstip) { 619 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 620 } else { 621 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 622 } 623 624 return old; 625 } 626 627 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 628 void *arg) 629 { 630 env->rdtime_fn = fn; 631 env->rdtime_fn_arg = arg; 632 } 633 634 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 635 int (*rmw_fn)(void *arg, 636 target_ulong reg, 637 target_ulong *val, 638 target_ulong new_val, 639 target_ulong write_mask), 640 void *rmw_fn_arg) 641 { 642 if (priv <= PRV_M) { 643 env->aia_ireg_rmw_fn[priv] = rmw_fn; 644 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 645 } 646 } 647 648 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 649 { 650 if (newpriv > PRV_M) { 651 g_assert_not_reached(); 652 } 653 if (newpriv == PRV_H) { 654 newpriv = PRV_U; 655 } 656 if (icount_enabled() && newpriv != env->priv) { 657 riscv_itrigger_update_priv(env); 658 } 659 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 660 env->priv = newpriv; 661 env->xl = cpu_recompute_xl(env); 662 riscv_cpu_update_mask(env); 663 664 /* 665 * Clear the load reservation - otherwise a reservation placed in one 666 * context/process can be used by another, resulting in an SC succeeding 667 * incorrectly. Version 2.2 of the ISA specification explicitly requires 668 * this behaviour, while later revisions say that the kernel "should" use 669 * an SC instruction to force the yielding of a load reservation on a 670 * preemptive context switch. As a result, do both. 671 */ 672 env->load_res = -1; 673 } 674 675 /* 676 * get_physical_address_pmp - check PMP permission for this physical address 677 * 678 * Match the PMP region and check permission for this physical address and it's 679 * TLB page. Returns 0 if the permission checking was successful 680 * 681 * @env: CPURISCVState 682 * @prot: The returned protection attributes 683 * @tlb_size: TLB page size containing addr. It could be modified after PMP 684 * permission checking. NULL if not set TLB page for addr. 685 * @addr: The physical address to be checked permission 686 * @access_type: The type of MMU access 687 * @mode: Indicates current privilege level. 688 */ 689 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 690 target_ulong *tlb_size, hwaddr addr, 691 int size, MMUAccessType access_type, 692 int mode) 693 { 694 pmp_priv_t pmp_priv; 695 int pmp_index = -1; 696 697 if (!riscv_cpu_cfg(env)->pmp) { 698 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 699 return TRANSLATE_SUCCESS; 700 } 701 702 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 703 &pmp_priv, mode); 704 if (pmp_index < 0) { 705 *prot = 0; 706 return TRANSLATE_PMP_FAIL; 707 } 708 709 *prot = pmp_priv_to_page_prot(pmp_priv); 710 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 711 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 712 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 713 714 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 715 } 716 717 return TRANSLATE_SUCCESS; 718 } 719 720 /* 721 * get_physical_address - get the physical address for this virtual address 722 * 723 * Do a page table walk to obtain the physical address corresponding to a 724 * virtual address. Returns 0 if the translation was successful 725 * 726 * Adapted from Spike's mmu_t::translate and mmu_t::walk 727 * 728 * @env: CPURISCVState 729 * @physical: This will be set to the calculated physical address 730 * @prot: The returned protection attributes 731 * @addr: The virtual address or guest physical address to be translated 732 * @fault_pte_addr: If not NULL, this will be set to fault pte address 733 * when a error occurs on pte address translation. 734 * This will already be shifted to match htval. 735 * @access_type: The type of MMU access 736 * @mmu_idx: Indicates current privilege level 737 * @first_stage: Are we in first stage translation? 738 * Second stage is used for hypervisor guest translation 739 * @two_stage: Are we going to perform two stage translation 740 * @is_debug: Is this access from a debugger or the monitor? 741 */ 742 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 743 int *prot, vaddr addr, 744 target_ulong *fault_pte_addr, 745 int access_type, int mmu_idx, 746 bool first_stage, bool two_stage, 747 bool is_debug) 748 { 749 /* 750 * NOTE: the env->pc value visible here will not be 751 * correct, but the value visible to the exception handler 752 * (riscv_cpu_do_interrupt) is correct 753 */ 754 MemTxResult res; 755 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 756 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 757 bool use_background = false; 758 hwaddr ppn; 759 int napot_bits = 0; 760 target_ulong napot_mask; 761 762 /* 763 * Check if we should use the background registers for the two 764 * stage translation. We don't need to check if we actually need 765 * two stage translation as that happened before this function 766 * was called. Background registers will be used if the guest has 767 * forced a two stage translation to be on (in HS or M mode). 768 */ 769 if (!env->virt_enabled && two_stage) { 770 use_background = true; 771 } 772 773 /* 774 * MPRV does not affect the virtual-machine load/store 775 * instructions, HLV, HLVX, and HSV. 776 */ 777 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 778 mode = get_field(env->hstatus, HSTATUS_SPVP); 779 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 780 if (get_field(env->mstatus, MSTATUS_MPRV)) { 781 mode = get_field(env->mstatus, MSTATUS_MPP); 782 } 783 } 784 785 if (first_stage == false) { 786 /* 787 * We are in stage 2 translation, this is similar to stage 1. 788 * Stage 2 is always taken as U-mode 789 */ 790 mode = PRV_U; 791 } 792 793 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 794 *physical = addr; 795 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 796 return TRANSLATE_SUCCESS; 797 } 798 799 *prot = 0; 800 801 hwaddr base; 802 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 803 804 if (first_stage == true) { 805 mxr = get_field(env->mstatus, MSTATUS_MXR); 806 } else { 807 mxr = get_field(env->vsstatus, MSTATUS_MXR); 808 } 809 810 if (first_stage == true) { 811 if (use_background) { 812 if (riscv_cpu_mxl(env) == MXL_RV32) { 813 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 814 vm = get_field(env->vsatp, SATP32_MODE); 815 } else { 816 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 817 vm = get_field(env->vsatp, SATP64_MODE); 818 } 819 } else { 820 if (riscv_cpu_mxl(env) == MXL_RV32) { 821 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 822 vm = get_field(env->satp, SATP32_MODE); 823 } else { 824 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 825 vm = get_field(env->satp, SATP64_MODE); 826 } 827 } 828 widened = 0; 829 } else { 830 if (riscv_cpu_mxl(env) == MXL_RV32) { 831 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 832 vm = get_field(env->hgatp, SATP32_MODE); 833 } else { 834 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 835 vm = get_field(env->hgatp, SATP64_MODE); 836 } 837 widened = 2; 838 } 839 /* status.SUM will be ignored if execute on background */ 840 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 841 switch (vm) { 842 case VM_1_10_SV32: 843 levels = 2; ptidxbits = 10; ptesize = 4; break; 844 case VM_1_10_SV39: 845 levels = 3; ptidxbits = 9; ptesize = 8; break; 846 case VM_1_10_SV48: 847 levels = 4; ptidxbits = 9; ptesize = 8; break; 848 case VM_1_10_SV57: 849 levels = 5; ptidxbits = 9; ptesize = 8; break; 850 case VM_1_10_MBARE: 851 *physical = addr; 852 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 853 return TRANSLATE_SUCCESS; 854 default: 855 g_assert_not_reached(); 856 } 857 858 CPUState *cs = env_cpu(env); 859 int va_bits = PGSHIFT + levels * ptidxbits + widened; 860 target_ulong mask, masked_msbs; 861 862 if (TARGET_LONG_BITS > (va_bits - 1)) { 863 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 864 } else { 865 mask = 0; 866 } 867 masked_msbs = (addr >> (va_bits - 1)) & mask; 868 869 if (masked_msbs != 0 && masked_msbs != mask) { 870 return TRANSLATE_FAIL; 871 } 872 873 int ptshift = (levels - 1) * ptidxbits; 874 int i; 875 876 #if !TCG_OVERSIZED_GUEST 877 restart: 878 #endif 879 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 880 target_ulong idx; 881 if (i == 0) { 882 idx = (addr >> (PGSHIFT + ptshift)) & 883 ((1 << (ptidxbits + widened)) - 1); 884 } else { 885 idx = (addr >> (PGSHIFT + ptshift)) & 886 ((1 << ptidxbits) - 1); 887 } 888 889 /* check that physical address of PTE is legal */ 890 hwaddr pte_addr; 891 892 if (two_stage && first_stage) { 893 int vbase_prot; 894 hwaddr vbase; 895 896 /* Do the second stage translation on the base PTE address. */ 897 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 898 base, NULL, MMU_DATA_LOAD, 899 mmu_idx, false, true, 900 is_debug); 901 902 if (vbase_ret != TRANSLATE_SUCCESS) { 903 if (fault_pte_addr) { 904 *fault_pte_addr = (base + idx * ptesize) >> 2; 905 } 906 return TRANSLATE_G_STAGE_FAIL; 907 } 908 909 pte_addr = vbase + idx * ptesize; 910 } else { 911 pte_addr = base + idx * ptesize; 912 } 913 914 int pmp_prot; 915 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 916 sizeof(target_ulong), 917 MMU_DATA_LOAD, PRV_S); 918 if (pmp_ret != TRANSLATE_SUCCESS) { 919 return TRANSLATE_PMP_FAIL; 920 } 921 922 target_ulong pte; 923 if (riscv_cpu_mxl(env) == MXL_RV32) { 924 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 925 } else { 926 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 927 } 928 929 if (res != MEMTX_OK) { 930 return TRANSLATE_FAIL; 931 } 932 933 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 934 bool hade = env->menvcfg & MENVCFG_HADE; 935 936 if (first_stage && two_stage && env->virt_enabled) { 937 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 938 hade = hade && (env->henvcfg & HENVCFG_HADE); 939 } 940 941 if (riscv_cpu_sxl(env) == MXL_RV32) { 942 ppn = pte >> PTE_PPN_SHIFT; 943 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 944 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 945 } else { 946 ppn = pte >> PTE_PPN_SHIFT; 947 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 948 return TRANSLATE_FAIL; 949 } 950 } 951 952 if (!(pte & PTE_V)) { 953 /* Invalid PTE */ 954 return TRANSLATE_FAIL; 955 } else if (!pbmte && (pte & PTE_PBMT)) { 956 return TRANSLATE_FAIL; 957 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 958 /* Inner PTE, continue walking */ 959 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 960 return TRANSLATE_FAIL; 961 } 962 base = ppn << PGSHIFT; 963 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 964 /* Reserved leaf PTE flags: PTE_W */ 965 return TRANSLATE_FAIL; 966 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 967 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 968 return TRANSLATE_FAIL; 969 } else if ((pte & PTE_U) && ((mode != PRV_U) && 970 (!sum || access_type == MMU_INST_FETCH))) { 971 /* User PTE flags when not U mode and mstatus.SUM is not set, 972 or the access type is an instruction fetch */ 973 return TRANSLATE_FAIL; 974 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 975 /* Supervisor PTE flags when not S mode */ 976 return TRANSLATE_FAIL; 977 } else if (ppn & ((1ULL << ptshift) - 1)) { 978 /* Misaligned PPN */ 979 return TRANSLATE_FAIL; 980 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 981 ((pte & PTE_X) && mxr))) { 982 /* Read access check failed */ 983 return TRANSLATE_FAIL; 984 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 985 /* Write access check failed */ 986 return TRANSLATE_FAIL; 987 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 988 /* Fetch access check failed */ 989 return TRANSLATE_FAIL; 990 } else { 991 /* if necessary, set accessed and dirty bits. */ 992 target_ulong updated_pte = pte | PTE_A | 993 (access_type == MMU_DATA_STORE ? PTE_D : 0); 994 995 /* Page table updates need to be atomic with MTTCG enabled */ 996 if (updated_pte != pte) { 997 if (!hade) { 998 return TRANSLATE_FAIL; 999 } 1000 1001 /* 1002 * - if accessed or dirty bits need updating, and the PTE is 1003 * in RAM, then we do so atomically with a compare and swap. 1004 * - if the PTE is in IO space or ROM, then it can't be updated 1005 * and we return TRANSLATE_FAIL. 1006 * - if the PTE changed by the time we went to update it, then 1007 * it is no longer valid and we must re-walk the page table. 1008 */ 1009 MemoryRegion *mr; 1010 hwaddr l = sizeof(target_ulong), addr1; 1011 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1012 false, MEMTXATTRS_UNSPECIFIED); 1013 if (memory_region_is_ram(mr)) { 1014 target_ulong *pte_pa = 1015 qemu_map_ram_ptr(mr->ram_block, addr1); 1016 #if TCG_OVERSIZED_GUEST 1017 /* 1018 * MTTCG is not enabled on oversized TCG guests so 1019 * page table updates do not need to be atomic 1020 */ 1021 *pte_pa = pte = updated_pte; 1022 #else 1023 target_ulong old_pte = 1024 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1025 if (old_pte != pte) { 1026 goto restart; 1027 } else { 1028 pte = updated_pte; 1029 } 1030 #endif 1031 } else { 1032 /* 1033 * misconfigured PTE in ROM (AD bits are not preset) or 1034 * PTE is in IO space and can't be updated atomically 1035 */ 1036 return TRANSLATE_FAIL; 1037 } 1038 } 1039 1040 /* 1041 * for superpage mappings, make a fake leaf PTE for the TLB's 1042 * benefit. 1043 */ 1044 target_ulong vpn = addr >> PGSHIFT; 1045 1046 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1047 napot_bits = ctzl(ppn) + 1; 1048 if ((i != (levels - 1)) || (napot_bits != 4)) { 1049 return TRANSLATE_FAIL; 1050 } 1051 } 1052 1053 napot_mask = (1 << napot_bits) - 1; 1054 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1055 (vpn & (((target_ulong)1 << ptshift) - 1)) 1056 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1057 1058 /* set permissions on the TLB entry */ 1059 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1060 *prot |= PAGE_READ; 1061 } 1062 if (pte & PTE_X) { 1063 *prot |= PAGE_EXEC; 1064 } 1065 /* 1066 * add write permission on stores or if the page is already dirty, 1067 * so that we TLB miss on later writes to update the dirty bit 1068 */ 1069 if ((pte & PTE_W) && 1070 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1071 *prot |= PAGE_WRITE; 1072 } 1073 return TRANSLATE_SUCCESS; 1074 } 1075 } 1076 return TRANSLATE_FAIL; 1077 } 1078 1079 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1080 MMUAccessType access_type, bool pmp_violation, 1081 bool first_stage, bool two_stage, 1082 bool two_stage_indirect) 1083 { 1084 CPUState *cs = env_cpu(env); 1085 int page_fault_exceptions, vm; 1086 uint64_t stap_mode; 1087 1088 if (riscv_cpu_mxl(env) == MXL_RV32) { 1089 stap_mode = SATP32_MODE; 1090 } else { 1091 stap_mode = SATP64_MODE; 1092 } 1093 1094 if (first_stage) { 1095 vm = get_field(env->satp, stap_mode); 1096 } else { 1097 vm = get_field(env->hgatp, stap_mode); 1098 } 1099 1100 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1101 1102 switch (access_type) { 1103 case MMU_INST_FETCH: 1104 if (env->virt_enabled && !first_stage) { 1105 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1106 } else { 1107 cs->exception_index = page_fault_exceptions ? 1108 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1109 } 1110 break; 1111 case MMU_DATA_LOAD: 1112 if (two_stage && !first_stage) { 1113 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1114 } else { 1115 cs->exception_index = page_fault_exceptions ? 1116 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1117 } 1118 break; 1119 case MMU_DATA_STORE: 1120 if (two_stage && !first_stage) { 1121 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1122 } else { 1123 cs->exception_index = page_fault_exceptions ? 1124 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1125 } 1126 break; 1127 default: 1128 g_assert_not_reached(); 1129 } 1130 env->badaddr = address; 1131 env->two_stage_lookup = two_stage; 1132 env->two_stage_indirect_lookup = two_stage_indirect; 1133 } 1134 1135 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1136 { 1137 RISCVCPU *cpu = RISCV_CPU(cs); 1138 CPURISCVState *env = &cpu->env; 1139 hwaddr phys_addr; 1140 int prot; 1141 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1142 1143 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1144 true, env->virt_enabled, true)) { 1145 return -1; 1146 } 1147 1148 if (env->virt_enabled) { 1149 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1150 0, mmu_idx, false, true, true)) { 1151 return -1; 1152 } 1153 } 1154 1155 return phys_addr & TARGET_PAGE_MASK; 1156 } 1157 1158 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1159 vaddr addr, unsigned size, 1160 MMUAccessType access_type, 1161 int mmu_idx, MemTxAttrs attrs, 1162 MemTxResult response, uintptr_t retaddr) 1163 { 1164 RISCVCPU *cpu = RISCV_CPU(cs); 1165 CPURISCVState *env = &cpu->env; 1166 1167 if (access_type == MMU_DATA_STORE) { 1168 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1169 } else if (access_type == MMU_DATA_LOAD) { 1170 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1171 } else { 1172 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1173 } 1174 1175 env->badaddr = addr; 1176 env->two_stage_lookup = env->virt_enabled || 1177 riscv_cpu_two_stage_lookup(mmu_idx); 1178 env->two_stage_indirect_lookup = false; 1179 cpu_loop_exit_restore(cs, retaddr); 1180 } 1181 1182 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1183 MMUAccessType access_type, int mmu_idx, 1184 uintptr_t retaddr) 1185 { 1186 RISCVCPU *cpu = RISCV_CPU(cs); 1187 CPURISCVState *env = &cpu->env; 1188 switch (access_type) { 1189 case MMU_INST_FETCH: 1190 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1191 break; 1192 case MMU_DATA_LOAD: 1193 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1194 break; 1195 case MMU_DATA_STORE: 1196 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1197 break; 1198 default: 1199 g_assert_not_reached(); 1200 } 1201 env->badaddr = addr; 1202 env->two_stage_lookup = env->virt_enabled || 1203 riscv_cpu_two_stage_lookup(mmu_idx); 1204 env->two_stage_indirect_lookup = false; 1205 cpu_loop_exit_restore(cs, retaddr); 1206 } 1207 1208 1209 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1210 { 1211 enum riscv_pmu_event_idx pmu_event_type; 1212 1213 switch (access_type) { 1214 case MMU_INST_FETCH: 1215 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1216 break; 1217 case MMU_DATA_LOAD: 1218 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1219 break; 1220 case MMU_DATA_STORE: 1221 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1222 break; 1223 default: 1224 return; 1225 } 1226 1227 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1228 } 1229 1230 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1231 MMUAccessType access_type, int mmu_idx, 1232 bool probe, uintptr_t retaddr) 1233 { 1234 RISCVCPU *cpu = RISCV_CPU(cs); 1235 CPURISCVState *env = &cpu->env; 1236 vaddr im_address; 1237 hwaddr pa = 0; 1238 int prot, prot2, prot_pmp; 1239 bool pmp_violation = false; 1240 bool first_stage_error = true; 1241 bool two_stage_lookup = false; 1242 bool two_stage_indirect_error = false; 1243 int ret = TRANSLATE_FAIL; 1244 int mode = mmu_idx; 1245 /* default TLB page size */ 1246 target_ulong tlb_size = TARGET_PAGE_SIZE; 1247 1248 env->guest_phys_fault_addr = 0; 1249 1250 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1251 __func__, address, access_type, mmu_idx); 1252 1253 /* 1254 * MPRV does not affect the virtual-machine load/store 1255 * instructions, HLV, HLVX, and HSV. 1256 */ 1257 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1258 mode = get_field(env->hstatus, HSTATUS_SPVP); 1259 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1260 get_field(env->mstatus, MSTATUS_MPRV)) { 1261 mode = get_field(env->mstatus, MSTATUS_MPP); 1262 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1263 two_stage_lookup = true; 1264 } 1265 } 1266 1267 pmu_tlb_fill_incr_ctr(cpu, access_type); 1268 if (env->virt_enabled || 1269 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1270 access_type != MMU_INST_FETCH)) { 1271 /* Two stage lookup */ 1272 ret = get_physical_address(env, &pa, &prot, address, 1273 &env->guest_phys_fault_addr, access_type, 1274 mmu_idx, true, true, false); 1275 1276 /* 1277 * A G-stage exception may be triggered during two state lookup. 1278 * And the env->guest_phys_fault_addr has already been set in 1279 * get_physical_address(). 1280 */ 1281 if (ret == TRANSLATE_G_STAGE_FAIL) { 1282 first_stage_error = false; 1283 two_stage_indirect_error = true; 1284 access_type = MMU_DATA_LOAD; 1285 } 1286 1287 qemu_log_mask(CPU_LOG_MMU, 1288 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1289 HWADDR_FMT_plx " prot %d\n", 1290 __func__, address, ret, pa, prot); 1291 1292 if (ret == TRANSLATE_SUCCESS) { 1293 /* Second stage lookup */ 1294 im_address = pa; 1295 1296 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1297 access_type, mmu_idx, false, true, 1298 false); 1299 1300 qemu_log_mask(CPU_LOG_MMU, 1301 "%s 2nd-stage address=%" VADDR_PRIx 1302 " ret %d physical " 1303 HWADDR_FMT_plx " prot %d\n", 1304 __func__, im_address, ret, pa, prot2); 1305 1306 prot &= prot2; 1307 1308 if (ret == TRANSLATE_SUCCESS) { 1309 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1310 size, access_type, mode); 1311 1312 qemu_log_mask(CPU_LOG_MMU, 1313 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1314 " %d tlb_size " TARGET_FMT_lu "\n", 1315 __func__, pa, ret, prot_pmp, tlb_size); 1316 1317 prot &= prot_pmp; 1318 } 1319 1320 if (ret != TRANSLATE_SUCCESS) { 1321 /* 1322 * Guest physical address translation failed, this is a HS 1323 * level exception 1324 */ 1325 first_stage_error = false; 1326 env->guest_phys_fault_addr = (im_address | 1327 (address & 1328 (TARGET_PAGE_SIZE - 1))) >> 2; 1329 } 1330 } 1331 } else { 1332 /* Single stage lookup */ 1333 ret = get_physical_address(env, &pa, &prot, address, NULL, 1334 access_type, mmu_idx, true, false, false); 1335 1336 qemu_log_mask(CPU_LOG_MMU, 1337 "%s address=%" VADDR_PRIx " ret %d physical " 1338 HWADDR_FMT_plx " prot %d\n", 1339 __func__, address, ret, pa, prot); 1340 1341 if (ret == TRANSLATE_SUCCESS) { 1342 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1343 size, access_type, mode); 1344 1345 qemu_log_mask(CPU_LOG_MMU, 1346 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1347 " %d tlb_size " TARGET_FMT_lu "\n", 1348 __func__, pa, ret, prot_pmp, tlb_size); 1349 1350 prot &= prot_pmp; 1351 } 1352 } 1353 1354 if (ret == TRANSLATE_PMP_FAIL) { 1355 pmp_violation = true; 1356 } 1357 1358 if (ret == TRANSLATE_SUCCESS) { 1359 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1360 prot, mmu_idx, tlb_size); 1361 return true; 1362 } else if (probe) { 1363 return false; 1364 } else { 1365 raise_mmu_exception(env, address, access_type, pmp_violation, 1366 first_stage_error, 1367 env->virt_enabled || 1368 riscv_cpu_two_stage_lookup(mmu_idx), 1369 two_stage_indirect_error); 1370 cpu_loop_exit_restore(cs, retaddr); 1371 } 1372 1373 return true; 1374 } 1375 1376 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1377 target_ulong insn, 1378 target_ulong taddr) 1379 { 1380 target_ulong xinsn = 0; 1381 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1382 1383 /* 1384 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1385 * be uncompressed. The Quadrant 1 of RVC instruction space need 1386 * not be transformed because these instructions won't generate 1387 * any load/store trap. 1388 */ 1389 1390 if ((insn & 0x3) != 0x3) { 1391 /* Transform 16bit instruction into 32bit instruction */ 1392 switch (GET_C_OP(insn)) { 1393 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1394 switch (GET_C_FUNC(insn)) { 1395 case OPC_RISC_C_FUNC_FLD_LQ: 1396 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1397 xinsn = OPC_RISC_FLD; 1398 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1399 access_rs1 = GET_C_RS1S(insn); 1400 access_imm = GET_C_LD_IMM(insn); 1401 access_size = 8; 1402 } 1403 break; 1404 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1405 xinsn = OPC_RISC_LW; 1406 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1407 access_rs1 = GET_C_RS1S(insn); 1408 access_imm = GET_C_LW_IMM(insn); 1409 access_size = 4; 1410 break; 1411 case OPC_RISC_C_FUNC_FLW_LD: 1412 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1413 xinsn = OPC_RISC_FLW; 1414 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1415 access_rs1 = GET_C_RS1S(insn); 1416 access_imm = GET_C_LW_IMM(insn); 1417 access_size = 4; 1418 } else { /* C.LD (RV64/RV128) */ 1419 xinsn = OPC_RISC_LD; 1420 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1421 access_rs1 = GET_C_RS1S(insn); 1422 access_imm = GET_C_LD_IMM(insn); 1423 access_size = 8; 1424 } 1425 break; 1426 case OPC_RISC_C_FUNC_FSD_SQ: 1427 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1428 xinsn = OPC_RISC_FSD; 1429 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1430 access_rs1 = GET_C_RS1S(insn); 1431 access_imm = GET_C_SD_IMM(insn); 1432 access_size = 8; 1433 } 1434 break; 1435 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1436 xinsn = OPC_RISC_SW; 1437 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1438 access_rs1 = GET_C_RS1S(insn); 1439 access_imm = GET_C_SW_IMM(insn); 1440 access_size = 4; 1441 break; 1442 case OPC_RISC_C_FUNC_FSW_SD: 1443 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1444 xinsn = OPC_RISC_FSW; 1445 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1446 access_rs1 = GET_C_RS1S(insn); 1447 access_imm = GET_C_SW_IMM(insn); 1448 access_size = 4; 1449 } else { /* C.SD (RV64/RV128) */ 1450 xinsn = OPC_RISC_SD; 1451 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1452 access_rs1 = GET_C_RS1S(insn); 1453 access_imm = GET_C_SD_IMM(insn); 1454 access_size = 8; 1455 } 1456 break; 1457 default: 1458 break; 1459 } 1460 break; 1461 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1462 switch (GET_C_FUNC(insn)) { 1463 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1464 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1465 xinsn = OPC_RISC_FLD; 1466 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1467 access_rs1 = 2; 1468 access_imm = GET_C_LDSP_IMM(insn); 1469 access_size = 8; 1470 } 1471 break; 1472 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1473 xinsn = OPC_RISC_LW; 1474 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1475 access_rs1 = 2; 1476 access_imm = GET_C_LWSP_IMM(insn); 1477 access_size = 4; 1478 break; 1479 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1480 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1481 xinsn = OPC_RISC_FLW; 1482 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1483 access_rs1 = 2; 1484 access_imm = GET_C_LWSP_IMM(insn); 1485 access_size = 4; 1486 } else { /* C.LDSP (RV64/RV128) */ 1487 xinsn = OPC_RISC_LD; 1488 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1489 access_rs1 = 2; 1490 access_imm = GET_C_LDSP_IMM(insn); 1491 access_size = 8; 1492 } 1493 break; 1494 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1495 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1496 xinsn = OPC_RISC_FSD; 1497 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1498 access_rs1 = 2; 1499 access_imm = GET_C_SDSP_IMM(insn); 1500 access_size = 8; 1501 } 1502 break; 1503 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1504 xinsn = OPC_RISC_SW; 1505 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1506 access_rs1 = 2; 1507 access_imm = GET_C_SWSP_IMM(insn); 1508 access_size = 4; 1509 break; 1510 case 7: 1511 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1512 xinsn = OPC_RISC_FSW; 1513 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1514 access_rs1 = 2; 1515 access_imm = GET_C_SWSP_IMM(insn); 1516 access_size = 4; 1517 } else { /* C.SDSP (RV64/RV128) */ 1518 xinsn = OPC_RISC_SD; 1519 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1520 access_rs1 = 2; 1521 access_imm = GET_C_SDSP_IMM(insn); 1522 access_size = 8; 1523 } 1524 break; 1525 default: 1526 break; 1527 } 1528 break; 1529 default: 1530 break; 1531 } 1532 1533 /* 1534 * Clear Bit1 of transformed instruction to indicate that 1535 * original insruction was a 16bit instruction 1536 */ 1537 xinsn &= ~((target_ulong)0x2); 1538 } else { 1539 /* Transform 32bit (or wider) instructions */ 1540 switch (MASK_OP_MAJOR(insn)) { 1541 case OPC_RISC_ATOMIC: 1542 xinsn = insn; 1543 access_rs1 = GET_RS1(insn); 1544 access_size = 1 << GET_FUNCT3(insn); 1545 break; 1546 case OPC_RISC_LOAD: 1547 case OPC_RISC_FP_LOAD: 1548 xinsn = SET_I_IMM(insn, 0); 1549 access_rs1 = GET_RS1(insn); 1550 access_imm = GET_IMM(insn); 1551 access_size = 1 << GET_FUNCT3(insn); 1552 break; 1553 case OPC_RISC_STORE: 1554 case OPC_RISC_FP_STORE: 1555 xinsn = SET_S_IMM(insn, 0); 1556 access_rs1 = GET_RS1(insn); 1557 access_imm = GET_STORE_IMM(insn); 1558 access_size = 1 << GET_FUNCT3(insn); 1559 break; 1560 case OPC_RISC_SYSTEM: 1561 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1562 xinsn = insn; 1563 access_rs1 = GET_RS1(insn); 1564 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1565 access_size = 1 << access_size; 1566 } 1567 break; 1568 default: 1569 break; 1570 } 1571 } 1572 1573 if (access_size) { 1574 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1575 (access_size - 1)); 1576 } 1577 1578 return xinsn; 1579 } 1580 #endif /* !CONFIG_USER_ONLY */ 1581 1582 /* 1583 * Handle Traps 1584 * 1585 * Adapted from Spike's processor_t::take_trap. 1586 * 1587 */ 1588 void riscv_cpu_do_interrupt(CPUState *cs) 1589 { 1590 #if !defined(CONFIG_USER_ONLY) 1591 1592 RISCVCPU *cpu = RISCV_CPU(cs); 1593 CPURISCVState *env = &cpu->env; 1594 bool write_gva = false; 1595 uint64_t s; 1596 1597 /* 1598 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1599 * so we mask off the MSB and separate into trap type and cause. 1600 */ 1601 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1602 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1603 uint64_t deleg = async ? env->mideleg : env->medeleg; 1604 target_ulong tval = 0; 1605 target_ulong tinst = 0; 1606 target_ulong htval = 0; 1607 target_ulong mtval2 = 0; 1608 1609 if (cause == RISCV_EXCP_SEMIHOST) { 1610 do_common_semihosting(cs); 1611 env->pc += 4; 1612 return; 1613 } 1614 1615 if (!async) { 1616 /* set tval to badaddr for traps with address information */ 1617 switch (cause) { 1618 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1619 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1620 case RISCV_EXCP_LOAD_ADDR_MIS: 1621 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1622 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1623 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1624 case RISCV_EXCP_LOAD_PAGE_FAULT: 1625 case RISCV_EXCP_STORE_PAGE_FAULT: 1626 write_gva = env->two_stage_lookup; 1627 tval = env->badaddr; 1628 if (env->two_stage_indirect_lookup) { 1629 /* 1630 * special pseudoinstruction for G-stage fault taken while 1631 * doing VS-stage page table walk. 1632 */ 1633 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1634 } else { 1635 /* 1636 * The "Addr. Offset" field in transformed instruction is 1637 * non-zero only for misaligned access. 1638 */ 1639 tinst = riscv_transformed_insn(env, env->bins, tval); 1640 } 1641 break; 1642 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1643 case RISCV_EXCP_INST_ADDR_MIS: 1644 case RISCV_EXCP_INST_ACCESS_FAULT: 1645 case RISCV_EXCP_INST_PAGE_FAULT: 1646 write_gva = env->two_stage_lookup; 1647 tval = env->badaddr; 1648 if (env->two_stage_indirect_lookup) { 1649 /* 1650 * special pseudoinstruction for G-stage fault taken while 1651 * doing VS-stage page table walk. 1652 */ 1653 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1654 } 1655 break; 1656 case RISCV_EXCP_ILLEGAL_INST: 1657 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1658 tval = env->bins; 1659 break; 1660 case RISCV_EXCP_BREAKPOINT: 1661 if (cs->watchpoint_hit) { 1662 tval = cs->watchpoint_hit->hitaddr; 1663 cs->watchpoint_hit = NULL; 1664 } 1665 break; 1666 default: 1667 break; 1668 } 1669 /* ecall is dispatched as one cause so translate based on mode */ 1670 if (cause == RISCV_EXCP_U_ECALL) { 1671 assert(env->priv <= 3); 1672 1673 if (env->priv == PRV_M) { 1674 cause = RISCV_EXCP_M_ECALL; 1675 } else if (env->priv == PRV_S && env->virt_enabled) { 1676 cause = RISCV_EXCP_VS_ECALL; 1677 } else if (env->priv == PRV_S && !env->virt_enabled) { 1678 cause = RISCV_EXCP_S_ECALL; 1679 } else if (env->priv == PRV_U) { 1680 cause = RISCV_EXCP_U_ECALL; 1681 } 1682 } 1683 } 1684 1685 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1686 riscv_cpu_get_trap_name(cause, async)); 1687 1688 qemu_log_mask(CPU_LOG_INT, 1689 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1690 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1691 __func__, env->mhartid, async, cause, env->pc, tval, 1692 riscv_cpu_get_trap_name(cause, async)); 1693 1694 if (env->priv <= PRV_S && 1695 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1696 /* handle the trap in S-mode */ 1697 if (riscv_has_ext(env, RVH)) { 1698 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1699 1700 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1701 /* Trap to VS mode */ 1702 /* 1703 * See if we need to adjust cause. Yes if its VS mode interrupt 1704 * no if hypervisor has delegated one of hs mode's interrupt 1705 */ 1706 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1707 cause == IRQ_VS_EXT) { 1708 cause = cause - 1; 1709 } 1710 write_gva = false; 1711 } else if (env->virt_enabled) { 1712 /* Trap into HS mode, from virt */ 1713 riscv_cpu_swap_hypervisor_regs(env); 1714 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1715 env->priv); 1716 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1717 1718 htval = env->guest_phys_fault_addr; 1719 1720 riscv_cpu_set_virt_enabled(env, 0); 1721 } else { 1722 /* Trap into HS mode */ 1723 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1724 htval = env->guest_phys_fault_addr; 1725 } 1726 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1727 } 1728 1729 s = env->mstatus; 1730 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1731 s = set_field(s, MSTATUS_SPP, env->priv); 1732 s = set_field(s, MSTATUS_SIE, 0); 1733 env->mstatus = s; 1734 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1735 env->sepc = env->pc; 1736 env->stval = tval; 1737 env->htval = htval; 1738 env->htinst = tinst; 1739 env->pc = (env->stvec >> 2 << 2) + 1740 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1741 riscv_cpu_set_mode(env, PRV_S); 1742 } else { 1743 /* handle the trap in M-mode */ 1744 if (riscv_has_ext(env, RVH)) { 1745 if (env->virt_enabled) { 1746 riscv_cpu_swap_hypervisor_regs(env); 1747 } 1748 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1749 env->virt_enabled); 1750 if (env->virt_enabled && tval) { 1751 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1752 } 1753 1754 mtval2 = env->guest_phys_fault_addr; 1755 1756 /* Trapping to M mode, virt is disabled */ 1757 riscv_cpu_set_virt_enabled(env, 0); 1758 } 1759 1760 s = env->mstatus; 1761 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1762 s = set_field(s, MSTATUS_MPP, env->priv); 1763 s = set_field(s, MSTATUS_MIE, 0); 1764 env->mstatus = s; 1765 env->mcause = cause | ~(((target_ulong)-1) >> async); 1766 env->mepc = env->pc; 1767 env->mtval = tval; 1768 env->mtval2 = mtval2; 1769 env->mtinst = tinst; 1770 env->pc = (env->mtvec >> 2 << 2) + 1771 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1772 riscv_cpu_set_mode(env, PRV_M); 1773 } 1774 1775 /* 1776 * NOTE: it is not necessary to yield load reservations here. It is only 1777 * necessary for an SC from "another hart" to cause a load reservation 1778 * to be yielded. Refer to the memory consistency model section of the 1779 * RISC-V ISA Specification. 1780 */ 1781 1782 env->two_stage_lookup = false; 1783 env->two_stage_indirect_lookup = false; 1784 #endif 1785 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1786 } 1787