1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (cpu->cfg.ext_zve32f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 } else { 78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 79 } 80 81 #ifdef CONFIG_USER_ONLY 82 flags |= TB_FLAGS_MSTATUS_FS; 83 flags |= TB_FLAGS_MSTATUS_VS; 84 #else 85 flags |= cpu_mmu_index(env, 0); 86 if (riscv_cpu_fp_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_FS; 88 } 89 90 if (riscv_cpu_vector_enabled(env)) { 91 flags |= env->mstatus & MSTATUS_VS; 92 } 93 94 if (riscv_has_ext(env, RVH)) { 95 if (env->priv == PRV_M || 96 (env->priv == PRV_S && !env->virt_enabled) || 97 (env->priv == PRV_U && !env->virt_enabled && 98 get_field(env->hstatus, HSTATUS_HU))) { 99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 100 } 101 102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 103 get_field(env->mstatus_hs, MSTATUS_FS)); 104 105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 106 get_field(env->mstatus_hs, MSTATUS_VS)); 107 } 108 if (cpu->cfg.debug && !icount_enabled()) { 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 110 } 111 #endif 112 113 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 114 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 115 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 116 } 117 if (env->cur_pmbase != 0) { 118 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 119 } 120 121 *pflags = flags; 122 } 123 124 void riscv_cpu_update_mask(CPURISCVState *env) 125 { 126 target_ulong mask = -1, base = 0; 127 /* 128 * TODO: Current RVJ spec does not specify 129 * how the extension interacts with XLEN. 130 */ 131 #ifndef CONFIG_USER_ONLY 132 if (riscv_has_ext(env, RVJ)) { 133 switch (env->priv) { 134 case PRV_M: 135 if (env->mmte & M_PM_ENABLE) { 136 mask = env->mpmmask; 137 base = env->mpmbase; 138 } 139 break; 140 case PRV_S: 141 if (env->mmte & S_PM_ENABLE) { 142 mask = env->spmmask; 143 base = env->spmbase; 144 } 145 break; 146 case PRV_U: 147 if (env->mmte & U_PM_ENABLE) { 148 mask = env->upmmask; 149 base = env->upmbase; 150 } 151 break; 152 default: 153 g_assert_not_reached(); 154 } 155 } 156 #endif 157 if (env->xl == MXL_RV32) { 158 env->cur_pmmask = mask & UINT32_MAX; 159 env->cur_pmbase = base & UINT32_MAX; 160 } else { 161 env->cur_pmmask = mask; 162 env->cur_pmbase = base; 163 } 164 } 165 166 #ifndef CONFIG_USER_ONLY 167 168 /* 169 * The HS-mode is allowed to configure priority only for the 170 * following VS-mode local interrupts: 171 * 172 * 0 (Reserved interrupt, reads as zero) 173 * 1 Supervisor software interrupt 174 * 4 (Reserved interrupt, reads as zero) 175 * 5 Supervisor timer interrupt 176 * 8 (Reserved interrupt, reads as zero) 177 * 13 (Reserved interrupt) 178 * 14 " 179 * 15 " 180 * 16 " 181 * 17 " 182 * 18 " 183 * 19 " 184 * 20 " 185 * 21 " 186 * 22 " 187 * 23 " 188 */ 189 190 static const int hviprio_index2irq[] = { 191 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 192 static const int hviprio_index2rdzero[] = { 193 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 194 195 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 196 { 197 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 198 return -EINVAL; 199 } 200 201 if (out_irq) { 202 *out_irq = hviprio_index2irq[index]; 203 } 204 205 if (out_rdzero) { 206 *out_rdzero = hviprio_index2rdzero[index]; 207 } 208 209 return 0; 210 } 211 212 /* 213 * Default priorities of local interrupts are defined in the 214 * RISC-V Advanced Interrupt Architecture specification. 215 * 216 * ---------------------------------------------------------------- 217 * Default | 218 * Priority | Major Interrupt Numbers 219 * ---------------------------------------------------------------- 220 * Highest | 47, 23, 46, 45, 22, 44, 221 * | 43, 21, 42, 41, 20, 40 222 * | 223 * | 11 (0b), 3 (03), 7 (07) 224 * | 9 (09), 1 (01), 5 (05) 225 * | 12 (0c) 226 * | 10 (0a), 2 (02), 6 (06) 227 * | 228 * | 39, 19, 38, 37, 18, 36, 229 * Lowest | 35, 17, 34, 33, 16, 32 230 * ---------------------------------------------------------------- 231 */ 232 static const uint8_t default_iprio[64] = { 233 /* Custom interrupts 48 to 63 */ 234 [63] = IPRIO_MMAXIPRIO, 235 [62] = IPRIO_MMAXIPRIO, 236 [61] = IPRIO_MMAXIPRIO, 237 [60] = IPRIO_MMAXIPRIO, 238 [59] = IPRIO_MMAXIPRIO, 239 [58] = IPRIO_MMAXIPRIO, 240 [57] = IPRIO_MMAXIPRIO, 241 [56] = IPRIO_MMAXIPRIO, 242 [55] = IPRIO_MMAXIPRIO, 243 [54] = IPRIO_MMAXIPRIO, 244 [53] = IPRIO_MMAXIPRIO, 245 [52] = IPRIO_MMAXIPRIO, 246 [51] = IPRIO_MMAXIPRIO, 247 [50] = IPRIO_MMAXIPRIO, 248 [49] = IPRIO_MMAXIPRIO, 249 [48] = IPRIO_MMAXIPRIO, 250 251 /* Custom interrupts 24 to 31 */ 252 [31] = IPRIO_MMAXIPRIO, 253 [30] = IPRIO_MMAXIPRIO, 254 [29] = IPRIO_MMAXIPRIO, 255 [28] = IPRIO_MMAXIPRIO, 256 [27] = IPRIO_MMAXIPRIO, 257 [26] = IPRIO_MMAXIPRIO, 258 [25] = IPRIO_MMAXIPRIO, 259 [24] = IPRIO_MMAXIPRIO, 260 261 [47] = IPRIO_DEFAULT_UPPER, 262 [23] = IPRIO_DEFAULT_UPPER + 1, 263 [46] = IPRIO_DEFAULT_UPPER + 2, 264 [45] = IPRIO_DEFAULT_UPPER + 3, 265 [22] = IPRIO_DEFAULT_UPPER + 4, 266 [44] = IPRIO_DEFAULT_UPPER + 5, 267 268 [43] = IPRIO_DEFAULT_UPPER + 6, 269 [21] = IPRIO_DEFAULT_UPPER + 7, 270 [42] = IPRIO_DEFAULT_UPPER + 8, 271 [41] = IPRIO_DEFAULT_UPPER + 9, 272 [20] = IPRIO_DEFAULT_UPPER + 10, 273 [40] = IPRIO_DEFAULT_UPPER + 11, 274 275 [11] = IPRIO_DEFAULT_M, 276 [3] = IPRIO_DEFAULT_M + 1, 277 [7] = IPRIO_DEFAULT_M + 2, 278 279 [9] = IPRIO_DEFAULT_S, 280 [1] = IPRIO_DEFAULT_S + 1, 281 [5] = IPRIO_DEFAULT_S + 2, 282 283 [12] = IPRIO_DEFAULT_SGEXT, 284 285 [10] = IPRIO_DEFAULT_VS, 286 [2] = IPRIO_DEFAULT_VS + 1, 287 [6] = IPRIO_DEFAULT_VS + 2, 288 289 [39] = IPRIO_DEFAULT_LOWER, 290 [19] = IPRIO_DEFAULT_LOWER + 1, 291 [38] = IPRIO_DEFAULT_LOWER + 2, 292 [37] = IPRIO_DEFAULT_LOWER + 3, 293 [18] = IPRIO_DEFAULT_LOWER + 4, 294 [36] = IPRIO_DEFAULT_LOWER + 5, 295 296 [35] = IPRIO_DEFAULT_LOWER + 6, 297 [17] = IPRIO_DEFAULT_LOWER + 7, 298 [34] = IPRIO_DEFAULT_LOWER + 8, 299 [33] = IPRIO_DEFAULT_LOWER + 9, 300 [16] = IPRIO_DEFAULT_LOWER + 10, 301 [32] = IPRIO_DEFAULT_LOWER + 11, 302 }; 303 304 uint8_t riscv_cpu_default_priority(int irq) 305 { 306 if (irq < 0 || irq > 63) { 307 return IPRIO_MMAXIPRIO; 308 } 309 310 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 311 }; 312 313 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 314 int extirq, unsigned int extirq_def_prio, 315 uint64_t pending, uint8_t *iprio) 316 { 317 int irq, best_irq = RISCV_EXCP_NONE; 318 unsigned int prio, best_prio = UINT_MAX; 319 320 if (!pending) { 321 return RISCV_EXCP_NONE; 322 } 323 324 irq = ctz64(pending); 325 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 326 riscv_cpu_cfg(env)->ext_ssaia)) { 327 return irq; 328 } 329 330 pending = pending >> irq; 331 while (pending) { 332 prio = iprio[irq]; 333 if (!prio) { 334 if (irq == extirq) { 335 prio = extirq_def_prio; 336 } else { 337 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 338 1 : IPRIO_MMAXIPRIO; 339 } 340 } 341 if ((pending & 0x1) && (prio <= best_prio)) { 342 best_irq = irq; 343 best_prio = prio; 344 } 345 irq++; 346 pending = pending >> 1; 347 } 348 349 return best_irq; 350 } 351 352 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 353 { 354 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 355 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 356 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 357 358 return (env->mip | vsgein | vstip) & env->mie; 359 } 360 361 int riscv_cpu_mirq_pending(CPURISCVState *env) 362 { 363 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 364 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 365 366 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 367 irqs, env->miprio); 368 } 369 370 int riscv_cpu_sirq_pending(CPURISCVState *env) 371 { 372 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 373 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 374 375 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 376 irqs, env->siprio); 377 } 378 379 int riscv_cpu_vsirq_pending(CPURISCVState *env) 380 { 381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 382 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 383 384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 385 irqs >> 1, env->hviprio); 386 } 387 388 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 389 { 390 int virq; 391 uint64_t irqs, pending, mie, hsie, vsie; 392 393 /* Determine interrupt enable state of all privilege modes */ 394 if (env->virt_enabled) { 395 mie = 1; 396 hsie = 1; 397 vsie = (env->priv < PRV_S) || 398 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 399 } else { 400 mie = (env->priv < PRV_M) || 401 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 402 hsie = (env->priv < PRV_S) || 403 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 404 vsie = 0; 405 } 406 407 /* Determine all pending interrupts */ 408 pending = riscv_cpu_all_pending(env); 409 410 /* Check M-mode interrupts */ 411 irqs = pending & ~env->mideleg & -mie; 412 if (irqs) { 413 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 414 irqs, env->miprio); 415 } 416 417 /* Check HS-mode interrupts */ 418 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 419 if (irqs) { 420 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 421 irqs, env->siprio); 422 } 423 424 /* Check VS-mode interrupts */ 425 irqs = pending & env->mideleg & env->hideleg & -vsie; 426 if (irqs) { 427 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 428 irqs >> 1, env->hviprio); 429 return (virq <= 0) ? virq : virq + 1; 430 } 431 432 /* Indicate no pending interrupt */ 433 return RISCV_EXCP_NONE; 434 } 435 436 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 437 { 438 if (interrupt_request & CPU_INTERRUPT_HARD) { 439 RISCVCPU *cpu = RISCV_CPU(cs); 440 CPURISCVState *env = &cpu->env; 441 int interruptno = riscv_cpu_local_irq_pending(env); 442 if (interruptno >= 0) { 443 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 444 riscv_cpu_do_interrupt(cs); 445 return true; 446 } 447 } 448 return false; 449 } 450 451 /* Return true is floating point support is currently enabled */ 452 bool riscv_cpu_fp_enabled(CPURISCVState *env) 453 { 454 if (env->mstatus & MSTATUS_FS) { 455 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 456 return false; 457 } 458 return true; 459 } 460 461 return false; 462 } 463 464 /* Return true is vector support is currently enabled */ 465 bool riscv_cpu_vector_enabled(CPURISCVState *env) 466 { 467 if (env->mstatus & MSTATUS_VS) { 468 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 469 return false; 470 } 471 return true; 472 } 473 474 return false; 475 } 476 477 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 478 { 479 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 480 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 481 MSTATUS64_UXL | MSTATUS_VS; 482 483 if (riscv_has_ext(env, RVF)) { 484 mstatus_mask |= MSTATUS_FS; 485 } 486 bool current_virt = env->virt_enabled; 487 488 g_assert(riscv_has_ext(env, RVH)); 489 490 if (current_virt) { 491 /* Current V=1 and we are about to change to V=0 */ 492 env->vsstatus = env->mstatus & mstatus_mask; 493 env->mstatus &= ~mstatus_mask; 494 env->mstatus |= env->mstatus_hs; 495 496 env->vstvec = env->stvec; 497 env->stvec = env->stvec_hs; 498 499 env->vsscratch = env->sscratch; 500 env->sscratch = env->sscratch_hs; 501 502 env->vsepc = env->sepc; 503 env->sepc = env->sepc_hs; 504 505 env->vscause = env->scause; 506 env->scause = env->scause_hs; 507 508 env->vstval = env->stval; 509 env->stval = env->stval_hs; 510 511 env->vsatp = env->satp; 512 env->satp = env->satp_hs; 513 } else { 514 /* Current V=0 and we are about to change to V=1 */ 515 env->mstatus_hs = env->mstatus & mstatus_mask; 516 env->mstatus &= ~mstatus_mask; 517 env->mstatus |= env->vsstatus; 518 519 env->stvec_hs = env->stvec; 520 env->stvec = env->vstvec; 521 522 env->sscratch_hs = env->sscratch; 523 env->sscratch = env->vsscratch; 524 525 env->sepc_hs = env->sepc; 526 env->sepc = env->vsepc; 527 528 env->scause_hs = env->scause; 529 env->scause = env->vscause; 530 531 env->stval_hs = env->stval; 532 env->stval = env->vstval; 533 534 env->satp_hs = env->satp; 535 env->satp = env->vsatp; 536 } 537 } 538 539 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 540 { 541 if (!riscv_has_ext(env, RVH)) { 542 return 0; 543 } 544 545 return env->geilen; 546 } 547 548 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 549 { 550 if (!riscv_has_ext(env, RVH)) { 551 return; 552 } 553 554 if (geilen > (TARGET_LONG_BITS - 1)) { 555 return; 556 } 557 558 env->geilen = geilen; 559 } 560 561 /* This function can only be called to set virt when RVH is enabled */ 562 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 563 { 564 /* Flush the TLB on all virt mode changes. */ 565 if (env->virt_enabled != enable) { 566 tlb_flush(env_cpu(env)); 567 } 568 569 env->virt_enabled = enable; 570 571 if (enable) { 572 /* 573 * The guest external interrupts from an interrupt controller are 574 * delivered only when the Guest/VM is running (i.e. V=1). This means 575 * any guest external interrupt which is triggered while the Guest/VM 576 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 577 * with sluggish response to serial console input and other I/O events. 578 * 579 * To solve this, we check and inject interrupt after setting V=1. 580 */ 581 riscv_cpu_update_mip(env, 0, 0); 582 } 583 } 584 585 bool riscv_cpu_two_stage_lookup(int mmu_idx) 586 { 587 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 588 } 589 590 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 591 { 592 CPURISCVState *env = &cpu->env; 593 if (env->miclaim & interrupts) { 594 return -1; 595 } else { 596 env->miclaim |= interrupts; 597 return 0; 598 } 599 } 600 601 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 602 uint64_t value) 603 { 604 CPUState *cs = env_cpu(env); 605 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 606 607 if (env->virt_enabled) { 608 gein = get_field(env->hstatus, HSTATUS_VGEIN); 609 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 610 } 611 612 vstip = env->vstime_irq ? MIP_VSTIP : 0; 613 614 QEMU_IOTHREAD_LOCK_GUARD(); 615 616 env->mip = (env->mip & ~mask) | (value & mask); 617 618 if (env->mip | vsgein | vstip) { 619 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 620 } else { 621 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 622 } 623 624 return old; 625 } 626 627 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 628 void *arg) 629 { 630 env->rdtime_fn = fn; 631 env->rdtime_fn_arg = arg; 632 } 633 634 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 635 int (*rmw_fn)(void *arg, 636 target_ulong reg, 637 target_ulong *val, 638 target_ulong new_val, 639 target_ulong write_mask), 640 void *rmw_fn_arg) 641 { 642 if (priv <= PRV_M) { 643 env->aia_ireg_rmw_fn[priv] = rmw_fn; 644 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 645 } 646 } 647 648 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 649 { 650 if (newpriv > PRV_M) { 651 g_assert_not_reached(); 652 } 653 if (newpriv == PRV_H) { 654 newpriv = PRV_U; 655 } 656 if (icount_enabled() && newpriv != env->priv) { 657 riscv_itrigger_update_priv(env); 658 } 659 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 660 env->priv = newpriv; 661 env->xl = cpu_recompute_xl(env); 662 riscv_cpu_update_mask(env); 663 664 /* 665 * Clear the load reservation - otherwise a reservation placed in one 666 * context/process can be used by another, resulting in an SC succeeding 667 * incorrectly. Version 2.2 of the ISA specification explicitly requires 668 * this behaviour, while later revisions say that the kernel "should" use 669 * an SC instruction to force the yielding of a load reservation on a 670 * preemptive context switch. As a result, do both. 671 */ 672 env->load_res = -1; 673 } 674 675 /* 676 * get_physical_address_pmp - check PMP permission for this physical address 677 * 678 * Match the PMP region and check permission for this physical address and it's 679 * TLB page. Returns 0 if the permission checking was successful 680 * 681 * @env: CPURISCVState 682 * @prot: The returned protection attributes 683 * @tlb_size: TLB page size containing addr. It could be modified after PMP 684 * permission checking. NULL if not set TLB page for addr. 685 * @addr: The physical address to be checked permission 686 * @access_type: The type of MMU access 687 * @mode: Indicates current privilege level. 688 */ 689 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 690 target_ulong *tlb_size, hwaddr addr, 691 int size, MMUAccessType access_type, 692 int mode) 693 { 694 pmp_priv_t pmp_priv; 695 int pmp_index = -1; 696 697 if (!riscv_cpu_cfg(env)->pmp) { 698 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 699 return TRANSLATE_SUCCESS; 700 } 701 702 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 703 &pmp_priv, mode); 704 if (pmp_index < 0) { 705 *prot = 0; 706 return TRANSLATE_PMP_FAIL; 707 } 708 709 *prot = pmp_priv_to_page_prot(pmp_priv); 710 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 711 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 712 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 713 714 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 715 } 716 717 return TRANSLATE_SUCCESS; 718 } 719 720 /* get_physical_address - get the physical address for this virtual address 721 * 722 * Do a page table walk to obtain the physical address corresponding to a 723 * virtual address. Returns 0 if the translation was successful 724 * 725 * Adapted from Spike's mmu_t::translate and mmu_t::walk 726 * 727 * @env: CPURISCVState 728 * @physical: This will be set to the calculated physical address 729 * @prot: The returned protection attributes 730 * @addr: The virtual address or guest physical address to be translated 731 * @fault_pte_addr: If not NULL, this will be set to fault pte address 732 * when a error occurs on pte address translation. 733 * This will already be shifted to match htval. 734 * @access_type: The type of MMU access 735 * @mmu_idx: Indicates current privilege level 736 * @first_stage: Are we in first stage translation? 737 * Second stage is used for hypervisor guest translation 738 * @two_stage: Are we going to perform two stage translation 739 * @is_debug: Is this access from a debugger or the monitor? 740 */ 741 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 742 int *prot, vaddr addr, 743 target_ulong *fault_pte_addr, 744 int access_type, int mmu_idx, 745 bool first_stage, bool two_stage, 746 bool is_debug) 747 { 748 /* NOTE: the env->pc value visible here will not be 749 * correct, but the value visible to the exception handler 750 * (riscv_cpu_do_interrupt) is correct */ 751 MemTxResult res; 752 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 753 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 754 bool use_background = false; 755 hwaddr ppn; 756 int napot_bits = 0; 757 target_ulong napot_mask; 758 759 /* 760 * Check if we should use the background registers for the two 761 * stage translation. We don't need to check if we actually need 762 * two stage translation as that happened before this function 763 * was called. Background registers will be used if the guest has 764 * forced a two stage translation to be on (in HS or M mode). 765 */ 766 if (!env->virt_enabled && two_stage) { 767 use_background = true; 768 } 769 770 /* MPRV does not affect the virtual-machine load/store 771 instructions, HLV, HLVX, and HSV. */ 772 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 773 mode = get_field(env->hstatus, HSTATUS_SPVP); 774 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 775 if (get_field(env->mstatus, MSTATUS_MPRV)) { 776 mode = get_field(env->mstatus, MSTATUS_MPP); 777 } 778 } 779 780 if (first_stage == false) { 781 /* We are in stage 2 translation, this is similar to stage 1. */ 782 /* Stage 2 is always taken as U-mode */ 783 mode = PRV_U; 784 } 785 786 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 787 *physical = addr; 788 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 789 return TRANSLATE_SUCCESS; 790 } 791 792 *prot = 0; 793 794 hwaddr base; 795 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 796 797 if (first_stage == true) { 798 mxr = get_field(env->mstatus, MSTATUS_MXR); 799 } else { 800 mxr = get_field(env->vsstatus, MSTATUS_MXR); 801 } 802 803 if (first_stage == true) { 804 if (use_background) { 805 if (riscv_cpu_mxl(env) == MXL_RV32) { 806 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 807 vm = get_field(env->vsatp, SATP32_MODE); 808 } else { 809 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 810 vm = get_field(env->vsatp, SATP64_MODE); 811 } 812 } else { 813 if (riscv_cpu_mxl(env) == MXL_RV32) { 814 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 815 vm = get_field(env->satp, SATP32_MODE); 816 } else { 817 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 818 vm = get_field(env->satp, SATP64_MODE); 819 } 820 } 821 widened = 0; 822 } else { 823 if (riscv_cpu_mxl(env) == MXL_RV32) { 824 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 825 vm = get_field(env->hgatp, SATP32_MODE); 826 } else { 827 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 828 vm = get_field(env->hgatp, SATP64_MODE); 829 } 830 widened = 2; 831 } 832 /* status.SUM will be ignored if execute on background */ 833 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 834 switch (vm) { 835 case VM_1_10_SV32: 836 levels = 2; ptidxbits = 10; ptesize = 4; break; 837 case VM_1_10_SV39: 838 levels = 3; ptidxbits = 9; ptesize = 8; break; 839 case VM_1_10_SV48: 840 levels = 4; ptidxbits = 9; ptesize = 8; break; 841 case VM_1_10_SV57: 842 levels = 5; ptidxbits = 9; ptesize = 8; break; 843 case VM_1_10_MBARE: 844 *physical = addr; 845 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 846 return TRANSLATE_SUCCESS; 847 default: 848 g_assert_not_reached(); 849 } 850 851 CPUState *cs = env_cpu(env); 852 int va_bits = PGSHIFT + levels * ptidxbits + widened; 853 target_ulong mask, masked_msbs; 854 855 if (TARGET_LONG_BITS > (va_bits - 1)) { 856 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 857 } else { 858 mask = 0; 859 } 860 masked_msbs = (addr >> (va_bits - 1)) & mask; 861 862 if (masked_msbs != 0 && masked_msbs != mask) { 863 return TRANSLATE_FAIL; 864 } 865 866 int ptshift = (levels - 1) * ptidxbits; 867 int i; 868 869 #if !TCG_OVERSIZED_GUEST 870 restart: 871 #endif 872 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 873 target_ulong idx; 874 if (i == 0) { 875 idx = (addr >> (PGSHIFT + ptshift)) & 876 ((1 << (ptidxbits + widened)) - 1); 877 } else { 878 idx = (addr >> (PGSHIFT + ptshift)) & 879 ((1 << ptidxbits) - 1); 880 } 881 882 /* check that physical address of PTE is legal */ 883 hwaddr pte_addr; 884 885 if (two_stage && first_stage) { 886 int vbase_prot; 887 hwaddr vbase; 888 889 /* Do the second stage translation on the base PTE address. */ 890 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 891 base, NULL, MMU_DATA_LOAD, 892 mmu_idx, false, true, 893 is_debug); 894 895 if (vbase_ret != TRANSLATE_SUCCESS) { 896 if (fault_pte_addr) { 897 *fault_pte_addr = (base + idx * ptesize) >> 2; 898 } 899 return TRANSLATE_G_STAGE_FAIL; 900 } 901 902 pte_addr = vbase + idx * ptesize; 903 } else { 904 pte_addr = base + idx * ptesize; 905 } 906 907 int pmp_prot; 908 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 909 sizeof(target_ulong), 910 MMU_DATA_LOAD, PRV_S); 911 if (pmp_ret != TRANSLATE_SUCCESS) { 912 return TRANSLATE_PMP_FAIL; 913 } 914 915 target_ulong pte; 916 if (riscv_cpu_mxl(env) == MXL_RV32) { 917 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 918 } else { 919 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 920 } 921 922 if (res != MEMTX_OK) { 923 return TRANSLATE_FAIL; 924 } 925 926 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 927 bool hade = env->menvcfg & MENVCFG_HADE; 928 929 if (first_stage && two_stage && env->virt_enabled) { 930 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 931 hade = hade && (env->henvcfg & HENVCFG_HADE); 932 } 933 934 if (riscv_cpu_sxl(env) == MXL_RV32) { 935 ppn = pte >> PTE_PPN_SHIFT; 936 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 937 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 938 } else { 939 ppn = pte >> PTE_PPN_SHIFT; 940 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 941 return TRANSLATE_FAIL; 942 } 943 } 944 945 if (!(pte & PTE_V)) { 946 /* Invalid PTE */ 947 return TRANSLATE_FAIL; 948 } else if (!pbmte && (pte & PTE_PBMT)) { 949 return TRANSLATE_FAIL; 950 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 951 /* Inner PTE, continue walking */ 952 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 953 return TRANSLATE_FAIL; 954 } 955 base = ppn << PGSHIFT; 956 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 957 /* Reserved leaf PTE flags: PTE_W */ 958 return TRANSLATE_FAIL; 959 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 960 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 961 return TRANSLATE_FAIL; 962 } else if ((pte & PTE_U) && ((mode != PRV_U) && 963 (!sum || access_type == MMU_INST_FETCH))) { 964 /* User PTE flags when not U mode and mstatus.SUM is not set, 965 or the access type is an instruction fetch */ 966 return TRANSLATE_FAIL; 967 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 968 /* Supervisor PTE flags when not S mode */ 969 return TRANSLATE_FAIL; 970 } else if (ppn & ((1ULL << ptshift) - 1)) { 971 /* Misaligned PPN */ 972 return TRANSLATE_FAIL; 973 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 974 ((pte & PTE_X) && mxr))) { 975 /* Read access check failed */ 976 return TRANSLATE_FAIL; 977 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 978 /* Write access check failed */ 979 return TRANSLATE_FAIL; 980 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 981 /* Fetch access check failed */ 982 return TRANSLATE_FAIL; 983 } else { 984 /* if necessary, set accessed and dirty bits. */ 985 target_ulong updated_pte = pte | PTE_A | 986 (access_type == MMU_DATA_STORE ? PTE_D : 0); 987 988 /* Page table updates need to be atomic with MTTCG enabled */ 989 if (updated_pte != pte) { 990 if (!hade) { 991 return TRANSLATE_FAIL; 992 } 993 994 /* 995 * - if accessed or dirty bits need updating, and the PTE is 996 * in RAM, then we do so atomically with a compare and swap. 997 * - if the PTE is in IO space or ROM, then it can't be updated 998 * and we return TRANSLATE_FAIL. 999 * - if the PTE changed by the time we went to update it, then 1000 * it is no longer valid and we must re-walk the page table. 1001 */ 1002 MemoryRegion *mr; 1003 hwaddr l = sizeof(target_ulong), addr1; 1004 mr = address_space_translate(cs->as, pte_addr, 1005 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 1006 if (memory_region_is_ram(mr)) { 1007 target_ulong *pte_pa = 1008 qemu_map_ram_ptr(mr->ram_block, addr1); 1009 #if TCG_OVERSIZED_GUEST 1010 /* MTTCG is not enabled on oversized TCG guests so 1011 * page table updates do not need to be atomic */ 1012 *pte_pa = pte = updated_pte; 1013 #else 1014 target_ulong old_pte = 1015 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1016 if (old_pte != pte) { 1017 goto restart; 1018 } else { 1019 pte = updated_pte; 1020 } 1021 #endif 1022 } else { 1023 /* misconfigured PTE in ROM (AD bits are not preset) or 1024 * PTE is in IO space and can't be updated atomically */ 1025 return TRANSLATE_FAIL; 1026 } 1027 } 1028 1029 /* for superpage mappings, make a fake leaf PTE for the TLB's 1030 benefit. */ 1031 target_ulong vpn = addr >> PGSHIFT; 1032 1033 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1034 napot_bits = ctzl(ppn) + 1; 1035 if ((i != (levels - 1)) || (napot_bits != 4)) { 1036 return TRANSLATE_FAIL; 1037 } 1038 } 1039 1040 napot_mask = (1 << napot_bits) - 1; 1041 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1042 (vpn & (((target_ulong)1 << ptshift) - 1)) 1043 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1044 1045 /* set permissions on the TLB entry */ 1046 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1047 *prot |= PAGE_READ; 1048 } 1049 if (pte & PTE_X) { 1050 *prot |= PAGE_EXEC; 1051 } 1052 /* add write permission on stores or if the page is already dirty, 1053 so that we TLB miss on later writes to update the dirty bit */ 1054 if ((pte & PTE_W) && 1055 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1056 *prot |= PAGE_WRITE; 1057 } 1058 return TRANSLATE_SUCCESS; 1059 } 1060 } 1061 return TRANSLATE_FAIL; 1062 } 1063 1064 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1065 MMUAccessType access_type, bool pmp_violation, 1066 bool first_stage, bool two_stage, 1067 bool two_stage_indirect) 1068 { 1069 CPUState *cs = env_cpu(env); 1070 int page_fault_exceptions, vm; 1071 uint64_t stap_mode; 1072 1073 if (riscv_cpu_mxl(env) == MXL_RV32) { 1074 stap_mode = SATP32_MODE; 1075 } else { 1076 stap_mode = SATP64_MODE; 1077 } 1078 1079 if (first_stage) { 1080 vm = get_field(env->satp, stap_mode); 1081 } else { 1082 vm = get_field(env->hgatp, stap_mode); 1083 } 1084 1085 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1086 1087 switch (access_type) { 1088 case MMU_INST_FETCH: 1089 if (env->virt_enabled && !first_stage) { 1090 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1091 } else { 1092 cs->exception_index = page_fault_exceptions ? 1093 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1094 } 1095 break; 1096 case MMU_DATA_LOAD: 1097 if (two_stage && !first_stage) { 1098 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1099 } else { 1100 cs->exception_index = page_fault_exceptions ? 1101 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1102 } 1103 break; 1104 case MMU_DATA_STORE: 1105 if (two_stage && !first_stage) { 1106 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1107 } else { 1108 cs->exception_index = page_fault_exceptions ? 1109 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1110 } 1111 break; 1112 default: 1113 g_assert_not_reached(); 1114 } 1115 env->badaddr = address; 1116 env->two_stage_lookup = two_stage; 1117 env->two_stage_indirect_lookup = two_stage_indirect; 1118 } 1119 1120 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1121 { 1122 RISCVCPU *cpu = RISCV_CPU(cs); 1123 CPURISCVState *env = &cpu->env; 1124 hwaddr phys_addr; 1125 int prot; 1126 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1127 1128 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1129 true, env->virt_enabled, true)) { 1130 return -1; 1131 } 1132 1133 if (env->virt_enabled) { 1134 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1135 0, mmu_idx, false, true, true)) { 1136 return -1; 1137 } 1138 } 1139 1140 return phys_addr & TARGET_PAGE_MASK; 1141 } 1142 1143 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1144 vaddr addr, unsigned size, 1145 MMUAccessType access_type, 1146 int mmu_idx, MemTxAttrs attrs, 1147 MemTxResult response, uintptr_t retaddr) 1148 { 1149 RISCVCPU *cpu = RISCV_CPU(cs); 1150 CPURISCVState *env = &cpu->env; 1151 1152 if (access_type == MMU_DATA_STORE) { 1153 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1154 } else if (access_type == MMU_DATA_LOAD) { 1155 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1156 } else { 1157 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1158 } 1159 1160 env->badaddr = addr; 1161 env->two_stage_lookup = env->virt_enabled || 1162 riscv_cpu_two_stage_lookup(mmu_idx); 1163 env->two_stage_indirect_lookup = false; 1164 cpu_loop_exit_restore(cs, retaddr); 1165 } 1166 1167 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1168 MMUAccessType access_type, int mmu_idx, 1169 uintptr_t retaddr) 1170 { 1171 RISCVCPU *cpu = RISCV_CPU(cs); 1172 CPURISCVState *env = &cpu->env; 1173 switch (access_type) { 1174 case MMU_INST_FETCH: 1175 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1176 break; 1177 case MMU_DATA_LOAD: 1178 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1179 break; 1180 case MMU_DATA_STORE: 1181 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1182 break; 1183 default: 1184 g_assert_not_reached(); 1185 } 1186 env->badaddr = addr; 1187 env->two_stage_lookup = env->virt_enabled || 1188 riscv_cpu_two_stage_lookup(mmu_idx); 1189 env->two_stage_indirect_lookup = false; 1190 cpu_loop_exit_restore(cs, retaddr); 1191 } 1192 1193 1194 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1195 { 1196 enum riscv_pmu_event_idx pmu_event_type; 1197 1198 switch (access_type) { 1199 case MMU_INST_FETCH: 1200 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1201 break; 1202 case MMU_DATA_LOAD: 1203 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1204 break; 1205 case MMU_DATA_STORE: 1206 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1207 break; 1208 default: 1209 return; 1210 } 1211 1212 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1213 } 1214 1215 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1216 MMUAccessType access_type, int mmu_idx, 1217 bool probe, uintptr_t retaddr) 1218 { 1219 RISCVCPU *cpu = RISCV_CPU(cs); 1220 CPURISCVState *env = &cpu->env; 1221 vaddr im_address; 1222 hwaddr pa = 0; 1223 int prot, prot2, prot_pmp; 1224 bool pmp_violation = false; 1225 bool first_stage_error = true; 1226 bool two_stage_lookup = false; 1227 bool two_stage_indirect_error = false; 1228 int ret = TRANSLATE_FAIL; 1229 int mode = mmu_idx; 1230 /* default TLB page size */ 1231 target_ulong tlb_size = TARGET_PAGE_SIZE; 1232 1233 env->guest_phys_fault_addr = 0; 1234 1235 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1236 __func__, address, access_type, mmu_idx); 1237 1238 /* MPRV does not affect the virtual-machine load/store 1239 instructions, HLV, HLVX, and HSV. */ 1240 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1241 mode = get_field(env->hstatus, HSTATUS_SPVP); 1242 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1243 get_field(env->mstatus, MSTATUS_MPRV)) { 1244 mode = get_field(env->mstatus, MSTATUS_MPP); 1245 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1246 two_stage_lookup = true; 1247 } 1248 } 1249 1250 pmu_tlb_fill_incr_ctr(cpu, access_type); 1251 if (env->virt_enabled || 1252 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1253 access_type != MMU_INST_FETCH)) { 1254 /* Two stage lookup */ 1255 ret = get_physical_address(env, &pa, &prot, address, 1256 &env->guest_phys_fault_addr, access_type, 1257 mmu_idx, true, true, false); 1258 1259 /* 1260 * A G-stage exception may be triggered during two state lookup. 1261 * And the env->guest_phys_fault_addr has already been set in 1262 * get_physical_address(). 1263 */ 1264 if (ret == TRANSLATE_G_STAGE_FAIL) { 1265 first_stage_error = false; 1266 two_stage_indirect_error = true; 1267 access_type = MMU_DATA_LOAD; 1268 } 1269 1270 qemu_log_mask(CPU_LOG_MMU, 1271 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1272 HWADDR_FMT_plx " prot %d\n", 1273 __func__, address, ret, pa, prot); 1274 1275 if (ret == TRANSLATE_SUCCESS) { 1276 /* Second stage lookup */ 1277 im_address = pa; 1278 1279 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1280 access_type, mmu_idx, false, true, 1281 false); 1282 1283 qemu_log_mask(CPU_LOG_MMU, 1284 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 1285 HWADDR_FMT_plx " prot %d\n", 1286 __func__, im_address, ret, pa, prot2); 1287 1288 prot &= prot2; 1289 1290 if (ret == TRANSLATE_SUCCESS) { 1291 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1292 size, access_type, mode); 1293 1294 qemu_log_mask(CPU_LOG_MMU, 1295 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1296 " %d tlb_size " TARGET_FMT_lu "\n", 1297 __func__, pa, ret, prot_pmp, tlb_size); 1298 1299 prot &= prot_pmp; 1300 } 1301 1302 if (ret != TRANSLATE_SUCCESS) { 1303 /* 1304 * Guest physical address translation failed, this is a HS 1305 * level exception 1306 */ 1307 first_stage_error = false; 1308 env->guest_phys_fault_addr = (im_address | 1309 (address & 1310 (TARGET_PAGE_SIZE - 1))) >> 2; 1311 } 1312 } 1313 } else { 1314 /* Single stage lookup */ 1315 ret = get_physical_address(env, &pa, &prot, address, NULL, 1316 access_type, mmu_idx, true, false, false); 1317 1318 qemu_log_mask(CPU_LOG_MMU, 1319 "%s address=%" VADDR_PRIx " ret %d physical " 1320 HWADDR_FMT_plx " prot %d\n", 1321 __func__, address, ret, pa, prot); 1322 1323 if (ret == TRANSLATE_SUCCESS) { 1324 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1325 size, access_type, mode); 1326 1327 qemu_log_mask(CPU_LOG_MMU, 1328 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1329 " %d tlb_size " TARGET_FMT_lu "\n", 1330 __func__, pa, ret, prot_pmp, tlb_size); 1331 1332 prot &= prot_pmp; 1333 } 1334 } 1335 1336 if (ret == TRANSLATE_PMP_FAIL) { 1337 pmp_violation = true; 1338 } 1339 1340 if (ret == TRANSLATE_SUCCESS) { 1341 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1342 prot, mmu_idx, tlb_size); 1343 return true; 1344 } else if (probe) { 1345 return false; 1346 } else { 1347 raise_mmu_exception(env, address, access_type, pmp_violation, 1348 first_stage_error, 1349 env->virt_enabled || 1350 riscv_cpu_two_stage_lookup(mmu_idx), 1351 two_stage_indirect_error); 1352 cpu_loop_exit_restore(cs, retaddr); 1353 } 1354 1355 return true; 1356 } 1357 1358 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1359 target_ulong insn, 1360 target_ulong taddr) 1361 { 1362 target_ulong xinsn = 0; 1363 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1364 1365 /* 1366 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1367 * be uncompressed. The Quadrant 1 of RVC instruction space need 1368 * not be transformed because these instructions won't generate 1369 * any load/store trap. 1370 */ 1371 1372 if ((insn & 0x3) != 0x3) { 1373 /* Transform 16bit instruction into 32bit instruction */ 1374 switch (GET_C_OP(insn)) { 1375 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1376 switch (GET_C_FUNC(insn)) { 1377 case OPC_RISC_C_FUNC_FLD_LQ: 1378 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1379 xinsn = OPC_RISC_FLD; 1380 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1381 access_rs1 = GET_C_RS1S(insn); 1382 access_imm = GET_C_LD_IMM(insn); 1383 access_size = 8; 1384 } 1385 break; 1386 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1387 xinsn = OPC_RISC_LW; 1388 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1389 access_rs1 = GET_C_RS1S(insn); 1390 access_imm = GET_C_LW_IMM(insn); 1391 access_size = 4; 1392 break; 1393 case OPC_RISC_C_FUNC_FLW_LD: 1394 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1395 xinsn = OPC_RISC_FLW; 1396 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1397 access_rs1 = GET_C_RS1S(insn); 1398 access_imm = GET_C_LW_IMM(insn); 1399 access_size = 4; 1400 } else { /* C.LD (RV64/RV128) */ 1401 xinsn = OPC_RISC_LD; 1402 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1403 access_rs1 = GET_C_RS1S(insn); 1404 access_imm = GET_C_LD_IMM(insn); 1405 access_size = 8; 1406 } 1407 break; 1408 case OPC_RISC_C_FUNC_FSD_SQ: 1409 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1410 xinsn = OPC_RISC_FSD; 1411 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1412 access_rs1 = GET_C_RS1S(insn); 1413 access_imm = GET_C_SD_IMM(insn); 1414 access_size = 8; 1415 } 1416 break; 1417 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1418 xinsn = OPC_RISC_SW; 1419 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1420 access_rs1 = GET_C_RS1S(insn); 1421 access_imm = GET_C_SW_IMM(insn); 1422 access_size = 4; 1423 break; 1424 case OPC_RISC_C_FUNC_FSW_SD: 1425 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1426 xinsn = OPC_RISC_FSW; 1427 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1428 access_rs1 = GET_C_RS1S(insn); 1429 access_imm = GET_C_SW_IMM(insn); 1430 access_size = 4; 1431 } else { /* C.SD (RV64/RV128) */ 1432 xinsn = OPC_RISC_SD; 1433 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1434 access_rs1 = GET_C_RS1S(insn); 1435 access_imm = GET_C_SD_IMM(insn); 1436 access_size = 8; 1437 } 1438 break; 1439 default: 1440 break; 1441 } 1442 break; 1443 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1444 switch (GET_C_FUNC(insn)) { 1445 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1446 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1447 xinsn = OPC_RISC_FLD; 1448 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1449 access_rs1 = 2; 1450 access_imm = GET_C_LDSP_IMM(insn); 1451 access_size = 8; 1452 } 1453 break; 1454 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1455 xinsn = OPC_RISC_LW; 1456 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1457 access_rs1 = 2; 1458 access_imm = GET_C_LWSP_IMM(insn); 1459 access_size = 4; 1460 break; 1461 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1462 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1463 xinsn = OPC_RISC_FLW; 1464 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1465 access_rs1 = 2; 1466 access_imm = GET_C_LWSP_IMM(insn); 1467 access_size = 4; 1468 } else { /* C.LDSP (RV64/RV128) */ 1469 xinsn = OPC_RISC_LD; 1470 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1471 access_rs1 = 2; 1472 access_imm = GET_C_LDSP_IMM(insn); 1473 access_size = 8; 1474 } 1475 break; 1476 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1477 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1478 xinsn = OPC_RISC_FSD; 1479 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1480 access_rs1 = 2; 1481 access_imm = GET_C_SDSP_IMM(insn); 1482 access_size = 8; 1483 } 1484 break; 1485 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1486 xinsn = OPC_RISC_SW; 1487 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1488 access_rs1 = 2; 1489 access_imm = GET_C_SWSP_IMM(insn); 1490 access_size = 4; 1491 break; 1492 case 7: 1493 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1494 xinsn = OPC_RISC_FSW; 1495 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1496 access_rs1 = 2; 1497 access_imm = GET_C_SWSP_IMM(insn); 1498 access_size = 4; 1499 } else { /* C.SDSP (RV64/RV128) */ 1500 xinsn = OPC_RISC_SD; 1501 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1502 access_rs1 = 2; 1503 access_imm = GET_C_SDSP_IMM(insn); 1504 access_size = 8; 1505 } 1506 break; 1507 default: 1508 break; 1509 } 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 /* 1516 * Clear Bit1 of transformed instruction to indicate that 1517 * original insruction was a 16bit instruction 1518 */ 1519 xinsn &= ~((target_ulong)0x2); 1520 } else { 1521 /* Transform 32bit (or wider) instructions */ 1522 switch (MASK_OP_MAJOR(insn)) { 1523 case OPC_RISC_ATOMIC: 1524 xinsn = insn; 1525 access_rs1 = GET_RS1(insn); 1526 access_size = 1 << GET_FUNCT3(insn); 1527 break; 1528 case OPC_RISC_LOAD: 1529 case OPC_RISC_FP_LOAD: 1530 xinsn = SET_I_IMM(insn, 0); 1531 access_rs1 = GET_RS1(insn); 1532 access_imm = GET_IMM(insn); 1533 access_size = 1 << GET_FUNCT3(insn); 1534 break; 1535 case OPC_RISC_STORE: 1536 case OPC_RISC_FP_STORE: 1537 xinsn = SET_S_IMM(insn, 0); 1538 access_rs1 = GET_RS1(insn); 1539 access_imm = GET_STORE_IMM(insn); 1540 access_size = 1 << GET_FUNCT3(insn); 1541 break; 1542 case OPC_RISC_SYSTEM: 1543 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1544 xinsn = insn; 1545 access_rs1 = GET_RS1(insn); 1546 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1547 access_size = 1 << access_size; 1548 } 1549 break; 1550 default: 1551 break; 1552 } 1553 } 1554 1555 if (access_size) { 1556 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1557 (access_size - 1)); 1558 } 1559 1560 return xinsn; 1561 } 1562 #endif /* !CONFIG_USER_ONLY */ 1563 1564 /* 1565 * Handle Traps 1566 * 1567 * Adapted from Spike's processor_t::take_trap. 1568 * 1569 */ 1570 void riscv_cpu_do_interrupt(CPUState *cs) 1571 { 1572 #if !defined(CONFIG_USER_ONLY) 1573 1574 RISCVCPU *cpu = RISCV_CPU(cs); 1575 CPURISCVState *env = &cpu->env; 1576 bool write_gva = false; 1577 uint64_t s; 1578 1579 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1580 * so we mask off the MSB and separate into trap type and cause. 1581 */ 1582 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1583 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1584 uint64_t deleg = async ? env->mideleg : env->medeleg; 1585 target_ulong tval = 0; 1586 target_ulong tinst = 0; 1587 target_ulong htval = 0; 1588 target_ulong mtval2 = 0; 1589 1590 if (cause == RISCV_EXCP_SEMIHOST) { 1591 do_common_semihosting(cs); 1592 env->pc += 4; 1593 return; 1594 } 1595 1596 if (!async) { 1597 /* set tval to badaddr for traps with address information */ 1598 switch (cause) { 1599 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1600 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1601 case RISCV_EXCP_LOAD_ADDR_MIS: 1602 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1603 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1604 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1605 case RISCV_EXCP_LOAD_PAGE_FAULT: 1606 case RISCV_EXCP_STORE_PAGE_FAULT: 1607 write_gva = env->two_stage_lookup; 1608 tval = env->badaddr; 1609 if (env->two_stage_indirect_lookup) { 1610 /* 1611 * special pseudoinstruction for G-stage fault taken while 1612 * doing VS-stage page table walk. 1613 */ 1614 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1615 } else { 1616 /* 1617 * The "Addr. Offset" field in transformed instruction is 1618 * non-zero only for misaligned access. 1619 */ 1620 tinst = riscv_transformed_insn(env, env->bins, tval); 1621 } 1622 break; 1623 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1624 case RISCV_EXCP_INST_ADDR_MIS: 1625 case RISCV_EXCP_INST_ACCESS_FAULT: 1626 case RISCV_EXCP_INST_PAGE_FAULT: 1627 write_gva = env->two_stage_lookup; 1628 tval = env->badaddr; 1629 if (env->two_stage_indirect_lookup) { 1630 /* 1631 * special pseudoinstruction for G-stage fault taken while 1632 * doing VS-stage page table walk. 1633 */ 1634 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1635 } 1636 break; 1637 case RISCV_EXCP_ILLEGAL_INST: 1638 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1639 tval = env->bins; 1640 break; 1641 case RISCV_EXCP_BREAKPOINT: 1642 if (cs->watchpoint_hit) { 1643 tval = cs->watchpoint_hit->hitaddr; 1644 cs->watchpoint_hit = NULL; 1645 } 1646 break; 1647 default: 1648 break; 1649 } 1650 /* ecall is dispatched as one cause so translate based on mode */ 1651 if (cause == RISCV_EXCP_U_ECALL) { 1652 assert(env->priv <= 3); 1653 1654 if (env->priv == PRV_M) { 1655 cause = RISCV_EXCP_M_ECALL; 1656 } else if (env->priv == PRV_S && env->virt_enabled) { 1657 cause = RISCV_EXCP_VS_ECALL; 1658 } else if (env->priv == PRV_S && !env->virt_enabled) { 1659 cause = RISCV_EXCP_S_ECALL; 1660 } else if (env->priv == PRV_U) { 1661 cause = RISCV_EXCP_U_ECALL; 1662 } 1663 } 1664 } 1665 1666 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1667 riscv_cpu_get_trap_name(cause, async)); 1668 1669 qemu_log_mask(CPU_LOG_INT, 1670 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1671 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1672 __func__, env->mhartid, async, cause, env->pc, tval, 1673 riscv_cpu_get_trap_name(cause, async)); 1674 1675 if (env->priv <= PRV_S && 1676 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1677 /* handle the trap in S-mode */ 1678 if (riscv_has_ext(env, RVH)) { 1679 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1680 1681 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1682 /* Trap to VS mode */ 1683 /* 1684 * See if we need to adjust cause. Yes if its VS mode interrupt 1685 * no if hypervisor has delegated one of hs mode's interrupt 1686 */ 1687 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1688 cause == IRQ_VS_EXT) { 1689 cause = cause - 1; 1690 } 1691 write_gva = false; 1692 } else if (env->virt_enabled) { 1693 /* Trap into HS mode, from virt */ 1694 riscv_cpu_swap_hypervisor_regs(env); 1695 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1696 env->priv); 1697 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1698 1699 htval = env->guest_phys_fault_addr; 1700 1701 riscv_cpu_set_virt_enabled(env, 0); 1702 } else { 1703 /* Trap into HS mode */ 1704 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1705 htval = env->guest_phys_fault_addr; 1706 } 1707 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1708 } 1709 1710 s = env->mstatus; 1711 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1712 s = set_field(s, MSTATUS_SPP, env->priv); 1713 s = set_field(s, MSTATUS_SIE, 0); 1714 env->mstatus = s; 1715 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1716 env->sepc = env->pc; 1717 env->stval = tval; 1718 env->htval = htval; 1719 env->htinst = tinst; 1720 env->pc = (env->stvec >> 2 << 2) + 1721 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1722 riscv_cpu_set_mode(env, PRV_S); 1723 } else { 1724 /* handle the trap in M-mode */ 1725 if (riscv_has_ext(env, RVH)) { 1726 if (env->virt_enabled) { 1727 riscv_cpu_swap_hypervisor_regs(env); 1728 } 1729 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1730 env->virt_enabled); 1731 if (env->virt_enabled && tval) { 1732 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1733 } 1734 1735 mtval2 = env->guest_phys_fault_addr; 1736 1737 /* Trapping to M mode, virt is disabled */ 1738 riscv_cpu_set_virt_enabled(env, 0); 1739 } 1740 1741 s = env->mstatus; 1742 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1743 s = set_field(s, MSTATUS_MPP, env->priv); 1744 s = set_field(s, MSTATUS_MIE, 0); 1745 env->mstatus = s; 1746 env->mcause = cause | ~(((target_ulong)-1) >> async); 1747 env->mepc = env->pc; 1748 env->mtval = tval; 1749 env->mtval2 = mtval2; 1750 env->mtinst = tinst; 1751 env->pc = (env->mtvec >> 2 << 2) + 1752 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1753 riscv_cpu_set_mode(env, PRV_M); 1754 } 1755 1756 /* NOTE: it is not necessary to yield load reservations here. It is only 1757 * necessary for an SC from "another hart" to cause a load reservation 1758 * to be yielded. Refer to the memory consistency model section of the 1759 * RISC-V ISA Specification. 1760 */ 1761 1762 env->two_stage_lookup = false; 1763 env->two_stage_indirect_lookup = false; 1764 #endif 1765 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1766 } 1767