1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "instmap.h" 26 #include "tcg/tcg-op.h" 27 #include "trace.h" 28 #include "semihosting/common-semi.h" 29 30 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 31 { 32 #ifdef CONFIG_USER_ONLY 33 return 0; 34 #else 35 return env->priv; 36 #endif 37 } 38 39 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 40 target_ulong *cs_base, uint32_t *pflags) 41 { 42 CPUState *cs = env_cpu(env); 43 RISCVCPU *cpu = RISCV_CPU(cs); 44 45 uint32_t flags = 0; 46 47 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 48 *cs_base = 0; 49 50 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 51 /* 52 * If env->vl equals to VLMAX, we can use generic vector operation 53 * expanders (GVEC) to accerlate the vector operations. 54 * However, as LMUL could be a fractional number. The maximum 55 * vector size can be operated might be less than 8 bytes, 56 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 57 * only when maxsz >= 8 bytes. 58 */ 59 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 60 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 61 uint32_t maxsz = vlmax << sew; 62 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 63 (maxsz >= 8); 64 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 65 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 66 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 67 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 68 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 69 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 70 FIELD_EX64(env->vtype, VTYPE, VTA)); 71 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 72 FIELD_EX64(env->vtype, VTYPE, VMA)); 73 } else { 74 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 75 } 76 77 #ifdef CONFIG_USER_ONLY 78 flags |= TB_FLAGS_MSTATUS_FS; 79 flags |= TB_FLAGS_MSTATUS_VS; 80 #else 81 flags |= cpu_mmu_index(env, 0); 82 if (riscv_cpu_fp_enabled(env)) { 83 flags |= env->mstatus & MSTATUS_FS; 84 } 85 86 if (riscv_cpu_vector_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_VS; 88 } 89 90 if (riscv_has_ext(env, RVH)) { 91 if (env->priv == PRV_M || 92 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 93 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 94 get_field(env->hstatus, HSTATUS_HU))) { 95 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 96 } 97 98 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 99 get_field(env->mstatus_hs, MSTATUS_FS)); 100 101 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 102 get_field(env->mstatus_hs, MSTATUS_VS)); 103 } 104 #endif 105 106 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 107 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 108 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 109 } 110 if (env->cur_pmbase != 0) { 111 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 112 } 113 114 *pflags = flags; 115 } 116 117 void riscv_cpu_update_mask(CPURISCVState *env) 118 { 119 target_ulong mask = -1, base = 0; 120 /* 121 * TODO: Current RVJ spec does not specify 122 * how the extension interacts with XLEN. 123 */ 124 #ifndef CONFIG_USER_ONLY 125 if (riscv_has_ext(env, RVJ)) { 126 switch (env->priv) { 127 case PRV_M: 128 if (env->mmte & M_PM_ENABLE) { 129 mask = env->mpmmask; 130 base = env->mpmbase; 131 } 132 break; 133 case PRV_S: 134 if (env->mmte & S_PM_ENABLE) { 135 mask = env->spmmask; 136 base = env->spmbase; 137 } 138 break; 139 case PRV_U: 140 if (env->mmte & U_PM_ENABLE) { 141 mask = env->upmmask; 142 base = env->upmbase; 143 } 144 break; 145 default: 146 g_assert_not_reached(); 147 } 148 } 149 #endif 150 if (env->xl == MXL_RV32) { 151 env->cur_pmmask = mask & UINT32_MAX; 152 env->cur_pmbase = base & UINT32_MAX; 153 } else { 154 env->cur_pmmask = mask; 155 env->cur_pmbase = base; 156 } 157 } 158 159 #ifndef CONFIG_USER_ONLY 160 161 /* 162 * The HS-mode is allowed to configure priority only for the 163 * following VS-mode local interrupts: 164 * 165 * 0 (Reserved interrupt, reads as zero) 166 * 1 Supervisor software interrupt 167 * 4 (Reserved interrupt, reads as zero) 168 * 5 Supervisor timer interrupt 169 * 8 (Reserved interrupt, reads as zero) 170 * 13 (Reserved interrupt) 171 * 14 " 172 * 15 " 173 * 16 " 174 * 17 " 175 * 18 " 176 * 19 " 177 * 20 " 178 * 21 " 179 * 22 " 180 * 23 " 181 */ 182 183 static const int hviprio_index2irq[] = { 184 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 185 static const int hviprio_index2rdzero[] = { 186 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 187 188 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 189 { 190 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 191 return -EINVAL; 192 } 193 194 if (out_irq) { 195 *out_irq = hviprio_index2irq[index]; 196 } 197 198 if (out_rdzero) { 199 *out_rdzero = hviprio_index2rdzero[index]; 200 } 201 202 return 0; 203 } 204 205 /* 206 * Default priorities of local interrupts are defined in the 207 * RISC-V Advanced Interrupt Architecture specification. 208 * 209 * ---------------------------------------------------------------- 210 * Default | 211 * Priority | Major Interrupt Numbers 212 * ---------------------------------------------------------------- 213 * Highest | 47, 23, 46, 45, 22, 44, 214 * | 43, 21, 42, 41, 20, 40 215 * | 216 * | 11 (0b), 3 (03), 7 (07) 217 * | 9 (09), 1 (01), 5 (05) 218 * | 12 (0c) 219 * | 10 (0a), 2 (02), 6 (06) 220 * | 221 * | 39, 19, 38, 37, 18, 36, 222 * Lowest | 35, 17, 34, 33, 16, 32 223 * ---------------------------------------------------------------- 224 */ 225 static const uint8_t default_iprio[64] = { 226 /* Custom interrupts 48 to 63 */ 227 [63] = IPRIO_MMAXIPRIO, 228 [62] = IPRIO_MMAXIPRIO, 229 [61] = IPRIO_MMAXIPRIO, 230 [60] = IPRIO_MMAXIPRIO, 231 [59] = IPRIO_MMAXIPRIO, 232 [58] = IPRIO_MMAXIPRIO, 233 [57] = IPRIO_MMAXIPRIO, 234 [56] = IPRIO_MMAXIPRIO, 235 [55] = IPRIO_MMAXIPRIO, 236 [54] = IPRIO_MMAXIPRIO, 237 [53] = IPRIO_MMAXIPRIO, 238 [52] = IPRIO_MMAXIPRIO, 239 [51] = IPRIO_MMAXIPRIO, 240 [50] = IPRIO_MMAXIPRIO, 241 [49] = IPRIO_MMAXIPRIO, 242 [48] = IPRIO_MMAXIPRIO, 243 244 /* Custom interrupts 24 to 31 */ 245 [31] = IPRIO_MMAXIPRIO, 246 [30] = IPRIO_MMAXIPRIO, 247 [29] = IPRIO_MMAXIPRIO, 248 [28] = IPRIO_MMAXIPRIO, 249 [27] = IPRIO_MMAXIPRIO, 250 [26] = IPRIO_MMAXIPRIO, 251 [25] = IPRIO_MMAXIPRIO, 252 [24] = IPRIO_MMAXIPRIO, 253 254 [47] = IPRIO_DEFAULT_UPPER, 255 [23] = IPRIO_DEFAULT_UPPER + 1, 256 [46] = IPRIO_DEFAULT_UPPER + 2, 257 [45] = IPRIO_DEFAULT_UPPER + 3, 258 [22] = IPRIO_DEFAULT_UPPER + 4, 259 [44] = IPRIO_DEFAULT_UPPER + 5, 260 261 [43] = IPRIO_DEFAULT_UPPER + 6, 262 [21] = IPRIO_DEFAULT_UPPER + 7, 263 [42] = IPRIO_DEFAULT_UPPER + 8, 264 [41] = IPRIO_DEFAULT_UPPER + 9, 265 [20] = IPRIO_DEFAULT_UPPER + 10, 266 [40] = IPRIO_DEFAULT_UPPER + 11, 267 268 [11] = IPRIO_DEFAULT_M, 269 [3] = IPRIO_DEFAULT_M + 1, 270 [7] = IPRIO_DEFAULT_M + 2, 271 272 [9] = IPRIO_DEFAULT_S, 273 [1] = IPRIO_DEFAULT_S + 1, 274 [5] = IPRIO_DEFAULT_S + 2, 275 276 [12] = IPRIO_DEFAULT_SGEXT, 277 278 [10] = IPRIO_DEFAULT_VS, 279 [2] = IPRIO_DEFAULT_VS + 1, 280 [6] = IPRIO_DEFAULT_VS + 2, 281 282 [39] = IPRIO_DEFAULT_LOWER, 283 [19] = IPRIO_DEFAULT_LOWER + 1, 284 [38] = IPRIO_DEFAULT_LOWER + 2, 285 [37] = IPRIO_DEFAULT_LOWER + 3, 286 [18] = IPRIO_DEFAULT_LOWER + 4, 287 [36] = IPRIO_DEFAULT_LOWER + 5, 288 289 [35] = IPRIO_DEFAULT_LOWER + 6, 290 [17] = IPRIO_DEFAULT_LOWER + 7, 291 [34] = IPRIO_DEFAULT_LOWER + 8, 292 [33] = IPRIO_DEFAULT_LOWER + 9, 293 [16] = IPRIO_DEFAULT_LOWER + 10, 294 [32] = IPRIO_DEFAULT_LOWER + 11, 295 }; 296 297 uint8_t riscv_cpu_default_priority(int irq) 298 { 299 if (irq < 0 || irq > 63) { 300 return IPRIO_MMAXIPRIO; 301 } 302 303 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 304 }; 305 306 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 307 int extirq, unsigned int extirq_def_prio, 308 uint64_t pending, uint8_t *iprio) 309 { 310 int irq, best_irq = RISCV_EXCP_NONE; 311 unsigned int prio, best_prio = UINT_MAX; 312 313 if (!pending) { 314 return RISCV_EXCP_NONE; 315 } 316 317 irq = ctz64(pending); 318 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 319 return irq; 320 } 321 322 pending = pending >> irq; 323 while (pending) { 324 prio = iprio[irq]; 325 if (!prio) { 326 if (irq == extirq) { 327 prio = extirq_def_prio; 328 } else { 329 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 330 1 : IPRIO_MMAXIPRIO; 331 } 332 } 333 if ((pending & 0x1) && (prio <= best_prio)) { 334 best_irq = irq; 335 best_prio = prio; 336 } 337 irq++; 338 pending = pending >> 1; 339 } 340 341 return best_irq; 342 } 343 344 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 345 { 346 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 347 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 348 349 return (env->mip | vsgein) & env->mie; 350 } 351 352 int riscv_cpu_mirq_pending(CPURISCVState *env) 353 { 354 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 355 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 356 357 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 358 irqs, env->miprio); 359 } 360 361 int riscv_cpu_sirq_pending(CPURISCVState *env) 362 { 363 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 364 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 365 366 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 367 irqs, env->siprio); 368 } 369 370 int riscv_cpu_vsirq_pending(CPURISCVState *env) 371 { 372 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 373 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 374 375 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 376 irqs >> 1, env->hviprio); 377 } 378 379 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 380 { 381 int virq; 382 uint64_t irqs, pending, mie, hsie, vsie; 383 384 /* Determine interrupt enable state of all privilege modes */ 385 if (riscv_cpu_virt_enabled(env)) { 386 mie = 1; 387 hsie = 1; 388 vsie = (env->priv < PRV_S) || 389 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 390 } else { 391 mie = (env->priv < PRV_M) || 392 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 393 hsie = (env->priv < PRV_S) || 394 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 395 vsie = 0; 396 } 397 398 /* Determine all pending interrupts */ 399 pending = riscv_cpu_all_pending(env); 400 401 /* Check M-mode interrupts */ 402 irqs = pending & ~env->mideleg & -mie; 403 if (irqs) { 404 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 405 irqs, env->miprio); 406 } 407 408 /* Check HS-mode interrupts */ 409 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 410 if (irqs) { 411 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 412 irqs, env->siprio); 413 } 414 415 /* Check VS-mode interrupts */ 416 irqs = pending & env->mideleg & env->hideleg & -vsie; 417 if (irqs) { 418 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 419 irqs >> 1, env->hviprio); 420 return (virq <= 0) ? virq : virq + 1; 421 } 422 423 /* Indicate no pending interrupt */ 424 return RISCV_EXCP_NONE; 425 } 426 427 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 428 { 429 if (interrupt_request & CPU_INTERRUPT_HARD) { 430 RISCVCPU *cpu = RISCV_CPU(cs); 431 CPURISCVState *env = &cpu->env; 432 int interruptno = riscv_cpu_local_irq_pending(env); 433 if (interruptno >= 0) { 434 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 435 riscv_cpu_do_interrupt(cs); 436 return true; 437 } 438 } 439 return false; 440 } 441 442 /* Return true is floating point support is currently enabled */ 443 bool riscv_cpu_fp_enabled(CPURISCVState *env) 444 { 445 if (env->mstatus & MSTATUS_FS) { 446 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 447 return false; 448 } 449 return true; 450 } 451 452 return false; 453 } 454 455 /* Return true is vector support is currently enabled */ 456 bool riscv_cpu_vector_enabled(CPURISCVState *env) 457 { 458 if (env->mstatus & MSTATUS_VS) { 459 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 460 return false; 461 } 462 return true; 463 } 464 465 return false; 466 } 467 468 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 469 { 470 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 471 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 472 MSTATUS64_UXL | MSTATUS_VS; 473 474 if (riscv_has_ext(env, RVF)) { 475 mstatus_mask |= MSTATUS_FS; 476 } 477 bool current_virt = riscv_cpu_virt_enabled(env); 478 479 g_assert(riscv_has_ext(env, RVH)); 480 481 if (current_virt) { 482 /* Current V=1 and we are about to change to V=0 */ 483 env->vsstatus = env->mstatus & mstatus_mask; 484 env->mstatus &= ~mstatus_mask; 485 env->mstatus |= env->mstatus_hs; 486 487 env->vstvec = env->stvec; 488 env->stvec = env->stvec_hs; 489 490 env->vsscratch = env->sscratch; 491 env->sscratch = env->sscratch_hs; 492 493 env->vsepc = env->sepc; 494 env->sepc = env->sepc_hs; 495 496 env->vscause = env->scause; 497 env->scause = env->scause_hs; 498 499 env->vstval = env->stval; 500 env->stval = env->stval_hs; 501 502 env->vsatp = env->satp; 503 env->satp = env->satp_hs; 504 } else { 505 /* Current V=0 and we are about to change to V=1 */ 506 env->mstatus_hs = env->mstatus & mstatus_mask; 507 env->mstatus &= ~mstatus_mask; 508 env->mstatus |= env->vsstatus; 509 510 env->stvec_hs = env->stvec; 511 env->stvec = env->vstvec; 512 513 env->sscratch_hs = env->sscratch; 514 env->sscratch = env->vsscratch; 515 516 env->sepc_hs = env->sepc; 517 env->sepc = env->vsepc; 518 519 env->scause_hs = env->scause; 520 env->scause = env->vscause; 521 522 env->stval_hs = env->stval; 523 env->stval = env->vstval; 524 525 env->satp_hs = env->satp; 526 env->satp = env->vsatp; 527 } 528 } 529 530 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 531 { 532 if (!riscv_has_ext(env, RVH)) { 533 return 0; 534 } 535 536 return env->geilen; 537 } 538 539 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 540 { 541 if (!riscv_has_ext(env, RVH)) { 542 return; 543 } 544 545 if (geilen > (TARGET_LONG_BITS - 1)) { 546 return; 547 } 548 549 env->geilen = geilen; 550 } 551 552 bool riscv_cpu_virt_enabled(CPURISCVState *env) 553 { 554 if (!riscv_has_ext(env, RVH)) { 555 return false; 556 } 557 558 return get_field(env->virt, VIRT_ONOFF); 559 } 560 561 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 562 { 563 if (!riscv_has_ext(env, RVH)) { 564 return; 565 } 566 567 /* Flush the TLB on all virt mode changes. */ 568 if (get_field(env->virt, VIRT_ONOFF) != enable) { 569 tlb_flush(env_cpu(env)); 570 } 571 572 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 573 574 if (enable) { 575 /* 576 * The guest external interrupts from an interrupt controller are 577 * delivered only when the Guest/VM is running (i.e. V=1). This means 578 * any guest external interrupt which is triggered while the Guest/VM 579 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 580 * with sluggish response to serial console input and other I/O events. 581 * 582 * To solve this, we check and inject interrupt after setting V=1. 583 */ 584 riscv_cpu_update_mip(env_archcpu(env), 0, 0); 585 } 586 } 587 588 bool riscv_cpu_two_stage_lookup(int mmu_idx) 589 { 590 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 591 } 592 593 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 594 { 595 CPURISCVState *env = &cpu->env; 596 if (env->miclaim & interrupts) { 597 return -1; 598 } else { 599 env->miclaim |= interrupts; 600 return 0; 601 } 602 } 603 604 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) 605 { 606 CPURISCVState *env = &cpu->env; 607 CPUState *cs = CPU(cpu); 608 uint64_t gein, vsgein = 0, old = env->mip; 609 bool locked = false; 610 611 if (riscv_cpu_virt_enabled(env)) { 612 gein = get_field(env->hstatus, HSTATUS_VGEIN); 613 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 614 } 615 616 if (!qemu_mutex_iothread_locked()) { 617 locked = true; 618 qemu_mutex_lock_iothread(); 619 } 620 621 env->mip = (env->mip & ~mask) | (value & mask); 622 623 if (env->mip | vsgein) { 624 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 625 } else { 626 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 627 } 628 629 if (locked) { 630 qemu_mutex_unlock_iothread(); 631 } 632 633 return old; 634 } 635 636 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 637 void *arg) 638 { 639 env->rdtime_fn = fn; 640 env->rdtime_fn_arg = arg; 641 } 642 643 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 644 int (*rmw_fn)(void *arg, 645 target_ulong reg, 646 target_ulong *val, 647 target_ulong new_val, 648 target_ulong write_mask), 649 void *rmw_fn_arg) 650 { 651 if (priv <= PRV_M) { 652 env->aia_ireg_rmw_fn[priv] = rmw_fn; 653 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 654 } 655 } 656 657 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 658 { 659 if (newpriv > PRV_M) { 660 g_assert_not_reached(); 661 } 662 if (newpriv == PRV_H) { 663 newpriv = PRV_U; 664 } 665 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 666 env->priv = newpriv; 667 env->xl = cpu_recompute_xl(env); 668 riscv_cpu_update_mask(env); 669 670 /* 671 * Clear the load reservation - otherwise a reservation placed in one 672 * context/process can be used by another, resulting in an SC succeeding 673 * incorrectly. Version 2.2 of the ISA specification explicitly requires 674 * this behaviour, while later revisions say that the kernel "should" use 675 * an SC instruction to force the yielding of a load reservation on a 676 * preemptive context switch. As a result, do both. 677 */ 678 env->load_res = -1; 679 } 680 681 /* 682 * get_physical_address_pmp - check PMP permission for this physical address 683 * 684 * Match the PMP region and check permission for this physical address and it's 685 * TLB page. Returns 0 if the permission checking was successful 686 * 687 * @env: CPURISCVState 688 * @prot: The returned protection attributes 689 * @tlb_size: TLB page size containing addr. It could be modified after PMP 690 * permission checking. NULL if not set TLB page for addr. 691 * @addr: The physical address to be checked permission 692 * @access_type: The type of MMU access 693 * @mode: Indicates current privilege level. 694 */ 695 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 696 target_ulong *tlb_size, hwaddr addr, 697 int size, MMUAccessType access_type, 698 int mode) 699 { 700 pmp_priv_t pmp_priv; 701 target_ulong tlb_size_pmp = 0; 702 703 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 704 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 705 return TRANSLATE_SUCCESS; 706 } 707 708 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, 709 mode)) { 710 *prot = 0; 711 return TRANSLATE_PMP_FAIL; 712 } 713 714 *prot = pmp_priv_to_page_prot(pmp_priv); 715 if (tlb_size != NULL) { 716 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { 717 *tlb_size = tlb_size_pmp; 718 } 719 } 720 721 return TRANSLATE_SUCCESS; 722 } 723 724 /* get_physical_address - get the physical address for this virtual address 725 * 726 * Do a page table walk to obtain the physical address corresponding to a 727 * virtual address. Returns 0 if the translation was successful 728 * 729 * Adapted from Spike's mmu_t::translate and mmu_t::walk 730 * 731 * @env: CPURISCVState 732 * @physical: This will be set to the calculated physical address 733 * @prot: The returned protection attributes 734 * @addr: The virtual address to be translated 735 * @fault_pte_addr: If not NULL, this will be set to fault pte address 736 * when a error occurs on pte address translation. 737 * This will already be shifted to match htval. 738 * @access_type: The type of MMU access 739 * @mmu_idx: Indicates current privilege level 740 * @first_stage: Are we in first stage translation? 741 * Second stage is used for hypervisor guest translation 742 * @two_stage: Are we going to perform two stage translation 743 * @is_debug: Is this access from a debugger or the monitor? 744 */ 745 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 746 int *prot, target_ulong addr, 747 target_ulong *fault_pte_addr, 748 int access_type, int mmu_idx, 749 bool first_stage, bool two_stage, 750 bool is_debug) 751 { 752 /* NOTE: the env->pc value visible here will not be 753 * correct, but the value visible to the exception handler 754 * (riscv_cpu_do_interrupt) is correct */ 755 MemTxResult res; 756 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 757 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 758 bool use_background = false; 759 hwaddr ppn; 760 RISCVCPU *cpu = env_archcpu(env); 761 int napot_bits = 0; 762 target_ulong napot_mask; 763 764 /* 765 * Check if we should use the background registers for the two 766 * stage translation. We don't need to check if we actually need 767 * two stage translation as that happened before this function 768 * was called. Background registers will be used if the guest has 769 * forced a two stage translation to be on (in HS or M mode). 770 */ 771 if (!riscv_cpu_virt_enabled(env) && two_stage) { 772 use_background = true; 773 } 774 775 /* MPRV does not affect the virtual-machine load/store 776 instructions, HLV, HLVX, and HSV. */ 777 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 778 mode = get_field(env->hstatus, HSTATUS_SPVP); 779 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 780 if (get_field(env->mstatus, MSTATUS_MPRV)) { 781 mode = get_field(env->mstatus, MSTATUS_MPP); 782 } 783 } 784 785 if (first_stage == false) { 786 /* We are in stage 2 translation, this is similar to stage 1. */ 787 /* Stage 2 is always taken as U-mode */ 788 mode = PRV_U; 789 } 790 791 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 792 *physical = addr; 793 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 794 return TRANSLATE_SUCCESS; 795 } 796 797 *prot = 0; 798 799 hwaddr base; 800 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 801 802 if (first_stage == true) { 803 mxr = get_field(env->mstatus, MSTATUS_MXR); 804 } else { 805 mxr = get_field(env->vsstatus, MSTATUS_MXR); 806 } 807 808 if (first_stage == true) { 809 if (use_background) { 810 if (riscv_cpu_mxl(env) == MXL_RV32) { 811 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 812 vm = get_field(env->vsatp, SATP32_MODE); 813 } else { 814 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 815 vm = get_field(env->vsatp, SATP64_MODE); 816 } 817 } else { 818 if (riscv_cpu_mxl(env) == MXL_RV32) { 819 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 820 vm = get_field(env->satp, SATP32_MODE); 821 } else { 822 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 823 vm = get_field(env->satp, SATP64_MODE); 824 } 825 } 826 widened = 0; 827 } else { 828 if (riscv_cpu_mxl(env) == MXL_RV32) { 829 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 830 vm = get_field(env->hgatp, SATP32_MODE); 831 } else { 832 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 833 vm = get_field(env->hgatp, SATP64_MODE); 834 } 835 widened = 2; 836 } 837 /* status.SUM will be ignored if execute on background */ 838 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 839 switch (vm) { 840 case VM_1_10_SV32: 841 levels = 2; ptidxbits = 10; ptesize = 4; break; 842 case VM_1_10_SV39: 843 levels = 3; ptidxbits = 9; ptesize = 8; break; 844 case VM_1_10_SV48: 845 levels = 4; ptidxbits = 9; ptesize = 8; break; 846 case VM_1_10_SV57: 847 levels = 5; ptidxbits = 9; ptesize = 8; break; 848 case VM_1_10_MBARE: 849 *physical = addr; 850 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 851 return TRANSLATE_SUCCESS; 852 default: 853 g_assert_not_reached(); 854 } 855 856 CPUState *cs = env_cpu(env); 857 int va_bits = PGSHIFT + levels * ptidxbits + widened; 858 target_ulong mask, masked_msbs; 859 860 if (TARGET_LONG_BITS > (va_bits - 1)) { 861 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 862 } else { 863 mask = 0; 864 } 865 masked_msbs = (addr >> (va_bits - 1)) & mask; 866 867 if (masked_msbs != 0 && masked_msbs != mask) { 868 return TRANSLATE_FAIL; 869 } 870 871 int ptshift = (levels - 1) * ptidxbits; 872 int i; 873 874 #if !TCG_OVERSIZED_GUEST 875 restart: 876 #endif 877 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 878 target_ulong idx; 879 if (i == 0) { 880 idx = (addr >> (PGSHIFT + ptshift)) & 881 ((1 << (ptidxbits + widened)) - 1); 882 } else { 883 idx = (addr >> (PGSHIFT + ptshift)) & 884 ((1 << ptidxbits) - 1); 885 } 886 887 /* check that physical address of PTE is legal */ 888 hwaddr pte_addr; 889 890 if (two_stage && first_stage) { 891 int vbase_prot; 892 hwaddr vbase; 893 894 /* Do the second stage translation on the base PTE address. */ 895 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 896 base, NULL, MMU_DATA_LOAD, 897 mmu_idx, false, true, 898 is_debug); 899 900 if (vbase_ret != TRANSLATE_SUCCESS) { 901 if (fault_pte_addr) { 902 *fault_pte_addr = (base + idx * ptesize) >> 2; 903 } 904 return TRANSLATE_G_STAGE_FAIL; 905 } 906 907 pte_addr = vbase + idx * ptesize; 908 } else { 909 pte_addr = base + idx * ptesize; 910 } 911 912 int pmp_prot; 913 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 914 sizeof(target_ulong), 915 MMU_DATA_LOAD, PRV_S); 916 if (pmp_ret != TRANSLATE_SUCCESS) { 917 return TRANSLATE_PMP_FAIL; 918 } 919 920 target_ulong pte; 921 if (riscv_cpu_mxl(env) == MXL_RV32) { 922 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 923 } else { 924 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 925 } 926 927 if (res != MEMTX_OK) { 928 return TRANSLATE_FAIL; 929 } 930 931 if (riscv_cpu_sxl(env) == MXL_RV32) { 932 ppn = pte >> PTE_PPN_SHIFT; 933 } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { 934 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 935 } else { 936 ppn = pte >> PTE_PPN_SHIFT; 937 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 938 return TRANSLATE_FAIL; 939 } 940 } 941 942 if (!(pte & PTE_V)) { 943 /* Invalid PTE */ 944 return TRANSLATE_FAIL; 945 } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { 946 return TRANSLATE_FAIL; 947 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 948 /* Inner PTE, continue walking */ 949 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 950 return TRANSLATE_FAIL; 951 } 952 base = ppn << PGSHIFT; 953 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 954 /* Reserved leaf PTE flags: PTE_W */ 955 return TRANSLATE_FAIL; 956 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 957 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 958 return TRANSLATE_FAIL; 959 } else if ((pte & PTE_U) && ((mode != PRV_U) && 960 (!sum || access_type == MMU_INST_FETCH))) { 961 /* User PTE flags when not U mode and mstatus.SUM is not set, 962 or the access type is an instruction fetch */ 963 return TRANSLATE_FAIL; 964 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 965 /* Supervisor PTE flags when not S mode */ 966 return TRANSLATE_FAIL; 967 } else if (ppn & ((1ULL << ptshift) - 1)) { 968 /* Misaligned PPN */ 969 return TRANSLATE_FAIL; 970 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 971 ((pte & PTE_X) && mxr))) { 972 /* Read access check failed */ 973 return TRANSLATE_FAIL; 974 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 975 /* Write access check failed */ 976 return TRANSLATE_FAIL; 977 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 978 /* Fetch access check failed */ 979 return TRANSLATE_FAIL; 980 } else { 981 /* if necessary, set accessed and dirty bits. */ 982 target_ulong updated_pte = pte | PTE_A | 983 (access_type == MMU_DATA_STORE ? PTE_D : 0); 984 985 /* Page table updates need to be atomic with MTTCG enabled */ 986 if (updated_pte != pte) { 987 /* 988 * - if accessed or dirty bits need updating, and the PTE is 989 * in RAM, then we do so atomically with a compare and swap. 990 * - if the PTE is in IO space or ROM, then it can't be updated 991 * and we return TRANSLATE_FAIL. 992 * - if the PTE changed by the time we went to update it, then 993 * it is no longer valid and we must re-walk the page table. 994 */ 995 MemoryRegion *mr; 996 hwaddr l = sizeof(target_ulong), addr1; 997 mr = address_space_translate(cs->as, pte_addr, 998 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 999 if (memory_region_is_ram(mr)) { 1000 target_ulong *pte_pa = 1001 qemu_map_ram_ptr(mr->ram_block, addr1); 1002 #if TCG_OVERSIZED_GUEST 1003 /* MTTCG is not enabled on oversized TCG guests so 1004 * page table updates do not need to be atomic */ 1005 *pte_pa = pte = updated_pte; 1006 #else 1007 target_ulong old_pte = 1008 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1009 if (old_pte != pte) { 1010 goto restart; 1011 } else { 1012 pte = updated_pte; 1013 } 1014 #endif 1015 } else { 1016 /* misconfigured PTE in ROM (AD bits are not preset) or 1017 * PTE is in IO space and can't be updated atomically */ 1018 return TRANSLATE_FAIL; 1019 } 1020 } 1021 1022 /* for superpage mappings, make a fake leaf PTE for the TLB's 1023 benefit. */ 1024 target_ulong vpn = addr >> PGSHIFT; 1025 1026 if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { 1027 napot_bits = ctzl(ppn) + 1; 1028 if ((i != (levels - 1)) || (napot_bits != 4)) { 1029 return TRANSLATE_FAIL; 1030 } 1031 } 1032 1033 napot_mask = (1 << napot_bits) - 1; 1034 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1035 (vpn & (((target_ulong)1 << ptshift) - 1)) 1036 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1037 1038 /* set permissions on the TLB entry */ 1039 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1040 *prot |= PAGE_READ; 1041 } 1042 if ((pte & PTE_X)) { 1043 *prot |= PAGE_EXEC; 1044 } 1045 /* add write permission on stores or if the page is already dirty, 1046 so that we TLB miss on later writes to update the dirty bit */ 1047 if ((pte & PTE_W) && 1048 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1049 *prot |= PAGE_WRITE; 1050 } 1051 return TRANSLATE_SUCCESS; 1052 } 1053 } 1054 return TRANSLATE_FAIL; 1055 } 1056 1057 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1058 MMUAccessType access_type, bool pmp_violation, 1059 bool first_stage, bool two_stage, 1060 bool two_stage_indirect) 1061 { 1062 CPUState *cs = env_cpu(env); 1063 int page_fault_exceptions, vm; 1064 uint64_t stap_mode; 1065 1066 if (riscv_cpu_mxl(env) == MXL_RV32) { 1067 stap_mode = SATP32_MODE; 1068 } else { 1069 stap_mode = SATP64_MODE; 1070 } 1071 1072 if (first_stage) { 1073 vm = get_field(env->satp, stap_mode); 1074 } else { 1075 vm = get_field(env->hgatp, stap_mode); 1076 } 1077 1078 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1079 1080 switch (access_type) { 1081 case MMU_INST_FETCH: 1082 if (riscv_cpu_virt_enabled(env) && !first_stage) { 1083 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1084 } else { 1085 cs->exception_index = page_fault_exceptions ? 1086 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1087 } 1088 break; 1089 case MMU_DATA_LOAD: 1090 if (two_stage && !first_stage) { 1091 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1092 } else { 1093 cs->exception_index = page_fault_exceptions ? 1094 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1095 } 1096 break; 1097 case MMU_DATA_STORE: 1098 if (two_stage && !first_stage) { 1099 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1100 } else { 1101 cs->exception_index = page_fault_exceptions ? 1102 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1103 } 1104 break; 1105 default: 1106 g_assert_not_reached(); 1107 } 1108 env->badaddr = address; 1109 env->two_stage_lookup = two_stage; 1110 env->two_stage_indirect_lookup = two_stage_indirect; 1111 } 1112 1113 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1114 { 1115 RISCVCPU *cpu = RISCV_CPU(cs); 1116 CPURISCVState *env = &cpu->env; 1117 hwaddr phys_addr; 1118 int prot; 1119 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1120 1121 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1122 true, riscv_cpu_virt_enabled(env), true)) { 1123 return -1; 1124 } 1125 1126 if (riscv_cpu_virt_enabled(env)) { 1127 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1128 0, mmu_idx, false, true, true)) { 1129 return -1; 1130 } 1131 } 1132 1133 return phys_addr & TARGET_PAGE_MASK; 1134 } 1135 1136 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1137 vaddr addr, unsigned size, 1138 MMUAccessType access_type, 1139 int mmu_idx, MemTxAttrs attrs, 1140 MemTxResult response, uintptr_t retaddr) 1141 { 1142 RISCVCPU *cpu = RISCV_CPU(cs); 1143 CPURISCVState *env = &cpu->env; 1144 1145 if (access_type == MMU_DATA_STORE) { 1146 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1147 } else if (access_type == MMU_DATA_LOAD) { 1148 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1149 } else { 1150 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1151 } 1152 1153 env->badaddr = addr; 1154 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1155 riscv_cpu_two_stage_lookup(mmu_idx); 1156 env->two_stage_indirect_lookup = false; 1157 cpu_loop_exit_restore(cs, retaddr); 1158 } 1159 1160 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1161 MMUAccessType access_type, int mmu_idx, 1162 uintptr_t retaddr) 1163 { 1164 RISCVCPU *cpu = RISCV_CPU(cs); 1165 CPURISCVState *env = &cpu->env; 1166 switch (access_type) { 1167 case MMU_INST_FETCH: 1168 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1169 break; 1170 case MMU_DATA_LOAD: 1171 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1172 break; 1173 case MMU_DATA_STORE: 1174 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1175 break; 1176 default: 1177 g_assert_not_reached(); 1178 } 1179 env->badaddr = addr; 1180 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1181 riscv_cpu_two_stage_lookup(mmu_idx); 1182 env->two_stage_indirect_lookup = false; 1183 cpu_loop_exit_restore(cs, retaddr); 1184 } 1185 1186 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1187 MMUAccessType access_type, int mmu_idx, 1188 bool probe, uintptr_t retaddr) 1189 { 1190 RISCVCPU *cpu = RISCV_CPU(cs); 1191 CPURISCVState *env = &cpu->env; 1192 vaddr im_address; 1193 hwaddr pa = 0; 1194 int prot, prot2, prot_pmp; 1195 bool pmp_violation = false; 1196 bool first_stage_error = true; 1197 bool two_stage_lookup = false; 1198 bool two_stage_indirect_error = false; 1199 int ret = TRANSLATE_FAIL; 1200 int mode = mmu_idx; 1201 /* default TLB page size */ 1202 target_ulong tlb_size = TARGET_PAGE_SIZE; 1203 1204 env->guest_phys_fault_addr = 0; 1205 1206 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1207 __func__, address, access_type, mmu_idx); 1208 1209 /* MPRV does not affect the virtual-machine load/store 1210 instructions, HLV, HLVX, and HSV. */ 1211 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1212 mode = get_field(env->hstatus, HSTATUS_SPVP); 1213 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1214 get_field(env->mstatus, MSTATUS_MPRV)) { 1215 mode = get_field(env->mstatus, MSTATUS_MPP); 1216 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1217 two_stage_lookup = true; 1218 } 1219 } 1220 1221 if (riscv_cpu_virt_enabled(env) || 1222 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1223 access_type != MMU_INST_FETCH)) { 1224 /* Two stage lookup */ 1225 ret = get_physical_address(env, &pa, &prot, address, 1226 &env->guest_phys_fault_addr, access_type, 1227 mmu_idx, true, true, false); 1228 1229 /* 1230 * A G-stage exception may be triggered during two state lookup. 1231 * And the env->guest_phys_fault_addr has already been set in 1232 * get_physical_address(). 1233 */ 1234 if (ret == TRANSLATE_G_STAGE_FAIL) { 1235 first_stage_error = false; 1236 two_stage_indirect_error = true; 1237 access_type = MMU_DATA_LOAD; 1238 } 1239 1240 qemu_log_mask(CPU_LOG_MMU, 1241 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1242 TARGET_FMT_plx " prot %d\n", 1243 __func__, address, ret, pa, prot); 1244 1245 if (ret == TRANSLATE_SUCCESS) { 1246 /* Second stage lookup */ 1247 im_address = pa; 1248 1249 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1250 access_type, mmu_idx, false, true, 1251 false); 1252 1253 qemu_log_mask(CPU_LOG_MMU, 1254 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 1255 TARGET_FMT_plx " prot %d\n", 1256 __func__, im_address, ret, pa, prot2); 1257 1258 prot &= prot2; 1259 1260 if (ret == TRANSLATE_SUCCESS) { 1261 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1262 size, access_type, mode); 1263 1264 qemu_log_mask(CPU_LOG_MMU, 1265 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1266 " %d tlb_size " TARGET_FMT_lu "\n", 1267 __func__, pa, ret, prot_pmp, tlb_size); 1268 1269 prot &= prot_pmp; 1270 } 1271 1272 if (ret != TRANSLATE_SUCCESS) { 1273 /* 1274 * Guest physical address translation failed, this is a HS 1275 * level exception 1276 */ 1277 first_stage_error = false; 1278 env->guest_phys_fault_addr = (im_address | 1279 (address & 1280 (TARGET_PAGE_SIZE - 1))) >> 2; 1281 } 1282 } 1283 } else { 1284 /* Single stage lookup */ 1285 ret = get_physical_address(env, &pa, &prot, address, NULL, 1286 access_type, mmu_idx, true, false, false); 1287 1288 qemu_log_mask(CPU_LOG_MMU, 1289 "%s address=%" VADDR_PRIx " ret %d physical " 1290 TARGET_FMT_plx " prot %d\n", 1291 __func__, address, ret, pa, prot); 1292 1293 if (ret == TRANSLATE_SUCCESS) { 1294 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1295 size, access_type, mode); 1296 1297 qemu_log_mask(CPU_LOG_MMU, 1298 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1299 " %d tlb_size " TARGET_FMT_lu "\n", 1300 __func__, pa, ret, prot_pmp, tlb_size); 1301 1302 prot &= prot_pmp; 1303 } 1304 } 1305 1306 if (ret == TRANSLATE_PMP_FAIL) { 1307 pmp_violation = true; 1308 } 1309 1310 if (ret == TRANSLATE_SUCCESS) { 1311 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1312 prot, mmu_idx, tlb_size); 1313 return true; 1314 } else if (probe) { 1315 return false; 1316 } else { 1317 raise_mmu_exception(env, address, access_type, pmp_violation, 1318 first_stage_error, 1319 riscv_cpu_virt_enabled(env) || 1320 riscv_cpu_two_stage_lookup(mmu_idx), 1321 two_stage_indirect_error); 1322 cpu_loop_exit_restore(cs, retaddr); 1323 } 1324 1325 return true; 1326 } 1327 1328 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1329 target_ulong insn, 1330 target_ulong taddr) 1331 { 1332 target_ulong xinsn = 0; 1333 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1334 1335 /* 1336 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1337 * be uncompressed. The Quadrant 1 of RVC instruction space need 1338 * not be transformed because these instructions won't generate 1339 * any load/store trap. 1340 */ 1341 1342 if ((insn & 0x3) != 0x3) { 1343 /* Transform 16bit instruction into 32bit instruction */ 1344 switch (GET_C_OP(insn)) { 1345 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1346 switch (GET_C_FUNC(insn)) { 1347 case OPC_RISC_C_FUNC_FLD_LQ: 1348 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1349 xinsn = OPC_RISC_FLD; 1350 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1351 access_rs1 = GET_C_RS1S(insn); 1352 access_imm = GET_C_LD_IMM(insn); 1353 access_size = 8; 1354 } 1355 break; 1356 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1357 xinsn = OPC_RISC_LW; 1358 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1359 access_rs1 = GET_C_RS1S(insn); 1360 access_imm = GET_C_LW_IMM(insn); 1361 access_size = 4; 1362 break; 1363 case OPC_RISC_C_FUNC_FLW_LD: 1364 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1365 xinsn = OPC_RISC_FLW; 1366 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1367 access_rs1 = GET_C_RS1S(insn); 1368 access_imm = GET_C_LW_IMM(insn); 1369 access_size = 4; 1370 } else { /* C.LD (RV64/RV128) */ 1371 xinsn = OPC_RISC_LD; 1372 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1373 access_rs1 = GET_C_RS1S(insn); 1374 access_imm = GET_C_LD_IMM(insn); 1375 access_size = 8; 1376 } 1377 break; 1378 case OPC_RISC_C_FUNC_FSD_SQ: 1379 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1380 xinsn = OPC_RISC_FSD; 1381 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1382 access_rs1 = GET_C_RS1S(insn); 1383 access_imm = GET_C_SD_IMM(insn); 1384 access_size = 8; 1385 } 1386 break; 1387 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1388 xinsn = OPC_RISC_SW; 1389 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1390 access_rs1 = GET_C_RS1S(insn); 1391 access_imm = GET_C_SW_IMM(insn); 1392 access_size = 4; 1393 break; 1394 case OPC_RISC_C_FUNC_FSW_SD: 1395 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1396 xinsn = OPC_RISC_FSW; 1397 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1398 access_rs1 = GET_C_RS1S(insn); 1399 access_imm = GET_C_SW_IMM(insn); 1400 access_size = 4; 1401 } else { /* C.SD (RV64/RV128) */ 1402 xinsn = OPC_RISC_SD; 1403 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1404 access_rs1 = GET_C_RS1S(insn); 1405 access_imm = GET_C_SD_IMM(insn); 1406 access_size = 8; 1407 } 1408 break; 1409 default: 1410 break; 1411 } 1412 break; 1413 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1414 switch (GET_C_FUNC(insn)) { 1415 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1416 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1417 xinsn = OPC_RISC_FLD; 1418 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1419 access_rs1 = 2; 1420 access_imm = GET_C_LDSP_IMM(insn); 1421 access_size = 8; 1422 } 1423 break; 1424 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1425 xinsn = OPC_RISC_LW; 1426 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1427 access_rs1 = 2; 1428 access_imm = GET_C_LWSP_IMM(insn); 1429 access_size = 4; 1430 break; 1431 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1432 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1433 xinsn = OPC_RISC_FLW; 1434 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1435 access_rs1 = 2; 1436 access_imm = GET_C_LWSP_IMM(insn); 1437 access_size = 4; 1438 } else { /* C.LDSP (RV64/RV128) */ 1439 xinsn = OPC_RISC_LD; 1440 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1441 access_rs1 = 2; 1442 access_imm = GET_C_LDSP_IMM(insn); 1443 access_size = 8; 1444 } 1445 break; 1446 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1447 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1448 xinsn = OPC_RISC_FSD; 1449 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1450 access_rs1 = 2; 1451 access_imm = GET_C_SDSP_IMM(insn); 1452 access_size = 8; 1453 } 1454 break; 1455 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1456 xinsn = OPC_RISC_SW; 1457 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1458 access_rs1 = 2; 1459 access_imm = GET_C_SWSP_IMM(insn); 1460 access_size = 4; 1461 break; 1462 case 7: 1463 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1464 xinsn = OPC_RISC_FSW; 1465 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1466 access_rs1 = 2; 1467 access_imm = GET_C_SWSP_IMM(insn); 1468 access_size = 4; 1469 } else { /* C.SDSP (RV64/RV128) */ 1470 xinsn = OPC_RISC_SD; 1471 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1472 access_rs1 = 2; 1473 access_imm = GET_C_SDSP_IMM(insn); 1474 access_size = 8; 1475 } 1476 break; 1477 default: 1478 break; 1479 } 1480 break; 1481 default: 1482 break; 1483 } 1484 1485 /* 1486 * Clear Bit1 of transformed instruction to indicate that 1487 * original insruction was a 16bit instruction 1488 */ 1489 xinsn &= ~((target_ulong)0x2); 1490 } else { 1491 /* Transform 32bit (or wider) instructions */ 1492 switch (MASK_OP_MAJOR(insn)) { 1493 case OPC_RISC_ATOMIC: 1494 xinsn = insn; 1495 access_rs1 = GET_RS1(insn); 1496 access_size = 1 << GET_FUNCT3(insn); 1497 break; 1498 case OPC_RISC_LOAD: 1499 case OPC_RISC_FP_LOAD: 1500 xinsn = SET_I_IMM(insn, 0); 1501 access_rs1 = GET_RS1(insn); 1502 access_imm = GET_IMM(insn); 1503 access_size = 1 << GET_FUNCT3(insn); 1504 break; 1505 case OPC_RISC_STORE: 1506 case OPC_RISC_FP_STORE: 1507 xinsn = SET_S_IMM(insn, 0); 1508 access_rs1 = GET_RS1(insn); 1509 access_imm = GET_STORE_IMM(insn); 1510 access_size = 1 << GET_FUNCT3(insn); 1511 break; 1512 case OPC_RISC_SYSTEM: 1513 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1514 xinsn = insn; 1515 access_rs1 = GET_RS1(insn); 1516 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1517 access_size = 1 << access_size; 1518 } 1519 break; 1520 default: 1521 break; 1522 } 1523 } 1524 1525 if (access_size) { 1526 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1527 (access_size - 1)); 1528 } 1529 1530 return xinsn; 1531 } 1532 #endif /* !CONFIG_USER_ONLY */ 1533 1534 /* 1535 * Handle Traps 1536 * 1537 * Adapted from Spike's processor_t::take_trap. 1538 * 1539 */ 1540 void riscv_cpu_do_interrupt(CPUState *cs) 1541 { 1542 #if !defined(CONFIG_USER_ONLY) 1543 1544 RISCVCPU *cpu = RISCV_CPU(cs); 1545 CPURISCVState *env = &cpu->env; 1546 bool write_gva = false; 1547 uint64_t s; 1548 1549 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1550 * so we mask off the MSB and separate into trap type and cause. 1551 */ 1552 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1553 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1554 uint64_t deleg = async ? env->mideleg : env->medeleg; 1555 target_ulong tval = 0; 1556 target_ulong tinst = 0; 1557 target_ulong htval = 0; 1558 target_ulong mtval2 = 0; 1559 1560 if (cause == RISCV_EXCP_SEMIHOST) { 1561 if (env->priv >= PRV_S) { 1562 do_common_semihosting(cs); 1563 env->pc += 4; 1564 return; 1565 } 1566 cause = RISCV_EXCP_BREAKPOINT; 1567 } 1568 1569 if (!async) { 1570 /* set tval to badaddr for traps with address information */ 1571 switch (cause) { 1572 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1573 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1574 case RISCV_EXCP_LOAD_ADDR_MIS: 1575 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1576 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1577 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1578 case RISCV_EXCP_LOAD_PAGE_FAULT: 1579 case RISCV_EXCP_STORE_PAGE_FAULT: 1580 write_gva = env->two_stage_lookup; 1581 tval = env->badaddr; 1582 if (env->two_stage_indirect_lookup) { 1583 /* 1584 * special pseudoinstruction for G-stage fault taken while 1585 * doing VS-stage page table walk. 1586 */ 1587 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1588 } else { 1589 /* 1590 * The "Addr. Offset" field in transformed instruction is 1591 * non-zero only for misaligned access. 1592 */ 1593 tinst = riscv_transformed_insn(env, env->bins, tval); 1594 } 1595 break; 1596 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1597 case RISCV_EXCP_INST_ADDR_MIS: 1598 case RISCV_EXCP_INST_ACCESS_FAULT: 1599 case RISCV_EXCP_INST_PAGE_FAULT: 1600 write_gva = env->two_stage_lookup; 1601 tval = env->badaddr; 1602 if (env->two_stage_indirect_lookup) { 1603 /* 1604 * special pseudoinstruction for G-stage fault taken while 1605 * doing VS-stage page table walk. 1606 */ 1607 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1608 } 1609 break; 1610 case RISCV_EXCP_ILLEGAL_INST: 1611 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1612 tval = env->bins; 1613 break; 1614 default: 1615 break; 1616 } 1617 /* ecall is dispatched as one cause so translate based on mode */ 1618 if (cause == RISCV_EXCP_U_ECALL) { 1619 assert(env->priv <= 3); 1620 1621 if (env->priv == PRV_M) { 1622 cause = RISCV_EXCP_M_ECALL; 1623 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1624 cause = RISCV_EXCP_VS_ECALL; 1625 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1626 cause = RISCV_EXCP_S_ECALL; 1627 } else if (env->priv == PRV_U) { 1628 cause = RISCV_EXCP_U_ECALL; 1629 } 1630 } 1631 } 1632 1633 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1634 riscv_cpu_get_trap_name(cause, async)); 1635 1636 qemu_log_mask(CPU_LOG_INT, 1637 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1638 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1639 __func__, env->mhartid, async, cause, env->pc, tval, 1640 riscv_cpu_get_trap_name(cause, async)); 1641 1642 if (env->priv <= PRV_S && 1643 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1644 /* handle the trap in S-mode */ 1645 if (riscv_has_ext(env, RVH)) { 1646 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1647 1648 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1649 /* Trap to VS mode */ 1650 /* 1651 * See if we need to adjust cause. Yes if its VS mode interrupt 1652 * no if hypervisor has delegated one of hs mode's interrupt 1653 */ 1654 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1655 cause == IRQ_VS_EXT) { 1656 cause = cause - 1; 1657 } 1658 write_gva = false; 1659 } else if (riscv_cpu_virt_enabled(env)) { 1660 /* Trap into HS mode, from virt */ 1661 riscv_cpu_swap_hypervisor_regs(env); 1662 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1663 env->priv); 1664 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1665 riscv_cpu_virt_enabled(env)); 1666 1667 1668 htval = env->guest_phys_fault_addr; 1669 1670 riscv_cpu_set_virt_enabled(env, 0); 1671 } else { 1672 /* Trap into HS mode */ 1673 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1674 htval = env->guest_phys_fault_addr; 1675 } 1676 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1677 } 1678 1679 s = env->mstatus; 1680 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1681 s = set_field(s, MSTATUS_SPP, env->priv); 1682 s = set_field(s, MSTATUS_SIE, 0); 1683 env->mstatus = s; 1684 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1685 env->sepc = env->pc; 1686 env->stval = tval; 1687 env->htval = htval; 1688 env->htinst = tinst; 1689 env->pc = (env->stvec >> 2 << 2) + 1690 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1691 riscv_cpu_set_mode(env, PRV_S); 1692 } else { 1693 /* handle the trap in M-mode */ 1694 if (riscv_has_ext(env, RVH)) { 1695 if (riscv_cpu_virt_enabled(env)) { 1696 riscv_cpu_swap_hypervisor_regs(env); 1697 } 1698 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1699 riscv_cpu_virt_enabled(env)); 1700 if (riscv_cpu_virt_enabled(env) && tval) { 1701 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1702 } 1703 1704 mtval2 = env->guest_phys_fault_addr; 1705 1706 /* Trapping to M mode, virt is disabled */ 1707 riscv_cpu_set_virt_enabled(env, 0); 1708 } 1709 1710 s = env->mstatus; 1711 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1712 s = set_field(s, MSTATUS_MPP, env->priv); 1713 s = set_field(s, MSTATUS_MIE, 0); 1714 env->mstatus = s; 1715 env->mcause = cause | ~(((target_ulong)-1) >> async); 1716 env->mepc = env->pc; 1717 env->mtval = tval; 1718 env->mtval2 = mtval2; 1719 env->mtinst = tinst; 1720 env->pc = (env->mtvec >> 2 << 2) + 1721 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1722 riscv_cpu_set_mode(env, PRV_M); 1723 } 1724 1725 /* NOTE: it is not necessary to yield load reservations here. It is only 1726 * necessary for an SC from "another hart" to cause a load reservation 1727 * to be yielded. Refer to the memory consistency model section of the 1728 * RISC-V ISA Specification. 1729 */ 1730 1731 env->two_stage_lookup = false; 1732 env->two_stage_indirect_lookup = false; 1733 #endif 1734 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1735 } 1736