1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 } else { 78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 79 } 80 81 #ifdef CONFIG_USER_ONLY 82 flags |= TB_FLAGS_MSTATUS_FS; 83 flags |= TB_FLAGS_MSTATUS_VS; 84 #else 85 flags |= cpu_mmu_index(env, 0); 86 if (riscv_cpu_fp_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_FS; 88 } 89 90 if (riscv_cpu_vector_enabled(env)) { 91 flags |= env->mstatus & MSTATUS_VS; 92 } 93 94 if (riscv_has_ext(env, RVH)) { 95 if (env->priv == PRV_M || 96 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 97 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 98 get_field(env->hstatus, HSTATUS_HU))) { 99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 100 } 101 102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 103 get_field(env->mstatus_hs, MSTATUS_FS)); 104 105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 106 get_field(env->mstatus_hs, MSTATUS_VS)); 107 } 108 if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, 110 riscv_itrigger_enabled(env)); 111 } 112 #endif 113 114 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 115 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 116 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 117 } 118 if (env->cur_pmbase != 0) { 119 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 120 } 121 122 *pflags = flags; 123 } 124 125 void riscv_cpu_update_mask(CPURISCVState *env) 126 { 127 target_ulong mask = -1, base = 0; 128 /* 129 * TODO: Current RVJ spec does not specify 130 * how the extension interacts with XLEN. 131 */ 132 #ifndef CONFIG_USER_ONLY 133 if (riscv_has_ext(env, RVJ)) { 134 switch (env->priv) { 135 case PRV_M: 136 if (env->mmte & M_PM_ENABLE) { 137 mask = env->mpmmask; 138 base = env->mpmbase; 139 } 140 break; 141 case PRV_S: 142 if (env->mmte & S_PM_ENABLE) { 143 mask = env->spmmask; 144 base = env->spmbase; 145 } 146 break; 147 case PRV_U: 148 if (env->mmte & U_PM_ENABLE) { 149 mask = env->upmmask; 150 base = env->upmbase; 151 } 152 break; 153 default: 154 g_assert_not_reached(); 155 } 156 } 157 #endif 158 if (env->xl == MXL_RV32) { 159 env->cur_pmmask = mask & UINT32_MAX; 160 env->cur_pmbase = base & UINT32_MAX; 161 } else { 162 env->cur_pmmask = mask; 163 env->cur_pmbase = base; 164 } 165 } 166 167 #ifndef CONFIG_USER_ONLY 168 169 /* 170 * The HS-mode is allowed to configure priority only for the 171 * following VS-mode local interrupts: 172 * 173 * 0 (Reserved interrupt, reads as zero) 174 * 1 Supervisor software interrupt 175 * 4 (Reserved interrupt, reads as zero) 176 * 5 Supervisor timer interrupt 177 * 8 (Reserved interrupt, reads as zero) 178 * 13 (Reserved interrupt) 179 * 14 " 180 * 15 " 181 * 16 " 182 * 17 " 183 * 18 " 184 * 19 " 185 * 20 " 186 * 21 " 187 * 22 " 188 * 23 " 189 */ 190 191 static const int hviprio_index2irq[] = { 192 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 193 static const int hviprio_index2rdzero[] = { 194 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 195 196 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 197 { 198 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 199 return -EINVAL; 200 } 201 202 if (out_irq) { 203 *out_irq = hviprio_index2irq[index]; 204 } 205 206 if (out_rdzero) { 207 *out_rdzero = hviprio_index2rdzero[index]; 208 } 209 210 return 0; 211 } 212 213 /* 214 * Default priorities of local interrupts are defined in the 215 * RISC-V Advanced Interrupt Architecture specification. 216 * 217 * ---------------------------------------------------------------- 218 * Default | 219 * Priority | Major Interrupt Numbers 220 * ---------------------------------------------------------------- 221 * Highest | 47, 23, 46, 45, 22, 44, 222 * | 43, 21, 42, 41, 20, 40 223 * | 224 * | 11 (0b), 3 (03), 7 (07) 225 * | 9 (09), 1 (01), 5 (05) 226 * | 12 (0c) 227 * | 10 (0a), 2 (02), 6 (06) 228 * | 229 * | 39, 19, 38, 37, 18, 36, 230 * Lowest | 35, 17, 34, 33, 16, 32 231 * ---------------------------------------------------------------- 232 */ 233 static const uint8_t default_iprio[64] = { 234 /* Custom interrupts 48 to 63 */ 235 [63] = IPRIO_MMAXIPRIO, 236 [62] = IPRIO_MMAXIPRIO, 237 [61] = IPRIO_MMAXIPRIO, 238 [60] = IPRIO_MMAXIPRIO, 239 [59] = IPRIO_MMAXIPRIO, 240 [58] = IPRIO_MMAXIPRIO, 241 [57] = IPRIO_MMAXIPRIO, 242 [56] = IPRIO_MMAXIPRIO, 243 [55] = IPRIO_MMAXIPRIO, 244 [54] = IPRIO_MMAXIPRIO, 245 [53] = IPRIO_MMAXIPRIO, 246 [52] = IPRIO_MMAXIPRIO, 247 [51] = IPRIO_MMAXIPRIO, 248 [50] = IPRIO_MMAXIPRIO, 249 [49] = IPRIO_MMAXIPRIO, 250 [48] = IPRIO_MMAXIPRIO, 251 252 /* Custom interrupts 24 to 31 */ 253 [31] = IPRIO_MMAXIPRIO, 254 [30] = IPRIO_MMAXIPRIO, 255 [29] = IPRIO_MMAXIPRIO, 256 [28] = IPRIO_MMAXIPRIO, 257 [27] = IPRIO_MMAXIPRIO, 258 [26] = IPRIO_MMAXIPRIO, 259 [25] = IPRIO_MMAXIPRIO, 260 [24] = IPRIO_MMAXIPRIO, 261 262 [47] = IPRIO_DEFAULT_UPPER, 263 [23] = IPRIO_DEFAULT_UPPER + 1, 264 [46] = IPRIO_DEFAULT_UPPER + 2, 265 [45] = IPRIO_DEFAULT_UPPER + 3, 266 [22] = IPRIO_DEFAULT_UPPER + 4, 267 [44] = IPRIO_DEFAULT_UPPER + 5, 268 269 [43] = IPRIO_DEFAULT_UPPER + 6, 270 [21] = IPRIO_DEFAULT_UPPER + 7, 271 [42] = IPRIO_DEFAULT_UPPER + 8, 272 [41] = IPRIO_DEFAULT_UPPER + 9, 273 [20] = IPRIO_DEFAULT_UPPER + 10, 274 [40] = IPRIO_DEFAULT_UPPER + 11, 275 276 [11] = IPRIO_DEFAULT_M, 277 [3] = IPRIO_DEFAULT_M + 1, 278 [7] = IPRIO_DEFAULT_M + 2, 279 280 [9] = IPRIO_DEFAULT_S, 281 [1] = IPRIO_DEFAULT_S + 1, 282 [5] = IPRIO_DEFAULT_S + 2, 283 284 [12] = IPRIO_DEFAULT_SGEXT, 285 286 [10] = IPRIO_DEFAULT_VS, 287 [2] = IPRIO_DEFAULT_VS + 1, 288 [6] = IPRIO_DEFAULT_VS + 2, 289 290 [39] = IPRIO_DEFAULT_LOWER, 291 [19] = IPRIO_DEFAULT_LOWER + 1, 292 [38] = IPRIO_DEFAULT_LOWER + 2, 293 [37] = IPRIO_DEFAULT_LOWER + 3, 294 [18] = IPRIO_DEFAULT_LOWER + 4, 295 [36] = IPRIO_DEFAULT_LOWER + 5, 296 297 [35] = IPRIO_DEFAULT_LOWER + 6, 298 [17] = IPRIO_DEFAULT_LOWER + 7, 299 [34] = IPRIO_DEFAULT_LOWER + 8, 300 [33] = IPRIO_DEFAULT_LOWER + 9, 301 [16] = IPRIO_DEFAULT_LOWER + 10, 302 [32] = IPRIO_DEFAULT_LOWER + 11, 303 }; 304 305 uint8_t riscv_cpu_default_priority(int irq) 306 { 307 if (irq < 0 || irq > 63) { 308 return IPRIO_MMAXIPRIO; 309 } 310 311 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 312 }; 313 314 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 315 int extirq, unsigned int extirq_def_prio, 316 uint64_t pending, uint8_t *iprio) 317 { 318 RISCVCPU *cpu = env_archcpu(env); 319 int irq, best_irq = RISCV_EXCP_NONE; 320 unsigned int prio, best_prio = UINT_MAX; 321 322 if (!pending) { 323 return RISCV_EXCP_NONE; 324 } 325 326 irq = ctz64(pending); 327 if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) { 328 return irq; 329 } 330 331 pending = pending >> irq; 332 while (pending) { 333 prio = iprio[irq]; 334 if (!prio) { 335 if (irq == extirq) { 336 prio = extirq_def_prio; 337 } else { 338 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 339 1 : IPRIO_MMAXIPRIO; 340 } 341 } 342 if ((pending & 0x1) && (prio <= best_prio)) { 343 best_irq = irq; 344 best_prio = prio; 345 } 346 irq++; 347 pending = pending >> 1; 348 } 349 350 return best_irq; 351 } 352 353 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 354 { 355 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 356 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 357 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 358 359 return (env->mip | vsgein | vstip) & env->mie; 360 } 361 362 int riscv_cpu_mirq_pending(CPURISCVState *env) 363 { 364 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 365 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 366 367 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 368 irqs, env->miprio); 369 } 370 371 int riscv_cpu_sirq_pending(CPURISCVState *env) 372 { 373 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 374 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 375 376 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 377 irqs, env->siprio); 378 } 379 380 int riscv_cpu_vsirq_pending(CPURISCVState *env) 381 { 382 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 383 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 384 385 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 386 irqs >> 1, env->hviprio); 387 } 388 389 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 390 { 391 int virq; 392 uint64_t irqs, pending, mie, hsie, vsie; 393 394 /* Determine interrupt enable state of all privilege modes */ 395 if (riscv_cpu_virt_enabled(env)) { 396 mie = 1; 397 hsie = 1; 398 vsie = (env->priv < PRV_S) || 399 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 400 } else { 401 mie = (env->priv < PRV_M) || 402 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 403 hsie = (env->priv < PRV_S) || 404 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 405 vsie = 0; 406 } 407 408 /* Determine all pending interrupts */ 409 pending = riscv_cpu_all_pending(env); 410 411 /* Check M-mode interrupts */ 412 irqs = pending & ~env->mideleg & -mie; 413 if (irqs) { 414 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 415 irqs, env->miprio); 416 } 417 418 /* Check HS-mode interrupts */ 419 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 420 if (irqs) { 421 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 422 irqs, env->siprio); 423 } 424 425 /* Check VS-mode interrupts */ 426 irqs = pending & env->mideleg & env->hideleg & -vsie; 427 if (irqs) { 428 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 429 irqs >> 1, env->hviprio); 430 return (virq <= 0) ? virq : virq + 1; 431 } 432 433 /* Indicate no pending interrupt */ 434 return RISCV_EXCP_NONE; 435 } 436 437 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 438 { 439 if (interrupt_request & CPU_INTERRUPT_HARD) { 440 RISCVCPU *cpu = RISCV_CPU(cs); 441 CPURISCVState *env = &cpu->env; 442 int interruptno = riscv_cpu_local_irq_pending(env); 443 if (interruptno >= 0) { 444 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 445 riscv_cpu_do_interrupt(cs); 446 return true; 447 } 448 } 449 return false; 450 } 451 452 /* Return true is floating point support is currently enabled */ 453 bool riscv_cpu_fp_enabled(CPURISCVState *env) 454 { 455 if (env->mstatus & MSTATUS_FS) { 456 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 457 return false; 458 } 459 return true; 460 } 461 462 return false; 463 } 464 465 /* Return true is vector support is currently enabled */ 466 bool riscv_cpu_vector_enabled(CPURISCVState *env) 467 { 468 if (env->mstatus & MSTATUS_VS) { 469 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 470 return false; 471 } 472 return true; 473 } 474 475 return false; 476 } 477 478 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 479 { 480 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 481 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 482 MSTATUS64_UXL | MSTATUS_VS; 483 484 if (riscv_has_ext(env, RVF)) { 485 mstatus_mask |= MSTATUS_FS; 486 } 487 bool current_virt = riscv_cpu_virt_enabled(env); 488 489 g_assert(riscv_has_ext(env, RVH)); 490 491 if (current_virt) { 492 /* Current V=1 and we are about to change to V=0 */ 493 env->vsstatus = env->mstatus & mstatus_mask; 494 env->mstatus &= ~mstatus_mask; 495 env->mstatus |= env->mstatus_hs; 496 497 env->vstvec = env->stvec; 498 env->stvec = env->stvec_hs; 499 500 env->vsscratch = env->sscratch; 501 env->sscratch = env->sscratch_hs; 502 503 env->vsepc = env->sepc; 504 env->sepc = env->sepc_hs; 505 506 env->vscause = env->scause; 507 env->scause = env->scause_hs; 508 509 env->vstval = env->stval; 510 env->stval = env->stval_hs; 511 512 env->vsatp = env->satp; 513 env->satp = env->satp_hs; 514 } else { 515 /* Current V=0 and we are about to change to V=1 */ 516 env->mstatus_hs = env->mstatus & mstatus_mask; 517 env->mstatus &= ~mstatus_mask; 518 env->mstatus |= env->vsstatus; 519 520 env->stvec_hs = env->stvec; 521 env->stvec = env->vstvec; 522 523 env->sscratch_hs = env->sscratch; 524 env->sscratch = env->vsscratch; 525 526 env->sepc_hs = env->sepc; 527 env->sepc = env->vsepc; 528 529 env->scause_hs = env->scause; 530 env->scause = env->vscause; 531 532 env->stval_hs = env->stval; 533 env->stval = env->vstval; 534 535 env->satp_hs = env->satp; 536 env->satp = env->vsatp; 537 } 538 } 539 540 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 541 { 542 if (!riscv_has_ext(env, RVH)) { 543 return 0; 544 } 545 546 return env->geilen; 547 } 548 549 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 550 { 551 if (!riscv_has_ext(env, RVH)) { 552 return; 553 } 554 555 if (geilen > (TARGET_LONG_BITS - 1)) { 556 return; 557 } 558 559 env->geilen = geilen; 560 } 561 562 bool riscv_cpu_virt_enabled(CPURISCVState *env) 563 { 564 if (!riscv_has_ext(env, RVH)) { 565 return false; 566 } 567 568 return get_field(env->virt, VIRT_ONOFF); 569 } 570 571 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 572 { 573 if (!riscv_has_ext(env, RVH)) { 574 return; 575 } 576 577 /* Flush the TLB on all virt mode changes. */ 578 if (get_field(env->virt, VIRT_ONOFF) != enable) { 579 tlb_flush(env_cpu(env)); 580 } 581 582 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 583 584 if (enable) { 585 /* 586 * The guest external interrupts from an interrupt controller are 587 * delivered only when the Guest/VM is running (i.e. V=1). This means 588 * any guest external interrupt which is triggered while the Guest/VM 589 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 590 * with sluggish response to serial console input and other I/O events. 591 * 592 * To solve this, we check and inject interrupt after setting V=1. 593 */ 594 riscv_cpu_update_mip(env_archcpu(env), 0, 0); 595 } 596 } 597 598 bool riscv_cpu_two_stage_lookup(int mmu_idx) 599 { 600 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 601 } 602 603 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 604 { 605 CPURISCVState *env = &cpu->env; 606 if (env->miclaim & interrupts) { 607 return -1; 608 } else { 609 env->miclaim |= interrupts; 610 return 0; 611 } 612 } 613 614 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) 615 { 616 CPURISCVState *env = &cpu->env; 617 CPUState *cs = CPU(cpu); 618 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 619 bool locked = false; 620 621 if (riscv_cpu_virt_enabled(env)) { 622 gein = get_field(env->hstatus, HSTATUS_VGEIN); 623 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 624 } 625 626 /* No need to update mip for VSTIP */ 627 mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; 628 vstip = env->vstime_irq ? MIP_VSTIP : 0; 629 630 if (!qemu_mutex_iothread_locked()) { 631 locked = true; 632 qemu_mutex_lock_iothread(); 633 } 634 635 env->mip = (env->mip & ~mask) | (value & mask); 636 637 if (env->mip | vsgein | vstip) { 638 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 639 } else { 640 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 641 } 642 643 if (locked) { 644 qemu_mutex_unlock_iothread(); 645 } 646 647 return old; 648 } 649 650 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 651 void *arg) 652 { 653 env->rdtime_fn = fn; 654 env->rdtime_fn_arg = arg; 655 } 656 657 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 658 int (*rmw_fn)(void *arg, 659 target_ulong reg, 660 target_ulong *val, 661 target_ulong new_val, 662 target_ulong write_mask), 663 void *rmw_fn_arg) 664 { 665 if (priv <= PRV_M) { 666 env->aia_ireg_rmw_fn[priv] = rmw_fn; 667 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 668 } 669 } 670 671 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 672 { 673 if (newpriv > PRV_M) { 674 g_assert_not_reached(); 675 } 676 if (newpriv == PRV_H) { 677 newpriv = PRV_U; 678 } 679 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 680 env->priv = newpriv; 681 env->xl = cpu_recompute_xl(env); 682 riscv_cpu_update_mask(env); 683 684 /* 685 * Clear the load reservation - otherwise a reservation placed in one 686 * context/process can be used by another, resulting in an SC succeeding 687 * incorrectly. Version 2.2 of the ISA specification explicitly requires 688 * this behaviour, while later revisions say that the kernel "should" use 689 * an SC instruction to force the yielding of a load reservation on a 690 * preemptive context switch. As a result, do both. 691 */ 692 env->load_res = -1; 693 } 694 695 /* 696 * get_physical_address_pmp - check PMP permission for this physical address 697 * 698 * Match the PMP region and check permission for this physical address and it's 699 * TLB page. Returns 0 if the permission checking was successful 700 * 701 * @env: CPURISCVState 702 * @prot: The returned protection attributes 703 * @tlb_size: TLB page size containing addr. It could be modified after PMP 704 * permission checking. NULL if not set TLB page for addr. 705 * @addr: The physical address to be checked permission 706 * @access_type: The type of MMU access 707 * @mode: Indicates current privilege level. 708 */ 709 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 710 target_ulong *tlb_size, hwaddr addr, 711 int size, MMUAccessType access_type, 712 int mode) 713 { 714 pmp_priv_t pmp_priv; 715 int pmp_index = -1; 716 717 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 718 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 719 return TRANSLATE_SUCCESS; 720 } 721 722 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 723 &pmp_priv, mode); 724 if (pmp_index < 0) { 725 *prot = 0; 726 return TRANSLATE_PMP_FAIL; 727 } 728 729 *prot = pmp_priv_to_page_prot(pmp_priv); 730 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 731 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 732 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 733 734 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 735 } 736 737 return TRANSLATE_SUCCESS; 738 } 739 740 /* get_physical_address - get the physical address for this virtual address 741 * 742 * Do a page table walk to obtain the physical address corresponding to a 743 * virtual address. Returns 0 if the translation was successful 744 * 745 * Adapted from Spike's mmu_t::translate and mmu_t::walk 746 * 747 * @env: CPURISCVState 748 * @physical: This will be set to the calculated physical address 749 * @prot: The returned protection attributes 750 * @addr: The virtual address to be translated 751 * @fault_pte_addr: If not NULL, this will be set to fault pte address 752 * when a error occurs on pte address translation. 753 * This will already be shifted to match htval. 754 * @access_type: The type of MMU access 755 * @mmu_idx: Indicates current privilege level 756 * @first_stage: Are we in first stage translation? 757 * Second stage is used for hypervisor guest translation 758 * @two_stage: Are we going to perform two stage translation 759 * @is_debug: Is this access from a debugger or the monitor? 760 */ 761 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 762 int *prot, target_ulong addr, 763 target_ulong *fault_pte_addr, 764 int access_type, int mmu_idx, 765 bool first_stage, bool two_stage, 766 bool is_debug) 767 { 768 /* NOTE: the env->pc value visible here will not be 769 * correct, but the value visible to the exception handler 770 * (riscv_cpu_do_interrupt) is correct */ 771 MemTxResult res; 772 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 773 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 774 bool use_background = false; 775 hwaddr ppn; 776 RISCVCPU *cpu = env_archcpu(env); 777 int napot_bits = 0; 778 target_ulong napot_mask; 779 780 /* 781 * Check if we should use the background registers for the two 782 * stage translation. We don't need to check if we actually need 783 * two stage translation as that happened before this function 784 * was called. Background registers will be used if the guest has 785 * forced a two stage translation to be on (in HS or M mode). 786 */ 787 if (!riscv_cpu_virt_enabled(env) && two_stage) { 788 use_background = true; 789 } 790 791 /* MPRV does not affect the virtual-machine load/store 792 instructions, HLV, HLVX, and HSV. */ 793 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 794 mode = get_field(env->hstatus, HSTATUS_SPVP); 795 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 796 if (get_field(env->mstatus, MSTATUS_MPRV)) { 797 mode = get_field(env->mstatus, MSTATUS_MPP); 798 } 799 } 800 801 if (first_stage == false) { 802 /* We are in stage 2 translation, this is similar to stage 1. */ 803 /* Stage 2 is always taken as U-mode */ 804 mode = PRV_U; 805 } 806 807 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 808 *physical = addr; 809 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 810 return TRANSLATE_SUCCESS; 811 } 812 813 *prot = 0; 814 815 hwaddr base; 816 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 817 818 if (first_stage == true) { 819 mxr = get_field(env->mstatus, MSTATUS_MXR); 820 } else { 821 mxr = get_field(env->vsstatus, MSTATUS_MXR); 822 } 823 824 if (first_stage == true) { 825 if (use_background) { 826 if (riscv_cpu_mxl(env) == MXL_RV32) { 827 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 828 vm = get_field(env->vsatp, SATP32_MODE); 829 } else { 830 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 831 vm = get_field(env->vsatp, SATP64_MODE); 832 } 833 } else { 834 if (riscv_cpu_mxl(env) == MXL_RV32) { 835 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 836 vm = get_field(env->satp, SATP32_MODE); 837 } else { 838 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 839 vm = get_field(env->satp, SATP64_MODE); 840 } 841 } 842 widened = 0; 843 } else { 844 if (riscv_cpu_mxl(env) == MXL_RV32) { 845 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 846 vm = get_field(env->hgatp, SATP32_MODE); 847 } else { 848 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 849 vm = get_field(env->hgatp, SATP64_MODE); 850 } 851 widened = 2; 852 } 853 /* status.SUM will be ignored if execute on background */ 854 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 855 switch (vm) { 856 case VM_1_10_SV32: 857 levels = 2; ptidxbits = 10; ptesize = 4; break; 858 case VM_1_10_SV39: 859 levels = 3; ptidxbits = 9; ptesize = 8; break; 860 case VM_1_10_SV48: 861 levels = 4; ptidxbits = 9; ptesize = 8; break; 862 case VM_1_10_SV57: 863 levels = 5; ptidxbits = 9; ptesize = 8; break; 864 case VM_1_10_MBARE: 865 *physical = addr; 866 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 867 return TRANSLATE_SUCCESS; 868 default: 869 g_assert_not_reached(); 870 } 871 872 CPUState *cs = env_cpu(env); 873 int va_bits = PGSHIFT + levels * ptidxbits + widened; 874 target_ulong mask, masked_msbs; 875 876 if (TARGET_LONG_BITS > (va_bits - 1)) { 877 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 878 } else { 879 mask = 0; 880 } 881 masked_msbs = (addr >> (va_bits - 1)) & mask; 882 883 if (masked_msbs != 0 && masked_msbs != mask) { 884 return TRANSLATE_FAIL; 885 } 886 887 int ptshift = (levels - 1) * ptidxbits; 888 int i; 889 890 #if !TCG_OVERSIZED_GUEST 891 restart: 892 #endif 893 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 894 target_ulong idx; 895 if (i == 0) { 896 idx = (addr >> (PGSHIFT + ptshift)) & 897 ((1 << (ptidxbits + widened)) - 1); 898 } else { 899 idx = (addr >> (PGSHIFT + ptshift)) & 900 ((1 << ptidxbits) - 1); 901 } 902 903 /* check that physical address of PTE is legal */ 904 hwaddr pte_addr; 905 906 if (two_stage && first_stage) { 907 int vbase_prot; 908 hwaddr vbase; 909 910 /* Do the second stage translation on the base PTE address. */ 911 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 912 base, NULL, MMU_DATA_LOAD, 913 mmu_idx, false, true, 914 is_debug); 915 916 if (vbase_ret != TRANSLATE_SUCCESS) { 917 if (fault_pte_addr) { 918 *fault_pte_addr = (base + idx * ptesize) >> 2; 919 } 920 return TRANSLATE_G_STAGE_FAIL; 921 } 922 923 pte_addr = vbase + idx * ptesize; 924 } else { 925 pte_addr = base + idx * ptesize; 926 } 927 928 int pmp_prot; 929 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 930 sizeof(target_ulong), 931 MMU_DATA_LOAD, PRV_S); 932 if (pmp_ret != TRANSLATE_SUCCESS) { 933 return TRANSLATE_PMP_FAIL; 934 } 935 936 target_ulong pte; 937 if (riscv_cpu_mxl(env) == MXL_RV32) { 938 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 939 } else { 940 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 941 } 942 943 if (res != MEMTX_OK) { 944 return TRANSLATE_FAIL; 945 } 946 947 if (riscv_cpu_sxl(env) == MXL_RV32) { 948 ppn = pte >> PTE_PPN_SHIFT; 949 } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { 950 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 951 } else { 952 ppn = pte >> PTE_PPN_SHIFT; 953 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 954 return TRANSLATE_FAIL; 955 } 956 } 957 958 if (!(pte & PTE_V)) { 959 /* Invalid PTE */ 960 return TRANSLATE_FAIL; 961 } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { 962 return TRANSLATE_FAIL; 963 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 964 /* Inner PTE, continue walking */ 965 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 966 return TRANSLATE_FAIL; 967 } 968 base = ppn << PGSHIFT; 969 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 970 /* Reserved leaf PTE flags: PTE_W */ 971 return TRANSLATE_FAIL; 972 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 973 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 974 return TRANSLATE_FAIL; 975 } else if ((pte & PTE_U) && ((mode != PRV_U) && 976 (!sum || access_type == MMU_INST_FETCH))) { 977 /* User PTE flags when not U mode and mstatus.SUM is not set, 978 or the access type is an instruction fetch */ 979 return TRANSLATE_FAIL; 980 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 981 /* Supervisor PTE flags when not S mode */ 982 return TRANSLATE_FAIL; 983 } else if (ppn & ((1ULL << ptshift) - 1)) { 984 /* Misaligned PPN */ 985 return TRANSLATE_FAIL; 986 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 987 ((pte & PTE_X) && mxr))) { 988 /* Read access check failed */ 989 return TRANSLATE_FAIL; 990 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 991 /* Write access check failed */ 992 return TRANSLATE_FAIL; 993 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 994 /* Fetch access check failed */ 995 return TRANSLATE_FAIL; 996 } else { 997 /* if necessary, set accessed and dirty bits. */ 998 target_ulong updated_pte = pte | PTE_A | 999 (access_type == MMU_DATA_STORE ? PTE_D : 0); 1000 1001 /* Page table updates need to be atomic with MTTCG enabled */ 1002 if (updated_pte != pte) { 1003 /* 1004 * - if accessed or dirty bits need updating, and the PTE is 1005 * in RAM, then we do so atomically with a compare and swap. 1006 * - if the PTE is in IO space or ROM, then it can't be updated 1007 * and we return TRANSLATE_FAIL. 1008 * - if the PTE changed by the time we went to update it, then 1009 * it is no longer valid and we must re-walk the page table. 1010 */ 1011 MemoryRegion *mr; 1012 hwaddr l = sizeof(target_ulong), addr1; 1013 mr = address_space_translate(cs->as, pte_addr, 1014 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 1015 if (memory_region_is_ram(mr)) { 1016 target_ulong *pte_pa = 1017 qemu_map_ram_ptr(mr->ram_block, addr1); 1018 #if TCG_OVERSIZED_GUEST 1019 /* MTTCG is not enabled on oversized TCG guests so 1020 * page table updates do not need to be atomic */ 1021 *pte_pa = pte = updated_pte; 1022 #else 1023 target_ulong old_pte = 1024 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1025 if (old_pte != pte) { 1026 goto restart; 1027 } else { 1028 pte = updated_pte; 1029 } 1030 #endif 1031 } else { 1032 /* misconfigured PTE in ROM (AD bits are not preset) or 1033 * PTE is in IO space and can't be updated atomically */ 1034 return TRANSLATE_FAIL; 1035 } 1036 } 1037 1038 /* for superpage mappings, make a fake leaf PTE for the TLB's 1039 benefit. */ 1040 target_ulong vpn = addr >> PGSHIFT; 1041 1042 if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { 1043 napot_bits = ctzl(ppn) + 1; 1044 if ((i != (levels - 1)) || (napot_bits != 4)) { 1045 return TRANSLATE_FAIL; 1046 } 1047 } 1048 1049 napot_mask = (1 << napot_bits) - 1; 1050 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1051 (vpn & (((target_ulong)1 << ptshift) - 1)) 1052 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1053 1054 /* set permissions on the TLB entry */ 1055 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1056 *prot |= PAGE_READ; 1057 } 1058 if ((pte & PTE_X)) { 1059 *prot |= PAGE_EXEC; 1060 } 1061 /* add write permission on stores or if the page is already dirty, 1062 so that we TLB miss on later writes to update the dirty bit */ 1063 if ((pte & PTE_W) && 1064 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1065 *prot |= PAGE_WRITE; 1066 } 1067 return TRANSLATE_SUCCESS; 1068 } 1069 } 1070 return TRANSLATE_FAIL; 1071 } 1072 1073 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1074 MMUAccessType access_type, bool pmp_violation, 1075 bool first_stage, bool two_stage, 1076 bool two_stage_indirect) 1077 { 1078 CPUState *cs = env_cpu(env); 1079 int page_fault_exceptions, vm; 1080 uint64_t stap_mode; 1081 1082 if (riscv_cpu_mxl(env) == MXL_RV32) { 1083 stap_mode = SATP32_MODE; 1084 } else { 1085 stap_mode = SATP64_MODE; 1086 } 1087 1088 if (first_stage) { 1089 vm = get_field(env->satp, stap_mode); 1090 } else { 1091 vm = get_field(env->hgatp, stap_mode); 1092 } 1093 1094 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1095 1096 switch (access_type) { 1097 case MMU_INST_FETCH: 1098 if (riscv_cpu_virt_enabled(env) && !first_stage) { 1099 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1100 } else { 1101 cs->exception_index = page_fault_exceptions ? 1102 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1103 } 1104 break; 1105 case MMU_DATA_LOAD: 1106 if (two_stage && !first_stage) { 1107 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1108 } else { 1109 cs->exception_index = page_fault_exceptions ? 1110 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1111 } 1112 break; 1113 case MMU_DATA_STORE: 1114 if (two_stage && !first_stage) { 1115 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1116 } else { 1117 cs->exception_index = page_fault_exceptions ? 1118 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1119 } 1120 break; 1121 default: 1122 g_assert_not_reached(); 1123 } 1124 env->badaddr = address; 1125 env->two_stage_lookup = two_stage; 1126 env->two_stage_indirect_lookup = two_stage_indirect; 1127 } 1128 1129 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1130 { 1131 RISCVCPU *cpu = RISCV_CPU(cs); 1132 CPURISCVState *env = &cpu->env; 1133 hwaddr phys_addr; 1134 int prot; 1135 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1136 1137 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1138 true, riscv_cpu_virt_enabled(env), true)) { 1139 return -1; 1140 } 1141 1142 if (riscv_cpu_virt_enabled(env)) { 1143 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1144 0, mmu_idx, false, true, true)) { 1145 return -1; 1146 } 1147 } 1148 1149 return phys_addr & TARGET_PAGE_MASK; 1150 } 1151 1152 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1153 vaddr addr, unsigned size, 1154 MMUAccessType access_type, 1155 int mmu_idx, MemTxAttrs attrs, 1156 MemTxResult response, uintptr_t retaddr) 1157 { 1158 RISCVCPU *cpu = RISCV_CPU(cs); 1159 CPURISCVState *env = &cpu->env; 1160 1161 if (access_type == MMU_DATA_STORE) { 1162 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1163 } else if (access_type == MMU_DATA_LOAD) { 1164 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1165 } else { 1166 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1167 } 1168 1169 env->badaddr = addr; 1170 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1171 riscv_cpu_two_stage_lookup(mmu_idx); 1172 env->two_stage_indirect_lookup = false; 1173 cpu_loop_exit_restore(cs, retaddr); 1174 } 1175 1176 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1177 MMUAccessType access_type, int mmu_idx, 1178 uintptr_t retaddr) 1179 { 1180 RISCVCPU *cpu = RISCV_CPU(cs); 1181 CPURISCVState *env = &cpu->env; 1182 switch (access_type) { 1183 case MMU_INST_FETCH: 1184 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1185 break; 1186 case MMU_DATA_LOAD: 1187 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1188 break; 1189 case MMU_DATA_STORE: 1190 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1191 break; 1192 default: 1193 g_assert_not_reached(); 1194 } 1195 env->badaddr = addr; 1196 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1197 riscv_cpu_two_stage_lookup(mmu_idx); 1198 env->two_stage_indirect_lookup = false; 1199 cpu_loop_exit_restore(cs, retaddr); 1200 } 1201 1202 1203 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1204 { 1205 enum riscv_pmu_event_idx pmu_event_type; 1206 1207 switch (access_type) { 1208 case MMU_INST_FETCH: 1209 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1210 break; 1211 case MMU_DATA_LOAD: 1212 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1213 break; 1214 case MMU_DATA_STORE: 1215 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1216 break; 1217 default: 1218 return; 1219 } 1220 1221 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1222 } 1223 1224 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1225 MMUAccessType access_type, int mmu_idx, 1226 bool probe, uintptr_t retaddr) 1227 { 1228 RISCVCPU *cpu = RISCV_CPU(cs); 1229 CPURISCVState *env = &cpu->env; 1230 vaddr im_address; 1231 hwaddr pa = 0; 1232 int prot, prot2, prot_pmp; 1233 bool pmp_violation = false; 1234 bool first_stage_error = true; 1235 bool two_stage_lookup = false; 1236 bool two_stage_indirect_error = false; 1237 int ret = TRANSLATE_FAIL; 1238 int mode = mmu_idx; 1239 /* default TLB page size */ 1240 target_ulong tlb_size = TARGET_PAGE_SIZE; 1241 1242 env->guest_phys_fault_addr = 0; 1243 1244 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1245 __func__, address, access_type, mmu_idx); 1246 1247 /* MPRV does not affect the virtual-machine load/store 1248 instructions, HLV, HLVX, and HSV. */ 1249 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1250 mode = get_field(env->hstatus, HSTATUS_SPVP); 1251 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1252 get_field(env->mstatus, MSTATUS_MPRV)) { 1253 mode = get_field(env->mstatus, MSTATUS_MPP); 1254 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1255 two_stage_lookup = true; 1256 } 1257 } 1258 1259 if (riscv_cpu_virt_enabled(env) || 1260 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1261 access_type != MMU_INST_FETCH)) { 1262 /* Two stage lookup */ 1263 ret = get_physical_address(env, &pa, &prot, address, 1264 &env->guest_phys_fault_addr, access_type, 1265 mmu_idx, true, true, false); 1266 1267 /* 1268 * A G-stage exception may be triggered during two state lookup. 1269 * And the env->guest_phys_fault_addr has already been set in 1270 * get_physical_address(). 1271 */ 1272 if (ret == TRANSLATE_G_STAGE_FAIL) { 1273 first_stage_error = false; 1274 two_stage_indirect_error = true; 1275 access_type = MMU_DATA_LOAD; 1276 } 1277 1278 qemu_log_mask(CPU_LOG_MMU, 1279 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1280 TARGET_FMT_plx " prot %d\n", 1281 __func__, address, ret, pa, prot); 1282 1283 if (ret == TRANSLATE_SUCCESS) { 1284 /* Second stage lookup */ 1285 im_address = pa; 1286 1287 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1288 access_type, mmu_idx, false, true, 1289 false); 1290 1291 qemu_log_mask(CPU_LOG_MMU, 1292 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 1293 TARGET_FMT_plx " prot %d\n", 1294 __func__, im_address, ret, pa, prot2); 1295 1296 prot &= prot2; 1297 1298 if (ret == TRANSLATE_SUCCESS) { 1299 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1300 size, access_type, mode); 1301 1302 qemu_log_mask(CPU_LOG_MMU, 1303 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1304 " %d tlb_size " TARGET_FMT_lu "\n", 1305 __func__, pa, ret, prot_pmp, tlb_size); 1306 1307 prot &= prot_pmp; 1308 } 1309 1310 if (ret != TRANSLATE_SUCCESS) { 1311 /* 1312 * Guest physical address translation failed, this is a HS 1313 * level exception 1314 */ 1315 first_stage_error = false; 1316 env->guest_phys_fault_addr = (im_address | 1317 (address & 1318 (TARGET_PAGE_SIZE - 1))) >> 2; 1319 } 1320 } 1321 } else { 1322 pmu_tlb_fill_incr_ctr(cpu, access_type); 1323 /* Single stage lookup */ 1324 ret = get_physical_address(env, &pa, &prot, address, NULL, 1325 access_type, mmu_idx, true, false, false); 1326 1327 qemu_log_mask(CPU_LOG_MMU, 1328 "%s address=%" VADDR_PRIx " ret %d physical " 1329 TARGET_FMT_plx " prot %d\n", 1330 __func__, address, ret, pa, prot); 1331 1332 if (ret == TRANSLATE_SUCCESS) { 1333 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1334 size, access_type, mode); 1335 1336 qemu_log_mask(CPU_LOG_MMU, 1337 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1338 " %d tlb_size " TARGET_FMT_lu "\n", 1339 __func__, pa, ret, prot_pmp, tlb_size); 1340 1341 prot &= prot_pmp; 1342 } 1343 } 1344 1345 if (ret == TRANSLATE_PMP_FAIL) { 1346 pmp_violation = true; 1347 } 1348 1349 if (ret == TRANSLATE_SUCCESS) { 1350 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1351 prot, mmu_idx, tlb_size); 1352 return true; 1353 } else if (probe) { 1354 return false; 1355 } else { 1356 raise_mmu_exception(env, address, access_type, pmp_violation, 1357 first_stage_error, 1358 riscv_cpu_virt_enabled(env) || 1359 riscv_cpu_two_stage_lookup(mmu_idx), 1360 two_stage_indirect_error); 1361 cpu_loop_exit_restore(cs, retaddr); 1362 } 1363 1364 return true; 1365 } 1366 1367 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1368 target_ulong insn, 1369 target_ulong taddr) 1370 { 1371 target_ulong xinsn = 0; 1372 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1373 1374 /* 1375 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1376 * be uncompressed. The Quadrant 1 of RVC instruction space need 1377 * not be transformed because these instructions won't generate 1378 * any load/store trap. 1379 */ 1380 1381 if ((insn & 0x3) != 0x3) { 1382 /* Transform 16bit instruction into 32bit instruction */ 1383 switch (GET_C_OP(insn)) { 1384 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1385 switch (GET_C_FUNC(insn)) { 1386 case OPC_RISC_C_FUNC_FLD_LQ: 1387 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1388 xinsn = OPC_RISC_FLD; 1389 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1390 access_rs1 = GET_C_RS1S(insn); 1391 access_imm = GET_C_LD_IMM(insn); 1392 access_size = 8; 1393 } 1394 break; 1395 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1396 xinsn = OPC_RISC_LW; 1397 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1398 access_rs1 = GET_C_RS1S(insn); 1399 access_imm = GET_C_LW_IMM(insn); 1400 access_size = 4; 1401 break; 1402 case OPC_RISC_C_FUNC_FLW_LD: 1403 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1404 xinsn = OPC_RISC_FLW; 1405 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1406 access_rs1 = GET_C_RS1S(insn); 1407 access_imm = GET_C_LW_IMM(insn); 1408 access_size = 4; 1409 } else { /* C.LD (RV64/RV128) */ 1410 xinsn = OPC_RISC_LD; 1411 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1412 access_rs1 = GET_C_RS1S(insn); 1413 access_imm = GET_C_LD_IMM(insn); 1414 access_size = 8; 1415 } 1416 break; 1417 case OPC_RISC_C_FUNC_FSD_SQ: 1418 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1419 xinsn = OPC_RISC_FSD; 1420 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1421 access_rs1 = GET_C_RS1S(insn); 1422 access_imm = GET_C_SD_IMM(insn); 1423 access_size = 8; 1424 } 1425 break; 1426 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1427 xinsn = OPC_RISC_SW; 1428 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1429 access_rs1 = GET_C_RS1S(insn); 1430 access_imm = GET_C_SW_IMM(insn); 1431 access_size = 4; 1432 break; 1433 case OPC_RISC_C_FUNC_FSW_SD: 1434 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1435 xinsn = OPC_RISC_FSW; 1436 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1437 access_rs1 = GET_C_RS1S(insn); 1438 access_imm = GET_C_SW_IMM(insn); 1439 access_size = 4; 1440 } else { /* C.SD (RV64/RV128) */ 1441 xinsn = OPC_RISC_SD; 1442 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1443 access_rs1 = GET_C_RS1S(insn); 1444 access_imm = GET_C_SD_IMM(insn); 1445 access_size = 8; 1446 } 1447 break; 1448 default: 1449 break; 1450 } 1451 break; 1452 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1453 switch (GET_C_FUNC(insn)) { 1454 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1455 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1456 xinsn = OPC_RISC_FLD; 1457 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1458 access_rs1 = 2; 1459 access_imm = GET_C_LDSP_IMM(insn); 1460 access_size = 8; 1461 } 1462 break; 1463 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1464 xinsn = OPC_RISC_LW; 1465 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1466 access_rs1 = 2; 1467 access_imm = GET_C_LWSP_IMM(insn); 1468 access_size = 4; 1469 break; 1470 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1471 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1472 xinsn = OPC_RISC_FLW; 1473 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1474 access_rs1 = 2; 1475 access_imm = GET_C_LWSP_IMM(insn); 1476 access_size = 4; 1477 } else { /* C.LDSP (RV64/RV128) */ 1478 xinsn = OPC_RISC_LD; 1479 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1480 access_rs1 = 2; 1481 access_imm = GET_C_LDSP_IMM(insn); 1482 access_size = 8; 1483 } 1484 break; 1485 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1486 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1487 xinsn = OPC_RISC_FSD; 1488 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1489 access_rs1 = 2; 1490 access_imm = GET_C_SDSP_IMM(insn); 1491 access_size = 8; 1492 } 1493 break; 1494 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1495 xinsn = OPC_RISC_SW; 1496 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1497 access_rs1 = 2; 1498 access_imm = GET_C_SWSP_IMM(insn); 1499 access_size = 4; 1500 break; 1501 case 7: 1502 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1503 xinsn = OPC_RISC_FSW; 1504 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1505 access_rs1 = 2; 1506 access_imm = GET_C_SWSP_IMM(insn); 1507 access_size = 4; 1508 } else { /* C.SDSP (RV64/RV128) */ 1509 xinsn = OPC_RISC_SD; 1510 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1511 access_rs1 = 2; 1512 access_imm = GET_C_SDSP_IMM(insn); 1513 access_size = 8; 1514 } 1515 break; 1516 default: 1517 break; 1518 } 1519 break; 1520 default: 1521 break; 1522 } 1523 1524 /* 1525 * Clear Bit1 of transformed instruction to indicate that 1526 * original insruction was a 16bit instruction 1527 */ 1528 xinsn &= ~((target_ulong)0x2); 1529 } else { 1530 /* Transform 32bit (or wider) instructions */ 1531 switch (MASK_OP_MAJOR(insn)) { 1532 case OPC_RISC_ATOMIC: 1533 xinsn = insn; 1534 access_rs1 = GET_RS1(insn); 1535 access_size = 1 << GET_FUNCT3(insn); 1536 break; 1537 case OPC_RISC_LOAD: 1538 case OPC_RISC_FP_LOAD: 1539 xinsn = SET_I_IMM(insn, 0); 1540 access_rs1 = GET_RS1(insn); 1541 access_imm = GET_IMM(insn); 1542 access_size = 1 << GET_FUNCT3(insn); 1543 break; 1544 case OPC_RISC_STORE: 1545 case OPC_RISC_FP_STORE: 1546 xinsn = SET_S_IMM(insn, 0); 1547 access_rs1 = GET_RS1(insn); 1548 access_imm = GET_STORE_IMM(insn); 1549 access_size = 1 << GET_FUNCT3(insn); 1550 break; 1551 case OPC_RISC_SYSTEM: 1552 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1553 xinsn = insn; 1554 access_rs1 = GET_RS1(insn); 1555 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1556 access_size = 1 << access_size; 1557 } 1558 break; 1559 default: 1560 break; 1561 } 1562 } 1563 1564 if (access_size) { 1565 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1566 (access_size - 1)); 1567 } 1568 1569 return xinsn; 1570 } 1571 #endif /* !CONFIG_USER_ONLY */ 1572 1573 /* 1574 * Handle Traps 1575 * 1576 * Adapted from Spike's processor_t::take_trap. 1577 * 1578 */ 1579 void riscv_cpu_do_interrupt(CPUState *cs) 1580 { 1581 #if !defined(CONFIG_USER_ONLY) 1582 1583 RISCVCPU *cpu = RISCV_CPU(cs); 1584 CPURISCVState *env = &cpu->env; 1585 bool write_gva = false; 1586 uint64_t s; 1587 1588 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1589 * so we mask off the MSB and separate into trap type and cause. 1590 */ 1591 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1592 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1593 uint64_t deleg = async ? env->mideleg : env->medeleg; 1594 target_ulong tval = 0; 1595 target_ulong tinst = 0; 1596 target_ulong htval = 0; 1597 target_ulong mtval2 = 0; 1598 1599 if (cause == RISCV_EXCP_SEMIHOST) { 1600 do_common_semihosting(cs); 1601 env->pc += 4; 1602 return; 1603 } 1604 1605 if (!async) { 1606 /* set tval to badaddr for traps with address information */ 1607 switch (cause) { 1608 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1609 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1610 case RISCV_EXCP_LOAD_ADDR_MIS: 1611 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1612 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1613 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1614 case RISCV_EXCP_LOAD_PAGE_FAULT: 1615 case RISCV_EXCP_STORE_PAGE_FAULT: 1616 write_gva = env->two_stage_lookup; 1617 tval = env->badaddr; 1618 if (env->two_stage_indirect_lookup) { 1619 /* 1620 * special pseudoinstruction for G-stage fault taken while 1621 * doing VS-stage page table walk. 1622 */ 1623 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1624 } else { 1625 /* 1626 * The "Addr. Offset" field in transformed instruction is 1627 * non-zero only for misaligned access. 1628 */ 1629 tinst = riscv_transformed_insn(env, env->bins, tval); 1630 } 1631 break; 1632 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1633 case RISCV_EXCP_INST_ADDR_MIS: 1634 case RISCV_EXCP_INST_ACCESS_FAULT: 1635 case RISCV_EXCP_INST_PAGE_FAULT: 1636 write_gva = env->two_stage_lookup; 1637 tval = env->badaddr; 1638 if (env->two_stage_indirect_lookup) { 1639 /* 1640 * special pseudoinstruction for G-stage fault taken while 1641 * doing VS-stage page table walk. 1642 */ 1643 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1644 } 1645 break; 1646 case RISCV_EXCP_ILLEGAL_INST: 1647 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1648 tval = env->bins; 1649 break; 1650 default: 1651 break; 1652 } 1653 /* ecall is dispatched as one cause so translate based on mode */ 1654 if (cause == RISCV_EXCP_U_ECALL) { 1655 assert(env->priv <= 3); 1656 1657 if (env->priv == PRV_M) { 1658 cause = RISCV_EXCP_M_ECALL; 1659 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1660 cause = RISCV_EXCP_VS_ECALL; 1661 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1662 cause = RISCV_EXCP_S_ECALL; 1663 } else if (env->priv == PRV_U) { 1664 cause = RISCV_EXCP_U_ECALL; 1665 } 1666 } 1667 } 1668 1669 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1670 riscv_cpu_get_trap_name(cause, async)); 1671 1672 qemu_log_mask(CPU_LOG_INT, 1673 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1674 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1675 __func__, env->mhartid, async, cause, env->pc, tval, 1676 riscv_cpu_get_trap_name(cause, async)); 1677 1678 if (env->priv <= PRV_S && 1679 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1680 /* handle the trap in S-mode */ 1681 if (riscv_has_ext(env, RVH)) { 1682 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1683 1684 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1685 /* Trap to VS mode */ 1686 /* 1687 * See if we need to adjust cause. Yes if its VS mode interrupt 1688 * no if hypervisor has delegated one of hs mode's interrupt 1689 */ 1690 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1691 cause == IRQ_VS_EXT) { 1692 cause = cause - 1; 1693 } 1694 write_gva = false; 1695 } else if (riscv_cpu_virt_enabled(env)) { 1696 /* Trap into HS mode, from virt */ 1697 riscv_cpu_swap_hypervisor_regs(env); 1698 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1699 env->priv); 1700 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1701 riscv_cpu_virt_enabled(env)); 1702 1703 1704 htval = env->guest_phys_fault_addr; 1705 1706 riscv_cpu_set_virt_enabled(env, 0); 1707 } else { 1708 /* Trap into HS mode */ 1709 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1710 htval = env->guest_phys_fault_addr; 1711 } 1712 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1713 } 1714 1715 s = env->mstatus; 1716 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1717 s = set_field(s, MSTATUS_SPP, env->priv); 1718 s = set_field(s, MSTATUS_SIE, 0); 1719 env->mstatus = s; 1720 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1721 env->sepc = env->pc; 1722 env->stval = tval; 1723 env->htval = htval; 1724 env->htinst = tinst; 1725 env->pc = (env->stvec >> 2 << 2) + 1726 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1727 riscv_cpu_set_mode(env, PRV_S); 1728 } else { 1729 /* handle the trap in M-mode */ 1730 if (riscv_has_ext(env, RVH)) { 1731 if (riscv_cpu_virt_enabled(env)) { 1732 riscv_cpu_swap_hypervisor_regs(env); 1733 } 1734 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1735 riscv_cpu_virt_enabled(env)); 1736 if (riscv_cpu_virt_enabled(env) && tval) { 1737 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1738 } 1739 1740 mtval2 = env->guest_phys_fault_addr; 1741 1742 /* Trapping to M mode, virt is disabled */ 1743 riscv_cpu_set_virt_enabled(env, 0); 1744 } 1745 1746 s = env->mstatus; 1747 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1748 s = set_field(s, MSTATUS_MPP, env->priv); 1749 s = set_field(s, MSTATUS_MIE, 0); 1750 env->mstatus = s; 1751 env->mcause = cause | ~(((target_ulong)-1) >> async); 1752 env->mepc = env->pc; 1753 env->mtval = tval; 1754 env->mtval2 = mtval2; 1755 env->mtinst = tinst; 1756 env->pc = (env->mtvec >> 2 << 2) + 1757 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1758 riscv_cpu_set_mode(env, PRV_M); 1759 } 1760 1761 /* NOTE: it is not necessary to yield load reservations here. It is only 1762 * necessary for an SC from "another hart" to cause a load reservation 1763 * to be yielded. Refer to the memory consistency model section of the 1764 * RISC-V ISA Specification. 1765 */ 1766 1767 env->two_stage_lookup = false; 1768 env->two_stage_indirect_lookup = false; 1769 #endif 1770 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1771 } 1772