1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "exec/exec-all.h" 26 #include "instmap.h" 27 #include "tcg/tcg-op.h" 28 #include "trace.h" 29 #include "semihosting/common-semi.h" 30 #include "sysemu/cpu-timers.h" 31 #include "cpu_bits.h" 32 #include "debug.h" 33 34 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return 0; 38 #else 39 return env->priv; 40 #endif 41 } 42 43 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 44 target_ulong *cs_base, uint32_t *pflags) 45 { 46 CPUState *cs = env_cpu(env); 47 RISCVCPU *cpu = RISCV_CPU(cs); 48 49 uint32_t flags = 0; 50 51 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 52 *cs_base = 0; 53 54 if (cpu->cfg.ext_zve32f) { 55 /* 56 * If env->vl equals to VLMAX, we can use generic vector operation 57 * expanders (GVEC) to accerlate the vector operations. 58 * However, as LMUL could be a fractional number. The maximum 59 * vector size can be operated might be less than 8 bytes, 60 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 61 * only when maxsz >= 8 bytes. 62 */ 63 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 64 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 65 uint32_t maxsz = vlmax << sew; 66 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 67 (maxsz >= 8); 68 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 69 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 70 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 71 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 72 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 73 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 74 FIELD_EX64(env->vtype, VTYPE, VTA)); 75 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 76 FIELD_EX64(env->vtype, VTYPE, VMA)); 77 } else { 78 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 79 } 80 81 #ifdef CONFIG_USER_ONLY 82 flags |= TB_FLAGS_MSTATUS_FS; 83 flags |= TB_FLAGS_MSTATUS_VS; 84 #else 85 flags |= cpu_mmu_index(env, 0); 86 if (riscv_cpu_fp_enabled(env)) { 87 flags |= env->mstatus & MSTATUS_FS; 88 } 89 90 if (riscv_cpu_vector_enabled(env)) { 91 flags |= env->mstatus & MSTATUS_VS; 92 } 93 94 if (riscv_has_ext(env, RVH)) { 95 if (env->priv == PRV_M || 96 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 97 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 98 get_field(env->hstatus, HSTATUS_HU))) { 99 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 100 } 101 102 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 103 get_field(env->mstatus_hs, MSTATUS_FS)); 104 105 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 106 get_field(env->mstatus_hs, MSTATUS_VS)); 107 } 108 if (cpu->cfg.debug && !icount_enabled()) { 109 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 110 } 111 #endif 112 113 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 114 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 115 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 116 } 117 if (env->cur_pmbase != 0) { 118 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 119 } 120 121 *pflags = flags; 122 } 123 124 void riscv_cpu_update_mask(CPURISCVState *env) 125 { 126 target_ulong mask = -1, base = 0; 127 /* 128 * TODO: Current RVJ spec does not specify 129 * how the extension interacts with XLEN. 130 */ 131 #ifndef CONFIG_USER_ONLY 132 if (riscv_has_ext(env, RVJ)) { 133 switch (env->priv) { 134 case PRV_M: 135 if (env->mmte & M_PM_ENABLE) { 136 mask = env->mpmmask; 137 base = env->mpmbase; 138 } 139 break; 140 case PRV_S: 141 if (env->mmte & S_PM_ENABLE) { 142 mask = env->spmmask; 143 base = env->spmbase; 144 } 145 break; 146 case PRV_U: 147 if (env->mmte & U_PM_ENABLE) { 148 mask = env->upmmask; 149 base = env->upmbase; 150 } 151 break; 152 default: 153 g_assert_not_reached(); 154 } 155 } 156 #endif 157 if (env->xl == MXL_RV32) { 158 env->cur_pmmask = mask & UINT32_MAX; 159 env->cur_pmbase = base & UINT32_MAX; 160 } else { 161 env->cur_pmmask = mask; 162 env->cur_pmbase = base; 163 } 164 } 165 166 #ifndef CONFIG_USER_ONLY 167 168 /* 169 * The HS-mode is allowed to configure priority only for the 170 * following VS-mode local interrupts: 171 * 172 * 0 (Reserved interrupt, reads as zero) 173 * 1 Supervisor software interrupt 174 * 4 (Reserved interrupt, reads as zero) 175 * 5 Supervisor timer interrupt 176 * 8 (Reserved interrupt, reads as zero) 177 * 13 (Reserved interrupt) 178 * 14 " 179 * 15 " 180 * 16 " 181 * 17 " 182 * 18 " 183 * 19 " 184 * 20 " 185 * 21 " 186 * 22 " 187 * 23 " 188 */ 189 190 static const int hviprio_index2irq[] = { 191 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 192 static const int hviprio_index2rdzero[] = { 193 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 194 195 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 196 { 197 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 198 return -EINVAL; 199 } 200 201 if (out_irq) { 202 *out_irq = hviprio_index2irq[index]; 203 } 204 205 if (out_rdzero) { 206 *out_rdzero = hviprio_index2rdzero[index]; 207 } 208 209 return 0; 210 } 211 212 /* 213 * Default priorities of local interrupts are defined in the 214 * RISC-V Advanced Interrupt Architecture specification. 215 * 216 * ---------------------------------------------------------------- 217 * Default | 218 * Priority | Major Interrupt Numbers 219 * ---------------------------------------------------------------- 220 * Highest | 47, 23, 46, 45, 22, 44, 221 * | 43, 21, 42, 41, 20, 40 222 * | 223 * | 11 (0b), 3 (03), 7 (07) 224 * | 9 (09), 1 (01), 5 (05) 225 * | 12 (0c) 226 * | 10 (0a), 2 (02), 6 (06) 227 * | 228 * | 39, 19, 38, 37, 18, 36, 229 * Lowest | 35, 17, 34, 33, 16, 32 230 * ---------------------------------------------------------------- 231 */ 232 static const uint8_t default_iprio[64] = { 233 /* Custom interrupts 48 to 63 */ 234 [63] = IPRIO_MMAXIPRIO, 235 [62] = IPRIO_MMAXIPRIO, 236 [61] = IPRIO_MMAXIPRIO, 237 [60] = IPRIO_MMAXIPRIO, 238 [59] = IPRIO_MMAXIPRIO, 239 [58] = IPRIO_MMAXIPRIO, 240 [57] = IPRIO_MMAXIPRIO, 241 [56] = IPRIO_MMAXIPRIO, 242 [55] = IPRIO_MMAXIPRIO, 243 [54] = IPRIO_MMAXIPRIO, 244 [53] = IPRIO_MMAXIPRIO, 245 [52] = IPRIO_MMAXIPRIO, 246 [51] = IPRIO_MMAXIPRIO, 247 [50] = IPRIO_MMAXIPRIO, 248 [49] = IPRIO_MMAXIPRIO, 249 [48] = IPRIO_MMAXIPRIO, 250 251 /* Custom interrupts 24 to 31 */ 252 [31] = IPRIO_MMAXIPRIO, 253 [30] = IPRIO_MMAXIPRIO, 254 [29] = IPRIO_MMAXIPRIO, 255 [28] = IPRIO_MMAXIPRIO, 256 [27] = IPRIO_MMAXIPRIO, 257 [26] = IPRIO_MMAXIPRIO, 258 [25] = IPRIO_MMAXIPRIO, 259 [24] = IPRIO_MMAXIPRIO, 260 261 [47] = IPRIO_DEFAULT_UPPER, 262 [23] = IPRIO_DEFAULT_UPPER + 1, 263 [46] = IPRIO_DEFAULT_UPPER + 2, 264 [45] = IPRIO_DEFAULT_UPPER + 3, 265 [22] = IPRIO_DEFAULT_UPPER + 4, 266 [44] = IPRIO_DEFAULT_UPPER + 5, 267 268 [43] = IPRIO_DEFAULT_UPPER + 6, 269 [21] = IPRIO_DEFAULT_UPPER + 7, 270 [42] = IPRIO_DEFAULT_UPPER + 8, 271 [41] = IPRIO_DEFAULT_UPPER + 9, 272 [20] = IPRIO_DEFAULT_UPPER + 10, 273 [40] = IPRIO_DEFAULT_UPPER + 11, 274 275 [11] = IPRIO_DEFAULT_M, 276 [3] = IPRIO_DEFAULT_M + 1, 277 [7] = IPRIO_DEFAULT_M + 2, 278 279 [9] = IPRIO_DEFAULT_S, 280 [1] = IPRIO_DEFAULT_S + 1, 281 [5] = IPRIO_DEFAULT_S + 2, 282 283 [12] = IPRIO_DEFAULT_SGEXT, 284 285 [10] = IPRIO_DEFAULT_VS, 286 [2] = IPRIO_DEFAULT_VS + 1, 287 [6] = IPRIO_DEFAULT_VS + 2, 288 289 [39] = IPRIO_DEFAULT_LOWER, 290 [19] = IPRIO_DEFAULT_LOWER + 1, 291 [38] = IPRIO_DEFAULT_LOWER + 2, 292 [37] = IPRIO_DEFAULT_LOWER + 3, 293 [18] = IPRIO_DEFAULT_LOWER + 4, 294 [36] = IPRIO_DEFAULT_LOWER + 5, 295 296 [35] = IPRIO_DEFAULT_LOWER + 6, 297 [17] = IPRIO_DEFAULT_LOWER + 7, 298 [34] = IPRIO_DEFAULT_LOWER + 8, 299 [33] = IPRIO_DEFAULT_LOWER + 9, 300 [16] = IPRIO_DEFAULT_LOWER + 10, 301 [32] = IPRIO_DEFAULT_LOWER + 11, 302 }; 303 304 uint8_t riscv_cpu_default_priority(int irq) 305 { 306 if (irq < 0 || irq > 63) { 307 return IPRIO_MMAXIPRIO; 308 } 309 310 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 311 }; 312 313 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 314 int extirq, unsigned int extirq_def_prio, 315 uint64_t pending, uint8_t *iprio) 316 { 317 int irq, best_irq = RISCV_EXCP_NONE; 318 unsigned int prio, best_prio = UINT_MAX; 319 320 if (!pending) { 321 return RISCV_EXCP_NONE; 322 } 323 324 irq = ctz64(pending); 325 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 326 riscv_cpu_cfg(env)->ext_ssaia)) { 327 return irq; 328 } 329 330 pending = pending >> irq; 331 while (pending) { 332 prio = iprio[irq]; 333 if (!prio) { 334 if (irq == extirq) { 335 prio = extirq_def_prio; 336 } else { 337 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 338 1 : IPRIO_MMAXIPRIO; 339 } 340 } 341 if ((pending & 0x1) && (prio <= best_prio)) { 342 best_irq = irq; 343 best_prio = prio; 344 } 345 irq++; 346 pending = pending >> 1; 347 } 348 349 return best_irq; 350 } 351 352 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 353 { 354 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 355 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 356 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 357 358 return (env->mip | vsgein | vstip) & env->mie; 359 } 360 361 int riscv_cpu_mirq_pending(CPURISCVState *env) 362 { 363 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 364 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 365 366 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 367 irqs, env->miprio); 368 } 369 370 int riscv_cpu_sirq_pending(CPURISCVState *env) 371 { 372 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 373 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 374 375 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 376 irqs, env->siprio); 377 } 378 379 int riscv_cpu_vsirq_pending(CPURISCVState *env) 380 { 381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 382 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 383 384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 385 irqs >> 1, env->hviprio); 386 } 387 388 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 389 { 390 int virq; 391 uint64_t irqs, pending, mie, hsie, vsie; 392 393 /* Determine interrupt enable state of all privilege modes */ 394 if (riscv_cpu_virt_enabled(env)) { 395 mie = 1; 396 hsie = 1; 397 vsie = (env->priv < PRV_S) || 398 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 399 } else { 400 mie = (env->priv < PRV_M) || 401 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 402 hsie = (env->priv < PRV_S) || 403 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 404 vsie = 0; 405 } 406 407 /* Determine all pending interrupts */ 408 pending = riscv_cpu_all_pending(env); 409 410 /* Check M-mode interrupts */ 411 irqs = pending & ~env->mideleg & -mie; 412 if (irqs) { 413 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 414 irqs, env->miprio); 415 } 416 417 /* Check HS-mode interrupts */ 418 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 419 if (irqs) { 420 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 421 irqs, env->siprio); 422 } 423 424 /* Check VS-mode interrupts */ 425 irqs = pending & env->mideleg & env->hideleg & -vsie; 426 if (irqs) { 427 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 428 irqs >> 1, env->hviprio); 429 return (virq <= 0) ? virq : virq + 1; 430 } 431 432 /* Indicate no pending interrupt */ 433 return RISCV_EXCP_NONE; 434 } 435 436 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 437 { 438 if (interrupt_request & CPU_INTERRUPT_HARD) { 439 RISCVCPU *cpu = RISCV_CPU(cs); 440 CPURISCVState *env = &cpu->env; 441 int interruptno = riscv_cpu_local_irq_pending(env); 442 if (interruptno >= 0) { 443 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 444 riscv_cpu_do_interrupt(cs); 445 return true; 446 } 447 } 448 return false; 449 } 450 451 /* Return true is floating point support is currently enabled */ 452 bool riscv_cpu_fp_enabled(CPURISCVState *env) 453 { 454 if (env->mstatus & MSTATUS_FS) { 455 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 456 return false; 457 } 458 return true; 459 } 460 461 return false; 462 } 463 464 /* Return true is vector support is currently enabled */ 465 bool riscv_cpu_vector_enabled(CPURISCVState *env) 466 { 467 if (env->mstatus & MSTATUS_VS) { 468 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 469 return false; 470 } 471 return true; 472 } 473 474 return false; 475 } 476 477 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 478 { 479 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 480 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 481 MSTATUS64_UXL | MSTATUS_VS; 482 483 if (riscv_has_ext(env, RVF)) { 484 mstatus_mask |= MSTATUS_FS; 485 } 486 bool current_virt = riscv_cpu_virt_enabled(env); 487 488 g_assert(riscv_has_ext(env, RVH)); 489 490 if (current_virt) { 491 /* Current V=1 and we are about to change to V=0 */ 492 env->vsstatus = env->mstatus & mstatus_mask; 493 env->mstatus &= ~mstatus_mask; 494 env->mstatus |= env->mstatus_hs; 495 496 env->vstvec = env->stvec; 497 env->stvec = env->stvec_hs; 498 499 env->vsscratch = env->sscratch; 500 env->sscratch = env->sscratch_hs; 501 502 env->vsepc = env->sepc; 503 env->sepc = env->sepc_hs; 504 505 env->vscause = env->scause; 506 env->scause = env->scause_hs; 507 508 env->vstval = env->stval; 509 env->stval = env->stval_hs; 510 511 env->vsatp = env->satp; 512 env->satp = env->satp_hs; 513 } else { 514 /* Current V=0 and we are about to change to V=1 */ 515 env->mstatus_hs = env->mstatus & mstatus_mask; 516 env->mstatus &= ~mstatus_mask; 517 env->mstatus |= env->vsstatus; 518 519 env->stvec_hs = env->stvec; 520 env->stvec = env->vstvec; 521 522 env->sscratch_hs = env->sscratch; 523 env->sscratch = env->vsscratch; 524 525 env->sepc_hs = env->sepc; 526 env->sepc = env->vsepc; 527 528 env->scause_hs = env->scause; 529 env->scause = env->vscause; 530 531 env->stval_hs = env->stval; 532 env->stval = env->vstval; 533 534 env->satp_hs = env->satp; 535 env->satp = env->vsatp; 536 } 537 } 538 539 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 540 { 541 if (!riscv_has_ext(env, RVH)) { 542 return 0; 543 } 544 545 return env->geilen; 546 } 547 548 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 549 { 550 if (!riscv_has_ext(env, RVH)) { 551 return; 552 } 553 554 if (geilen > (TARGET_LONG_BITS - 1)) { 555 return; 556 } 557 558 env->geilen = geilen; 559 } 560 561 bool riscv_cpu_virt_enabled(CPURISCVState *env) 562 { 563 return get_field(env->virt, VIRT_ONOFF); 564 } 565 566 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 567 { 568 if (!riscv_has_ext(env, RVH)) { 569 return; 570 } 571 572 /* Flush the TLB on all virt mode changes. */ 573 if (get_field(env->virt, VIRT_ONOFF) != enable) { 574 tlb_flush(env_cpu(env)); 575 } 576 577 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 578 579 if (enable) { 580 /* 581 * The guest external interrupts from an interrupt controller are 582 * delivered only when the Guest/VM is running (i.e. V=1). This means 583 * any guest external interrupt which is triggered while the Guest/VM 584 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 585 * with sluggish response to serial console input and other I/O events. 586 * 587 * To solve this, we check and inject interrupt after setting V=1. 588 */ 589 riscv_cpu_update_mip(env, 0, 0); 590 } 591 } 592 593 bool riscv_cpu_two_stage_lookup(int mmu_idx) 594 { 595 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 596 } 597 598 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 599 { 600 CPURISCVState *env = &cpu->env; 601 if (env->miclaim & interrupts) { 602 return -1; 603 } else { 604 env->miclaim |= interrupts; 605 return 0; 606 } 607 } 608 609 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 610 uint64_t value) 611 { 612 CPUState *cs = env_cpu(env); 613 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 614 615 if (riscv_cpu_virt_enabled(env)) { 616 gein = get_field(env->hstatus, HSTATUS_VGEIN); 617 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 618 } 619 620 vstip = env->vstime_irq ? MIP_VSTIP : 0; 621 622 QEMU_IOTHREAD_LOCK_GUARD(); 623 624 env->mip = (env->mip & ~mask) | (value & mask); 625 626 if (env->mip | vsgein | vstip) { 627 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 628 } else { 629 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 630 } 631 632 return old; 633 } 634 635 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 636 void *arg) 637 { 638 env->rdtime_fn = fn; 639 env->rdtime_fn_arg = arg; 640 } 641 642 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 643 int (*rmw_fn)(void *arg, 644 target_ulong reg, 645 target_ulong *val, 646 target_ulong new_val, 647 target_ulong write_mask), 648 void *rmw_fn_arg) 649 { 650 if (priv <= PRV_M) { 651 env->aia_ireg_rmw_fn[priv] = rmw_fn; 652 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 653 } 654 } 655 656 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 657 { 658 if (newpriv > PRV_M) { 659 g_assert_not_reached(); 660 } 661 if (newpriv == PRV_H) { 662 newpriv = PRV_U; 663 } 664 if (icount_enabled() && newpriv != env->priv) { 665 riscv_itrigger_update_priv(env); 666 } 667 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 668 env->priv = newpriv; 669 env->xl = cpu_recompute_xl(env); 670 riscv_cpu_update_mask(env); 671 672 /* 673 * Clear the load reservation - otherwise a reservation placed in one 674 * context/process can be used by another, resulting in an SC succeeding 675 * incorrectly. Version 2.2 of the ISA specification explicitly requires 676 * this behaviour, while later revisions say that the kernel "should" use 677 * an SC instruction to force the yielding of a load reservation on a 678 * preemptive context switch. As a result, do both. 679 */ 680 env->load_res = -1; 681 } 682 683 /* 684 * get_physical_address_pmp - check PMP permission for this physical address 685 * 686 * Match the PMP region and check permission for this physical address and it's 687 * TLB page. Returns 0 if the permission checking was successful 688 * 689 * @env: CPURISCVState 690 * @prot: The returned protection attributes 691 * @tlb_size: TLB page size containing addr. It could be modified after PMP 692 * permission checking. NULL if not set TLB page for addr. 693 * @addr: The physical address to be checked permission 694 * @access_type: The type of MMU access 695 * @mode: Indicates current privilege level. 696 */ 697 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 698 target_ulong *tlb_size, hwaddr addr, 699 int size, MMUAccessType access_type, 700 int mode) 701 { 702 pmp_priv_t pmp_priv; 703 int pmp_index = -1; 704 705 if (!riscv_cpu_cfg(env)->pmp) { 706 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 707 return TRANSLATE_SUCCESS; 708 } 709 710 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 711 &pmp_priv, mode); 712 if (pmp_index < 0) { 713 *prot = 0; 714 return TRANSLATE_PMP_FAIL; 715 } 716 717 *prot = pmp_priv_to_page_prot(pmp_priv); 718 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 719 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 720 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 721 722 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 723 } 724 725 return TRANSLATE_SUCCESS; 726 } 727 728 /* get_physical_address - get the physical address for this virtual address 729 * 730 * Do a page table walk to obtain the physical address corresponding to a 731 * virtual address. Returns 0 if the translation was successful 732 * 733 * Adapted from Spike's mmu_t::translate and mmu_t::walk 734 * 735 * @env: CPURISCVState 736 * @physical: This will be set to the calculated physical address 737 * @prot: The returned protection attributes 738 * @addr: The virtual address to be translated 739 * @fault_pte_addr: If not NULL, this will be set to fault pte address 740 * when a error occurs on pte address translation. 741 * This will already be shifted to match htval. 742 * @access_type: The type of MMU access 743 * @mmu_idx: Indicates current privilege level 744 * @first_stage: Are we in first stage translation? 745 * Second stage is used for hypervisor guest translation 746 * @two_stage: Are we going to perform two stage translation 747 * @is_debug: Is this access from a debugger or the monitor? 748 */ 749 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 750 int *prot, target_ulong addr, 751 target_ulong *fault_pte_addr, 752 int access_type, int mmu_idx, 753 bool first_stage, bool two_stage, 754 bool is_debug) 755 { 756 /* NOTE: the env->pc value visible here will not be 757 * correct, but the value visible to the exception handler 758 * (riscv_cpu_do_interrupt) is correct */ 759 MemTxResult res; 760 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 761 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 762 bool use_background = false; 763 hwaddr ppn; 764 int napot_bits = 0; 765 target_ulong napot_mask; 766 767 /* 768 * Check if we should use the background registers for the two 769 * stage translation. We don't need to check if we actually need 770 * two stage translation as that happened before this function 771 * was called. Background registers will be used if the guest has 772 * forced a two stage translation to be on (in HS or M mode). 773 */ 774 if (!riscv_cpu_virt_enabled(env) && two_stage) { 775 use_background = true; 776 } 777 778 /* MPRV does not affect the virtual-machine load/store 779 instructions, HLV, HLVX, and HSV. */ 780 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 781 mode = get_field(env->hstatus, HSTATUS_SPVP); 782 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 783 if (get_field(env->mstatus, MSTATUS_MPRV)) { 784 mode = get_field(env->mstatus, MSTATUS_MPP); 785 } 786 } 787 788 if (first_stage == false) { 789 /* We are in stage 2 translation, this is similar to stage 1. */ 790 /* Stage 2 is always taken as U-mode */ 791 mode = PRV_U; 792 } 793 794 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 795 *physical = addr; 796 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 797 return TRANSLATE_SUCCESS; 798 } 799 800 *prot = 0; 801 802 hwaddr base; 803 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 804 805 if (first_stage == true) { 806 mxr = get_field(env->mstatus, MSTATUS_MXR); 807 } else { 808 mxr = get_field(env->vsstatus, MSTATUS_MXR); 809 } 810 811 if (first_stage == true) { 812 if (use_background) { 813 if (riscv_cpu_mxl(env) == MXL_RV32) { 814 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 815 vm = get_field(env->vsatp, SATP32_MODE); 816 } else { 817 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 818 vm = get_field(env->vsatp, SATP64_MODE); 819 } 820 } else { 821 if (riscv_cpu_mxl(env) == MXL_RV32) { 822 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 823 vm = get_field(env->satp, SATP32_MODE); 824 } else { 825 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 826 vm = get_field(env->satp, SATP64_MODE); 827 } 828 } 829 widened = 0; 830 } else { 831 if (riscv_cpu_mxl(env) == MXL_RV32) { 832 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 833 vm = get_field(env->hgatp, SATP32_MODE); 834 } else { 835 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 836 vm = get_field(env->hgatp, SATP64_MODE); 837 } 838 widened = 2; 839 } 840 /* status.SUM will be ignored if execute on background */ 841 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 842 switch (vm) { 843 case VM_1_10_SV32: 844 levels = 2; ptidxbits = 10; ptesize = 4; break; 845 case VM_1_10_SV39: 846 levels = 3; ptidxbits = 9; ptesize = 8; break; 847 case VM_1_10_SV48: 848 levels = 4; ptidxbits = 9; ptesize = 8; break; 849 case VM_1_10_SV57: 850 levels = 5; ptidxbits = 9; ptesize = 8; break; 851 case VM_1_10_MBARE: 852 *physical = addr; 853 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 854 return TRANSLATE_SUCCESS; 855 default: 856 g_assert_not_reached(); 857 } 858 859 CPUState *cs = env_cpu(env); 860 int va_bits = PGSHIFT + levels * ptidxbits + widened; 861 target_ulong mask, masked_msbs; 862 863 if (TARGET_LONG_BITS > (va_bits - 1)) { 864 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 865 } else { 866 mask = 0; 867 } 868 masked_msbs = (addr >> (va_bits - 1)) & mask; 869 870 if (masked_msbs != 0 && masked_msbs != mask) { 871 return TRANSLATE_FAIL; 872 } 873 874 int ptshift = (levels - 1) * ptidxbits; 875 int i; 876 877 #if !TCG_OVERSIZED_GUEST 878 restart: 879 #endif 880 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 881 target_ulong idx; 882 if (i == 0) { 883 idx = (addr >> (PGSHIFT + ptshift)) & 884 ((1 << (ptidxbits + widened)) - 1); 885 } else { 886 idx = (addr >> (PGSHIFT + ptshift)) & 887 ((1 << ptidxbits) - 1); 888 } 889 890 /* check that physical address of PTE is legal */ 891 hwaddr pte_addr; 892 893 if (two_stage && first_stage) { 894 int vbase_prot; 895 hwaddr vbase; 896 897 /* Do the second stage translation on the base PTE address. */ 898 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 899 base, NULL, MMU_DATA_LOAD, 900 mmu_idx, false, true, 901 is_debug); 902 903 if (vbase_ret != TRANSLATE_SUCCESS) { 904 if (fault_pte_addr) { 905 *fault_pte_addr = (base + idx * ptesize) >> 2; 906 } 907 return TRANSLATE_G_STAGE_FAIL; 908 } 909 910 pte_addr = vbase + idx * ptesize; 911 } else { 912 pte_addr = base + idx * ptesize; 913 } 914 915 int pmp_prot; 916 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 917 sizeof(target_ulong), 918 MMU_DATA_LOAD, PRV_S); 919 if (pmp_ret != TRANSLATE_SUCCESS) { 920 return TRANSLATE_PMP_FAIL; 921 } 922 923 target_ulong pte; 924 if (riscv_cpu_mxl(env) == MXL_RV32) { 925 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 926 } else { 927 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 928 } 929 930 if (res != MEMTX_OK) { 931 return TRANSLATE_FAIL; 932 } 933 934 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 935 bool hade = env->menvcfg & MENVCFG_HADE; 936 937 if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { 938 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 939 hade = hade && (env->henvcfg & HENVCFG_HADE); 940 } 941 942 if (riscv_cpu_sxl(env) == MXL_RV32) { 943 ppn = pte >> PTE_PPN_SHIFT; 944 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 945 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 946 } else { 947 ppn = pte >> PTE_PPN_SHIFT; 948 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 949 return TRANSLATE_FAIL; 950 } 951 } 952 953 if (!(pte & PTE_V)) { 954 /* Invalid PTE */ 955 return TRANSLATE_FAIL; 956 } else if (!pbmte && (pte & PTE_PBMT)) { 957 return TRANSLATE_FAIL; 958 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 959 /* Inner PTE, continue walking */ 960 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 961 return TRANSLATE_FAIL; 962 } 963 base = ppn << PGSHIFT; 964 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 965 /* Reserved leaf PTE flags: PTE_W */ 966 return TRANSLATE_FAIL; 967 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 968 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 969 return TRANSLATE_FAIL; 970 } else if ((pte & PTE_U) && ((mode != PRV_U) && 971 (!sum || access_type == MMU_INST_FETCH))) { 972 /* User PTE flags when not U mode and mstatus.SUM is not set, 973 or the access type is an instruction fetch */ 974 return TRANSLATE_FAIL; 975 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 976 /* Supervisor PTE flags when not S mode */ 977 return TRANSLATE_FAIL; 978 } else if (ppn & ((1ULL << ptshift) - 1)) { 979 /* Misaligned PPN */ 980 return TRANSLATE_FAIL; 981 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 982 ((pte & PTE_X) && mxr))) { 983 /* Read access check failed */ 984 return TRANSLATE_FAIL; 985 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 986 /* Write access check failed */ 987 return TRANSLATE_FAIL; 988 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 989 /* Fetch access check failed */ 990 return TRANSLATE_FAIL; 991 } else { 992 /* if necessary, set accessed and dirty bits. */ 993 target_ulong updated_pte = pte | PTE_A | 994 (access_type == MMU_DATA_STORE ? PTE_D : 0); 995 996 /* Page table updates need to be atomic with MTTCG enabled */ 997 if (updated_pte != pte) { 998 if (!hade) { 999 return TRANSLATE_FAIL; 1000 } 1001 1002 /* 1003 * - if accessed or dirty bits need updating, and the PTE is 1004 * in RAM, then we do so atomically with a compare and swap. 1005 * - if the PTE is in IO space or ROM, then it can't be updated 1006 * and we return TRANSLATE_FAIL. 1007 * - if the PTE changed by the time we went to update it, then 1008 * it is no longer valid and we must re-walk the page table. 1009 */ 1010 MemoryRegion *mr; 1011 hwaddr l = sizeof(target_ulong), addr1; 1012 mr = address_space_translate(cs->as, pte_addr, 1013 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 1014 if (memory_region_is_ram(mr)) { 1015 target_ulong *pte_pa = 1016 qemu_map_ram_ptr(mr->ram_block, addr1); 1017 #if TCG_OVERSIZED_GUEST 1018 /* MTTCG is not enabled on oversized TCG guests so 1019 * page table updates do not need to be atomic */ 1020 *pte_pa = pte = updated_pte; 1021 #else 1022 target_ulong old_pte = 1023 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1024 if (old_pte != pte) { 1025 goto restart; 1026 } else { 1027 pte = updated_pte; 1028 } 1029 #endif 1030 } else { 1031 /* misconfigured PTE in ROM (AD bits are not preset) or 1032 * PTE is in IO space and can't be updated atomically */ 1033 return TRANSLATE_FAIL; 1034 } 1035 } 1036 1037 /* for superpage mappings, make a fake leaf PTE for the TLB's 1038 benefit. */ 1039 target_ulong vpn = addr >> PGSHIFT; 1040 1041 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1042 napot_bits = ctzl(ppn) + 1; 1043 if ((i != (levels - 1)) || (napot_bits != 4)) { 1044 return TRANSLATE_FAIL; 1045 } 1046 } 1047 1048 napot_mask = (1 << napot_bits) - 1; 1049 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1050 (vpn & (((target_ulong)1 << ptshift) - 1)) 1051 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1052 1053 /* set permissions on the TLB entry */ 1054 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1055 *prot |= PAGE_READ; 1056 } 1057 if ((pte & PTE_X)) { 1058 *prot |= PAGE_EXEC; 1059 } 1060 /* add write permission on stores or if the page is already dirty, 1061 so that we TLB miss on later writes to update the dirty bit */ 1062 if ((pte & PTE_W) && 1063 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1064 *prot |= PAGE_WRITE; 1065 } 1066 return TRANSLATE_SUCCESS; 1067 } 1068 } 1069 return TRANSLATE_FAIL; 1070 } 1071 1072 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1073 MMUAccessType access_type, bool pmp_violation, 1074 bool first_stage, bool two_stage, 1075 bool two_stage_indirect) 1076 { 1077 CPUState *cs = env_cpu(env); 1078 int page_fault_exceptions, vm; 1079 uint64_t stap_mode; 1080 1081 if (riscv_cpu_mxl(env) == MXL_RV32) { 1082 stap_mode = SATP32_MODE; 1083 } else { 1084 stap_mode = SATP64_MODE; 1085 } 1086 1087 if (first_stage) { 1088 vm = get_field(env->satp, stap_mode); 1089 } else { 1090 vm = get_field(env->hgatp, stap_mode); 1091 } 1092 1093 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1094 1095 switch (access_type) { 1096 case MMU_INST_FETCH: 1097 if (riscv_cpu_virt_enabled(env) && !first_stage) { 1098 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1099 } else { 1100 cs->exception_index = page_fault_exceptions ? 1101 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1102 } 1103 break; 1104 case MMU_DATA_LOAD: 1105 if (two_stage && !first_stage) { 1106 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1107 } else { 1108 cs->exception_index = page_fault_exceptions ? 1109 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1110 } 1111 break; 1112 case MMU_DATA_STORE: 1113 if (two_stage && !first_stage) { 1114 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1115 } else { 1116 cs->exception_index = page_fault_exceptions ? 1117 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1118 } 1119 break; 1120 default: 1121 g_assert_not_reached(); 1122 } 1123 env->badaddr = address; 1124 env->two_stage_lookup = two_stage; 1125 env->two_stage_indirect_lookup = two_stage_indirect; 1126 } 1127 1128 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1129 { 1130 RISCVCPU *cpu = RISCV_CPU(cs); 1131 CPURISCVState *env = &cpu->env; 1132 hwaddr phys_addr; 1133 int prot; 1134 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1135 1136 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1137 true, riscv_cpu_virt_enabled(env), true)) { 1138 return -1; 1139 } 1140 1141 if (riscv_cpu_virt_enabled(env)) { 1142 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1143 0, mmu_idx, false, true, true)) { 1144 return -1; 1145 } 1146 } 1147 1148 return phys_addr & TARGET_PAGE_MASK; 1149 } 1150 1151 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1152 vaddr addr, unsigned size, 1153 MMUAccessType access_type, 1154 int mmu_idx, MemTxAttrs attrs, 1155 MemTxResult response, uintptr_t retaddr) 1156 { 1157 RISCVCPU *cpu = RISCV_CPU(cs); 1158 CPURISCVState *env = &cpu->env; 1159 1160 if (access_type == MMU_DATA_STORE) { 1161 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1162 } else if (access_type == MMU_DATA_LOAD) { 1163 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1164 } else { 1165 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1166 } 1167 1168 env->badaddr = addr; 1169 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1170 riscv_cpu_two_stage_lookup(mmu_idx); 1171 env->two_stage_indirect_lookup = false; 1172 cpu_loop_exit_restore(cs, retaddr); 1173 } 1174 1175 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1176 MMUAccessType access_type, int mmu_idx, 1177 uintptr_t retaddr) 1178 { 1179 RISCVCPU *cpu = RISCV_CPU(cs); 1180 CPURISCVState *env = &cpu->env; 1181 switch (access_type) { 1182 case MMU_INST_FETCH: 1183 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1184 break; 1185 case MMU_DATA_LOAD: 1186 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1187 break; 1188 case MMU_DATA_STORE: 1189 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1190 break; 1191 default: 1192 g_assert_not_reached(); 1193 } 1194 env->badaddr = addr; 1195 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 1196 riscv_cpu_two_stage_lookup(mmu_idx); 1197 env->two_stage_indirect_lookup = false; 1198 cpu_loop_exit_restore(cs, retaddr); 1199 } 1200 1201 1202 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1203 { 1204 enum riscv_pmu_event_idx pmu_event_type; 1205 1206 switch (access_type) { 1207 case MMU_INST_FETCH: 1208 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1209 break; 1210 case MMU_DATA_LOAD: 1211 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1212 break; 1213 case MMU_DATA_STORE: 1214 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1215 break; 1216 default: 1217 return; 1218 } 1219 1220 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1221 } 1222 1223 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1224 MMUAccessType access_type, int mmu_idx, 1225 bool probe, uintptr_t retaddr) 1226 { 1227 RISCVCPU *cpu = RISCV_CPU(cs); 1228 CPURISCVState *env = &cpu->env; 1229 vaddr im_address; 1230 hwaddr pa = 0; 1231 int prot, prot2, prot_pmp; 1232 bool pmp_violation = false; 1233 bool first_stage_error = true; 1234 bool two_stage_lookup = false; 1235 bool two_stage_indirect_error = false; 1236 int ret = TRANSLATE_FAIL; 1237 int mode = mmu_idx; 1238 /* default TLB page size */ 1239 target_ulong tlb_size = TARGET_PAGE_SIZE; 1240 1241 env->guest_phys_fault_addr = 0; 1242 1243 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1244 __func__, address, access_type, mmu_idx); 1245 1246 /* MPRV does not affect the virtual-machine load/store 1247 instructions, HLV, HLVX, and HSV. */ 1248 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1249 mode = get_field(env->hstatus, HSTATUS_SPVP); 1250 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1251 get_field(env->mstatus, MSTATUS_MPRV)) { 1252 mode = get_field(env->mstatus, MSTATUS_MPP); 1253 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1254 two_stage_lookup = true; 1255 } 1256 } 1257 1258 pmu_tlb_fill_incr_ctr(cpu, access_type); 1259 if (riscv_cpu_virt_enabled(env) || 1260 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1261 access_type != MMU_INST_FETCH)) { 1262 /* Two stage lookup */ 1263 ret = get_physical_address(env, &pa, &prot, address, 1264 &env->guest_phys_fault_addr, access_type, 1265 mmu_idx, true, true, false); 1266 1267 /* 1268 * A G-stage exception may be triggered during two state lookup. 1269 * And the env->guest_phys_fault_addr has already been set in 1270 * get_physical_address(). 1271 */ 1272 if (ret == TRANSLATE_G_STAGE_FAIL) { 1273 first_stage_error = false; 1274 two_stage_indirect_error = true; 1275 access_type = MMU_DATA_LOAD; 1276 } 1277 1278 qemu_log_mask(CPU_LOG_MMU, 1279 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1280 HWADDR_FMT_plx " prot %d\n", 1281 __func__, address, ret, pa, prot); 1282 1283 if (ret == TRANSLATE_SUCCESS) { 1284 /* Second stage lookup */ 1285 im_address = pa; 1286 1287 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1288 access_type, mmu_idx, false, true, 1289 false); 1290 1291 qemu_log_mask(CPU_LOG_MMU, 1292 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 1293 HWADDR_FMT_plx " prot %d\n", 1294 __func__, im_address, ret, pa, prot2); 1295 1296 prot &= prot2; 1297 1298 if (ret == TRANSLATE_SUCCESS) { 1299 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1300 size, access_type, mode); 1301 1302 qemu_log_mask(CPU_LOG_MMU, 1303 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1304 " %d tlb_size " TARGET_FMT_lu "\n", 1305 __func__, pa, ret, prot_pmp, tlb_size); 1306 1307 prot &= prot_pmp; 1308 } 1309 1310 if (ret != TRANSLATE_SUCCESS) { 1311 /* 1312 * Guest physical address translation failed, this is a HS 1313 * level exception 1314 */ 1315 first_stage_error = false; 1316 env->guest_phys_fault_addr = (im_address | 1317 (address & 1318 (TARGET_PAGE_SIZE - 1))) >> 2; 1319 } 1320 } 1321 } else { 1322 /* Single stage lookup */ 1323 ret = get_physical_address(env, &pa, &prot, address, NULL, 1324 access_type, mmu_idx, true, false, false); 1325 1326 qemu_log_mask(CPU_LOG_MMU, 1327 "%s address=%" VADDR_PRIx " ret %d physical " 1328 HWADDR_FMT_plx " prot %d\n", 1329 __func__, address, ret, pa, prot); 1330 1331 if (ret == TRANSLATE_SUCCESS) { 1332 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1333 size, access_type, mode); 1334 1335 qemu_log_mask(CPU_LOG_MMU, 1336 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1337 " %d tlb_size " TARGET_FMT_lu "\n", 1338 __func__, pa, ret, prot_pmp, tlb_size); 1339 1340 prot &= prot_pmp; 1341 } 1342 } 1343 1344 if (ret == TRANSLATE_PMP_FAIL) { 1345 pmp_violation = true; 1346 } 1347 1348 if (ret == TRANSLATE_SUCCESS) { 1349 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1350 prot, mmu_idx, tlb_size); 1351 return true; 1352 } else if (probe) { 1353 return false; 1354 } else { 1355 raise_mmu_exception(env, address, access_type, pmp_violation, 1356 first_stage_error, 1357 riscv_cpu_virt_enabled(env) || 1358 riscv_cpu_two_stage_lookup(mmu_idx), 1359 two_stage_indirect_error); 1360 cpu_loop_exit_restore(cs, retaddr); 1361 } 1362 1363 return true; 1364 } 1365 1366 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1367 target_ulong insn, 1368 target_ulong taddr) 1369 { 1370 target_ulong xinsn = 0; 1371 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1372 1373 /* 1374 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1375 * be uncompressed. The Quadrant 1 of RVC instruction space need 1376 * not be transformed because these instructions won't generate 1377 * any load/store trap. 1378 */ 1379 1380 if ((insn & 0x3) != 0x3) { 1381 /* Transform 16bit instruction into 32bit instruction */ 1382 switch (GET_C_OP(insn)) { 1383 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1384 switch (GET_C_FUNC(insn)) { 1385 case OPC_RISC_C_FUNC_FLD_LQ: 1386 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1387 xinsn = OPC_RISC_FLD; 1388 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1389 access_rs1 = GET_C_RS1S(insn); 1390 access_imm = GET_C_LD_IMM(insn); 1391 access_size = 8; 1392 } 1393 break; 1394 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1395 xinsn = OPC_RISC_LW; 1396 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1397 access_rs1 = GET_C_RS1S(insn); 1398 access_imm = GET_C_LW_IMM(insn); 1399 access_size = 4; 1400 break; 1401 case OPC_RISC_C_FUNC_FLW_LD: 1402 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1403 xinsn = OPC_RISC_FLW; 1404 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1405 access_rs1 = GET_C_RS1S(insn); 1406 access_imm = GET_C_LW_IMM(insn); 1407 access_size = 4; 1408 } else { /* C.LD (RV64/RV128) */ 1409 xinsn = OPC_RISC_LD; 1410 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1411 access_rs1 = GET_C_RS1S(insn); 1412 access_imm = GET_C_LD_IMM(insn); 1413 access_size = 8; 1414 } 1415 break; 1416 case OPC_RISC_C_FUNC_FSD_SQ: 1417 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1418 xinsn = OPC_RISC_FSD; 1419 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1420 access_rs1 = GET_C_RS1S(insn); 1421 access_imm = GET_C_SD_IMM(insn); 1422 access_size = 8; 1423 } 1424 break; 1425 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1426 xinsn = OPC_RISC_SW; 1427 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1428 access_rs1 = GET_C_RS1S(insn); 1429 access_imm = GET_C_SW_IMM(insn); 1430 access_size = 4; 1431 break; 1432 case OPC_RISC_C_FUNC_FSW_SD: 1433 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1434 xinsn = OPC_RISC_FSW; 1435 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1436 access_rs1 = GET_C_RS1S(insn); 1437 access_imm = GET_C_SW_IMM(insn); 1438 access_size = 4; 1439 } else { /* C.SD (RV64/RV128) */ 1440 xinsn = OPC_RISC_SD; 1441 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1442 access_rs1 = GET_C_RS1S(insn); 1443 access_imm = GET_C_SD_IMM(insn); 1444 access_size = 8; 1445 } 1446 break; 1447 default: 1448 break; 1449 } 1450 break; 1451 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1452 switch (GET_C_FUNC(insn)) { 1453 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1454 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1455 xinsn = OPC_RISC_FLD; 1456 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1457 access_rs1 = 2; 1458 access_imm = GET_C_LDSP_IMM(insn); 1459 access_size = 8; 1460 } 1461 break; 1462 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1463 xinsn = OPC_RISC_LW; 1464 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1465 access_rs1 = 2; 1466 access_imm = GET_C_LWSP_IMM(insn); 1467 access_size = 4; 1468 break; 1469 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1470 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1471 xinsn = OPC_RISC_FLW; 1472 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1473 access_rs1 = 2; 1474 access_imm = GET_C_LWSP_IMM(insn); 1475 access_size = 4; 1476 } else { /* C.LDSP (RV64/RV128) */ 1477 xinsn = OPC_RISC_LD; 1478 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1479 access_rs1 = 2; 1480 access_imm = GET_C_LDSP_IMM(insn); 1481 access_size = 8; 1482 } 1483 break; 1484 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1485 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1486 xinsn = OPC_RISC_FSD; 1487 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1488 access_rs1 = 2; 1489 access_imm = GET_C_SDSP_IMM(insn); 1490 access_size = 8; 1491 } 1492 break; 1493 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1494 xinsn = OPC_RISC_SW; 1495 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1496 access_rs1 = 2; 1497 access_imm = GET_C_SWSP_IMM(insn); 1498 access_size = 4; 1499 break; 1500 case 7: 1501 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1502 xinsn = OPC_RISC_FSW; 1503 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1504 access_rs1 = 2; 1505 access_imm = GET_C_SWSP_IMM(insn); 1506 access_size = 4; 1507 } else { /* C.SDSP (RV64/RV128) */ 1508 xinsn = OPC_RISC_SD; 1509 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1510 access_rs1 = 2; 1511 access_imm = GET_C_SDSP_IMM(insn); 1512 access_size = 8; 1513 } 1514 break; 1515 default: 1516 break; 1517 } 1518 break; 1519 default: 1520 break; 1521 } 1522 1523 /* 1524 * Clear Bit1 of transformed instruction to indicate that 1525 * original insruction was a 16bit instruction 1526 */ 1527 xinsn &= ~((target_ulong)0x2); 1528 } else { 1529 /* Transform 32bit (or wider) instructions */ 1530 switch (MASK_OP_MAJOR(insn)) { 1531 case OPC_RISC_ATOMIC: 1532 xinsn = insn; 1533 access_rs1 = GET_RS1(insn); 1534 access_size = 1 << GET_FUNCT3(insn); 1535 break; 1536 case OPC_RISC_LOAD: 1537 case OPC_RISC_FP_LOAD: 1538 xinsn = SET_I_IMM(insn, 0); 1539 access_rs1 = GET_RS1(insn); 1540 access_imm = GET_IMM(insn); 1541 access_size = 1 << GET_FUNCT3(insn); 1542 break; 1543 case OPC_RISC_STORE: 1544 case OPC_RISC_FP_STORE: 1545 xinsn = SET_S_IMM(insn, 0); 1546 access_rs1 = GET_RS1(insn); 1547 access_imm = GET_STORE_IMM(insn); 1548 access_size = 1 << GET_FUNCT3(insn); 1549 break; 1550 case OPC_RISC_SYSTEM: 1551 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1552 xinsn = insn; 1553 access_rs1 = GET_RS1(insn); 1554 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1555 access_size = 1 << access_size; 1556 } 1557 break; 1558 default: 1559 break; 1560 } 1561 } 1562 1563 if (access_size) { 1564 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1565 (access_size - 1)); 1566 } 1567 1568 return xinsn; 1569 } 1570 #endif /* !CONFIG_USER_ONLY */ 1571 1572 /* 1573 * Handle Traps 1574 * 1575 * Adapted from Spike's processor_t::take_trap. 1576 * 1577 */ 1578 void riscv_cpu_do_interrupt(CPUState *cs) 1579 { 1580 #if !defined(CONFIG_USER_ONLY) 1581 1582 RISCVCPU *cpu = RISCV_CPU(cs); 1583 CPURISCVState *env = &cpu->env; 1584 bool write_gva = false; 1585 uint64_t s; 1586 1587 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1588 * so we mask off the MSB and separate into trap type and cause. 1589 */ 1590 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1591 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1592 uint64_t deleg = async ? env->mideleg : env->medeleg; 1593 target_ulong tval = 0; 1594 target_ulong tinst = 0; 1595 target_ulong htval = 0; 1596 target_ulong mtval2 = 0; 1597 1598 if (cause == RISCV_EXCP_SEMIHOST) { 1599 do_common_semihosting(cs); 1600 env->pc += 4; 1601 return; 1602 } 1603 1604 if (!async) { 1605 /* set tval to badaddr for traps with address information */ 1606 switch (cause) { 1607 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1608 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1609 case RISCV_EXCP_LOAD_ADDR_MIS: 1610 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1611 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1612 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1613 case RISCV_EXCP_LOAD_PAGE_FAULT: 1614 case RISCV_EXCP_STORE_PAGE_FAULT: 1615 write_gva = env->two_stage_lookup; 1616 tval = env->badaddr; 1617 if (env->two_stage_indirect_lookup) { 1618 /* 1619 * special pseudoinstruction for G-stage fault taken while 1620 * doing VS-stage page table walk. 1621 */ 1622 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1623 } else { 1624 /* 1625 * The "Addr. Offset" field in transformed instruction is 1626 * non-zero only for misaligned access. 1627 */ 1628 tinst = riscv_transformed_insn(env, env->bins, tval); 1629 } 1630 break; 1631 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1632 case RISCV_EXCP_INST_ADDR_MIS: 1633 case RISCV_EXCP_INST_ACCESS_FAULT: 1634 case RISCV_EXCP_INST_PAGE_FAULT: 1635 write_gva = env->two_stage_lookup; 1636 tval = env->badaddr; 1637 if (env->two_stage_indirect_lookup) { 1638 /* 1639 * special pseudoinstruction for G-stage fault taken while 1640 * doing VS-stage page table walk. 1641 */ 1642 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1643 } 1644 break; 1645 case RISCV_EXCP_ILLEGAL_INST: 1646 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1647 tval = env->bins; 1648 break; 1649 case RISCV_EXCP_BREAKPOINT: 1650 if (cs->watchpoint_hit) { 1651 tval = cs->watchpoint_hit->hitaddr; 1652 cs->watchpoint_hit = NULL; 1653 } 1654 break; 1655 default: 1656 break; 1657 } 1658 /* ecall is dispatched as one cause so translate based on mode */ 1659 if (cause == RISCV_EXCP_U_ECALL) { 1660 assert(env->priv <= 3); 1661 1662 if (env->priv == PRV_M) { 1663 cause = RISCV_EXCP_M_ECALL; 1664 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1665 cause = RISCV_EXCP_VS_ECALL; 1666 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1667 cause = RISCV_EXCP_S_ECALL; 1668 } else if (env->priv == PRV_U) { 1669 cause = RISCV_EXCP_U_ECALL; 1670 } 1671 } 1672 } 1673 1674 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1675 riscv_cpu_get_trap_name(cause, async)); 1676 1677 qemu_log_mask(CPU_LOG_INT, 1678 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1679 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1680 __func__, env->mhartid, async, cause, env->pc, tval, 1681 riscv_cpu_get_trap_name(cause, async)); 1682 1683 if (env->priv <= PRV_S && 1684 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1685 /* handle the trap in S-mode */ 1686 if (riscv_has_ext(env, RVH)) { 1687 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1688 1689 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1690 /* Trap to VS mode */ 1691 /* 1692 * See if we need to adjust cause. Yes if its VS mode interrupt 1693 * no if hypervisor has delegated one of hs mode's interrupt 1694 */ 1695 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1696 cause == IRQ_VS_EXT) { 1697 cause = cause - 1; 1698 } 1699 write_gva = false; 1700 } else if (riscv_cpu_virt_enabled(env)) { 1701 /* Trap into HS mode, from virt */ 1702 riscv_cpu_swap_hypervisor_regs(env); 1703 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1704 env->priv); 1705 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1706 1707 htval = env->guest_phys_fault_addr; 1708 1709 riscv_cpu_set_virt_enabled(env, 0); 1710 } else { 1711 /* Trap into HS mode */ 1712 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1713 htval = env->guest_phys_fault_addr; 1714 } 1715 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1716 } 1717 1718 s = env->mstatus; 1719 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1720 s = set_field(s, MSTATUS_SPP, env->priv); 1721 s = set_field(s, MSTATUS_SIE, 0); 1722 env->mstatus = s; 1723 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1724 env->sepc = env->pc; 1725 env->stval = tval; 1726 env->htval = htval; 1727 env->htinst = tinst; 1728 env->pc = (env->stvec >> 2 << 2) + 1729 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1730 riscv_cpu_set_mode(env, PRV_S); 1731 } else { 1732 /* handle the trap in M-mode */ 1733 if (riscv_has_ext(env, RVH)) { 1734 if (riscv_cpu_virt_enabled(env)) { 1735 riscv_cpu_swap_hypervisor_regs(env); 1736 } 1737 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1738 riscv_cpu_virt_enabled(env)); 1739 if (riscv_cpu_virt_enabled(env) && tval) { 1740 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1741 } 1742 1743 mtval2 = env->guest_phys_fault_addr; 1744 1745 /* Trapping to M mode, virt is disabled */ 1746 riscv_cpu_set_virt_enabled(env, 0); 1747 } 1748 1749 s = env->mstatus; 1750 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1751 s = set_field(s, MSTATUS_MPP, env->priv); 1752 s = set_field(s, MSTATUS_MIE, 0); 1753 env->mstatus = s; 1754 env->mcause = cause | ~(((target_ulong)-1) >> async); 1755 env->mepc = env->pc; 1756 env->mtval = tval; 1757 env->mtval2 = mtval2; 1758 env->mtinst = tinst; 1759 env->pc = (env->mtvec >> 2 << 2) + 1760 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1761 riscv_cpu_set_mode(env, PRV_M); 1762 } 1763 1764 /* NOTE: it is not necessary to yield load reservations here. It is only 1765 * necessary for an SC from "another hart" to cause a load reservation 1766 * to be yielded. Refer to the memory consistency model section of the 1767 * RISC-V ISA Specification. 1768 */ 1769 1770 env->two_stage_lookup = false; 1771 env->two_stage_indirect_lookup = false; 1772 #endif 1773 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1774 } 1775