1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 29 { 30 #ifdef CONFIG_USER_ONLY 31 return 0; 32 #else 33 return env->priv; 34 #endif 35 } 36 37 #ifndef CONFIG_USER_ONLY 38 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 39 { 40 target_ulong irqs; 41 42 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 43 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 44 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 45 46 target_ulong pending = env->mip & env->mie & 47 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 48 target_ulong vspending = (env->mip & env->mie & 49 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); 50 51 target_ulong mie = env->priv < PRV_M || 52 (env->priv == PRV_M && mstatus_mie); 53 target_ulong sie = env->priv < PRV_S || 54 (env->priv == PRV_S && mstatus_sie); 55 target_ulong hs_sie = env->priv < PRV_S || 56 (env->priv == PRV_S && hs_mstatus_sie); 57 58 if (riscv_cpu_virt_enabled(env)) { 59 target_ulong pending_hs_irq = pending & -hs_sie; 60 61 if (pending_hs_irq) { 62 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 63 return ctz64(pending_hs_irq); 64 } 65 66 pending = vspending; 67 } 68 69 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 70 71 if (irqs) { 72 return ctz64(irqs); /* since non-zero */ 73 } else { 74 return EXCP_NONE; /* indicates no pending interrupt */ 75 } 76 } 77 #endif 78 79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (interrupt_request & CPU_INTERRUPT_HARD) { 83 RISCVCPU *cpu = RISCV_CPU(cs); 84 CPURISCVState *env = &cpu->env; 85 int interruptno = riscv_cpu_local_irq_pending(env); 86 if (interruptno >= 0) { 87 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 88 riscv_cpu_do_interrupt(cs); 89 return true; 90 } 91 } 92 #endif 93 return false; 94 } 95 96 #if !defined(CONFIG_USER_ONLY) 97 98 /* Return true is floating point support is currently enabled */ 99 bool riscv_cpu_fp_enabled(CPURISCVState *env) 100 { 101 if (env->mstatus & MSTATUS_FS) { 102 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 103 return false; 104 } 105 return true; 106 } 107 108 return false; 109 } 110 111 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 112 { 113 target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 114 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; 115 bool current_virt = riscv_cpu_virt_enabled(env); 116 117 g_assert(riscv_has_ext(env, RVH)); 118 119 #if defined(TARGET_RISCV64) 120 mstatus_mask |= MSTATUS64_UXL; 121 #endif 122 123 if (current_virt) { 124 /* Current V=1 and we are about to change to V=0 */ 125 env->vsstatus = env->mstatus & mstatus_mask; 126 env->mstatus &= ~mstatus_mask; 127 env->mstatus |= env->mstatus_hs; 128 129 #if defined(TARGET_RISCV32) 130 env->vsstatush = env->mstatush; 131 env->mstatush |= env->mstatush_hs; 132 #endif 133 134 env->vstvec = env->stvec; 135 env->stvec = env->stvec_hs; 136 137 env->vsscratch = env->sscratch; 138 env->sscratch = env->sscratch_hs; 139 140 env->vsepc = env->sepc; 141 env->sepc = env->sepc_hs; 142 143 env->vscause = env->scause; 144 env->scause = env->scause_hs; 145 146 env->vstval = env->sbadaddr; 147 env->sbadaddr = env->stval_hs; 148 149 env->vsatp = env->satp; 150 env->satp = env->satp_hs; 151 } else { 152 /* Current V=0 and we are about to change to V=1 */ 153 env->mstatus_hs = env->mstatus & mstatus_mask; 154 env->mstatus &= ~mstatus_mask; 155 env->mstatus |= env->vsstatus; 156 157 #if defined(TARGET_RISCV32) 158 env->mstatush_hs = env->mstatush; 159 env->mstatush |= env->vsstatush; 160 #endif 161 162 env->stvec_hs = env->stvec; 163 env->stvec = env->vstvec; 164 165 env->sscratch_hs = env->sscratch; 166 env->sscratch = env->vsscratch; 167 168 env->sepc_hs = env->sepc; 169 env->sepc = env->vsepc; 170 171 env->scause_hs = env->scause; 172 env->scause = env->vscause; 173 174 env->stval_hs = env->sbadaddr; 175 env->sbadaddr = env->vstval; 176 177 env->satp_hs = env->satp; 178 env->satp = env->vsatp; 179 } 180 } 181 182 bool riscv_cpu_virt_enabled(CPURISCVState *env) 183 { 184 if (!riscv_has_ext(env, RVH)) { 185 return false; 186 } 187 188 return get_field(env->virt, VIRT_ONOFF); 189 } 190 191 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 192 { 193 if (!riscv_has_ext(env, RVH)) { 194 return; 195 } 196 197 /* Flush the TLB on all virt mode changes. */ 198 if (get_field(env->virt, VIRT_ONOFF) != enable) { 199 tlb_flush(env_cpu(env)); 200 } 201 202 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 203 } 204 205 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 206 { 207 if (!riscv_has_ext(env, RVH)) { 208 return false; 209 } 210 211 return get_field(env->virt, FORCE_HS_EXCEP); 212 } 213 214 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 215 { 216 if (!riscv_has_ext(env, RVH)) { 217 return; 218 } 219 220 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 221 } 222 223 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 224 { 225 CPURISCVState *env = &cpu->env; 226 if (env->miclaim & interrupts) { 227 return -1; 228 } else { 229 env->miclaim |= interrupts; 230 return 0; 231 } 232 } 233 234 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 235 { 236 CPURISCVState *env = &cpu->env; 237 CPUState *cs = CPU(cpu); 238 uint32_t old = env->mip; 239 bool locked = false; 240 241 if (!qemu_mutex_iothread_locked()) { 242 locked = true; 243 qemu_mutex_lock_iothread(); 244 } 245 246 env->mip = (env->mip & ~mask) | (value & mask); 247 248 if (env->mip) { 249 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 250 } else { 251 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 252 } 253 254 if (locked) { 255 qemu_mutex_unlock_iothread(); 256 } 257 258 return old; 259 } 260 261 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)) 262 { 263 env->rdtime_fn = fn; 264 } 265 266 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 267 { 268 if (newpriv > PRV_M) { 269 g_assert_not_reached(); 270 } 271 if (newpriv == PRV_H) { 272 newpriv = PRV_U; 273 } 274 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 275 env->priv = newpriv; 276 277 /* 278 * Clear the load reservation - otherwise a reservation placed in one 279 * context/process can be used by another, resulting in an SC succeeding 280 * incorrectly. Version 2.2 of the ISA specification explicitly requires 281 * this behaviour, while later revisions say that the kernel "should" use 282 * an SC instruction to force the yielding of a load reservation on a 283 * preemptive context switch. As a result, do both. 284 */ 285 env->load_res = -1; 286 } 287 288 /* get_physical_address - get the physical address for this virtual address 289 * 290 * Do a page table walk to obtain the physical address corresponding to a 291 * virtual address. Returns 0 if the translation was successful 292 * 293 * Adapted from Spike's mmu_t::translate and mmu_t::walk 294 * 295 * @env: CPURISCVState 296 * @physical: This will be set to the calculated physical address 297 * @prot: The returned protection attributes 298 * @addr: The virtual address to be translated 299 * @access_type: The type of MMU access 300 * @mmu_idx: Indicates current privilege level 301 * @first_stage: Are we in first stage translation? 302 * Second stage is used for hypervisor guest translation 303 * @two_stage: Are we going to perform two stage translation 304 */ 305 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 306 int *prot, target_ulong addr, 307 int access_type, int mmu_idx, 308 bool first_stage, bool two_stage) 309 { 310 /* NOTE: the env->pc value visible here will not be 311 * correct, but the value visible to the exception handler 312 * (riscv_cpu_do_interrupt) is correct */ 313 MemTxResult res; 314 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 315 int mode = mmu_idx; 316 bool use_background = false; 317 318 /* 319 * Check if we should use the background registers for the two 320 * stage translation. We don't need to check if we actually need 321 * two stage translation as that happened before this function 322 * was called. Background registers will be used if the guest has 323 * forced a two stage translation to be on (in HS or M mode). 324 */ 325 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 326 if (get_field(env->mstatus, MSTATUS_MPRV)) { 327 mode = get_field(env->mstatus, MSTATUS_MPP); 328 329 if (riscv_has_ext(env, RVH) && 330 MSTATUS_MPV_ISSET(env)) { 331 use_background = true; 332 } 333 } 334 } 335 336 if (mode == PRV_S && access_type != MMU_INST_FETCH && 337 riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { 338 if (get_field(env->hstatus, HSTATUS_SPRV)) { 339 mode = get_field(env->mstatus, SSTATUS_SPP); 340 use_background = true; 341 } 342 } 343 344 if (first_stage == false) { 345 /* We are in stage 2 translation, this is similar to stage 1. */ 346 /* Stage 2 is always taken as U-mode */ 347 mode = PRV_U; 348 } 349 350 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 351 *physical = addr; 352 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 353 return TRANSLATE_SUCCESS; 354 } 355 356 *prot = 0; 357 358 hwaddr base; 359 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 360 361 if (first_stage == true) { 362 mxr = get_field(env->mstatus, MSTATUS_MXR); 363 } else { 364 mxr = get_field(env->vsstatus, MSTATUS_MXR); 365 } 366 367 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 368 if (first_stage == true) { 369 if (use_background) { 370 base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; 371 vm = get_field(env->vsatp, SATP_MODE); 372 } else { 373 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 374 vm = get_field(env->satp, SATP_MODE); 375 } 376 widened = 0; 377 } else { 378 base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; 379 vm = get_field(env->hgatp, HGATP_MODE); 380 widened = 2; 381 } 382 sum = get_field(env->mstatus, MSTATUS_SUM); 383 switch (vm) { 384 case VM_1_10_SV32: 385 levels = 2; ptidxbits = 10; ptesize = 4; break; 386 case VM_1_10_SV39: 387 levels = 3; ptidxbits = 9; ptesize = 8; break; 388 case VM_1_10_SV48: 389 levels = 4; ptidxbits = 9; ptesize = 8; break; 390 case VM_1_10_SV57: 391 levels = 5; ptidxbits = 9; ptesize = 8; break; 392 case VM_1_10_MBARE: 393 *physical = addr; 394 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 395 return TRANSLATE_SUCCESS; 396 default: 397 g_assert_not_reached(); 398 } 399 } else { 400 widened = 0; 401 base = (hwaddr)(env->sptbr) << PGSHIFT; 402 sum = !get_field(env->mstatus, MSTATUS_PUM); 403 vm = get_field(env->mstatus, MSTATUS_VM); 404 switch (vm) { 405 case VM_1_09_SV32: 406 levels = 2; ptidxbits = 10; ptesize = 4; break; 407 case VM_1_09_SV39: 408 levels = 3; ptidxbits = 9; ptesize = 8; break; 409 case VM_1_09_SV48: 410 levels = 4; ptidxbits = 9; ptesize = 8; break; 411 case VM_1_09_MBARE: 412 *physical = addr; 413 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 414 return TRANSLATE_SUCCESS; 415 default: 416 g_assert_not_reached(); 417 } 418 } 419 420 CPUState *cs = env_cpu(env); 421 int va_bits = PGSHIFT + levels * ptidxbits + widened; 422 target_ulong mask, masked_msbs; 423 424 if (TARGET_LONG_BITS > (va_bits - 1)) { 425 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 426 } else { 427 mask = 0; 428 } 429 masked_msbs = (addr >> (va_bits - 1)) & mask; 430 431 if (masked_msbs != 0 && masked_msbs != mask) { 432 return TRANSLATE_FAIL; 433 } 434 435 int ptshift = (levels - 1) * ptidxbits; 436 int i; 437 438 #if !TCG_OVERSIZED_GUEST 439 restart: 440 #endif 441 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 442 target_ulong idx; 443 if (i == 0) { 444 idx = (addr >> (PGSHIFT + ptshift)) & 445 ((1 << (ptidxbits + widened)) - 1); 446 } else { 447 idx = (addr >> (PGSHIFT + ptshift)) & 448 ((1 << ptidxbits) - 1); 449 } 450 451 /* check that physical address of PTE is legal */ 452 hwaddr pte_addr; 453 454 if (two_stage && first_stage) { 455 hwaddr vbase; 456 457 /* Do the second stage translation on the base PTE address. */ 458 get_physical_address(env, &vbase, prot, base, access_type, 459 mmu_idx, false, true); 460 461 pte_addr = vbase + idx * ptesize; 462 } else { 463 pte_addr = base + idx * ptesize; 464 } 465 466 if (riscv_feature(env, RISCV_FEATURE_PMP) && 467 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), 468 1 << MMU_DATA_LOAD, PRV_S)) { 469 return TRANSLATE_PMP_FAIL; 470 } 471 472 #if defined(TARGET_RISCV32) 473 target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 474 #elif defined(TARGET_RISCV64) 475 target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 476 #endif 477 if (res != MEMTX_OK) { 478 return TRANSLATE_FAIL; 479 } 480 481 hwaddr ppn = pte >> PTE_PPN_SHIFT; 482 483 if (!(pte & PTE_V)) { 484 /* Invalid PTE */ 485 return TRANSLATE_FAIL; 486 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 487 /* Inner PTE, continue walking */ 488 base = ppn << PGSHIFT; 489 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 490 /* Reserved leaf PTE flags: PTE_W */ 491 return TRANSLATE_FAIL; 492 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 493 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 494 return TRANSLATE_FAIL; 495 } else if ((pte & PTE_U) && ((mode != PRV_U) && 496 (!sum || access_type == MMU_INST_FETCH))) { 497 /* User PTE flags when not U mode and mstatus.SUM is not set, 498 or the access type is an instruction fetch */ 499 return TRANSLATE_FAIL; 500 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 501 /* Supervisor PTE flags when not S mode */ 502 return TRANSLATE_FAIL; 503 } else if (ppn & ((1ULL << ptshift) - 1)) { 504 /* Misaligned PPN */ 505 return TRANSLATE_FAIL; 506 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 507 ((pte & PTE_X) && mxr))) { 508 /* Read access check failed */ 509 return TRANSLATE_FAIL; 510 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 511 /* Write access check failed */ 512 return TRANSLATE_FAIL; 513 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 514 /* Fetch access check failed */ 515 return TRANSLATE_FAIL; 516 } else { 517 /* if necessary, set accessed and dirty bits. */ 518 target_ulong updated_pte = pte | PTE_A | 519 (access_type == MMU_DATA_STORE ? PTE_D : 0); 520 521 /* Page table updates need to be atomic with MTTCG enabled */ 522 if (updated_pte != pte) { 523 /* 524 * - if accessed or dirty bits need updating, and the PTE is 525 * in RAM, then we do so atomically with a compare and swap. 526 * - if the PTE is in IO space or ROM, then it can't be updated 527 * and we return TRANSLATE_FAIL. 528 * - if the PTE changed by the time we went to update it, then 529 * it is no longer valid and we must re-walk the page table. 530 */ 531 MemoryRegion *mr; 532 hwaddr l = sizeof(target_ulong), addr1; 533 mr = address_space_translate(cs->as, pte_addr, 534 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 535 if (memory_region_is_ram(mr)) { 536 target_ulong *pte_pa = 537 qemu_map_ram_ptr(mr->ram_block, addr1); 538 #if TCG_OVERSIZED_GUEST 539 /* MTTCG is not enabled on oversized TCG guests so 540 * page table updates do not need to be atomic */ 541 *pte_pa = pte = updated_pte; 542 #else 543 target_ulong old_pte = 544 atomic_cmpxchg(pte_pa, pte, updated_pte); 545 if (old_pte != pte) { 546 goto restart; 547 } else { 548 pte = updated_pte; 549 } 550 #endif 551 } else { 552 /* misconfigured PTE in ROM (AD bits are not preset) or 553 * PTE is in IO space and can't be updated atomically */ 554 return TRANSLATE_FAIL; 555 } 556 } 557 558 /* for superpage mappings, make a fake leaf PTE for the TLB's 559 benefit. */ 560 target_ulong vpn = addr >> PGSHIFT; 561 if (i == 0) { 562 *physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) << 563 PGSHIFT; 564 } else { 565 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 566 } 567 568 /* set permissions on the TLB entry */ 569 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 570 *prot |= PAGE_READ; 571 } 572 if ((pte & PTE_X)) { 573 *prot |= PAGE_EXEC; 574 } 575 /* add write permission on stores or if the page is already dirty, 576 so that we TLB miss on later writes to update the dirty bit */ 577 if ((pte & PTE_W) && 578 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 579 *prot |= PAGE_WRITE; 580 } 581 return TRANSLATE_SUCCESS; 582 } 583 } 584 return TRANSLATE_FAIL; 585 } 586 587 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 588 MMUAccessType access_type, bool pmp_violation, 589 bool first_stage) 590 { 591 CPUState *cs = env_cpu(env); 592 int page_fault_exceptions; 593 if (first_stage) { 594 page_fault_exceptions = 595 (env->priv_ver >= PRIV_VERSION_1_10_0) && 596 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 597 !pmp_violation; 598 } else { 599 page_fault_exceptions = 600 get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE && 601 !pmp_violation; 602 } 603 switch (access_type) { 604 case MMU_INST_FETCH: 605 if (riscv_cpu_virt_enabled(env) && !first_stage) { 606 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 607 } else { 608 cs->exception_index = page_fault_exceptions ? 609 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 610 } 611 break; 612 case MMU_DATA_LOAD: 613 if (riscv_cpu_virt_enabled(env) && !first_stage) { 614 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 615 } else { 616 cs->exception_index = page_fault_exceptions ? 617 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 618 } 619 break; 620 case MMU_DATA_STORE: 621 if (riscv_cpu_virt_enabled(env) && !first_stage) { 622 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 623 } else { 624 cs->exception_index = page_fault_exceptions ? 625 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 626 } 627 break; 628 default: 629 g_assert_not_reached(); 630 } 631 env->badaddr = address; 632 } 633 634 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 635 { 636 RISCVCPU *cpu = RISCV_CPU(cs); 637 CPURISCVState *env = &cpu->env; 638 hwaddr phys_addr; 639 int prot; 640 int mmu_idx = cpu_mmu_index(&cpu->env, false); 641 642 if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, 643 true, riscv_cpu_virt_enabled(env))) { 644 return -1; 645 } 646 647 if (riscv_cpu_virt_enabled(env)) { 648 if (get_physical_address(env, &phys_addr, &prot, phys_addr, 649 0, mmu_idx, false, true)) { 650 return -1; 651 } 652 } 653 654 return phys_addr; 655 } 656 657 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 658 vaddr addr, unsigned size, 659 MMUAccessType access_type, 660 int mmu_idx, MemTxAttrs attrs, 661 MemTxResult response, uintptr_t retaddr) 662 { 663 RISCVCPU *cpu = RISCV_CPU(cs); 664 CPURISCVState *env = &cpu->env; 665 666 if (access_type == MMU_DATA_STORE) { 667 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 668 } else { 669 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 670 } 671 672 env->badaddr = addr; 673 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 674 } 675 676 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 677 MMUAccessType access_type, int mmu_idx, 678 uintptr_t retaddr) 679 { 680 RISCVCPU *cpu = RISCV_CPU(cs); 681 CPURISCVState *env = &cpu->env; 682 switch (access_type) { 683 case MMU_INST_FETCH: 684 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 685 break; 686 case MMU_DATA_LOAD: 687 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 688 break; 689 case MMU_DATA_STORE: 690 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 691 break; 692 default: 693 g_assert_not_reached(); 694 } 695 env->badaddr = addr; 696 riscv_raise_exception(env, cs->exception_index, retaddr); 697 } 698 #endif 699 700 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 701 MMUAccessType access_type, int mmu_idx, 702 bool probe, uintptr_t retaddr) 703 { 704 RISCVCPU *cpu = RISCV_CPU(cs); 705 CPURISCVState *env = &cpu->env; 706 #ifndef CONFIG_USER_ONLY 707 vaddr im_address; 708 hwaddr pa = 0; 709 int prot; 710 bool pmp_violation = false; 711 bool m_mode_two_stage = false; 712 bool hs_mode_two_stage = false; 713 bool first_stage_error = true; 714 int ret = TRANSLATE_FAIL; 715 int mode = mmu_idx; 716 717 env->guest_phys_fault_addr = 0; 718 719 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 720 __func__, address, access_type, mmu_idx); 721 722 /* 723 * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is 724 * set and we want to access a virtulisation address. 725 */ 726 if (riscv_has_ext(env, RVH)) { 727 m_mode_two_stage = env->priv == PRV_M && 728 access_type != MMU_INST_FETCH && 729 get_field(env->mstatus, MSTATUS_MPRV) && 730 MSTATUS_MPV_ISSET(env); 731 732 hs_mode_two_stage = env->priv == PRV_S && 733 !riscv_cpu_virt_enabled(env) && 734 access_type != MMU_INST_FETCH && 735 get_field(env->hstatus, HSTATUS_SPRV) && 736 get_field(env->hstatus, HSTATUS_SPV); 737 } 738 739 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 740 if (get_field(env->mstatus, MSTATUS_MPRV)) { 741 mode = get_field(env->mstatus, MSTATUS_MPP); 742 } 743 } 744 745 if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { 746 /* Two stage lookup */ 747 ret = get_physical_address(env, &pa, &prot, address, access_type, 748 mmu_idx, true, true); 749 750 qemu_log_mask(CPU_LOG_MMU, 751 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 752 TARGET_FMT_plx " prot %d\n", 753 __func__, address, ret, pa, prot); 754 755 if (ret != TRANSLATE_FAIL) { 756 /* Second stage lookup */ 757 im_address = pa; 758 759 ret = get_physical_address(env, &pa, &prot, im_address, 760 access_type, mmu_idx, false, true); 761 762 qemu_log_mask(CPU_LOG_MMU, 763 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 764 TARGET_FMT_plx " prot %d\n", 765 __func__, im_address, ret, pa, prot); 766 767 if (riscv_feature(env, RISCV_FEATURE_PMP) && 768 (ret == TRANSLATE_SUCCESS) && 769 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 770 ret = TRANSLATE_PMP_FAIL; 771 } 772 773 if (ret != TRANSLATE_SUCCESS) { 774 /* 775 * Guest physical address translation failed, this is a HS 776 * level exception 777 */ 778 first_stage_error = false; 779 env->guest_phys_fault_addr = (im_address | 780 (address & 781 (TARGET_PAGE_SIZE - 1))) >> 2; 782 } 783 } 784 } else { 785 /* Single stage lookup */ 786 ret = get_physical_address(env, &pa, &prot, address, access_type, 787 mmu_idx, true, false); 788 789 qemu_log_mask(CPU_LOG_MMU, 790 "%s address=%" VADDR_PRIx " ret %d physical " 791 TARGET_FMT_plx " prot %d\n", 792 __func__, address, ret, pa, prot); 793 } 794 795 if (riscv_feature(env, RISCV_FEATURE_PMP) && 796 (ret == TRANSLATE_SUCCESS) && 797 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 798 ret = TRANSLATE_PMP_FAIL; 799 } 800 if (ret == TRANSLATE_PMP_FAIL) { 801 pmp_violation = true; 802 } 803 804 if (ret == TRANSLATE_SUCCESS) { 805 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 806 prot, mmu_idx, TARGET_PAGE_SIZE); 807 return true; 808 } else if (probe) { 809 return false; 810 } else { 811 raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error); 812 riscv_raise_exception(env, cs->exception_index, retaddr); 813 } 814 815 return true; 816 817 #else 818 switch (access_type) { 819 case MMU_INST_FETCH: 820 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 821 break; 822 case MMU_DATA_LOAD: 823 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 824 break; 825 case MMU_DATA_STORE: 826 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 827 break; 828 default: 829 g_assert_not_reached(); 830 } 831 env->badaddr = address; 832 cpu_loop_exit_restore(cs, retaddr); 833 #endif 834 } 835 836 /* 837 * Handle Traps 838 * 839 * Adapted from Spike's processor_t::take_trap. 840 * 841 */ 842 void riscv_cpu_do_interrupt(CPUState *cs) 843 { 844 #if !defined(CONFIG_USER_ONLY) 845 846 RISCVCPU *cpu = RISCV_CPU(cs); 847 CPURISCVState *env = &cpu->env; 848 bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); 849 target_ulong s; 850 851 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 852 * so we mask off the MSB and separate into trap type and cause. 853 */ 854 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 855 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 856 target_ulong deleg = async ? env->mideleg : env->medeleg; 857 target_ulong tval = 0; 858 target_ulong htval = 0; 859 target_ulong mtval2 = 0; 860 861 if (!async) { 862 /* set tval to badaddr for traps with address information */ 863 switch (cause) { 864 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 865 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 866 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 867 force_hs_execp = true; 868 /* fallthrough */ 869 case RISCV_EXCP_INST_ADDR_MIS: 870 case RISCV_EXCP_INST_ACCESS_FAULT: 871 case RISCV_EXCP_LOAD_ADDR_MIS: 872 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 873 case RISCV_EXCP_LOAD_ACCESS_FAULT: 874 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 875 case RISCV_EXCP_INST_PAGE_FAULT: 876 case RISCV_EXCP_LOAD_PAGE_FAULT: 877 case RISCV_EXCP_STORE_PAGE_FAULT: 878 tval = env->badaddr; 879 break; 880 default: 881 break; 882 } 883 /* ecall is dispatched as one cause so translate based on mode */ 884 if (cause == RISCV_EXCP_U_ECALL) { 885 assert(env->priv <= 3); 886 887 if (env->priv == PRV_M) { 888 cause = RISCV_EXCP_M_ECALL; 889 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 890 cause = RISCV_EXCP_VS_ECALL; 891 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 892 cause = RISCV_EXCP_S_ECALL; 893 } else if (env->priv == PRV_U) { 894 cause = RISCV_EXCP_U_ECALL; 895 } 896 } 897 } 898 899 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? 900 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 901 902 if (env->priv <= PRV_S && 903 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 904 /* handle the trap in S-mode */ 905 if (riscv_has_ext(env, RVH)) { 906 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 907 908 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && 909 !force_hs_execp) { 910 /* 911 * See if we need to adjust cause. Yes if its VS mode interrupt 912 * no if hypervisor has delegated one of hs mode's interrupt 913 */ 914 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 915 cause == IRQ_VS_EXT) 916 cause = cause - 1; 917 /* Trap to VS mode */ 918 } else if (riscv_cpu_virt_enabled(env)) { 919 /* Trap into HS mode, from virt */ 920 riscv_cpu_swap_hypervisor_regs(env); 921 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 922 get_field(env->hstatus, HSTATUS_SPV)); 923 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 924 get_field(env->mstatus, SSTATUS_SPP)); 925 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 926 riscv_cpu_virt_enabled(env)); 927 928 htval = env->guest_phys_fault_addr; 929 930 riscv_cpu_set_virt_enabled(env, 0); 931 riscv_cpu_set_force_hs_excep(env, 0); 932 } else { 933 /* Trap into HS mode */ 934 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 935 get_field(env->hstatus, HSTATUS_SPV)); 936 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 937 get_field(env->mstatus, SSTATUS_SPP)); 938 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 939 riscv_cpu_virt_enabled(env)); 940 941 htval = env->guest_phys_fault_addr; 942 } 943 } 944 945 s = env->mstatus; 946 s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 947 get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); 948 s = set_field(s, MSTATUS_SPP, env->priv); 949 s = set_field(s, MSTATUS_SIE, 0); 950 env->mstatus = s; 951 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 952 env->sepc = env->pc; 953 env->sbadaddr = tval; 954 env->htval = htval; 955 env->pc = (env->stvec >> 2 << 2) + 956 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 957 riscv_cpu_set_mode(env, PRV_S); 958 } else { 959 /* handle the trap in M-mode */ 960 if (riscv_has_ext(env, RVH)) { 961 if (riscv_cpu_virt_enabled(env)) { 962 riscv_cpu_swap_hypervisor_regs(env); 963 } 964 #ifdef TARGET_RISCV32 965 env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 966 riscv_cpu_virt_enabled(env)); 967 env->mstatush = set_field(env->mstatush, MSTATUS_MTL, 968 riscv_cpu_force_hs_excep_enabled(env)); 969 #else 970 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 971 riscv_cpu_virt_enabled(env)); 972 env->mstatus = set_field(env->mstatus, MSTATUS_MTL, 973 riscv_cpu_force_hs_excep_enabled(env)); 974 #endif 975 976 mtval2 = env->guest_phys_fault_addr; 977 978 /* Trapping to M mode, virt is disabled */ 979 riscv_cpu_set_virt_enabled(env, 0); 980 riscv_cpu_set_force_hs_excep(env, 0); 981 } 982 983 s = env->mstatus; 984 s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 985 get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); 986 s = set_field(s, MSTATUS_MPP, env->priv); 987 s = set_field(s, MSTATUS_MIE, 0); 988 env->mstatus = s; 989 env->mcause = cause | ~(((target_ulong)-1) >> async); 990 env->mepc = env->pc; 991 env->mbadaddr = tval; 992 env->mtval2 = mtval2; 993 env->pc = (env->mtvec >> 2 << 2) + 994 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 995 riscv_cpu_set_mode(env, PRV_M); 996 } 997 998 /* NOTE: it is not necessary to yield load reservations here. It is only 999 * necessary for an SC from "another hart" to cause a load reservation 1000 * to be yielded. Refer to the memory consistency model section of the 1001 * RISC-V ISA Specification. 1002 */ 1003 1004 #endif 1005 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 1006 } 1007