1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 28 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 29 { 30 #ifdef CONFIG_USER_ONLY 31 return 0; 32 #else 33 return env->priv; 34 #endif 35 } 36 37 #ifndef CONFIG_USER_ONLY 38 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 39 { 40 target_ulong irqs; 41 42 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 43 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 44 target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); 45 46 target_ulong pending = env->mip & env->mie & 47 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 48 target_ulong vspending = (env->mip & env->mie & 49 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; 50 51 target_ulong mie = env->priv < PRV_M || 52 (env->priv == PRV_M && mstatus_mie); 53 target_ulong sie = env->priv < PRV_S || 54 (env->priv == PRV_S && mstatus_sie); 55 target_ulong hs_sie = env->priv < PRV_S || 56 (env->priv == PRV_S && hs_mstatus_sie); 57 58 if (riscv_cpu_virt_enabled(env)) { 59 target_ulong pending_hs_irq = pending & -hs_sie; 60 61 if (pending_hs_irq) { 62 riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); 63 return ctz64(pending_hs_irq); 64 } 65 66 pending = vspending; 67 } 68 69 irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); 70 71 if (irqs) { 72 return ctz64(irqs); /* since non-zero */ 73 } else { 74 return EXCP_NONE; /* indicates no pending interrupt */ 75 } 76 } 77 #endif 78 79 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (interrupt_request & CPU_INTERRUPT_HARD) { 83 RISCVCPU *cpu = RISCV_CPU(cs); 84 CPURISCVState *env = &cpu->env; 85 int interruptno = riscv_cpu_local_irq_pending(env); 86 if (interruptno >= 0) { 87 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 88 riscv_cpu_do_interrupt(cs); 89 return true; 90 } 91 } 92 #endif 93 return false; 94 } 95 96 #if !defined(CONFIG_USER_ONLY) 97 98 /* Return true is floating point support is currently enabled */ 99 bool riscv_cpu_fp_enabled(CPURISCVState *env) 100 { 101 if (env->mstatus & MSTATUS_FS) { 102 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 103 return false; 104 } 105 return true; 106 } 107 108 return false; 109 } 110 111 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 112 { 113 target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 114 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; 115 bool current_virt = riscv_cpu_virt_enabled(env); 116 117 g_assert(riscv_has_ext(env, RVH)); 118 119 #if defined(TARGET_RISCV64) 120 mstatus_mask |= MSTATUS64_UXL; 121 #endif 122 123 if (current_virt) { 124 /* Current V=1 and we are about to change to V=0 */ 125 env->vsstatus = env->mstatus & mstatus_mask; 126 env->mstatus &= ~mstatus_mask; 127 env->mstatus |= env->mstatus_hs; 128 129 env->vstvec = env->stvec; 130 env->stvec = env->stvec_hs; 131 132 env->vsscratch = env->sscratch; 133 env->sscratch = env->sscratch_hs; 134 135 env->vsepc = env->sepc; 136 env->sepc = env->sepc_hs; 137 138 env->vscause = env->scause; 139 env->scause = env->scause_hs; 140 141 env->vstval = env->sbadaddr; 142 env->sbadaddr = env->stval_hs; 143 144 env->vsatp = env->satp; 145 env->satp = env->satp_hs; 146 } else { 147 /* Current V=0 and we are about to change to V=1 */ 148 env->mstatus_hs = env->mstatus & mstatus_mask; 149 env->mstatus &= ~mstatus_mask; 150 env->mstatus |= env->vsstatus; 151 152 env->stvec_hs = env->stvec; 153 env->stvec = env->vstvec; 154 155 env->sscratch_hs = env->sscratch; 156 env->sscratch = env->vsscratch; 157 158 env->sepc_hs = env->sepc; 159 env->sepc = env->vsepc; 160 161 env->scause_hs = env->scause; 162 env->scause = env->vscause; 163 164 env->stval_hs = env->sbadaddr; 165 env->sbadaddr = env->vstval; 166 167 env->satp_hs = env->satp; 168 env->satp = env->vsatp; 169 } 170 } 171 172 bool riscv_cpu_virt_enabled(CPURISCVState *env) 173 { 174 if (!riscv_has_ext(env, RVH)) { 175 return false; 176 } 177 178 return get_field(env->virt, VIRT_ONOFF); 179 } 180 181 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 182 { 183 if (!riscv_has_ext(env, RVH)) { 184 return; 185 } 186 187 /* Flush the TLB on all virt mode changes. */ 188 if (get_field(env->virt, VIRT_ONOFF) != enable) { 189 tlb_flush(env_cpu(env)); 190 } 191 192 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 193 } 194 195 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) 196 { 197 if (!riscv_has_ext(env, RVH)) { 198 return false; 199 } 200 201 return get_field(env->virt, FORCE_HS_EXCEP); 202 } 203 204 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) 205 { 206 if (!riscv_has_ext(env, RVH)) { 207 return; 208 } 209 210 env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); 211 } 212 213 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 214 { 215 CPURISCVState *env = &cpu->env; 216 if (env->miclaim & interrupts) { 217 return -1; 218 } else { 219 env->miclaim |= interrupts; 220 return 0; 221 } 222 } 223 224 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 225 { 226 CPURISCVState *env = &cpu->env; 227 CPUState *cs = CPU(cpu); 228 uint32_t old = env->mip; 229 bool locked = false; 230 231 if (!qemu_mutex_iothread_locked()) { 232 locked = true; 233 qemu_mutex_lock_iothread(); 234 } 235 236 env->mip = (env->mip & ~mask) | (value & mask); 237 238 if (env->mip) { 239 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 240 } else { 241 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 242 } 243 244 if (locked) { 245 qemu_mutex_unlock_iothread(); 246 } 247 248 return old; 249 } 250 251 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 252 { 253 if (newpriv > PRV_M) { 254 g_assert_not_reached(); 255 } 256 if (newpriv == PRV_H) { 257 newpriv = PRV_U; 258 } 259 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 260 env->priv = newpriv; 261 262 /* 263 * Clear the load reservation - otherwise a reservation placed in one 264 * context/process can be used by another, resulting in an SC succeeding 265 * incorrectly. Version 2.2 of the ISA specification explicitly requires 266 * this behaviour, while later revisions say that the kernel "should" use 267 * an SC instruction to force the yielding of a load reservation on a 268 * preemptive context switch. As a result, do both. 269 */ 270 env->load_res = -1; 271 } 272 273 /* get_physical_address - get the physical address for this virtual address 274 * 275 * Do a page table walk to obtain the physical address corresponding to a 276 * virtual address. Returns 0 if the translation was successful 277 * 278 * Adapted from Spike's mmu_t::translate and mmu_t::walk 279 * 280 * @env: CPURISCVState 281 * @physical: This will be set to the calculated physical address 282 * @prot: The returned protection attributes 283 * @addr: The virtual address to be translated 284 * @access_type: The type of MMU access 285 * @mmu_idx: Indicates current privilege level 286 * @first_stage: Are we in first stage translation? 287 * Second stage is used for hypervisor guest translation 288 */ 289 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 290 int *prot, target_ulong addr, 291 int access_type, int mmu_idx, 292 bool first_stage) 293 { 294 /* NOTE: the env->pc value visible here will not be 295 * correct, but the value visible to the exception handler 296 * (riscv_cpu_do_interrupt) is correct */ 297 MemTxResult res; 298 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 299 int mode = mmu_idx; 300 301 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 302 if (get_field(env->mstatus, MSTATUS_MPRV)) { 303 mode = get_field(env->mstatus, MSTATUS_MPP); 304 } 305 } 306 307 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 308 *physical = addr; 309 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 310 return TRANSLATE_SUCCESS; 311 } 312 313 *prot = 0; 314 315 hwaddr base; 316 int levels, ptidxbits, ptesize, vm, sum; 317 int mxr = get_field(env->mstatus, MSTATUS_MXR); 318 319 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 320 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 321 sum = get_field(env->mstatus, MSTATUS_SUM); 322 vm = get_field(env->satp, SATP_MODE); 323 switch (vm) { 324 case VM_1_10_SV32: 325 levels = 2; ptidxbits = 10; ptesize = 4; break; 326 case VM_1_10_SV39: 327 levels = 3; ptidxbits = 9; ptesize = 8; break; 328 case VM_1_10_SV48: 329 levels = 4; ptidxbits = 9; ptesize = 8; break; 330 case VM_1_10_SV57: 331 levels = 5; ptidxbits = 9; ptesize = 8; break; 332 case VM_1_10_MBARE: 333 *physical = addr; 334 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 335 return TRANSLATE_SUCCESS; 336 default: 337 g_assert_not_reached(); 338 } 339 } else { 340 base = (hwaddr)(env->sptbr) << PGSHIFT; 341 sum = !get_field(env->mstatus, MSTATUS_PUM); 342 vm = get_field(env->mstatus, MSTATUS_VM); 343 switch (vm) { 344 case VM_1_09_SV32: 345 levels = 2; ptidxbits = 10; ptesize = 4; break; 346 case VM_1_09_SV39: 347 levels = 3; ptidxbits = 9; ptesize = 8; break; 348 case VM_1_09_SV48: 349 levels = 4; ptidxbits = 9; ptesize = 8; break; 350 case VM_1_09_MBARE: 351 *physical = addr; 352 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 353 return TRANSLATE_SUCCESS; 354 default: 355 g_assert_not_reached(); 356 } 357 } 358 359 CPUState *cs = env_cpu(env); 360 int va_bits = PGSHIFT + levels * ptidxbits; 361 target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 362 target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; 363 if (masked_msbs != 0 && masked_msbs != mask) { 364 return TRANSLATE_FAIL; 365 } 366 367 int ptshift = (levels - 1) * ptidxbits; 368 int i; 369 370 #if !TCG_OVERSIZED_GUEST 371 restart: 372 #endif 373 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 374 target_ulong idx = (addr >> (PGSHIFT + ptshift)) & 375 ((1 << ptidxbits) - 1); 376 377 /* check that physical address of PTE is legal */ 378 hwaddr pte_addr = base + idx * ptesize; 379 380 if (riscv_feature(env, RISCV_FEATURE_PMP) && 381 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), 382 1 << MMU_DATA_LOAD, PRV_S)) { 383 return TRANSLATE_PMP_FAIL; 384 } 385 386 #if defined(TARGET_RISCV32) 387 target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 388 #elif defined(TARGET_RISCV64) 389 target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 390 #endif 391 if (res != MEMTX_OK) { 392 return TRANSLATE_FAIL; 393 } 394 395 hwaddr ppn = pte >> PTE_PPN_SHIFT; 396 397 if (!(pte & PTE_V)) { 398 /* Invalid PTE */ 399 return TRANSLATE_FAIL; 400 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 401 /* Inner PTE, continue walking */ 402 base = ppn << PGSHIFT; 403 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 404 /* Reserved leaf PTE flags: PTE_W */ 405 return TRANSLATE_FAIL; 406 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 407 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 408 return TRANSLATE_FAIL; 409 } else if ((pte & PTE_U) && ((mode != PRV_U) && 410 (!sum || access_type == MMU_INST_FETCH))) { 411 /* User PTE flags when not U mode and mstatus.SUM is not set, 412 or the access type is an instruction fetch */ 413 return TRANSLATE_FAIL; 414 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 415 /* Supervisor PTE flags when not S mode */ 416 return TRANSLATE_FAIL; 417 } else if (ppn & ((1ULL << ptshift) - 1)) { 418 /* Misaligned PPN */ 419 return TRANSLATE_FAIL; 420 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 421 ((pte & PTE_X) && mxr))) { 422 /* Read access check failed */ 423 return TRANSLATE_FAIL; 424 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 425 /* Write access check failed */ 426 return TRANSLATE_FAIL; 427 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 428 /* Fetch access check failed */ 429 return TRANSLATE_FAIL; 430 } else { 431 /* if necessary, set accessed and dirty bits. */ 432 target_ulong updated_pte = pte | PTE_A | 433 (access_type == MMU_DATA_STORE ? PTE_D : 0); 434 435 /* Page table updates need to be atomic with MTTCG enabled */ 436 if (updated_pte != pte) { 437 /* 438 * - if accessed or dirty bits need updating, and the PTE is 439 * in RAM, then we do so atomically with a compare and swap. 440 * - if the PTE is in IO space or ROM, then it can't be updated 441 * and we return TRANSLATE_FAIL. 442 * - if the PTE changed by the time we went to update it, then 443 * it is no longer valid and we must re-walk the page table. 444 */ 445 MemoryRegion *mr; 446 hwaddr l = sizeof(target_ulong), addr1; 447 mr = address_space_translate(cs->as, pte_addr, 448 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 449 if (memory_region_is_ram(mr)) { 450 target_ulong *pte_pa = 451 qemu_map_ram_ptr(mr->ram_block, addr1); 452 #if TCG_OVERSIZED_GUEST 453 /* MTTCG is not enabled on oversized TCG guests so 454 * page table updates do not need to be atomic */ 455 *pte_pa = pte = updated_pte; 456 #else 457 target_ulong old_pte = 458 atomic_cmpxchg(pte_pa, pte, updated_pte); 459 if (old_pte != pte) { 460 goto restart; 461 } else { 462 pte = updated_pte; 463 } 464 #endif 465 } else { 466 /* misconfigured PTE in ROM (AD bits are not preset) or 467 * PTE is in IO space and can't be updated atomically */ 468 return TRANSLATE_FAIL; 469 } 470 } 471 472 /* for superpage mappings, make a fake leaf PTE for the TLB's 473 benefit. */ 474 target_ulong vpn = addr >> PGSHIFT; 475 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 476 477 /* set permissions on the TLB entry */ 478 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 479 *prot |= PAGE_READ; 480 } 481 if ((pte & PTE_X)) { 482 *prot |= PAGE_EXEC; 483 } 484 /* add write permission on stores or if the page is already dirty, 485 so that we TLB miss on later writes to update the dirty bit */ 486 if ((pte & PTE_W) && 487 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 488 *prot |= PAGE_WRITE; 489 } 490 return TRANSLATE_SUCCESS; 491 } 492 } 493 return TRANSLATE_FAIL; 494 } 495 496 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 497 MMUAccessType access_type, bool pmp_violation, 498 bool first_stage) 499 { 500 CPUState *cs = env_cpu(env); 501 int page_fault_exceptions; 502 if (first_stage) { 503 page_fault_exceptions = 504 (env->priv_ver >= PRIV_VERSION_1_10_0) && 505 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 506 !pmp_violation; 507 } else { 508 page_fault_exceptions = 509 get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE && 510 !pmp_violation; 511 } 512 switch (access_type) { 513 case MMU_INST_FETCH: 514 cs->exception_index = page_fault_exceptions ? 515 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 516 break; 517 case MMU_DATA_LOAD: 518 cs->exception_index = page_fault_exceptions ? 519 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 520 break; 521 case MMU_DATA_STORE: 522 cs->exception_index = page_fault_exceptions ? 523 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 524 break; 525 default: 526 g_assert_not_reached(); 527 } 528 env->badaddr = address; 529 } 530 531 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 532 { 533 RISCVCPU *cpu = RISCV_CPU(cs); 534 hwaddr phys_addr; 535 int prot; 536 int mmu_idx = cpu_mmu_index(&cpu->env, false); 537 538 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, 539 true)) { 540 return -1; 541 } 542 return phys_addr; 543 } 544 545 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 546 vaddr addr, unsigned size, 547 MMUAccessType access_type, 548 int mmu_idx, MemTxAttrs attrs, 549 MemTxResult response, uintptr_t retaddr) 550 { 551 RISCVCPU *cpu = RISCV_CPU(cs); 552 CPURISCVState *env = &cpu->env; 553 554 if (access_type == MMU_DATA_STORE) { 555 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 556 } else { 557 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 558 } 559 560 env->badaddr = addr; 561 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 562 } 563 564 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 565 MMUAccessType access_type, int mmu_idx, 566 uintptr_t retaddr) 567 { 568 RISCVCPU *cpu = RISCV_CPU(cs); 569 CPURISCVState *env = &cpu->env; 570 switch (access_type) { 571 case MMU_INST_FETCH: 572 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 573 break; 574 case MMU_DATA_LOAD: 575 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 576 break; 577 case MMU_DATA_STORE: 578 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 579 break; 580 default: 581 g_assert_not_reached(); 582 } 583 env->badaddr = addr; 584 riscv_raise_exception(env, cs->exception_index, retaddr); 585 } 586 #endif 587 588 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 589 MMUAccessType access_type, int mmu_idx, 590 bool probe, uintptr_t retaddr) 591 { 592 RISCVCPU *cpu = RISCV_CPU(cs); 593 CPURISCVState *env = &cpu->env; 594 #ifndef CONFIG_USER_ONLY 595 hwaddr pa = 0; 596 int prot; 597 bool pmp_violation = false; 598 int ret = TRANSLATE_FAIL; 599 int mode = mmu_idx; 600 601 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 602 __func__, address, access_type, mmu_idx); 603 604 ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, 605 true); 606 607 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 608 if (get_field(env->mstatus, MSTATUS_MPRV)) { 609 mode = get_field(env->mstatus, MSTATUS_MPP); 610 } 611 } 612 613 qemu_log_mask(CPU_LOG_MMU, 614 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx 615 " prot %d\n", __func__, address, ret, pa, prot); 616 617 if (riscv_feature(env, RISCV_FEATURE_PMP) && 618 (ret == TRANSLATE_SUCCESS) && 619 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 620 ret = TRANSLATE_PMP_FAIL; 621 } 622 if (ret == TRANSLATE_PMP_FAIL) { 623 pmp_violation = true; 624 } 625 if (ret == TRANSLATE_SUCCESS) { 626 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 627 prot, mmu_idx, TARGET_PAGE_SIZE); 628 return true; 629 } else if (probe) { 630 return false; 631 } else { 632 raise_mmu_exception(env, address, access_type, pmp_violation, true); 633 riscv_raise_exception(env, cs->exception_index, retaddr); 634 } 635 #else 636 switch (access_type) { 637 case MMU_INST_FETCH: 638 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 639 break; 640 case MMU_DATA_LOAD: 641 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 642 break; 643 case MMU_DATA_STORE: 644 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 645 break; 646 default: 647 g_assert_not_reached(); 648 } 649 env->badaddr = address; 650 cpu_loop_exit_restore(cs, retaddr); 651 #endif 652 } 653 654 /* 655 * Handle Traps 656 * 657 * Adapted from Spike's processor_t::take_trap. 658 * 659 */ 660 void riscv_cpu_do_interrupt(CPUState *cs) 661 { 662 #if !defined(CONFIG_USER_ONLY) 663 664 RISCVCPU *cpu = RISCV_CPU(cs); 665 CPURISCVState *env = &cpu->env; 666 bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); 667 target_ulong s; 668 669 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 670 * so we mask off the MSB and separate into trap type and cause. 671 */ 672 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 673 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 674 target_ulong deleg = async ? env->mideleg : env->medeleg; 675 target_ulong tval = 0; 676 677 if (!async) { 678 /* set tval to badaddr for traps with address information */ 679 switch (cause) { 680 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 681 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 682 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 683 force_hs_execp = true; 684 /* fallthrough */ 685 case RISCV_EXCP_INST_ADDR_MIS: 686 case RISCV_EXCP_INST_ACCESS_FAULT: 687 case RISCV_EXCP_LOAD_ADDR_MIS: 688 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 689 case RISCV_EXCP_LOAD_ACCESS_FAULT: 690 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 691 case RISCV_EXCP_INST_PAGE_FAULT: 692 case RISCV_EXCP_LOAD_PAGE_FAULT: 693 case RISCV_EXCP_STORE_PAGE_FAULT: 694 tval = env->badaddr; 695 break; 696 default: 697 break; 698 } 699 /* ecall is dispatched as one cause so translate based on mode */ 700 if (cause == RISCV_EXCP_U_ECALL) { 701 assert(env->priv <= 3); 702 703 if (env->priv == PRV_M) { 704 cause = RISCV_EXCP_M_ECALL; 705 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 706 cause = RISCV_EXCP_VS_ECALL; 707 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 708 cause = RISCV_EXCP_S_ECALL; 709 } else if (env->priv == PRV_U) { 710 cause = RISCV_EXCP_U_ECALL; 711 } 712 } 713 } 714 715 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? 716 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 717 718 if (env->priv <= PRV_S && 719 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 720 /* handle the trap in S-mode */ 721 if (riscv_has_ext(env, RVH)) { 722 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 723 724 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && 725 !force_hs_execp) { 726 /* Trap to VS mode */ 727 } else if (riscv_cpu_virt_enabled(env)) { 728 /* Trap into HS mode, from virt */ 729 riscv_cpu_swap_hypervisor_regs(env); 730 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 731 get_field(env->hstatus, HSTATUS_SPV)); 732 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 733 get_field(env->mstatus, SSTATUS_SPP)); 734 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 735 riscv_cpu_virt_enabled(env)); 736 737 riscv_cpu_set_virt_enabled(env, 0); 738 riscv_cpu_set_force_hs_excep(env, 0); 739 } else { 740 /* Trap into HS mode */ 741 env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, 742 get_field(env->hstatus, HSTATUS_SPV)); 743 env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, 744 get_field(env->mstatus, SSTATUS_SPP)); 745 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 746 riscv_cpu_virt_enabled(env)); 747 } 748 } 749 750 s = env->mstatus; 751 s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 752 get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); 753 s = set_field(s, MSTATUS_SPP, env->priv); 754 s = set_field(s, MSTATUS_SIE, 0); 755 env->mstatus = s; 756 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 757 env->sepc = env->pc; 758 env->sbadaddr = tval; 759 env->pc = (env->stvec >> 2 << 2) + 760 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 761 riscv_cpu_set_mode(env, PRV_S); 762 } else { 763 /* handle the trap in M-mode */ 764 if (riscv_has_ext(env, RVH)) { 765 if (riscv_cpu_virt_enabled(env)) { 766 riscv_cpu_swap_hypervisor_regs(env); 767 } 768 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 769 riscv_cpu_virt_enabled(env)); 770 env->mstatus = set_field(env->mstatus, MSTATUS_MTL, 771 riscv_cpu_force_hs_excep_enabled(env)); 772 773 /* Trapping to M mode, virt is disabled */ 774 riscv_cpu_set_virt_enabled(env, 0); 775 riscv_cpu_set_force_hs_excep(env, 0); 776 } 777 778 s = env->mstatus; 779 s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 780 get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); 781 s = set_field(s, MSTATUS_MPP, env->priv); 782 s = set_field(s, MSTATUS_MIE, 0); 783 env->mstatus = s; 784 env->mcause = cause | ~(((target_ulong)-1) >> async); 785 env->mepc = env->pc; 786 env->mbadaddr = tval; 787 env->pc = (env->mtvec >> 2 << 2) + 788 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 789 riscv_cpu_set_mode(env, PRV_M); 790 } 791 792 /* NOTE: it is not necessary to yield load reservations here. It is only 793 * necessary for an SC from "another hart" to cause a load reservation 794 * to be yielded. Refer to the memory consistency model section of the 795 * RISC-V ISA Specification. 796 */ 797 798 #endif 799 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 800 } 801