1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "internals.h" 25 #include "pmu.h" 26 #include "exec/exec-all.h" 27 #include "instmap.h" 28 #include "tcg/tcg-op.h" 29 #include "trace.h" 30 #include "semihosting/common-semi.h" 31 #include "sysemu/cpu-timers.h" 32 #include "cpu_bits.h" 33 #include "debug.h" 34 35 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 36 { 37 #ifdef CONFIG_USER_ONLY 38 return 0; 39 #else 40 if (ifetch) { 41 return env->priv; 42 } 43 44 /* All priv -> mmu_idx mapping are here */ 45 int mode = env->priv; 46 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 47 mode = get_field(env->mstatus, MSTATUS_MPP); 48 } 49 if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { 50 return MMUIdx_S_SUM; 51 } 52 return mode; 53 #endif 54 } 55 56 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 57 target_ulong *cs_base, uint32_t *pflags) 58 { 59 CPUState *cs = env_cpu(env); 60 RISCVCPU *cpu = RISCV_CPU(cs); 61 RISCVExtStatus fs, vs; 62 uint32_t flags = 0; 63 64 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 65 *cs_base = 0; 66 67 if (cpu->cfg.ext_zve32f) { 68 /* 69 * If env->vl equals to VLMAX, we can use generic vector operation 70 * expanders (GVEC) to accerlate the vector operations. 71 * However, as LMUL could be a fractional number. The maximum 72 * vector size can be operated might be less than 8 bytes, 73 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 74 * only when maxsz >= 8 bytes. 75 */ 76 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 77 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 78 uint32_t maxsz = vlmax << sew; 79 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 80 (maxsz >= 8); 81 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 82 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 83 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 84 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 85 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 86 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 87 FIELD_EX64(env->vtype, VTYPE, VTA)); 88 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 89 FIELD_EX64(env->vtype, VTYPE, VMA)); 90 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); 91 } else { 92 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 93 } 94 95 #ifdef CONFIG_USER_ONLY 96 fs = EXT_STATUS_DIRTY; 97 vs = EXT_STATUS_DIRTY; 98 #else 99 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); 100 101 flags |= cpu_mmu_index(env, 0); 102 fs = get_field(env->mstatus, MSTATUS_FS); 103 vs = get_field(env->mstatus, MSTATUS_VS); 104 105 if (env->virt_enabled) { 106 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); 107 /* 108 * Merge DISABLED and !DIRTY states using MIN. 109 * We will set both fields when dirtying. 110 */ 111 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); 112 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); 113 } 114 115 if (cpu->cfg.debug && !icount_enabled()) { 116 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 117 } 118 #endif 119 120 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); 121 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); 122 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 123 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 124 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 125 } 126 if (env->cur_pmbase != 0) { 127 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 128 } 129 130 *pflags = flags; 131 } 132 133 void riscv_cpu_update_mask(CPURISCVState *env) 134 { 135 target_ulong mask = -1, base = 0; 136 /* 137 * TODO: Current RVJ spec does not specify 138 * how the extension interacts with XLEN. 139 */ 140 #ifndef CONFIG_USER_ONLY 141 if (riscv_has_ext(env, RVJ)) { 142 switch (env->priv) { 143 case PRV_M: 144 if (env->mmte & M_PM_ENABLE) { 145 mask = env->mpmmask; 146 base = env->mpmbase; 147 } 148 break; 149 case PRV_S: 150 if (env->mmte & S_PM_ENABLE) { 151 mask = env->spmmask; 152 base = env->spmbase; 153 } 154 break; 155 case PRV_U: 156 if (env->mmte & U_PM_ENABLE) { 157 mask = env->upmmask; 158 base = env->upmbase; 159 } 160 break; 161 default: 162 g_assert_not_reached(); 163 } 164 } 165 #endif 166 if (env->xl == MXL_RV32) { 167 env->cur_pmmask = mask & UINT32_MAX; 168 env->cur_pmbase = base & UINT32_MAX; 169 } else { 170 env->cur_pmmask = mask; 171 env->cur_pmbase = base; 172 } 173 } 174 175 #ifndef CONFIG_USER_ONLY 176 177 /* 178 * The HS-mode is allowed to configure priority only for the 179 * following VS-mode local interrupts: 180 * 181 * 0 (Reserved interrupt, reads as zero) 182 * 1 Supervisor software interrupt 183 * 4 (Reserved interrupt, reads as zero) 184 * 5 Supervisor timer interrupt 185 * 8 (Reserved interrupt, reads as zero) 186 * 13 (Reserved interrupt) 187 * 14 " 188 * 15 " 189 * 16 " 190 * 17 " 191 * 18 " 192 * 19 " 193 * 20 " 194 * 21 " 195 * 22 " 196 * 23 " 197 */ 198 199 static const int hviprio_index2irq[] = { 200 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 201 static const int hviprio_index2rdzero[] = { 202 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 203 204 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 205 { 206 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 207 return -EINVAL; 208 } 209 210 if (out_irq) { 211 *out_irq = hviprio_index2irq[index]; 212 } 213 214 if (out_rdzero) { 215 *out_rdzero = hviprio_index2rdzero[index]; 216 } 217 218 return 0; 219 } 220 221 /* 222 * Default priorities of local interrupts are defined in the 223 * RISC-V Advanced Interrupt Architecture specification. 224 * 225 * ---------------------------------------------------------------- 226 * Default | 227 * Priority | Major Interrupt Numbers 228 * ---------------------------------------------------------------- 229 * Highest | 47, 23, 46, 45, 22, 44, 230 * | 43, 21, 42, 41, 20, 40 231 * | 232 * | 11 (0b), 3 (03), 7 (07) 233 * | 9 (09), 1 (01), 5 (05) 234 * | 12 (0c) 235 * | 10 (0a), 2 (02), 6 (06) 236 * | 237 * | 39, 19, 38, 37, 18, 36, 238 * Lowest | 35, 17, 34, 33, 16, 32 239 * ---------------------------------------------------------------- 240 */ 241 static const uint8_t default_iprio[64] = { 242 /* Custom interrupts 48 to 63 */ 243 [63] = IPRIO_MMAXIPRIO, 244 [62] = IPRIO_MMAXIPRIO, 245 [61] = IPRIO_MMAXIPRIO, 246 [60] = IPRIO_MMAXIPRIO, 247 [59] = IPRIO_MMAXIPRIO, 248 [58] = IPRIO_MMAXIPRIO, 249 [57] = IPRIO_MMAXIPRIO, 250 [56] = IPRIO_MMAXIPRIO, 251 [55] = IPRIO_MMAXIPRIO, 252 [54] = IPRIO_MMAXIPRIO, 253 [53] = IPRIO_MMAXIPRIO, 254 [52] = IPRIO_MMAXIPRIO, 255 [51] = IPRIO_MMAXIPRIO, 256 [50] = IPRIO_MMAXIPRIO, 257 [49] = IPRIO_MMAXIPRIO, 258 [48] = IPRIO_MMAXIPRIO, 259 260 /* Custom interrupts 24 to 31 */ 261 [31] = IPRIO_MMAXIPRIO, 262 [30] = IPRIO_MMAXIPRIO, 263 [29] = IPRIO_MMAXIPRIO, 264 [28] = IPRIO_MMAXIPRIO, 265 [27] = IPRIO_MMAXIPRIO, 266 [26] = IPRIO_MMAXIPRIO, 267 [25] = IPRIO_MMAXIPRIO, 268 [24] = IPRIO_MMAXIPRIO, 269 270 [47] = IPRIO_DEFAULT_UPPER, 271 [23] = IPRIO_DEFAULT_UPPER + 1, 272 [46] = IPRIO_DEFAULT_UPPER + 2, 273 [45] = IPRIO_DEFAULT_UPPER + 3, 274 [22] = IPRIO_DEFAULT_UPPER + 4, 275 [44] = IPRIO_DEFAULT_UPPER + 5, 276 277 [43] = IPRIO_DEFAULT_UPPER + 6, 278 [21] = IPRIO_DEFAULT_UPPER + 7, 279 [42] = IPRIO_DEFAULT_UPPER + 8, 280 [41] = IPRIO_DEFAULT_UPPER + 9, 281 [20] = IPRIO_DEFAULT_UPPER + 10, 282 [40] = IPRIO_DEFAULT_UPPER + 11, 283 284 [11] = IPRIO_DEFAULT_M, 285 [3] = IPRIO_DEFAULT_M + 1, 286 [7] = IPRIO_DEFAULT_M + 2, 287 288 [9] = IPRIO_DEFAULT_S, 289 [1] = IPRIO_DEFAULT_S + 1, 290 [5] = IPRIO_DEFAULT_S + 2, 291 292 [12] = IPRIO_DEFAULT_SGEXT, 293 294 [10] = IPRIO_DEFAULT_VS, 295 [2] = IPRIO_DEFAULT_VS + 1, 296 [6] = IPRIO_DEFAULT_VS + 2, 297 298 [39] = IPRIO_DEFAULT_LOWER, 299 [19] = IPRIO_DEFAULT_LOWER + 1, 300 [38] = IPRIO_DEFAULT_LOWER + 2, 301 [37] = IPRIO_DEFAULT_LOWER + 3, 302 [18] = IPRIO_DEFAULT_LOWER + 4, 303 [36] = IPRIO_DEFAULT_LOWER + 5, 304 305 [35] = IPRIO_DEFAULT_LOWER + 6, 306 [17] = IPRIO_DEFAULT_LOWER + 7, 307 [34] = IPRIO_DEFAULT_LOWER + 8, 308 [33] = IPRIO_DEFAULT_LOWER + 9, 309 [16] = IPRIO_DEFAULT_LOWER + 10, 310 [32] = IPRIO_DEFAULT_LOWER + 11, 311 }; 312 313 uint8_t riscv_cpu_default_priority(int irq) 314 { 315 if (irq < 0 || irq > 63) { 316 return IPRIO_MMAXIPRIO; 317 } 318 319 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 320 }; 321 322 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 323 int extirq, unsigned int extirq_def_prio, 324 uint64_t pending, uint8_t *iprio) 325 { 326 int irq, best_irq = RISCV_EXCP_NONE; 327 unsigned int prio, best_prio = UINT_MAX; 328 329 if (!pending) { 330 return RISCV_EXCP_NONE; 331 } 332 333 irq = ctz64(pending); 334 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 335 riscv_cpu_cfg(env)->ext_ssaia)) { 336 return irq; 337 } 338 339 pending = pending >> irq; 340 while (pending) { 341 prio = iprio[irq]; 342 if (!prio) { 343 if (irq == extirq) { 344 prio = extirq_def_prio; 345 } else { 346 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 347 1 : IPRIO_MMAXIPRIO; 348 } 349 } 350 if ((pending & 0x1) && (prio <= best_prio)) { 351 best_irq = irq; 352 best_prio = prio; 353 } 354 irq++; 355 pending = pending >> 1; 356 } 357 358 return best_irq; 359 } 360 361 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 362 { 363 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 364 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 365 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 366 367 return (env->mip | vsgein | vstip) & env->mie; 368 } 369 370 int riscv_cpu_mirq_pending(CPURISCVState *env) 371 { 372 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 373 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 374 375 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 376 irqs, env->miprio); 377 } 378 379 int riscv_cpu_sirq_pending(CPURISCVState *env) 380 { 381 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 382 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 383 384 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 385 irqs, env->siprio); 386 } 387 388 int riscv_cpu_vsirq_pending(CPURISCVState *env) 389 { 390 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 391 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 392 393 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 394 irqs >> 1, env->hviprio); 395 } 396 397 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 398 { 399 int virq; 400 uint64_t irqs, pending, mie, hsie, vsie; 401 402 /* Determine interrupt enable state of all privilege modes */ 403 if (env->virt_enabled) { 404 mie = 1; 405 hsie = 1; 406 vsie = (env->priv < PRV_S) || 407 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 408 } else { 409 mie = (env->priv < PRV_M) || 410 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 411 hsie = (env->priv < PRV_S) || 412 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 413 vsie = 0; 414 } 415 416 /* Determine all pending interrupts */ 417 pending = riscv_cpu_all_pending(env); 418 419 /* Check M-mode interrupts */ 420 irqs = pending & ~env->mideleg & -mie; 421 if (irqs) { 422 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 423 irqs, env->miprio); 424 } 425 426 /* Check HS-mode interrupts */ 427 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 428 if (irqs) { 429 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 430 irqs, env->siprio); 431 } 432 433 /* Check VS-mode interrupts */ 434 irqs = pending & env->mideleg & env->hideleg & -vsie; 435 if (irqs) { 436 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 437 irqs >> 1, env->hviprio); 438 return (virq <= 0) ? virq : virq + 1; 439 } 440 441 /* Indicate no pending interrupt */ 442 return RISCV_EXCP_NONE; 443 } 444 445 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 446 { 447 if (interrupt_request & CPU_INTERRUPT_HARD) { 448 RISCVCPU *cpu = RISCV_CPU(cs); 449 CPURISCVState *env = &cpu->env; 450 int interruptno = riscv_cpu_local_irq_pending(env); 451 if (interruptno >= 0) { 452 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 453 riscv_cpu_do_interrupt(cs); 454 return true; 455 } 456 } 457 return false; 458 } 459 460 /* Return true is floating point support is currently enabled */ 461 bool riscv_cpu_fp_enabled(CPURISCVState *env) 462 { 463 if (env->mstatus & MSTATUS_FS) { 464 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 465 return false; 466 } 467 return true; 468 } 469 470 return false; 471 } 472 473 /* Return true is vector support is currently enabled */ 474 bool riscv_cpu_vector_enabled(CPURISCVState *env) 475 { 476 if (env->mstatus & MSTATUS_VS) { 477 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 478 return false; 479 } 480 return true; 481 } 482 483 return false; 484 } 485 486 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 487 { 488 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 489 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 490 MSTATUS64_UXL | MSTATUS_VS; 491 492 if (riscv_has_ext(env, RVF)) { 493 mstatus_mask |= MSTATUS_FS; 494 } 495 bool current_virt = env->virt_enabled; 496 497 g_assert(riscv_has_ext(env, RVH)); 498 499 if (current_virt) { 500 /* Current V=1 and we are about to change to V=0 */ 501 env->vsstatus = env->mstatus & mstatus_mask; 502 env->mstatus &= ~mstatus_mask; 503 env->mstatus |= env->mstatus_hs; 504 505 env->vstvec = env->stvec; 506 env->stvec = env->stvec_hs; 507 508 env->vsscratch = env->sscratch; 509 env->sscratch = env->sscratch_hs; 510 511 env->vsepc = env->sepc; 512 env->sepc = env->sepc_hs; 513 514 env->vscause = env->scause; 515 env->scause = env->scause_hs; 516 517 env->vstval = env->stval; 518 env->stval = env->stval_hs; 519 520 env->vsatp = env->satp; 521 env->satp = env->satp_hs; 522 } else { 523 /* Current V=0 and we are about to change to V=1 */ 524 env->mstatus_hs = env->mstatus & mstatus_mask; 525 env->mstatus &= ~mstatus_mask; 526 env->mstatus |= env->vsstatus; 527 528 env->stvec_hs = env->stvec; 529 env->stvec = env->vstvec; 530 531 env->sscratch_hs = env->sscratch; 532 env->sscratch = env->vsscratch; 533 534 env->sepc_hs = env->sepc; 535 env->sepc = env->vsepc; 536 537 env->scause_hs = env->scause; 538 env->scause = env->vscause; 539 540 env->stval_hs = env->stval; 541 env->stval = env->vstval; 542 543 env->satp_hs = env->satp; 544 env->satp = env->vsatp; 545 } 546 } 547 548 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 549 { 550 if (!riscv_has_ext(env, RVH)) { 551 return 0; 552 } 553 554 return env->geilen; 555 } 556 557 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 558 { 559 if (!riscv_has_ext(env, RVH)) { 560 return; 561 } 562 563 if (geilen > (TARGET_LONG_BITS - 1)) { 564 return; 565 } 566 567 env->geilen = geilen; 568 } 569 570 /* This function can only be called to set virt when RVH is enabled */ 571 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 572 { 573 /* Flush the TLB on all virt mode changes. */ 574 if (env->virt_enabled != enable) { 575 tlb_flush(env_cpu(env)); 576 } 577 578 env->virt_enabled = enable; 579 580 if (enable) { 581 /* 582 * The guest external interrupts from an interrupt controller are 583 * delivered only when the Guest/VM is running (i.e. V=1). This means 584 * any guest external interrupt which is triggered while the Guest/VM 585 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 586 * with sluggish response to serial console input and other I/O events. 587 * 588 * To solve this, we check and inject interrupt after setting V=1. 589 */ 590 riscv_cpu_update_mip(env, 0, 0); 591 } 592 } 593 594 bool riscv_cpu_two_stage_lookup(int mmu_idx) 595 { 596 return mmu_idx & MMU_HYP_ACCESS_BIT; 597 } 598 599 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 600 { 601 CPURISCVState *env = &cpu->env; 602 if (env->miclaim & interrupts) { 603 return -1; 604 } else { 605 env->miclaim |= interrupts; 606 return 0; 607 } 608 } 609 610 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 611 uint64_t value) 612 { 613 CPUState *cs = env_cpu(env); 614 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 615 616 if (env->virt_enabled) { 617 gein = get_field(env->hstatus, HSTATUS_VGEIN); 618 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 619 } 620 621 vstip = env->vstime_irq ? MIP_VSTIP : 0; 622 623 QEMU_IOTHREAD_LOCK_GUARD(); 624 625 env->mip = (env->mip & ~mask) | (value & mask); 626 627 if (env->mip | vsgein | vstip) { 628 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 629 } else { 630 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 631 } 632 633 return old; 634 } 635 636 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 637 void *arg) 638 { 639 env->rdtime_fn = fn; 640 env->rdtime_fn_arg = arg; 641 } 642 643 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 644 int (*rmw_fn)(void *arg, 645 target_ulong reg, 646 target_ulong *val, 647 target_ulong new_val, 648 target_ulong write_mask), 649 void *rmw_fn_arg) 650 { 651 if (priv <= PRV_M) { 652 env->aia_ireg_rmw_fn[priv] = rmw_fn; 653 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 654 } 655 } 656 657 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 658 { 659 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); 660 661 if (icount_enabled() && newpriv != env->priv) { 662 riscv_itrigger_update_priv(env); 663 } 664 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 665 env->priv = newpriv; 666 env->xl = cpu_recompute_xl(env); 667 riscv_cpu_update_mask(env); 668 669 /* 670 * Clear the load reservation - otherwise a reservation placed in one 671 * context/process can be used by another, resulting in an SC succeeding 672 * incorrectly. Version 2.2 of the ISA specification explicitly requires 673 * this behaviour, while later revisions say that the kernel "should" use 674 * an SC instruction to force the yielding of a load reservation on a 675 * preemptive context switch. As a result, do both. 676 */ 677 env->load_res = -1; 678 } 679 680 /* 681 * get_physical_address_pmp - check PMP permission for this physical address 682 * 683 * Match the PMP region and check permission for this physical address and it's 684 * TLB page. Returns 0 if the permission checking was successful 685 * 686 * @env: CPURISCVState 687 * @prot: The returned protection attributes 688 * @tlb_size: TLB page size containing addr. It could be modified after PMP 689 * permission checking. NULL if not set TLB page for addr. 690 * @addr: The physical address to be checked permission 691 * @access_type: The type of MMU access 692 * @mode: Indicates current privilege level. 693 */ 694 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 695 target_ulong *tlb_size, hwaddr addr, 696 int size, MMUAccessType access_type, 697 int mode) 698 { 699 pmp_priv_t pmp_priv; 700 int pmp_index = -1; 701 702 if (!riscv_cpu_cfg(env)->pmp) { 703 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 704 return TRANSLATE_SUCCESS; 705 } 706 707 pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type, 708 &pmp_priv, mode); 709 if (pmp_index < 0) { 710 *prot = 0; 711 return TRANSLATE_PMP_FAIL; 712 } 713 714 *prot = pmp_priv_to_page_prot(pmp_priv); 715 if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) { 716 target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 717 target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 718 719 *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea); 720 } 721 722 return TRANSLATE_SUCCESS; 723 } 724 725 /* 726 * get_physical_address - get the physical address for this virtual address 727 * 728 * Do a page table walk to obtain the physical address corresponding to a 729 * virtual address. Returns 0 if the translation was successful 730 * 731 * Adapted from Spike's mmu_t::translate and mmu_t::walk 732 * 733 * @env: CPURISCVState 734 * @physical: This will be set to the calculated physical address 735 * @prot: The returned protection attributes 736 * @addr: The virtual address or guest physical address to be translated 737 * @fault_pte_addr: If not NULL, this will be set to fault pte address 738 * when a error occurs on pte address translation. 739 * This will already be shifted to match htval. 740 * @access_type: The type of MMU access 741 * @mmu_idx: Indicates current privilege level 742 * @first_stage: Are we in first stage translation? 743 * Second stage is used for hypervisor guest translation 744 * @two_stage: Are we going to perform two stage translation 745 * @is_debug: Is this access from a debugger or the monitor? 746 */ 747 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 748 int *prot, vaddr addr, 749 target_ulong *fault_pte_addr, 750 int access_type, int mmu_idx, 751 bool first_stage, bool two_stage, 752 bool is_debug) 753 { 754 /* 755 * NOTE: the env->pc value visible here will not be 756 * correct, but the value visible to the exception handler 757 * (riscv_cpu_do_interrupt) is correct 758 */ 759 MemTxResult res; 760 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 761 int mode = env->priv; 762 bool use_background = false; 763 hwaddr ppn; 764 int napot_bits = 0; 765 target_ulong napot_mask; 766 767 /* 768 * Check if we should use the background registers for the two 769 * stage translation. We don't need to check if we actually need 770 * two stage translation as that happened before this function 771 * was called. Background registers will be used if the guest has 772 * forced a two stage translation to be on (in HS or M mode). 773 */ 774 if (!env->virt_enabled && two_stage) { 775 use_background = true; 776 } 777 778 /* 779 * MPRV does not affect the virtual-machine load/store 780 * instructions, HLV, HLVX, and HSV. 781 */ 782 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 783 mode = get_field(env->hstatus, HSTATUS_SPVP); 784 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 785 if (get_field(env->mstatus, MSTATUS_MPRV)) { 786 mode = get_field(env->mstatus, MSTATUS_MPP); 787 } 788 } 789 790 if (first_stage == false) { 791 /* 792 * We are in stage 2 translation, this is similar to stage 1. 793 * Stage 2 is always taken as U-mode 794 */ 795 mode = PRV_U; 796 } 797 798 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 799 *physical = addr; 800 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 801 return TRANSLATE_SUCCESS; 802 } 803 804 *prot = 0; 805 806 hwaddr base; 807 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 808 809 if (first_stage == true) { 810 mxr = get_field(env->mstatus, MSTATUS_MXR); 811 } else { 812 mxr = get_field(env->vsstatus, MSTATUS_MXR); 813 } 814 815 if (first_stage == true) { 816 if (use_background) { 817 if (riscv_cpu_mxl(env) == MXL_RV32) { 818 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 819 vm = get_field(env->vsatp, SATP32_MODE); 820 } else { 821 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 822 vm = get_field(env->vsatp, SATP64_MODE); 823 } 824 } else { 825 if (riscv_cpu_mxl(env) == MXL_RV32) { 826 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 827 vm = get_field(env->satp, SATP32_MODE); 828 } else { 829 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 830 vm = get_field(env->satp, SATP64_MODE); 831 } 832 } 833 widened = 0; 834 } else { 835 if (riscv_cpu_mxl(env) == MXL_RV32) { 836 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 837 vm = get_field(env->hgatp, SATP32_MODE); 838 } else { 839 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 840 vm = get_field(env->hgatp, SATP64_MODE); 841 } 842 widened = 2; 843 } 844 /* status.SUM will be ignored if execute on background */ 845 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 846 switch (vm) { 847 case VM_1_10_SV32: 848 levels = 2; ptidxbits = 10; ptesize = 4; break; 849 case VM_1_10_SV39: 850 levels = 3; ptidxbits = 9; ptesize = 8; break; 851 case VM_1_10_SV48: 852 levels = 4; ptidxbits = 9; ptesize = 8; break; 853 case VM_1_10_SV57: 854 levels = 5; ptidxbits = 9; ptesize = 8; break; 855 case VM_1_10_MBARE: 856 *physical = addr; 857 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 858 return TRANSLATE_SUCCESS; 859 default: 860 g_assert_not_reached(); 861 } 862 863 CPUState *cs = env_cpu(env); 864 int va_bits = PGSHIFT + levels * ptidxbits + widened; 865 target_ulong mask, masked_msbs; 866 867 if (TARGET_LONG_BITS > (va_bits - 1)) { 868 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 869 } else { 870 mask = 0; 871 } 872 masked_msbs = (addr >> (va_bits - 1)) & mask; 873 874 if (masked_msbs != 0 && masked_msbs != mask) { 875 return TRANSLATE_FAIL; 876 } 877 878 int ptshift = (levels - 1) * ptidxbits; 879 int i; 880 881 #if !TCG_OVERSIZED_GUEST 882 restart: 883 #endif 884 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 885 target_ulong idx; 886 if (i == 0) { 887 idx = (addr >> (PGSHIFT + ptshift)) & 888 ((1 << (ptidxbits + widened)) - 1); 889 } else { 890 idx = (addr >> (PGSHIFT + ptshift)) & 891 ((1 << ptidxbits) - 1); 892 } 893 894 /* check that physical address of PTE is legal */ 895 hwaddr pte_addr; 896 897 if (two_stage && first_stage) { 898 int vbase_prot; 899 hwaddr vbase; 900 901 /* Do the second stage translation on the base PTE address. */ 902 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 903 base, NULL, MMU_DATA_LOAD, 904 mmu_idx, false, true, 905 is_debug); 906 907 if (vbase_ret != TRANSLATE_SUCCESS) { 908 if (fault_pte_addr) { 909 *fault_pte_addr = (base + idx * ptesize) >> 2; 910 } 911 return TRANSLATE_G_STAGE_FAIL; 912 } 913 914 pte_addr = vbase + idx * ptesize; 915 } else { 916 pte_addr = base + idx * ptesize; 917 } 918 919 int pmp_prot; 920 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 921 sizeof(target_ulong), 922 MMU_DATA_LOAD, PRV_S); 923 if (pmp_ret != TRANSLATE_SUCCESS) { 924 return TRANSLATE_PMP_FAIL; 925 } 926 927 target_ulong pte; 928 if (riscv_cpu_mxl(env) == MXL_RV32) { 929 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 930 } else { 931 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 932 } 933 934 if (res != MEMTX_OK) { 935 return TRANSLATE_FAIL; 936 } 937 938 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 939 bool hade = env->menvcfg & MENVCFG_HADE; 940 941 if (first_stage && two_stage && env->virt_enabled) { 942 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 943 hade = hade && (env->henvcfg & HENVCFG_HADE); 944 } 945 946 if (riscv_cpu_sxl(env) == MXL_RV32) { 947 ppn = pte >> PTE_PPN_SHIFT; 948 } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { 949 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 950 } else { 951 ppn = pte >> PTE_PPN_SHIFT; 952 if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { 953 return TRANSLATE_FAIL; 954 } 955 } 956 957 if (!(pte & PTE_V)) { 958 /* Invalid PTE */ 959 return TRANSLATE_FAIL; 960 } else if (!pbmte && (pte & PTE_PBMT)) { 961 return TRANSLATE_FAIL; 962 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 963 /* Inner PTE, continue walking */ 964 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 965 return TRANSLATE_FAIL; 966 } 967 base = ppn << PGSHIFT; 968 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 969 /* Reserved leaf PTE flags: PTE_W */ 970 return TRANSLATE_FAIL; 971 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 972 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 973 return TRANSLATE_FAIL; 974 } else if ((pte & PTE_U) && ((mode != PRV_U) && 975 (!sum || access_type == MMU_INST_FETCH))) { 976 /* User PTE flags when not U mode and mstatus.SUM is not set, 977 or the access type is an instruction fetch */ 978 return TRANSLATE_FAIL; 979 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 980 /* Supervisor PTE flags when not S mode */ 981 return TRANSLATE_FAIL; 982 } else if (ppn & ((1ULL << ptshift) - 1)) { 983 /* Misaligned PPN */ 984 return TRANSLATE_FAIL; 985 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 986 ((pte & PTE_X) && mxr))) { 987 /* Read access check failed */ 988 return TRANSLATE_FAIL; 989 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 990 /* Write access check failed */ 991 return TRANSLATE_FAIL; 992 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 993 /* Fetch access check failed */ 994 return TRANSLATE_FAIL; 995 } else { 996 /* if necessary, set accessed and dirty bits. */ 997 target_ulong updated_pte = pte | PTE_A | 998 (access_type == MMU_DATA_STORE ? PTE_D : 0); 999 1000 /* Page table updates need to be atomic with MTTCG enabled */ 1001 if (updated_pte != pte) { 1002 if (!hade) { 1003 return TRANSLATE_FAIL; 1004 } 1005 1006 /* 1007 * - if accessed or dirty bits need updating, and the PTE is 1008 * in RAM, then we do so atomically with a compare and swap. 1009 * - if the PTE is in IO space or ROM, then it can't be updated 1010 * and we return TRANSLATE_FAIL. 1011 * - if the PTE changed by the time we went to update it, then 1012 * it is no longer valid and we must re-walk the page table. 1013 */ 1014 MemoryRegion *mr; 1015 hwaddr l = sizeof(target_ulong), addr1; 1016 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1017 false, MEMTXATTRS_UNSPECIFIED); 1018 if (memory_region_is_ram(mr)) { 1019 target_ulong *pte_pa = 1020 qemu_map_ram_ptr(mr->ram_block, addr1); 1021 #if TCG_OVERSIZED_GUEST 1022 /* 1023 * MTTCG is not enabled on oversized TCG guests so 1024 * page table updates do not need to be atomic 1025 */ 1026 *pte_pa = pte = updated_pte; 1027 #else 1028 target_ulong old_pte = 1029 qatomic_cmpxchg(pte_pa, pte, updated_pte); 1030 if (old_pte != pte) { 1031 goto restart; 1032 } else { 1033 pte = updated_pte; 1034 } 1035 #endif 1036 } else { 1037 /* 1038 * misconfigured PTE in ROM (AD bits are not preset) or 1039 * PTE is in IO space and can't be updated atomically 1040 */ 1041 return TRANSLATE_FAIL; 1042 } 1043 } 1044 1045 /* 1046 * for superpage mappings, make a fake leaf PTE for the TLB's 1047 * benefit. 1048 */ 1049 target_ulong vpn = addr >> PGSHIFT; 1050 1051 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1052 napot_bits = ctzl(ppn) + 1; 1053 if ((i != (levels - 1)) || (napot_bits != 4)) { 1054 return TRANSLATE_FAIL; 1055 } 1056 } 1057 1058 napot_mask = (1 << napot_bits) - 1; 1059 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1060 (vpn & (((target_ulong)1 << ptshift) - 1)) 1061 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1062 1063 /* set permissions on the TLB entry */ 1064 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 1065 *prot |= PAGE_READ; 1066 } 1067 if (pte & PTE_X) { 1068 *prot |= PAGE_EXEC; 1069 } 1070 /* 1071 * add write permission on stores or if the page is already dirty, 1072 * so that we TLB miss on later writes to update the dirty bit 1073 */ 1074 if ((pte & PTE_W) && 1075 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 1076 *prot |= PAGE_WRITE; 1077 } 1078 return TRANSLATE_SUCCESS; 1079 } 1080 } 1081 return TRANSLATE_FAIL; 1082 } 1083 1084 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1085 MMUAccessType access_type, bool pmp_violation, 1086 bool first_stage, bool two_stage, 1087 bool two_stage_indirect) 1088 { 1089 CPUState *cs = env_cpu(env); 1090 int page_fault_exceptions, vm; 1091 uint64_t stap_mode; 1092 1093 if (riscv_cpu_mxl(env) == MXL_RV32) { 1094 stap_mode = SATP32_MODE; 1095 } else { 1096 stap_mode = SATP64_MODE; 1097 } 1098 1099 if (first_stage) { 1100 vm = get_field(env->satp, stap_mode); 1101 } else { 1102 vm = get_field(env->hgatp, stap_mode); 1103 } 1104 1105 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1106 1107 switch (access_type) { 1108 case MMU_INST_FETCH: 1109 if (env->virt_enabled && !first_stage) { 1110 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1111 } else { 1112 cs->exception_index = page_fault_exceptions ? 1113 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1114 } 1115 break; 1116 case MMU_DATA_LOAD: 1117 if (two_stage && !first_stage) { 1118 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1119 } else { 1120 cs->exception_index = page_fault_exceptions ? 1121 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1122 } 1123 break; 1124 case MMU_DATA_STORE: 1125 if (two_stage && !first_stage) { 1126 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1127 } else { 1128 cs->exception_index = page_fault_exceptions ? 1129 RISCV_EXCP_STORE_PAGE_FAULT : 1130 RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1131 } 1132 break; 1133 default: 1134 g_assert_not_reached(); 1135 } 1136 env->badaddr = address; 1137 env->two_stage_lookup = two_stage; 1138 env->two_stage_indirect_lookup = two_stage_indirect; 1139 } 1140 1141 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1142 { 1143 RISCVCPU *cpu = RISCV_CPU(cs); 1144 CPURISCVState *env = &cpu->env; 1145 hwaddr phys_addr; 1146 int prot; 1147 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1148 1149 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1150 true, env->virt_enabled, true)) { 1151 return -1; 1152 } 1153 1154 if (env->virt_enabled) { 1155 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1156 0, mmu_idx, false, true, true)) { 1157 return -1; 1158 } 1159 } 1160 1161 return phys_addr & TARGET_PAGE_MASK; 1162 } 1163 1164 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1165 vaddr addr, unsigned size, 1166 MMUAccessType access_type, 1167 int mmu_idx, MemTxAttrs attrs, 1168 MemTxResult response, uintptr_t retaddr) 1169 { 1170 RISCVCPU *cpu = RISCV_CPU(cs); 1171 CPURISCVState *env = &cpu->env; 1172 1173 if (access_type == MMU_DATA_STORE) { 1174 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1175 } else if (access_type == MMU_DATA_LOAD) { 1176 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1177 } else { 1178 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1179 } 1180 1181 env->badaddr = addr; 1182 env->two_stage_lookup = env->virt_enabled || 1183 riscv_cpu_two_stage_lookup(mmu_idx); 1184 env->two_stage_indirect_lookup = false; 1185 cpu_loop_exit_restore(cs, retaddr); 1186 } 1187 1188 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1189 MMUAccessType access_type, int mmu_idx, 1190 uintptr_t retaddr) 1191 { 1192 RISCVCPU *cpu = RISCV_CPU(cs); 1193 CPURISCVState *env = &cpu->env; 1194 switch (access_type) { 1195 case MMU_INST_FETCH: 1196 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1197 break; 1198 case MMU_DATA_LOAD: 1199 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1200 break; 1201 case MMU_DATA_STORE: 1202 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1203 break; 1204 default: 1205 g_assert_not_reached(); 1206 } 1207 env->badaddr = addr; 1208 env->two_stage_lookup = env->virt_enabled || 1209 riscv_cpu_two_stage_lookup(mmu_idx); 1210 env->two_stage_indirect_lookup = false; 1211 cpu_loop_exit_restore(cs, retaddr); 1212 } 1213 1214 1215 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1216 { 1217 enum riscv_pmu_event_idx pmu_event_type; 1218 1219 switch (access_type) { 1220 case MMU_INST_FETCH: 1221 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1222 break; 1223 case MMU_DATA_LOAD: 1224 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1225 break; 1226 case MMU_DATA_STORE: 1227 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1228 break; 1229 default: 1230 return; 1231 } 1232 1233 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1234 } 1235 1236 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1237 MMUAccessType access_type, int mmu_idx, 1238 bool probe, uintptr_t retaddr) 1239 { 1240 RISCVCPU *cpu = RISCV_CPU(cs); 1241 CPURISCVState *env = &cpu->env; 1242 vaddr im_address; 1243 hwaddr pa = 0; 1244 int prot, prot2, prot_pmp; 1245 bool pmp_violation = false; 1246 bool first_stage_error = true; 1247 bool two_stage_lookup = false; 1248 bool two_stage_indirect_error = false; 1249 int ret = TRANSLATE_FAIL; 1250 int mode = mmu_idx; 1251 /* default TLB page size */ 1252 target_ulong tlb_size = TARGET_PAGE_SIZE; 1253 1254 env->guest_phys_fault_addr = 0; 1255 1256 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1257 __func__, address, access_type, mmu_idx); 1258 1259 /* 1260 * MPRV does not affect the virtual-machine load/store 1261 * instructions, HLV, HLVX, and HSV. 1262 */ 1263 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 1264 mode = get_field(env->hstatus, HSTATUS_SPVP); 1265 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 1266 get_field(env->mstatus, MSTATUS_MPRV)) { 1267 mode = get_field(env->mstatus, MSTATUS_MPP); 1268 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 1269 two_stage_lookup = true; 1270 } 1271 } 1272 1273 pmu_tlb_fill_incr_ctr(cpu, access_type); 1274 if (env->virt_enabled || 1275 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 1276 access_type != MMU_INST_FETCH)) { 1277 /* Two stage lookup */ 1278 ret = get_physical_address(env, &pa, &prot, address, 1279 &env->guest_phys_fault_addr, access_type, 1280 mmu_idx, true, true, false); 1281 1282 /* 1283 * A G-stage exception may be triggered during two state lookup. 1284 * And the env->guest_phys_fault_addr has already been set in 1285 * get_physical_address(). 1286 */ 1287 if (ret == TRANSLATE_G_STAGE_FAIL) { 1288 first_stage_error = false; 1289 two_stage_indirect_error = true; 1290 access_type = MMU_DATA_LOAD; 1291 } 1292 1293 qemu_log_mask(CPU_LOG_MMU, 1294 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1295 HWADDR_FMT_plx " prot %d\n", 1296 __func__, address, ret, pa, prot); 1297 1298 if (ret == TRANSLATE_SUCCESS) { 1299 /* Second stage lookup */ 1300 im_address = pa; 1301 1302 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1303 access_type, mmu_idx, false, true, 1304 false); 1305 1306 qemu_log_mask(CPU_LOG_MMU, 1307 "%s 2nd-stage address=%" VADDR_PRIx 1308 " ret %d physical " 1309 HWADDR_FMT_plx " prot %d\n", 1310 __func__, im_address, ret, pa, prot2); 1311 1312 prot &= prot2; 1313 1314 if (ret == TRANSLATE_SUCCESS) { 1315 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1316 size, access_type, mode); 1317 1318 qemu_log_mask(CPU_LOG_MMU, 1319 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1320 " %d tlb_size " TARGET_FMT_lu "\n", 1321 __func__, pa, ret, prot_pmp, tlb_size); 1322 1323 prot &= prot_pmp; 1324 } 1325 1326 if (ret != TRANSLATE_SUCCESS) { 1327 /* 1328 * Guest physical address translation failed, this is a HS 1329 * level exception 1330 */ 1331 first_stage_error = false; 1332 env->guest_phys_fault_addr = (im_address | 1333 (address & 1334 (TARGET_PAGE_SIZE - 1))) >> 2; 1335 } 1336 } 1337 } else { 1338 /* Single stage lookup */ 1339 ret = get_physical_address(env, &pa, &prot, address, NULL, 1340 access_type, mmu_idx, true, false, false); 1341 1342 qemu_log_mask(CPU_LOG_MMU, 1343 "%s address=%" VADDR_PRIx " ret %d physical " 1344 HWADDR_FMT_plx " prot %d\n", 1345 __func__, address, ret, pa, prot); 1346 1347 if (ret == TRANSLATE_SUCCESS) { 1348 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1349 size, access_type, mode); 1350 1351 qemu_log_mask(CPU_LOG_MMU, 1352 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1353 " %d tlb_size " TARGET_FMT_lu "\n", 1354 __func__, pa, ret, prot_pmp, tlb_size); 1355 1356 prot &= prot_pmp; 1357 } 1358 } 1359 1360 if (ret == TRANSLATE_PMP_FAIL) { 1361 pmp_violation = true; 1362 } 1363 1364 if (ret == TRANSLATE_SUCCESS) { 1365 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1366 prot, mmu_idx, tlb_size); 1367 return true; 1368 } else if (probe) { 1369 return false; 1370 } else { 1371 raise_mmu_exception(env, address, access_type, pmp_violation, 1372 first_stage_error, 1373 env->virt_enabled || 1374 riscv_cpu_two_stage_lookup(mmu_idx), 1375 two_stage_indirect_error); 1376 cpu_loop_exit_restore(cs, retaddr); 1377 } 1378 1379 return true; 1380 } 1381 1382 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1383 target_ulong insn, 1384 target_ulong taddr) 1385 { 1386 target_ulong xinsn = 0; 1387 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1388 1389 /* 1390 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1391 * be uncompressed. The Quadrant 1 of RVC instruction space need 1392 * not be transformed because these instructions won't generate 1393 * any load/store trap. 1394 */ 1395 1396 if ((insn & 0x3) != 0x3) { 1397 /* Transform 16bit instruction into 32bit instruction */ 1398 switch (GET_C_OP(insn)) { 1399 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1400 switch (GET_C_FUNC(insn)) { 1401 case OPC_RISC_C_FUNC_FLD_LQ: 1402 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1403 xinsn = OPC_RISC_FLD; 1404 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1405 access_rs1 = GET_C_RS1S(insn); 1406 access_imm = GET_C_LD_IMM(insn); 1407 access_size = 8; 1408 } 1409 break; 1410 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1411 xinsn = OPC_RISC_LW; 1412 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1413 access_rs1 = GET_C_RS1S(insn); 1414 access_imm = GET_C_LW_IMM(insn); 1415 access_size = 4; 1416 break; 1417 case OPC_RISC_C_FUNC_FLW_LD: 1418 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1419 xinsn = OPC_RISC_FLW; 1420 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1421 access_rs1 = GET_C_RS1S(insn); 1422 access_imm = GET_C_LW_IMM(insn); 1423 access_size = 4; 1424 } else { /* C.LD (RV64/RV128) */ 1425 xinsn = OPC_RISC_LD; 1426 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1427 access_rs1 = GET_C_RS1S(insn); 1428 access_imm = GET_C_LD_IMM(insn); 1429 access_size = 8; 1430 } 1431 break; 1432 case OPC_RISC_C_FUNC_FSD_SQ: 1433 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1434 xinsn = OPC_RISC_FSD; 1435 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1436 access_rs1 = GET_C_RS1S(insn); 1437 access_imm = GET_C_SD_IMM(insn); 1438 access_size = 8; 1439 } 1440 break; 1441 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1442 xinsn = OPC_RISC_SW; 1443 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1444 access_rs1 = GET_C_RS1S(insn); 1445 access_imm = GET_C_SW_IMM(insn); 1446 access_size = 4; 1447 break; 1448 case OPC_RISC_C_FUNC_FSW_SD: 1449 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1450 xinsn = OPC_RISC_FSW; 1451 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1452 access_rs1 = GET_C_RS1S(insn); 1453 access_imm = GET_C_SW_IMM(insn); 1454 access_size = 4; 1455 } else { /* C.SD (RV64/RV128) */ 1456 xinsn = OPC_RISC_SD; 1457 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1458 access_rs1 = GET_C_RS1S(insn); 1459 access_imm = GET_C_SD_IMM(insn); 1460 access_size = 8; 1461 } 1462 break; 1463 default: 1464 break; 1465 } 1466 break; 1467 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1468 switch (GET_C_FUNC(insn)) { 1469 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1470 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1471 xinsn = OPC_RISC_FLD; 1472 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1473 access_rs1 = 2; 1474 access_imm = GET_C_LDSP_IMM(insn); 1475 access_size = 8; 1476 } 1477 break; 1478 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1479 xinsn = OPC_RISC_LW; 1480 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1481 access_rs1 = 2; 1482 access_imm = GET_C_LWSP_IMM(insn); 1483 access_size = 4; 1484 break; 1485 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1486 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1487 xinsn = OPC_RISC_FLW; 1488 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1489 access_rs1 = 2; 1490 access_imm = GET_C_LWSP_IMM(insn); 1491 access_size = 4; 1492 } else { /* C.LDSP (RV64/RV128) */ 1493 xinsn = OPC_RISC_LD; 1494 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1495 access_rs1 = 2; 1496 access_imm = GET_C_LDSP_IMM(insn); 1497 access_size = 8; 1498 } 1499 break; 1500 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1501 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1502 xinsn = OPC_RISC_FSD; 1503 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1504 access_rs1 = 2; 1505 access_imm = GET_C_SDSP_IMM(insn); 1506 access_size = 8; 1507 } 1508 break; 1509 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1510 xinsn = OPC_RISC_SW; 1511 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1512 access_rs1 = 2; 1513 access_imm = GET_C_SWSP_IMM(insn); 1514 access_size = 4; 1515 break; 1516 case 7: 1517 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1518 xinsn = OPC_RISC_FSW; 1519 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1520 access_rs1 = 2; 1521 access_imm = GET_C_SWSP_IMM(insn); 1522 access_size = 4; 1523 } else { /* C.SDSP (RV64/RV128) */ 1524 xinsn = OPC_RISC_SD; 1525 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1526 access_rs1 = 2; 1527 access_imm = GET_C_SDSP_IMM(insn); 1528 access_size = 8; 1529 } 1530 break; 1531 default: 1532 break; 1533 } 1534 break; 1535 default: 1536 break; 1537 } 1538 1539 /* 1540 * Clear Bit1 of transformed instruction to indicate that 1541 * original insruction was a 16bit instruction 1542 */ 1543 xinsn &= ~((target_ulong)0x2); 1544 } else { 1545 /* Transform 32bit (or wider) instructions */ 1546 switch (MASK_OP_MAJOR(insn)) { 1547 case OPC_RISC_ATOMIC: 1548 xinsn = insn; 1549 access_rs1 = GET_RS1(insn); 1550 access_size = 1 << GET_FUNCT3(insn); 1551 break; 1552 case OPC_RISC_LOAD: 1553 case OPC_RISC_FP_LOAD: 1554 xinsn = SET_I_IMM(insn, 0); 1555 access_rs1 = GET_RS1(insn); 1556 access_imm = GET_IMM(insn); 1557 access_size = 1 << GET_FUNCT3(insn); 1558 break; 1559 case OPC_RISC_STORE: 1560 case OPC_RISC_FP_STORE: 1561 xinsn = SET_S_IMM(insn, 0); 1562 access_rs1 = GET_RS1(insn); 1563 access_imm = GET_STORE_IMM(insn); 1564 access_size = 1 << GET_FUNCT3(insn); 1565 break; 1566 case OPC_RISC_SYSTEM: 1567 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1568 xinsn = insn; 1569 access_rs1 = GET_RS1(insn); 1570 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1571 access_size = 1 << access_size; 1572 } 1573 break; 1574 default: 1575 break; 1576 } 1577 } 1578 1579 if (access_size) { 1580 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1581 (access_size - 1)); 1582 } 1583 1584 return xinsn; 1585 } 1586 #endif /* !CONFIG_USER_ONLY */ 1587 1588 /* 1589 * Handle Traps 1590 * 1591 * Adapted from Spike's processor_t::take_trap. 1592 * 1593 */ 1594 void riscv_cpu_do_interrupt(CPUState *cs) 1595 { 1596 #if !defined(CONFIG_USER_ONLY) 1597 1598 RISCVCPU *cpu = RISCV_CPU(cs); 1599 CPURISCVState *env = &cpu->env; 1600 bool write_gva = false; 1601 uint64_t s; 1602 1603 /* 1604 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1605 * so we mask off the MSB and separate into trap type and cause. 1606 */ 1607 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1608 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1609 uint64_t deleg = async ? env->mideleg : env->medeleg; 1610 target_ulong tval = 0; 1611 target_ulong tinst = 0; 1612 target_ulong htval = 0; 1613 target_ulong mtval2 = 0; 1614 1615 if (cause == RISCV_EXCP_SEMIHOST) { 1616 do_common_semihosting(cs); 1617 env->pc += 4; 1618 return; 1619 } 1620 1621 if (!async) { 1622 /* set tval to badaddr for traps with address information */ 1623 switch (cause) { 1624 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1625 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1626 case RISCV_EXCP_LOAD_ADDR_MIS: 1627 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1628 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1629 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1630 case RISCV_EXCP_LOAD_PAGE_FAULT: 1631 case RISCV_EXCP_STORE_PAGE_FAULT: 1632 write_gva = env->two_stage_lookup; 1633 tval = env->badaddr; 1634 if (env->two_stage_indirect_lookup) { 1635 /* 1636 * special pseudoinstruction for G-stage fault taken while 1637 * doing VS-stage page table walk. 1638 */ 1639 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1640 } else { 1641 /* 1642 * The "Addr. Offset" field in transformed instruction is 1643 * non-zero only for misaligned access. 1644 */ 1645 tinst = riscv_transformed_insn(env, env->bins, tval); 1646 } 1647 break; 1648 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1649 case RISCV_EXCP_INST_ADDR_MIS: 1650 case RISCV_EXCP_INST_ACCESS_FAULT: 1651 case RISCV_EXCP_INST_PAGE_FAULT: 1652 write_gva = env->two_stage_lookup; 1653 tval = env->badaddr; 1654 if (env->two_stage_indirect_lookup) { 1655 /* 1656 * special pseudoinstruction for G-stage fault taken while 1657 * doing VS-stage page table walk. 1658 */ 1659 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1660 } 1661 break; 1662 case RISCV_EXCP_ILLEGAL_INST: 1663 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1664 tval = env->bins; 1665 break; 1666 case RISCV_EXCP_BREAKPOINT: 1667 if (cs->watchpoint_hit) { 1668 tval = cs->watchpoint_hit->hitaddr; 1669 cs->watchpoint_hit = NULL; 1670 } 1671 break; 1672 default: 1673 break; 1674 } 1675 /* ecall is dispatched as one cause so translate based on mode */ 1676 if (cause == RISCV_EXCP_U_ECALL) { 1677 assert(env->priv <= 3); 1678 1679 if (env->priv == PRV_M) { 1680 cause = RISCV_EXCP_M_ECALL; 1681 } else if (env->priv == PRV_S && env->virt_enabled) { 1682 cause = RISCV_EXCP_VS_ECALL; 1683 } else if (env->priv == PRV_S && !env->virt_enabled) { 1684 cause = RISCV_EXCP_S_ECALL; 1685 } else if (env->priv == PRV_U) { 1686 cause = RISCV_EXCP_U_ECALL; 1687 } 1688 } 1689 } 1690 1691 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1692 riscv_cpu_get_trap_name(cause, async)); 1693 1694 qemu_log_mask(CPU_LOG_INT, 1695 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1696 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1697 __func__, env->mhartid, async, cause, env->pc, tval, 1698 riscv_cpu_get_trap_name(cause, async)); 1699 1700 if (env->priv <= PRV_S && 1701 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1702 /* handle the trap in S-mode */ 1703 if (riscv_has_ext(env, RVH)) { 1704 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1705 1706 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1707 /* Trap to VS mode */ 1708 /* 1709 * See if we need to adjust cause. Yes if its VS mode interrupt 1710 * no if hypervisor has delegated one of hs mode's interrupt 1711 */ 1712 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1713 cause == IRQ_VS_EXT) { 1714 cause = cause - 1; 1715 } 1716 write_gva = false; 1717 } else if (env->virt_enabled) { 1718 /* Trap into HS mode, from virt */ 1719 riscv_cpu_swap_hypervisor_regs(env); 1720 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1721 env->priv); 1722 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1723 1724 htval = env->guest_phys_fault_addr; 1725 1726 riscv_cpu_set_virt_enabled(env, 0); 1727 } else { 1728 /* Trap into HS mode */ 1729 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1730 htval = env->guest_phys_fault_addr; 1731 } 1732 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1733 } 1734 1735 s = env->mstatus; 1736 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1737 s = set_field(s, MSTATUS_SPP, env->priv); 1738 s = set_field(s, MSTATUS_SIE, 0); 1739 env->mstatus = s; 1740 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1741 env->sepc = env->pc; 1742 env->stval = tval; 1743 env->htval = htval; 1744 env->htinst = tinst; 1745 env->pc = (env->stvec >> 2 << 2) + 1746 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1747 riscv_cpu_set_mode(env, PRV_S); 1748 } else { 1749 /* handle the trap in M-mode */ 1750 if (riscv_has_ext(env, RVH)) { 1751 if (env->virt_enabled) { 1752 riscv_cpu_swap_hypervisor_regs(env); 1753 } 1754 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1755 env->virt_enabled); 1756 if (env->virt_enabled && tval) { 1757 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1758 } 1759 1760 mtval2 = env->guest_phys_fault_addr; 1761 1762 /* Trapping to M mode, virt is disabled */ 1763 riscv_cpu_set_virt_enabled(env, 0); 1764 } 1765 1766 s = env->mstatus; 1767 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1768 s = set_field(s, MSTATUS_MPP, env->priv); 1769 s = set_field(s, MSTATUS_MIE, 0); 1770 env->mstatus = s; 1771 env->mcause = cause | ~(((target_ulong)-1) >> async); 1772 env->mepc = env->pc; 1773 env->mtval = tval; 1774 env->mtval2 = mtval2; 1775 env->mtinst = tinst; 1776 env->pc = (env->mtvec >> 2 << 2) + 1777 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1778 riscv_cpu_set_mode(env, PRV_M); 1779 } 1780 1781 /* 1782 * NOTE: it is not necessary to yield load reservations here. It is only 1783 * necessary for an SC from "another hart" to cause a load reservation 1784 * to be yielded. Refer to the memory consistency model section of the 1785 * RISC-V ISA Specification. 1786 */ 1787 1788 env->two_stage_lookup = false; 1789 env->two_stage_indirect_lookup = false; 1790 #endif 1791 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1792 } 1793