1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "trace.h" 27 #include "semihosting/common-semi.h" 28 29 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 30 { 31 #ifdef CONFIG_USER_ONLY 32 return 0; 33 #else 34 return env->priv; 35 #endif 36 } 37 38 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 39 target_ulong *cs_base, uint32_t *pflags) 40 { 41 CPUState *cs = env_cpu(env); 42 RISCVCPU *cpu = RISCV_CPU(cs); 43 44 uint32_t flags = 0; 45 46 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 47 *cs_base = 0; 48 49 if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 50 /* 51 * If env->vl equals to VLMAX, we can use generic vector operation 52 * expanders (GVEC) to accerlate the vector operations. 53 * However, as LMUL could be a fractional number. The maximum 54 * vector size can be operated might be less than 8 bytes, 55 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 56 * only when maxsz >= 8 bytes. 57 */ 58 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 59 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 60 uint32_t maxsz = vlmax << sew; 61 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 62 (maxsz >= 8); 63 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 64 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 65 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 66 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 67 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 68 } else { 69 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 70 } 71 72 #ifdef CONFIG_USER_ONLY 73 flags |= TB_FLAGS_MSTATUS_FS; 74 flags |= TB_FLAGS_MSTATUS_VS; 75 #else 76 flags |= cpu_mmu_index(env, 0); 77 if (riscv_cpu_fp_enabled(env)) { 78 flags |= env->mstatus & MSTATUS_FS; 79 } 80 81 if (riscv_cpu_vector_enabled(env)) { 82 flags |= env->mstatus & MSTATUS_VS; 83 } 84 85 if (riscv_has_ext(env, RVH)) { 86 if (env->priv == PRV_M || 87 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 88 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 89 get_field(env->hstatus, HSTATUS_HU))) { 90 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 91 } 92 93 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 94 get_field(env->mstatus_hs, MSTATUS_FS)); 95 96 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, 97 get_field(env->mstatus_hs, MSTATUS_VS)); 98 } 99 #endif 100 101 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 102 if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { 103 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 104 } 105 if (env->cur_pmbase != 0) { 106 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 107 } 108 109 *pflags = flags; 110 } 111 112 void riscv_cpu_update_mask(CPURISCVState *env) 113 { 114 target_ulong mask = -1, base = 0; 115 /* 116 * TODO: Current RVJ spec does not specify 117 * how the extension interacts with XLEN. 118 */ 119 #ifndef CONFIG_USER_ONLY 120 if (riscv_has_ext(env, RVJ)) { 121 switch (env->priv) { 122 case PRV_M: 123 if (env->mmte & M_PM_ENABLE) { 124 mask = env->mpmmask; 125 base = env->mpmbase; 126 } 127 break; 128 case PRV_S: 129 if (env->mmte & S_PM_ENABLE) { 130 mask = env->spmmask; 131 base = env->spmbase; 132 } 133 break; 134 case PRV_U: 135 if (env->mmte & U_PM_ENABLE) { 136 mask = env->upmmask; 137 base = env->upmbase; 138 } 139 break; 140 default: 141 g_assert_not_reached(); 142 } 143 } 144 #endif 145 if (env->xl == MXL_RV32) { 146 env->cur_pmmask = mask & UINT32_MAX; 147 env->cur_pmbase = base & UINT32_MAX; 148 } else { 149 env->cur_pmmask = mask; 150 env->cur_pmbase = base; 151 } 152 } 153 154 #ifndef CONFIG_USER_ONLY 155 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 156 { 157 target_ulong virt_enabled = riscv_cpu_virt_enabled(env); 158 159 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 160 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 161 162 target_ulong vsgemask = 163 (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN); 164 target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0; 165 166 target_ulong pending = (env->mip | vsgein) & env->mie; 167 168 target_ulong mie = env->priv < PRV_M || 169 (env->priv == PRV_M && mstatus_mie); 170 target_ulong sie = env->priv < PRV_S || 171 (env->priv == PRV_S && mstatus_sie); 172 target_ulong hsie = virt_enabled || sie; 173 target_ulong vsie = virt_enabled && sie; 174 175 target_ulong irqs = 176 (pending & ~env->mideleg & -mie) | 177 (pending & env->mideleg & ~env->hideleg & -hsie) | 178 (pending & env->mideleg & env->hideleg & -vsie); 179 180 if (irqs) { 181 return ctz64(irqs); /* since non-zero */ 182 } else { 183 return RISCV_EXCP_NONE; /* indicates no pending interrupt */ 184 } 185 } 186 187 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 188 { 189 if (interrupt_request & CPU_INTERRUPT_HARD) { 190 RISCVCPU *cpu = RISCV_CPU(cs); 191 CPURISCVState *env = &cpu->env; 192 int interruptno = riscv_cpu_local_irq_pending(env); 193 if (interruptno >= 0) { 194 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 195 riscv_cpu_do_interrupt(cs); 196 return true; 197 } 198 } 199 return false; 200 } 201 202 /* Return true is floating point support is currently enabled */ 203 bool riscv_cpu_fp_enabled(CPURISCVState *env) 204 { 205 if (env->mstatus & MSTATUS_FS) { 206 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { 207 return false; 208 } 209 return true; 210 } 211 212 return false; 213 } 214 215 /* Return true is vector support is currently enabled */ 216 bool riscv_cpu_vector_enabled(CPURISCVState *env) 217 { 218 if (env->mstatus & MSTATUS_VS) { 219 if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { 220 return false; 221 } 222 return true; 223 } 224 225 return false; 226 } 227 228 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 229 { 230 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | 231 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 232 MSTATUS64_UXL | MSTATUS_VS; 233 bool current_virt = riscv_cpu_virt_enabled(env); 234 235 g_assert(riscv_has_ext(env, RVH)); 236 237 if (current_virt) { 238 /* Current V=1 and we are about to change to V=0 */ 239 env->vsstatus = env->mstatus & mstatus_mask; 240 env->mstatus &= ~mstatus_mask; 241 env->mstatus |= env->mstatus_hs; 242 243 env->vstvec = env->stvec; 244 env->stvec = env->stvec_hs; 245 246 env->vsscratch = env->sscratch; 247 env->sscratch = env->sscratch_hs; 248 249 env->vsepc = env->sepc; 250 env->sepc = env->sepc_hs; 251 252 env->vscause = env->scause; 253 env->scause = env->scause_hs; 254 255 env->vstval = env->stval; 256 env->stval = env->stval_hs; 257 258 env->vsatp = env->satp; 259 env->satp = env->satp_hs; 260 } else { 261 /* Current V=0 and we are about to change to V=1 */ 262 env->mstatus_hs = env->mstatus & mstatus_mask; 263 env->mstatus &= ~mstatus_mask; 264 env->mstatus |= env->vsstatus; 265 266 env->stvec_hs = env->stvec; 267 env->stvec = env->vstvec; 268 269 env->sscratch_hs = env->sscratch; 270 env->sscratch = env->vsscratch; 271 272 env->sepc_hs = env->sepc; 273 env->sepc = env->vsepc; 274 275 env->scause_hs = env->scause; 276 env->scause = env->vscause; 277 278 env->stval_hs = env->stval; 279 env->stval = env->vstval; 280 281 env->satp_hs = env->satp; 282 env->satp = env->vsatp; 283 } 284 } 285 286 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 287 { 288 if (!riscv_has_ext(env, RVH)) { 289 return 0; 290 } 291 292 return env->geilen; 293 } 294 295 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 296 { 297 if (!riscv_has_ext(env, RVH)) { 298 return; 299 } 300 301 if (geilen > (TARGET_LONG_BITS - 1)) { 302 return; 303 } 304 305 env->geilen = geilen; 306 } 307 308 bool riscv_cpu_virt_enabled(CPURISCVState *env) 309 { 310 if (!riscv_has_ext(env, RVH)) { 311 return false; 312 } 313 314 return get_field(env->virt, VIRT_ONOFF); 315 } 316 317 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 318 { 319 if (!riscv_has_ext(env, RVH)) { 320 return; 321 } 322 323 /* Flush the TLB on all virt mode changes. */ 324 if (get_field(env->virt, VIRT_ONOFF) != enable) { 325 tlb_flush(env_cpu(env)); 326 } 327 328 env->virt = set_field(env->virt, VIRT_ONOFF, enable); 329 330 if (enable) { 331 /* 332 * The guest external interrupts from an interrupt controller are 333 * delivered only when the Guest/VM is running (i.e. V=1). This means 334 * any guest external interrupt which is triggered while the Guest/VM 335 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 336 * with sluggish response to serial console input and other I/O events. 337 * 338 * To solve this, we check and inject interrupt after setting V=1. 339 */ 340 riscv_cpu_update_mip(env_archcpu(env), 0, 0); 341 } 342 } 343 344 bool riscv_cpu_two_stage_lookup(int mmu_idx) 345 { 346 return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; 347 } 348 349 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 350 { 351 CPURISCVState *env = &cpu->env; 352 if (env->miclaim & interrupts) { 353 return -1; 354 } else { 355 env->miclaim |= interrupts; 356 return 0; 357 } 358 } 359 360 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 361 { 362 CPURISCVState *env = &cpu->env; 363 CPUState *cs = CPU(cpu); 364 uint32_t gein, vsgein = 0, old = env->mip; 365 bool locked = false; 366 367 if (riscv_cpu_virt_enabled(env)) { 368 gein = get_field(env->hstatus, HSTATUS_VGEIN); 369 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 370 } 371 372 if (!qemu_mutex_iothread_locked()) { 373 locked = true; 374 qemu_mutex_lock_iothread(); 375 } 376 377 env->mip = (env->mip & ~mask) | (value & mask); 378 379 if (env->mip | vsgein) { 380 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 381 } else { 382 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 383 } 384 385 if (locked) { 386 qemu_mutex_unlock_iothread(); 387 } 388 389 return old; 390 } 391 392 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 393 uint32_t arg) 394 { 395 env->rdtime_fn = fn; 396 env->rdtime_fn_arg = arg; 397 } 398 399 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 400 { 401 if (newpriv > PRV_M) { 402 g_assert_not_reached(); 403 } 404 if (newpriv == PRV_H) { 405 newpriv = PRV_U; 406 } 407 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 408 env->priv = newpriv; 409 env->xl = cpu_recompute_xl(env); 410 riscv_cpu_update_mask(env); 411 412 /* 413 * Clear the load reservation - otherwise a reservation placed in one 414 * context/process can be used by another, resulting in an SC succeeding 415 * incorrectly. Version 2.2 of the ISA specification explicitly requires 416 * this behaviour, while later revisions say that the kernel "should" use 417 * an SC instruction to force the yielding of a load reservation on a 418 * preemptive context switch. As a result, do both. 419 */ 420 env->load_res = -1; 421 } 422 423 /* 424 * get_physical_address_pmp - check PMP permission for this physical address 425 * 426 * Match the PMP region and check permission for this physical address and it's 427 * TLB page. Returns 0 if the permission checking was successful 428 * 429 * @env: CPURISCVState 430 * @prot: The returned protection attributes 431 * @tlb_size: TLB page size containing addr. It could be modified after PMP 432 * permission checking. NULL if not set TLB page for addr. 433 * @addr: The physical address to be checked permission 434 * @access_type: The type of MMU access 435 * @mode: Indicates current privilege level. 436 */ 437 static int get_physical_address_pmp(CPURISCVState *env, int *prot, 438 target_ulong *tlb_size, hwaddr addr, 439 int size, MMUAccessType access_type, 440 int mode) 441 { 442 pmp_priv_t pmp_priv; 443 target_ulong tlb_size_pmp = 0; 444 445 if (!riscv_feature(env, RISCV_FEATURE_PMP)) { 446 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 447 return TRANSLATE_SUCCESS; 448 } 449 450 if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, 451 mode)) { 452 *prot = 0; 453 return TRANSLATE_PMP_FAIL; 454 } 455 456 *prot = pmp_priv_to_page_prot(pmp_priv); 457 if (tlb_size != NULL) { 458 if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { 459 *tlb_size = tlb_size_pmp; 460 } 461 } 462 463 return TRANSLATE_SUCCESS; 464 } 465 466 /* get_physical_address - get the physical address for this virtual address 467 * 468 * Do a page table walk to obtain the physical address corresponding to a 469 * virtual address. Returns 0 if the translation was successful 470 * 471 * Adapted from Spike's mmu_t::translate and mmu_t::walk 472 * 473 * @env: CPURISCVState 474 * @physical: This will be set to the calculated physical address 475 * @prot: The returned protection attributes 476 * @addr: The virtual address to be translated 477 * @fault_pte_addr: If not NULL, this will be set to fault pte address 478 * when a error occurs on pte address translation. 479 * This will already be shifted to match htval. 480 * @access_type: The type of MMU access 481 * @mmu_idx: Indicates current privilege level 482 * @first_stage: Are we in first stage translation? 483 * Second stage is used for hypervisor guest translation 484 * @two_stage: Are we going to perform two stage translation 485 * @is_debug: Is this access from a debugger or the monitor? 486 */ 487 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 488 int *prot, target_ulong addr, 489 target_ulong *fault_pte_addr, 490 int access_type, int mmu_idx, 491 bool first_stage, bool two_stage, 492 bool is_debug) 493 { 494 /* NOTE: the env->pc value visible here will not be 495 * correct, but the value visible to the exception handler 496 * (riscv_cpu_do_interrupt) is correct */ 497 MemTxResult res; 498 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 499 int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; 500 bool use_background = false; 501 502 /* 503 * Check if we should use the background registers for the two 504 * stage translation. We don't need to check if we actually need 505 * two stage translation as that happened before this function 506 * was called. Background registers will be used if the guest has 507 * forced a two stage translation to be on (in HS or M mode). 508 */ 509 if (!riscv_cpu_virt_enabled(env) && two_stage) { 510 use_background = true; 511 } 512 513 /* MPRV does not affect the virtual-machine load/store 514 instructions, HLV, HLVX, and HSV. */ 515 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 516 mode = get_field(env->hstatus, HSTATUS_SPVP); 517 } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { 518 if (get_field(env->mstatus, MSTATUS_MPRV)) { 519 mode = get_field(env->mstatus, MSTATUS_MPP); 520 } 521 } 522 523 if (first_stage == false) { 524 /* We are in stage 2 translation, this is similar to stage 1. */ 525 /* Stage 2 is always taken as U-mode */ 526 mode = PRV_U; 527 } 528 529 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 530 *physical = addr; 531 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 532 return TRANSLATE_SUCCESS; 533 } 534 535 *prot = 0; 536 537 hwaddr base; 538 int levels, ptidxbits, ptesize, vm, sum, mxr, widened; 539 540 if (first_stage == true) { 541 mxr = get_field(env->mstatus, MSTATUS_MXR); 542 } else { 543 mxr = get_field(env->vsstatus, MSTATUS_MXR); 544 } 545 546 if (first_stage == true) { 547 if (use_background) { 548 if (riscv_cpu_mxl(env) == MXL_RV32) { 549 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 550 vm = get_field(env->vsatp, SATP32_MODE); 551 } else { 552 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 553 vm = get_field(env->vsatp, SATP64_MODE); 554 } 555 } else { 556 if (riscv_cpu_mxl(env) == MXL_RV32) { 557 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 558 vm = get_field(env->satp, SATP32_MODE); 559 } else { 560 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 561 vm = get_field(env->satp, SATP64_MODE); 562 } 563 } 564 widened = 0; 565 } else { 566 if (riscv_cpu_mxl(env) == MXL_RV32) { 567 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 568 vm = get_field(env->hgatp, SATP32_MODE); 569 } else { 570 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 571 vm = get_field(env->hgatp, SATP64_MODE); 572 } 573 widened = 2; 574 } 575 /* status.SUM will be ignored if execute on background */ 576 sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; 577 switch (vm) { 578 case VM_1_10_SV32: 579 levels = 2; ptidxbits = 10; ptesize = 4; break; 580 case VM_1_10_SV39: 581 levels = 3; ptidxbits = 9; ptesize = 8; break; 582 case VM_1_10_SV48: 583 levels = 4; ptidxbits = 9; ptesize = 8; break; 584 case VM_1_10_SV57: 585 levels = 5; ptidxbits = 9; ptesize = 8; break; 586 case VM_1_10_MBARE: 587 *physical = addr; 588 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 589 return TRANSLATE_SUCCESS; 590 default: 591 g_assert_not_reached(); 592 } 593 594 CPUState *cs = env_cpu(env); 595 int va_bits = PGSHIFT + levels * ptidxbits + widened; 596 target_ulong mask, masked_msbs; 597 598 if (TARGET_LONG_BITS > (va_bits - 1)) { 599 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 600 } else { 601 mask = 0; 602 } 603 masked_msbs = (addr >> (va_bits - 1)) & mask; 604 605 if (masked_msbs != 0 && masked_msbs != mask) { 606 return TRANSLATE_FAIL; 607 } 608 609 int ptshift = (levels - 1) * ptidxbits; 610 int i; 611 612 #if !TCG_OVERSIZED_GUEST 613 restart: 614 #endif 615 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 616 target_ulong idx; 617 if (i == 0) { 618 idx = (addr >> (PGSHIFT + ptshift)) & 619 ((1 << (ptidxbits + widened)) - 1); 620 } else { 621 idx = (addr >> (PGSHIFT + ptshift)) & 622 ((1 << ptidxbits) - 1); 623 } 624 625 /* check that physical address of PTE is legal */ 626 hwaddr pte_addr; 627 628 if (two_stage && first_stage) { 629 int vbase_prot; 630 hwaddr vbase; 631 632 /* Do the second stage translation on the base PTE address. */ 633 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 634 base, NULL, MMU_DATA_LOAD, 635 mmu_idx, false, true, 636 is_debug); 637 638 if (vbase_ret != TRANSLATE_SUCCESS) { 639 if (fault_pte_addr) { 640 *fault_pte_addr = (base + idx * ptesize) >> 2; 641 } 642 return TRANSLATE_G_STAGE_FAIL; 643 } 644 645 pte_addr = vbase + idx * ptesize; 646 } else { 647 pte_addr = base + idx * ptesize; 648 } 649 650 int pmp_prot; 651 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, 652 sizeof(target_ulong), 653 MMU_DATA_LOAD, PRV_S); 654 if (pmp_ret != TRANSLATE_SUCCESS) { 655 return TRANSLATE_PMP_FAIL; 656 } 657 658 target_ulong pte; 659 if (riscv_cpu_mxl(env) == MXL_RV32) { 660 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 661 } else { 662 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 663 } 664 665 if (res != MEMTX_OK) { 666 return TRANSLATE_FAIL; 667 } 668 669 hwaddr ppn = pte >> PTE_PPN_SHIFT; 670 671 if (!(pte & PTE_V)) { 672 /* Invalid PTE */ 673 return TRANSLATE_FAIL; 674 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 675 /* Inner PTE, continue walking */ 676 base = ppn << PGSHIFT; 677 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 678 /* Reserved leaf PTE flags: PTE_W */ 679 return TRANSLATE_FAIL; 680 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 681 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 682 return TRANSLATE_FAIL; 683 } else if ((pte & PTE_U) && ((mode != PRV_U) && 684 (!sum || access_type == MMU_INST_FETCH))) { 685 /* User PTE flags when not U mode and mstatus.SUM is not set, 686 or the access type is an instruction fetch */ 687 return TRANSLATE_FAIL; 688 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 689 /* Supervisor PTE flags when not S mode */ 690 return TRANSLATE_FAIL; 691 } else if (ppn & ((1ULL << ptshift) - 1)) { 692 /* Misaligned PPN */ 693 return TRANSLATE_FAIL; 694 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 695 ((pte & PTE_X) && mxr))) { 696 /* Read access check failed */ 697 return TRANSLATE_FAIL; 698 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 699 /* Write access check failed */ 700 return TRANSLATE_FAIL; 701 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 702 /* Fetch access check failed */ 703 return TRANSLATE_FAIL; 704 } else { 705 /* if necessary, set accessed and dirty bits. */ 706 target_ulong updated_pte = pte | PTE_A | 707 (access_type == MMU_DATA_STORE ? PTE_D : 0); 708 709 /* Page table updates need to be atomic with MTTCG enabled */ 710 if (updated_pte != pte) { 711 /* 712 * - if accessed or dirty bits need updating, and the PTE is 713 * in RAM, then we do so atomically with a compare and swap. 714 * - if the PTE is in IO space or ROM, then it can't be updated 715 * and we return TRANSLATE_FAIL. 716 * - if the PTE changed by the time we went to update it, then 717 * it is no longer valid and we must re-walk the page table. 718 */ 719 MemoryRegion *mr; 720 hwaddr l = sizeof(target_ulong), addr1; 721 mr = address_space_translate(cs->as, pte_addr, 722 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 723 if (memory_region_is_ram(mr)) { 724 target_ulong *pte_pa = 725 qemu_map_ram_ptr(mr->ram_block, addr1); 726 #if TCG_OVERSIZED_GUEST 727 /* MTTCG is not enabled on oversized TCG guests so 728 * page table updates do not need to be atomic */ 729 *pte_pa = pte = updated_pte; 730 #else 731 target_ulong old_pte = 732 qatomic_cmpxchg(pte_pa, pte, updated_pte); 733 if (old_pte != pte) { 734 goto restart; 735 } else { 736 pte = updated_pte; 737 } 738 #endif 739 } else { 740 /* misconfigured PTE in ROM (AD bits are not preset) or 741 * PTE is in IO space and can't be updated atomically */ 742 return TRANSLATE_FAIL; 743 } 744 } 745 746 /* for superpage mappings, make a fake leaf PTE for the TLB's 747 benefit. */ 748 target_ulong vpn = addr >> PGSHIFT; 749 *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | 750 (addr & ~TARGET_PAGE_MASK); 751 752 /* set permissions on the TLB entry */ 753 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 754 *prot |= PAGE_READ; 755 } 756 if ((pte & PTE_X)) { 757 *prot |= PAGE_EXEC; 758 } 759 /* add write permission on stores or if the page is already dirty, 760 so that we TLB miss on later writes to update the dirty bit */ 761 if ((pte & PTE_W) && 762 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 763 *prot |= PAGE_WRITE; 764 } 765 return TRANSLATE_SUCCESS; 766 } 767 } 768 return TRANSLATE_FAIL; 769 } 770 771 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 772 MMUAccessType access_type, bool pmp_violation, 773 bool first_stage, bool two_stage) 774 { 775 CPUState *cs = env_cpu(env); 776 int page_fault_exceptions, vm; 777 uint64_t stap_mode; 778 779 if (riscv_cpu_mxl(env) == MXL_RV32) { 780 stap_mode = SATP32_MODE; 781 } else { 782 stap_mode = SATP64_MODE; 783 } 784 785 if (first_stage) { 786 vm = get_field(env->satp, stap_mode); 787 } else { 788 vm = get_field(env->hgatp, stap_mode); 789 } 790 791 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 792 793 switch (access_type) { 794 case MMU_INST_FETCH: 795 if (riscv_cpu_virt_enabled(env) && !first_stage) { 796 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 797 } else { 798 cs->exception_index = page_fault_exceptions ? 799 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 800 } 801 break; 802 case MMU_DATA_LOAD: 803 if (two_stage && !first_stage) { 804 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 805 } else { 806 cs->exception_index = page_fault_exceptions ? 807 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 808 } 809 break; 810 case MMU_DATA_STORE: 811 if (two_stage && !first_stage) { 812 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 813 } else { 814 cs->exception_index = page_fault_exceptions ? 815 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 816 } 817 break; 818 default: 819 g_assert_not_reached(); 820 } 821 env->badaddr = address; 822 env->two_stage_lookup = two_stage; 823 } 824 825 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 826 { 827 RISCVCPU *cpu = RISCV_CPU(cs); 828 CPURISCVState *env = &cpu->env; 829 hwaddr phys_addr; 830 int prot; 831 int mmu_idx = cpu_mmu_index(&cpu->env, false); 832 833 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 834 true, riscv_cpu_virt_enabled(env), true)) { 835 return -1; 836 } 837 838 if (riscv_cpu_virt_enabled(env)) { 839 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 840 0, mmu_idx, false, true, true)) { 841 return -1; 842 } 843 } 844 845 return phys_addr & TARGET_PAGE_MASK; 846 } 847 848 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 849 vaddr addr, unsigned size, 850 MMUAccessType access_type, 851 int mmu_idx, MemTxAttrs attrs, 852 MemTxResult response, uintptr_t retaddr) 853 { 854 RISCVCPU *cpu = RISCV_CPU(cs); 855 CPURISCVState *env = &cpu->env; 856 857 if (access_type == MMU_DATA_STORE) { 858 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 859 } else if (access_type == MMU_DATA_LOAD) { 860 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 861 } else { 862 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 863 } 864 865 env->badaddr = addr; 866 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 867 riscv_cpu_two_stage_lookup(mmu_idx); 868 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 869 } 870 871 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 872 MMUAccessType access_type, int mmu_idx, 873 uintptr_t retaddr) 874 { 875 RISCVCPU *cpu = RISCV_CPU(cs); 876 CPURISCVState *env = &cpu->env; 877 switch (access_type) { 878 case MMU_INST_FETCH: 879 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 880 break; 881 case MMU_DATA_LOAD: 882 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 883 break; 884 case MMU_DATA_STORE: 885 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 886 break; 887 default: 888 g_assert_not_reached(); 889 } 890 env->badaddr = addr; 891 env->two_stage_lookup = riscv_cpu_virt_enabled(env) || 892 riscv_cpu_two_stage_lookup(mmu_idx); 893 riscv_raise_exception(env, cs->exception_index, retaddr); 894 } 895 896 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 897 MMUAccessType access_type, int mmu_idx, 898 bool probe, uintptr_t retaddr) 899 { 900 RISCVCPU *cpu = RISCV_CPU(cs); 901 CPURISCVState *env = &cpu->env; 902 vaddr im_address; 903 hwaddr pa = 0; 904 int prot, prot2, prot_pmp; 905 bool pmp_violation = false; 906 bool first_stage_error = true; 907 bool two_stage_lookup = false; 908 int ret = TRANSLATE_FAIL; 909 int mode = mmu_idx; 910 /* default TLB page size */ 911 target_ulong tlb_size = TARGET_PAGE_SIZE; 912 913 env->guest_phys_fault_addr = 0; 914 915 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 916 __func__, address, access_type, mmu_idx); 917 918 /* MPRV does not affect the virtual-machine load/store 919 instructions, HLV, HLVX, and HSV. */ 920 if (riscv_cpu_two_stage_lookup(mmu_idx)) { 921 mode = get_field(env->hstatus, HSTATUS_SPVP); 922 } else if (mode == PRV_M && access_type != MMU_INST_FETCH && 923 get_field(env->mstatus, MSTATUS_MPRV)) { 924 mode = get_field(env->mstatus, MSTATUS_MPP); 925 if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { 926 two_stage_lookup = true; 927 } 928 } 929 930 if (riscv_cpu_virt_enabled(env) || 931 ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && 932 access_type != MMU_INST_FETCH)) { 933 /* Two stage lookup */ 934 ret = get_physical_address(env, &pa, &prot, address, 935 &env->guest_phys_fault_addr, access_type, 936 mmu_idx, true, true, false); 937 938 /* 939 * A G-stage exception may be triggered during two state lookup. 940 * And the env->guest_phys_fault_addr has already been set in 941 * get_physical_address(). 942 */ 943 if (ret == TRANSLATE_G_STAGE_FAIL) { 944 first_stage_error = false; 945 access_type = MMU_DATA_LOAD; 946 } 947 948 qemu_log_mask(CPU_LOG_MMU, 949 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 950 TARGET_FMT_plx " prot %d\n", 951 __func__, address, ret, pa, prot); 952 953 if (ret == TRANSLATE_SUCCESS) { 954 /* Second stage lookup */ 955 im_address = pa; 956 957 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 958 access_type, mmu_idx, false, true, 959 false); 960 961 qemu_log_mask(CPU_LOG_MMU, 962 "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " 963 TARGET_FMT_plx " prot %d\n", 964 __func__, im_address, ret, pa, prot2); 965 966 prot &= prot2; 967 968 if (ret == TRANSLATE_SUCCESS) { 969 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 970 size, access_type, mode); 971 972 qemu_log_mask(CPU_LOG_MMU, 973 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 974 " %d tlb_size " TARGET_FMT_lu "\n", 975 __func__, pa, ret, prot_pmp, tlb_size); 976 977 prot &= prot_pmp; 978 } 979 980 if (ret != TRANSLATE_SUCCESS) { 981 /* 982 * Guest physical address translation failed, this is a HS 983 * level exception 984 */ 985 first_stage_error = false; 986 env->guest_phys_fault_addr = (im_address | 987 (address & 988 (TARGET_PAGE_SIZE - 1))) >> 2; 989 } 990 } 991 } else { 992 /* Single stage lookup */ 993 ret = get_physical_address(env, &pa, &prot, address, NULL, 994 access_type, mmu_idx, true, false, false); 995 996 qemu_log_mask(CPU_LOG_MMU, 997 "%s address=%" VADDR_PRIx " ret %d physical " 998 TARGET_FMT_plx " prot %d\n", 999 __func__, address, ret, pa, prot); 1000 1001 if (ret == TRANSLATE_SUCCESS) { 1002 ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, 1003 size, access_type, mode); 1004 1005 qemu_log_mask(CPU_LOG_MMU, 1006 "%s PMP address=" TARGET_FMT_plx " ret %d prot" 1007 " %d tlb_size " TARGET_FMT_lu "\n", 1008 __func__, pa, ret, prot_pmp, tlb_size); 1009 1010 prot &= prot_pmp; 1011 } 1012 } 1013 1014 if (ret == TRANSLATE_PMP_FAIL) { 1015 pmp_violation = true; 1016 } 1017 1018 if (ret == TRANSLATE_SUCCESS) { 1019 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1020 prot, mmu_idx, tlb_size); 1021 return true; 1022 } else if (probe) { 1023 return false; 1024 } else { 1025 raise_mmu_exception(env, address, access_type, pmp_violation, 1026 first_stage_error, 1027 riscv_cpu_virt_enabled(env) || 1028 riscv_cpu_two_stage_lookup(mmu_idx)); 1029 riscv_raise_exception(env, cs->exception_index, retaddr); 1030 } 1031 1032 return true; 1033 } 1034 #endif /* !CONFIG_USER_ONLY */ 1035 1036 /* 1037 * Handle Traps 1038 * 1039 * Adapted from Spike's processor_t::take_trap. 1040 * 1041 */ 1042 void riscv_cpu_do_interrupt(CPUState *cs) 1043 { 1044 #if !defined(CONFIG_USER_ONLY) 1045 1046 RISCVCPU *cpu = RISCV_CPU(cs); 1047 CPURISCVState *env = &cpu->env; 1048 bool write_gva = false; 1049 uint64_t s; 1050 1051 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1052 * so we mask off the MSB and separate into trap type and cause. 1053 */ 1054 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1055 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1056 target_ulong deleg = async ? env->mideleg : env->medeleg; 1057 target_ulong tval = 0; 1058 target_ulong htval = 0; 1059 target_ulong mtval2 = 0; 1060 1061 if (cause == RISCV_EXCP_SEMIHOST) { 1062 if (env->priv >= PRV_S) { 1063 env->gpr[xA0] = do_common_semihosting(cs); 1064 env->pc += 4; 1065 return; 1066 } 1067 cause = RISCV_EXCP_BREAKPOINT; 1068 } 1069 1070 if (!async) { 1071 /* set tval to badaddr for traps with address information */ 1072 switch (cause) { 1073 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1074 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1075 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1076 case RISCV_EXCP_INST_ADDR_MIS: 1077 case RISCV_EXCP_INST_ACCESS_FAULT: 1078 case RISCV_EXCP_LOAD_ADDR_MIS: 1079 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1080 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1081 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1082 case RISCV_EXCP_INST_PAGE_FAULT: 1083 case RISCV_EXCP_LOAD_PAGE_FAULT: 1084 case RISCV_EXCP_STORE_PAGE_FAULT: 1085 write_gva = true; 1086 tval = env->badaddr; 1087 break; 1088 case RISCV_EXCP_ILLEGAL_INST: 1089 tval = env->bins; 1090 break; 1091 default: 1092 break; 1093 } 1094 /* ecall is dispatched as one cause so translate based on mode */ 1095 if (cause == RISCV_EXCP_U_ECALL) { 1096 assert(env->priv <= 3); 1097 1098 if (env->priv == PRV_M) { 1099 cause = RISCV_EXCP_M_ECALL; 1100 } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 1101 cause = RISCV_EXCP_VS_ECALL; 1102 } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { 1103 cause = RISCV_EXCP_S_ECALL; 1104 } else if (env->priv == PRV_U) { 1105 cause = RISCV_EXCP_U_ECALL; 1106 } 1107 } 1108 } 1109 1110 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1111 riscv_cpu_get_trap_name(cause, async)); 1112 1113 qemu_log_mask(CPU_LOG_INT, 1114 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1115 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1116 __func__, env->mhartid, async, cause, env->pc, tval, 1117 riscv_cpu_get_trap_name(cause, async)); 1118 1119 if (env->priv <= PRV_S && 1120 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1121 /* handle the trap in S-mode */ 1122 if (riscv_has_ext(env, RVH)) { 1123 target_ulong hdeleg = async ? env->hideleg : env->hedeleg; 1124 1125 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { 1126 /* Trap to VS mode */ 1127 /* 1128 * See if we need to adjust cause. Yes if its VS mode interrupt 1129 * no if hypervisor has delegated one of hs mode's interrupt 1130 */ 1131 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1132 cause == IRQ_VS_EXT) { 1133 cause = cause - 1; 1134 } 1135 write_gva = false; 1136 } else if (riscv_cpu_virt_enabled(env)) { 1137 /* Trap into HS mode, from virt */ 1138 riscv_cpu_swap_hypervisor_regs(env); 1139 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1140 env->priv); 1141 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, 1142 riscv_cpu_virt_enabled(env)); 1143 1144 1145 htval = env->guest_phys_fault_addr; 1146 1147 riscv_cpu_set_virt_enabled(env, 0); 1148 } else { 1149 /* Trap into HS mode */ 1150 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1151 htval = env->guest_phys_fault_addr; 1152 write_gva = false; 1153 } 1154 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1155 } 1156 1157 s = env->mstatus; 1158 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1159 s = set_field(s, MSTATUS_SPP, env->priv); 1160 s = set_field(s, MSTATUS_SIE, 0); 1161 env->mstatus = s; 1162 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1163 env->sepc = env->pc; 1164 env->stval = tval; 1165 env->htval = htval; 1166 env->pc = (env->stvec >> 2 << 2) + 1167 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1168 riscv_cpu_set_mode(env, PRV_S); 1169 } else { 1170 /* handle the trap in M-mode */ 1171 if (riscv_has_ext(env, RVH)) { 1172 if (riscv_cpu_virt_enabled(env)) { 1173 riscv_cpu_swap_hypervisor_regs(env); 1174 } 1175 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1176 riscv_cpu_virt_enabled(env)); 1177 if (riscv_cpu_virt_enabled(env) && tval) { 1178 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1179 } 1180 1181 mtval2 = env->guest_phys_fault_addr; 1182 1183 /* Trapping to M mode, virt is disabled */ 1184 riscv_cpu_set_virt_enabled(env, 0); 1185 } 1186 1187 s = env->mstatus; 1188 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1189 s = set_field(s, MSTATUS_MPP, env->priv); 1190 s = set_field(s, MSTATUS_MIE, 0); 1191 env->mstatus = s; 1192 env->mcause = cause | ~(((target_ulong)-1) >> async); 1193 env->mepc = env->pc; 1194 env->mtval = tval; 1195 env->mtval2 = mtval2; 1196 env->pc = (env->mtvec >> 2 << 2) + 1197 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1198 riscv_cpu_set_mode(env, PRV_M); 1199 } 1200 1201 /* NOTE: it is not necessary to yield load reservations here. It is only 1202 * necessary for an SC from "another hart" to cause a load reservation 1203 * to be yielded. Refer to the memory consistency model section of the 1204 * RISC-V ISA Specification. 1205 */ 1206 1207 env->two_stage_lookup = false; 1208 #endif 1209 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1210 } 1211