1 /* RISC-V ISA constants */ 2 3 #ifndef TARGET_RISCV_CPU_BITS_H 4 #define TARGET_RISCV_CPU_BITS_H 5 6 #define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ 9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ 10 (uint64_t)(mask))) 11 12 /* Floating point round mode */ 13 #define FSR_RD_SHIFT 5 14 #define FSR_RD (0x7 << FSR_RD_SHIFT) 15 16 /* Floating point accrued exception flags */ 17 #define FPEXC_NX 0x01 18 #define FPEXC_UF 0x02 19 #define FPEXC_OF 0x04 20 #define FPEXC_DZ 0x08 21 #define FPEXC_NV 0x10 22 23 /* Floating point status register bits */ 24 #define FSR_AEXC_SHIFT 0 25 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 26 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 27 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 29 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 31 32 /* Vector Fixed-Point round model */ 33 #define FSR_VXRM_SHIFT 9 34 #define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) 35 36 /* Vector Fixed-Point saturation flag */ 37 #define FSR_VXSAT_SHIFT 8 38 #define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) 39 40 /* Control and Status Registers */ 41 42 /* User Trap Setup */ 43 #define CSR_USTATUS 0x000 44 #define CSR_UIE 0x004 45 #define CSR_UTVEC 0x005 46 47 /* User Trap Handling */ 48 #define CSR_USCRATCH 0x040 49 #define CSR_UEPC 0x041 50 #define CSR_UCAUSE 0x042 51 #define CSR_UTVAL 0x043 52 #define CSR_UIP 0x044 53 54 /* User Floating-Point CSRs */ 55 #define CSR_FFLAGS 0x001 56 #define CSR_FRM 0x002 57 #define CSR_FCSR 0x003 58 59 /* User Vector CSRs */ 60 #define CSR_VSTART 0x008 61 #define CSR_VXSAT 0x009 62 #define CSR_VXRM 0x00a 63 #define CSR_VL 0xc20 64 #define CSR_VTYPE 0xc21 65 66 /* User Timers and Counters */ 67 #define CSR_CYCLE 0xc00 68 #define CSR_TIME 0xc01 69 #define CSR_INSTRET 0xc02 70 #define CSR_HPMCOUNTER3 0xc03 71 #define CSR_HPMCOUNTER4 0xc04 72 #define CSR_HPMCOUNTER5 0xc05 73 #define CSR_HPMCOUNTER6 0xc06 74 #define CSR_HPMCOUNTER7 0xc07 75 #define CSR_HPMCOUNTER8 0xc08 76 #define CSR_HPMCOUNTER9 0xc09 77 #define CSR_HPMCOUNTER10 0xc0a 78 #define CSR_HPMCOUNTER11 0xc0b 79 #define CSR_HPMCOUNTER12 0xc0c 80 #define CSR_HPMCOUNTER13 0xc0d 81 #define CSR_HPMCOUNTER14 0xc0e 82 #define CSR_HPMCOUNTER15 0xc0f 83 #define CSR_HPMCOUNTER16 0xc10 84 #define CSR_HPMCOUNTER17 0xc11 85 #define CSR_HPMCOUNTER18 0xc12 86 #define CSR_HPMCOUNTER19 0xc13 87 #define CSR_HPMCOUNTER20 0xc14 88 #define CSR_HPMCOUNTER21 0xc15 89 #define CSR_HPMCOUNTER22 0xc16 90 #define CSR_HPMCOUNTER23 0xc17 91 #define CSR_HPMCOUNTER24 0xc18 92 #define CSR_HPMCOUNTER25 0xc19 93 #define CSR_HPMCOUNTER26 0xc1a 94 #define CSR_HPMCOUNTER27 0xc1b 95 #define CSR_HPMCOUNTER28 0xc1c 96 #define CSR_HPMCOUNTER29 0xc1d 97 #define CSR_HPMCOUNTER30 0xc1e 98 #define CSR_HPMCOUNTER31 0xc1f 99 #define CSR_CYCLEH 0xc80 100 #define CSR_TIMEH 0xc81 101 #define CSR_INSTRETH 0xc82 102 #define CSR_HPMCOUNTER3H 0xc83 103 #define CSR_HPMCOUNTER4H 0xc84 104 #define CSR_HPMCOUNTER5H 0xc85 105 #define CSR_HPMCOUNTER6H 0xc86 106 #define CSR_HPMCOUNTER7H 0xc87 107 #define CSR_HPMCOUNTER8H 0xc88 108 #define CSR_HPMCOUNTER9H 0xc89 109 #define CSR_HPMCOUNTER10H 0xc8a 110 #define CSR_HPMCOUNTER11H 0xc8b 111 #define CSR_HPMCOUNTER12H 0xc8c 112 #define CSR_HPMCOUNTER13H 0xc8d 113 #define CSR_HPMCOUNTER14H 0xc8e 114 #define CSR_HPMCOUNTER15H 0xc8f 115 #define CSR_HPMCOUNTER16H 0xc90 116 #define CSR_HPMCOUNTER17H 0xc91 117 #define CSR_HPMCOUNTER18H 0xc92 118 #define CSR_HPMCOUNTER19H 0xc93 119 #define CSR_HPMCOUNTER20H 0xc94 120 #define CSR_HPMCOUNTER21H 0xc95 121 #define CSR_HPMCOUNTER22H 0xc96 122 #define CSR_HPMCOUNTER23H 0xc97 123 #define CSR_HPMCOUNTER24H 0xc98 124 #define CSR_HPMCOUNTER25H 0xc99 125 #define CSR_HPMCOUNTER26H 0xc9a 126 #define CSR_HPMCOUNTER27H 0xc9b 127 #define CSR_HPMCOUNTER28H 0xc9c 128 #define CSR_HPMCOUNTER29H 0xc9d 129 #define CSR_HPMCOUNTER30H 0xc9e 130 #define CSR_HPMCOUNTER31H 0xc9f 131 132 /* Machine Timers and Counters */ 133 #define CSR_MCYCLE 0xb00 134 #define CSR_MINSTRET 0xb02 135 #define CSR_MCYCLEH 0xb80 136 #define CSR_MINSTRETH 0xb82 137 138 /* Machine Information Registers */ 139 #define CSR_MVENDORID 0xf11 140 #define CSR_MARCHID 0xf12 141 #define CSR_MIMPID 0xf13 142 #define CSR_MHARTID 0xf14 143 144 /* Machine Trap Setup */ 145 #define CSR_MSTATUS 0x300 146 #define CSR_MISA 0x301 147 #define CSR_MEDELEG 0x302 148 #define CSR_MIDELEG 0x303 149 #define CSR_MIE 0x304 150 #define CSR_MTVEC 0x305 151 #define CSR_MCOUNTEREN 0x306 152 153 /* 32-bit only */ 154 #define CSR_MSTATUSH 0x310 155 156 /* Machine Trap Handling */ 157 #define CSR_MSCRATCH 0x340 158 #define CSR_MEPC 0x341 159 #define CSR_MCAUSE 0x342 160 #define CSR_MTVAL 0x343 161 #define CSR_MIP 0x344 162 163 /* Supervisor Trap Setup */ 164 #define CSR_SSTATUS 0x100 165 #define CSR_SEDELEG 0x102 166 #define CSR_SIDELEG 0x103 167 #define CSR_SIE 0x104 168 #define CSR_STVEC 0x105 169 #define CSR_SCOUNTEREN 0x106 170 171 /* Supervisor Trap Handling */ 172 #define CSR_SSCRATCH 0x140 173 #define CSR_SEPC 0x141 174 #define CSR_SCAUSE 0x142 175 #define CSR_STVAL 0x143 176 #define CSR_SIP 0x144 177 178 /* Supervisor Protection and Translation */ 179 #define CSR_SPTBR 0x180 180 #define CSR_SATP 0x180 181 182 /* Hpervisor CSRs */ 183 #define CSR_HSTATUS 0x600 184 #define CSR_HEDELEG 0x602 185 #define CSR_HIDELEG 0x603 186 #define CSR_HIE 0x604 187 #define CSR_HCOUNTEREN 0x606 188 #define CSR_HGEIE 0x607 189 #define CSR_HTVAL 0x643 190 #define CSR_HVIP 0x645 191 #define CSR_HIP 0x644 192 #define CSR_HTINST 0x64A 193 #define CSR_HGEIP 0xE12 194 #define CSR_HGATP 0x680 195 #define CSR_HTIMEDELTA 0x605 196 #define CSR_HTIMEDELTAH 0x615 197 198 /* Virtual CSRs */ 199 #define CSR_VSSTATUS 0x200 200 #define CSR_VSIE 0x204 201 #define CSR_VSTVEC 0x205 202 #define CSR_VSSCRATCH 0x240 203 #define CSR_VSEPC 0x241 204 #define CSR_VSCAUSE 0x242 205 #define CSR_VSTVAL 0x243 206 #define CSR_VSIP 0x244 207 #define CSR_VSATP 0x280 208 209 #define CSR_MTINST 0x34a 210 #define CSR_MTVAL2 0x34b 211 212 /* Enhanced Physical Memory Protection (ePMP) */ 213 #define CSR_MSECCFG 0x390 214 #define CSR_MSECCFGH 0x391 215 /* Physical Memory Protection */ 216 #define CSR_PMPCFG0 0x3a0 217 #define CSR_PMPCFG1 0x3a1 218 #define CSR_PMPCFG2 0x3a2 219 #define CSR_PMPCFG3 0x3a3 220 #define CSR_PMPADDR0 0x3b0 221 #define CSR_PMPADDR1 0x3b1 222 #define CSR_PMPADDR2 0x3b2 223 #define CSR_PMPADDR3 0x3b3 224 #define CSR_PMPADDR4 0x3b4 225 #define CSR_PMPADDR5 0x3b5 226 #define CSR_PMPADDR6 0x3b6 227 #define CSR_PMPADDR7 0x3b7 228 #define CSR_PMPADDR8 0x3b8 229 #define CSR_PMPADDR9 0x3b9 230 #define CSR_PMPADDR10 0x3ba 231 #define CSR_PMPADDR11 0x3bb 232 #define CSR_PMPADDR12 0x3bc 233 #define CSR_PMPADDR13 0x3bd 234 #define CSR_PMPADDR14 0x3be 235 #define CSR_PMPADDR15 0x3bf 236 237 /* Debug/Trace Registers (shared with Debug Mode) */ 238 #define CSR_TSELECT 0x7a0 239 #define CSR_TDATA1 0x7a1 240 #define CSR_TDATA2 0x7a2 241 #define CSR_TDATA3 0x7a3 242 243 /* Debug Mode Registers */ 244 #define CSR_DCSR 0x7b0 245 #define CSR_DPC 0x7b1 246 #define CSR_DSCRATCH 0x7b2 247 248 /* Performance Counters */ 249 #define CSR_MHPMCOUNTER3 0xb03 250 #define CSR_MHPMCOUNTER4 0xb04 251 #define CSR_MHPMCOUNTER5 0xb05 252 #define CSR_MHPMCOUNTER6 0xb06 253 #define CSR_MHPMCOUNTER7 0xb07 254 #define CSR_MHPMCOUNTER8 0xb08 255 #define CSR_MHPMCOUNTER9 0xb09 256 #define CSR_MHPMCOUNTER10 0xb0a 257 #define CSR_MHPMCOUNTER11 0xb0b 258 #define CSR_MHPMCOUNTER12 0xb0c 259 #define CSR_MHPMCOUNTER13 0xb0d 260 #define CSR_MHPMCOUNTER14 0xb0e 261 #define CSR_MHPMCOUNTER15 0xb0f 262 #define CSR_MHPMCOUNTER16 0xb10 263 #define CSR_MHPMCOUNTER17 0xb11 264 #define CSR_MHPMCOUNTER18 0xb12 265 #define CSR_MHPMCOUNTER19 0xb13 266 #define CSR_MHPMCOUNTER20 0xb14 267 #define CSR_MHPMCOUNTER21 0xb15 268 #define CSR_MHPMCOUNTER22 0xb16 269 #define CSR_MHPMCOUNTER23 0xb17 270 #define CSR_MHPMCOUNTER24 0xb18 271 #define CSR_MHPMCOUNTER25 0xb19 272 #define CSR_MHPMCOUNTER26 0xb1a 273 #define CSR_MHPMCOUNTER27 0xb1b 274 #define CSR_MHPMCOUNTER28 0xb1c 275 #define CSR_MHPMCOUNTER29 0xb1d 276 #define CSR_MHPMCOUNTER30 0xb1e 277 #define CSR_MHPMCOUNTER31 0xb1f 278 #define CSR_MHPMEVENT3 0x323 279 #define CSR_MHPMEVENT4 0x324 280 #define CSR_MHPMEVENT5 0x325 281 #define CSR_MHPMEVENT6 0x326 282 #define CSR_MHPMEVENT7 0x327 283 #define CSR_MHPMEVENT8 0x328 284 #define CSR_MHPMEVENT9 0x329 285 #define CSR_MHPMEVENT10 0x32a 286 #define CSR_MHPMEVENT11 0x32b 287 #define CSR_MHPMEVENT12 0x32c 288 #define CSR_MHPMEVENT13 0x32d 289 #define CSR_MHPMEVENT14 0x32e 290 #define CSR_MHPMEVENT15 0x32f 291 #define CSR_MHPMEVENT16 0x330 292 #define CSR_MHPMEVENT17 0x331 293 #define CSR_MHPMEVENT18 0x332 294 #define CSR_MHPMEVENT19 0x333 295 #define CSR_MHPMEVENT20 0x334 296 #define CSR_MHPMEVENT21 0x335 297 #define CSR_MHPMEVENT22 0x336 298 #define CSR_MHPMEVENT23 0x337 299 #define CSR_MHPMEVENT24 0x338 300 #define CSR_MHPMEVENT25 0x339 301 #define CSR_MHPMEVENT26 0x33a 302 #define CSR_MHPMEVENT27 0x33b 303 #define CSR_MHPMEVENT28 0x33c 304 #define CSR_MHPMEVENT29 0x33d 305 #define CSR_MHPMEVENT30 0x33e 306 #define CSR_MHPMEVENT31 0x33f 307 #define CSR_MHPMCOUNTER3H 0xb83 308 #define CSR_MHPMCOUNTER4H 0xb84 309 #define CSR_MHPMCOUNTER5H 0xb85 310 #define CSR_MHPMCOUNTER6H 0xb86 311 #define CSR_MHPMCOUNTER7H 0xb87 312 #define CSR_MHPMCOUNTER8H 0xb88 313 #define CSR_MHPMCOUNTER9H 0xb89 314 #define CSR_MHPMCOUNTER10H 0xb8a 315 #define CSR_MHPMCOUNTER11H 0xb8b 316 #define CSR_MHPMCOUNTER12H 0xb8c 317 #define CSR_MHPMCOUNTER13H 0xb8d 318 #define CSR_MHPMCOUNTER14H 0xb8e 319 #define CSR_MHPMCOUNTER15H 0xb8f 320 #define CSR_MHPMCOUNTER16H 0xb90 321 #define CSR_MHPMCOUNTER17H 0xb91 322 #define CSR_MHPMCOUNTER18H 0xb92 323 #define CSR_MHPMCOUNTER19H 0xb93 324 #define CSR_MHPMCOUNTER20H 0xb94 325 #define CSR_MHPMCOUNTER21H 0xb95 326 #define CSR_MHPMCOUNTER22H 0xb96 327 #define CSR_MHPMCOUNTER23H 0xb97 328 #define CSR_MHPMCOUNTER24H 0xb98 329 #define CSR_MHPMCOUNTER25H 0xb99 330 #define CSR_MHPMCOUNTER26H 0xb9a 331 #define CSR_MHPMCOUNTER27H 0xb9b 332 #define CSR_MHPMCOUNTER28H 0xb9c 333 #define CSR_MHPMCOUNTER29H 0xb9d 334 #define CSR_MHPMCOUNTER30H 0xb9e 335 #define CSR_MHPMCOUNTER31H 0xb9f 336 337 /* mstatus CSR bits */ 338 #define MSTATUS_UIE 0x00000001 339 #define MSTATUS_SIE 0x00000002 340 #define MSTATUS_MIE 0x00000008 341 #define MSTATUS_UPIE 0x00000010 342 #define MSTATUS_SPIE 0x00000020 343 #define MSTATUS_UBE 0x00000040 344 #define MSTATUS_MPIE 0x00000080 345 #define MSTATUS_SPP 0x00000100 346 #define MSTATUS_MPP 0x00001800 347 #define MSTATUS_FS 0x00006000 348 #define MSTATUS_XS 0x00018000 349 #define MSTATUS_MPRV 0x00020000 350 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 351 #define MSTATUS_MXR 0x00080000 352 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 353 #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ 354 #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ 355 #define MSTATUS_GVA 0x4000000000ULL 356 #define MSTATUS_MPV 0x8000000000ULL 357 358 #define MSTATUS64_UXL 0x0000000300000000ULL 359 #define MSTATUS64_SXL 0x0000000C00000000ULL 360 361 #define MSTATUS32_SD 0x80000000 362 #define MSTATUS64_SD 0x8000000000000000ULL 363 364 #define MISA32_MXL 0xC0000000 365 #define MISA64_MXL 0xC000000000000000ULL 366 367 #define MXL_RV32 1 368 #define MXL_RV64 2 369 #define MXL_RV128 3 370 371 #if defined(TARGET_RISCV32) 372 #define MSTATUS_SD MSTATUS32_SD 373 #define MISA_MXL MISA32_MXL 374 #define MXL_VAL MXL_RV32 375 #elif defined(TARGET_RISCV64) 376 #define MSTATUS_SD MSTATUS64_SD 377 #define MISA_MXL MISA64_MXL 378 #define MXL_VAL MXL_RV64 379 #endif 380 381 /* sstatus CSR bits */ 382 #define SSTATUS_UIE 0x00000001 383 #define SSTATUS_SIE 0x00000002 384 #define SSTATUS_UPIE 0x00000010 385 #define SSTATUS_SPIE 0x00000020 386 #define SSTATUS_SPP 0x00000100 387 #define SSTATUS_FS 0x00006000 388 #define SSTATUS_XS 0x00018000 389 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 390 #define SSTATUS_MXR 0x00080000 391 392 #define SSTATUS32_SD 0x80000000 393 #define SSTATUS64_SD 0x8000000000000000ULL 394 395 /* hstatus CSR bits */ 396 #define HSTATUS_VSBE 0x00000020 397 #define HSTATUS_GVA 0x00000040 398 #define HSTATUS_SPV 0x00000080 399 #define HSTATUS_SPVP 0x00000100 400 #define HSTATUS_HU 0x00000200 401 #define HSTATUS_VGEIN 0x0003F000 402 #define HSTATUS_VTVM 0x00100000 403 #define HSTATUS_VTSR 0x00400000 404 #define HSTATUS_VSXL 0x300000000 405 406 #define HSTATUS32_WPRI 0xFF8FF87E 407 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL 408 409 #if defined(TARGET_RISCV32) 410 #define HSTATUS_WPRI HSTATUS32_WPRI 411 #elif defined(TARGET_RISCV64) 412 #define HSTATUS_WPRI HSTATUS64_WPRI 413 #endif 414 415 #define HCOUNTEREN_CY (1 << 0) 416 #define HCOUNTEREN_TM (1 << 1) 417 #define HCOUNTEREN_IR (1 << 2) 418 #define HCOUNTEREN_HPM3 (1 << 3) 419 420 /* Privilege modes */ 421 #define PRV_U 0 422 #define PRV_S 1 423 #define PRV_H 2 /* Reserved */ 424 #define PRV_M 3 425 426 /* Virtulisation Register Fields */ 427 #define VIRT_ONOFF 1 428 /* This is used to save state for when we take an exception. If this is set 429 * that means that we want to force a HS level exception (no matter what the 430 * delegation is set to). This will occur for things such as a second level 431 * page table fault. 432 */ 433 #define FORCE_HS_EXCEP 2 434 435 /* RV32 satp CSR field masks */ 436 #define SATP32_MODE 0x80000000 437 #define SATP32_ASID 0x7fc00000 438 #define SATP32_PPN 0x003fffff 439 440 /* RV64 satp CSR field masks */ 441 #define SATP64_MODE 0xF000000000000000ULL 442 #define SATP64_ASID 0x0FFFF00000000000ULL 443 #define SATP64_PPN 0x00000FFFFFFFFFFFULL 444 445 #if defined(TARGET_RISCV32) 446 #define SATP_MODE SATP32_MODE 447 #define SATP_ASID SATP32_ASID 448 #define SATP_PPN SATP32_PPN 449 #endif 450 #if defined(TARGET_RISCV64) 451 #define SATP_MODE SATP64_MODE 452 #define SATP_ASID SATP64_ASID 453 #define SATP_PPN SATP64_PPN 454 #endif 455 456 /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ 457 #define VM_1_09_MBARE 0 458 #define VM_1_09_MBB 1 459 #define VM_1_09_MBBID 2 460 #define VM_1_09_SV32 8 461 #define VM_1_09_SV39 9 462 #define VM_1_09_SV48 10 463 464 /* VM modes (satp.mode) privileged ISA 1.10 */ 465 #define VM_1_10_MBARE 0 466 #define VM_1_10_SV32 1 467 #define VM_1_10_SV39 8 468 #define VM_1_10_SV48 9 469 #define VM_1_10_SV57 10 470 #define VM_1_10_SV64 11 471 472 /* Page table entry (PTE) fields */ 473 #define PTE_V 0x001 /* Valid */ 474 #define PTE_R 0x002 /* Read */ 475 #define PTE_W 0x004 /* Write */ 476 #define PTE_X 0x008 /* Execute */ 477 #define PTE_U 0x010 /* User */ 478 #define PTE_G 0x020 /* Global */ 479 #define PTE_A 0x040 /* Accessed */ 480 #define PTE_D 0x080 /* Dirty */ 481 #define PTE_SOFT 0x300 /* Reserved for Software */ 482 483 /* Page table PPN shift amount */ 484 #define PTE_PPN_SHIFT 10 485 486 /* Leaf page shift amount */ 487 #define PGSHIFT 12 488 489 /* Default Reset Vector adress */ 490 #define DEFAULT_RSTVEC 0x1000 491 492 /* Exception causes */ 493 typedef enum RISCVException { 494 RISCV_EXCP_NONE = -1, /* sentinel value */ 495 RISCV_EXCP_INST_ADDR_MIS = 0x0, 496 RISCV_EXCP_INST_ACCESS_FAULT = 0x1, 497 RISCV_EXCP_ILLEGAL_INST = 0x2, 498 RISCV_EXCP_BREAKPOINT = 0x3, 499 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, 500 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, 501 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, 502 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, 503 RISCV_EXCP_U_ECALL = 0x8, 504 RISCV_EXCP_S_ECALL = 0x9, 505 RISCV_EXCP_VS_ECALL = 0xa, 506 RISCV_EXCP_M_ECALL = 0xb, 507 RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ 508 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ 509 RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ 510 RISCV_EXCP_SEMIHOST = 0x10, 511 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, 512 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, 513 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, 514 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, 515 } RISCVException; 516 517 #define RISCV_EXCP_INT_FLAG 0x80000000 518 #define RISCV_EXCP_INT_MASK 0x7fffffff 519 520 /* Interrupt causes */ 521 #define IRQ_U_SOFT 0 522 #define IRQ_S_SOFT 1 523 #define IRQ_VS_SOFT 2 524 #define IRQ_M_SOFT 3 525 #define IRQ_U_TIMER 4 526 #define IRQ_S_TIMER 5 527 #define IRQ_VS_TIMER 6 528 #define IRQ_M_TIMER 7 529 #define IRQ_U_EXT 8 530 #define IRQ_S_EXT 9 531 #define IRQ_VS_EXT 10 532 #define IRQ_M_EXT 11 533 534 /* mip masks */ 535 #define MIP_USIP (1 << IRQ_U_SOFT) 536 #define MIP_SSIP (1 << IRQ_S_SOFT) 537 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 538 #define MIP_MSIP (1 << IRQ_M_SOFT) 539 #define MIP_UTIP (1 << IRQ_U_TIMER) 540 #define MIP_STIP (1 << IRQ_S_TIMER) 541 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 542 #define MIP_MTIP (1 << IRQ_M_TIMER) 543 #define MIP_UEIP (1 << IRQ_U_EXT) 544 #define MIP_SEIP (1 << IRQ_S_EXT) 545 #define MIP_VSEIP (1 << IRQ_VS_EXT) 546 #define MIP_MEIP (1 << IRQ_M_EXT) 547 548 /* sip masks */ 549 #define SIP_SSIP MIP_SSIP 550 #define SIP_STIP MIP_STIP 551 #define SIP_SEIP MIP_SEIP 552 553 /* MIE masks */ 554 #define MIE_SEIE (1 << IRQ_S_EXT) 555 #define MIE_UEIE (1 << IRQ_U_EXT) 556 #define MIE_STIE (1 << IRQ_S_TIMER) 557 #define MIE_UTIE (1 << IRQ_U_TIMER) 558 #define MIE_SSIE (1 << IRQ_S_SOFT) 559 #define MIE_USIE (1 << IRQ_U_SOFT) 560 #endif 561