xref: /openbmc/qemu/target/riscv/cpu_bits.h (revision 74154d7e)
1 /* RISC-V ISA constants */
2 
3 #ifndef TARGET_RISCV_CPU_BITS_H
4 #define TARGET_RISCV_CPU_BITS_H
5 
6 #define get_field(reg, mask) (((reg) & \
7                  (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
9                  (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
10                  (uint64_t)(mask)))
11 
12 /* Floating point round mode */
13 #define FSR_RD_SHIFT        5
14 #define FSR_RD              (0x7 << FSR_RD_SHIFT)
15 
16 /* Floating point accrued exception flags */
17 #define FPEXC_NX            0x01
18 #define FPEXC_UF            0x02
19 #define FPEXC_OF            0x04
20 #define FPEXC_DZ            0x08
21 #define FPEXC_NV            0x10
22 
23 /* Floating point status register bits */
24 #define FSR_AEXC_SHIFT      0
25 #define FSR_NVA             (FPEXC_NV << FSR_AEXC_SHIFT)
26 #define FSR_OFA             (FPEXC_OF << FSR_AEXC_SHIFT)
27 #define FSR_UFA             (FPEXC_UF << FSR_AEXC_SHIFT)
28 #define FSR_DZA             (FPEXC_DZ << FSR_AEXC_SHIFT)
29 #define FSR_NXA             (FPEXC_NX << FSR_AEXC_SHIFT)
30 #define FSR_AEXC            (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
31 
32 /* Vector Fixed-Point round model */
33 #define FSR_VXRM_SHIFT      9
34 #define FSR_VXRM            (0x3 << FSR_VXRM_SHIFT)
35 
36 /* Vector Fixed-Point saturation flag */
37 #define FSR_VXSAT_SHIFT     8
38 #define FSR_VXSAT           (0x1 << FSR_VXSAT_SHIFT)
39 
40 /* Control and Status Registers */
41 
42 /* User Trap Setup */
43 #define CSR_USTATUS         0x000
44 #define CSR_UIE             0x004
45 #define CSR_UTVEC           0x005
46 
47 /* User Trap Handling */
48 #define CSR_USCRATCH        0x040
49 #define CSR_UEPC            0x041
50 #define CSR_UCAUSE          0x042
51 #define CSR_UTVAL           0x043
52 #define CSR_UIP             0x044
53 
54 /* User Floating-Point CSRs */
55 #define CSR_FFLAGS          0x001
56 #define CSR_FRM             0x002
57 #define CSR_FCSR            0x003
58 
59 /* User Vector CSRs */
60 #define CSR_VSTART          0x008
61 #define CSR_VXSAT           0x009
62 #define CSR_VXRM            0x00a
63 #define CSR_VCSR            0x00f
64 #define CSR_VL              0xc20
65 #define CSR_VTYPE           0xc21
66 #define CSR_VLENB           0xc22
67 
68 /* VCSR fields */
69 #define VCSR_VXSAT_SHIFT    0
70 #define VCSR_VXSAT          (0x1 << VCSR_VXSAT_SHIFT)
71 #define VCSR_VXRM_SHIFT     1
72 #define VCSR_VXRM           (0x3 << VCSR_VXRM_SHIFT)
73 
74 /* User Timers and Counters */
75 #define CSR_CYCLE           0xc00
76 #define CSR_TIME            0xc01
77 #define CSR_INSTRET         0xc02
78 #define CSR_HPMCOUNTER3     0xc03
79 #define CSR_HPMCOUNTER4     0xc04
80 #define CSR_HPMCOUNTER5     0xc05
81 #define CSR_HPMCOUNTER6     0xc06
82 #define CSR_HPMCOUNTER7     0xc07
83 #define CSR_HPMCOUNTER8     0xc08
84 #define CSR_HPMCOUNTER9     0xc09
85 #define CSR_HPMCOUNTER10    0xc0a
86 #define CSR_HPMCOUNTER11    0xc0b
87 #define CSR_HPMCOUNTER12    0xc0c
88 #define CSR_HPMCOUNTER13    0xc0d
89 #define CSR_HPMCOUNTER14    0xc0e
90 #define CSR_HPMCOUNTER15    0xc0f
91 #define CSR_HPMCOUNTER16    0xc10
92 #define CSR_HPMCOUNTER17    0xc11
93 #define CSR_HPMCOUNTER18    0xc12
94 #define CSR_HPMCOUNTER19    0xc13
95 #define CSR_HPMCOUNTER20    0xc14
96 #define CSR_HPMCOUNTER21    0xc15
97 #define CSR_HPMCOUNTER22    0xc16
98 #define CSR_HPMCOUNTER23    0xc17
99 #define CSR_HPMCOUNTER24    0xc18
100 #define CSR_HPMCOUNTER25    0xc19
101 #define CSR_HPMCOUNTER26    0xc1a
102 #define CSR_HPMCOUNTER27    0xc1b
103 #define CSR_HPMCOUNTER28    0xc1c
104 #define CSR_HPMCOUNTER29    0xc1d
105 #define CSR_HPMCOUNTER30    0xc1e
106 #define CSR_HPMCOUNTER31    0xc1f
107 #define CSR_CYCLEH          0xc80
108 #define CSR_TIMEH           0xc81
109 #define CSR_INSTRETH        0xc82
110 #define CSR_HPMCOUNTER3H    0xc83
111 #define CSR_HPMCOUNTER4H    0xc84
112 #define CSR_HPMCOUNTER5H    0xc85
113 #define CSR_HPMCOUNTER6H    0xc86
114 #define CSR_HPMCOUNTER7H    0xc87
115 #define CSR_HPMCOUNTER8H    0xc88
116 #define CSR_HPMCOUNTER9H    0xc89
117 #define CSR_HPMCOUNTER10H   0xc8a
118 #define CSR_HPMCOUNTER11H   0xc8b
119 #define CSR_HPMCOUNTER12H   0xc8c
120 #define CSR_HPMCOUNTER13H   0xc8d
121 #define CSR_HPMCOUNTER14H   0xc8e
122 #define CSR_HPMCOUNTER15H   0xc8f
123 #define CSR_HPMCOUNTER16H   0xc90
124 #define CSR_HPMCOUNTER17H   0xc91
125 #define CSR_HPMCOUNTER18H   0xc92
126 #define CSR_HPMCOUNTER19H   0xc93
127 #define CSR_HPMCOUNTER20H   0xc94
128 #define CSR_HPMCOUNTER21H   0xc95
129 #define CSR_HPMCOUNTER22H   0xc96
130 #define CSR_HPMCOUNTER23H   0xc97
131 #define CSR_HPMCOUNTER24H   0xc98
132 #define CSR_HPMCOUNTER25H   0xc99
133 #define CSR_HPMCOUNTER26H   0xc9a
134 #define CSR_HPMCOUNTER27H   0xc9b
135 #define CSR_HPMCOUNTER28H   0xc9c
136 #define CSR_HPMCOUNTER29H   0xc9d
137 #define CSR_HPMCOUNTER30H   0xc9e
138 #define CSR_HPMCOUNTER31H   0xc9f
139 
140 /* Machine Timers and Counters */
141 #define CSR_MCYCLE          0xb00
142 #define CSR_MINSTRET        0xb02
143 #define CSR_MCYCLEH         0xb80
144 #define CSR_MINSTRETH       0xb82
145 
146 /* Machine Information Registers */
147 #define CSR_MVENDORID       0xf11
148 #define CSR_MARCHID         0xf12
149 #define CSR_MIMPID          0xf13
150 #define CSR_MHARTID         0xf14
151 
152 /* Machine Trap Setup */
153 #define CSR_MSTATUS         0x300
154 #define CSR_MISA            0x301
155 #define CSR_MEDELEG         0x302
156 #define CSR_MIDELEG         0x303
157 #define CSR_MIE             0x304
158 #define CSR_MTVEC           0x305
159 #define CSR_MCOUNTEREN      0x306
160 
161 /* 32-bit only */
162 #define CSR_MSTATUSH        0x310
163 
164 /* Machine Trap Handling */
165 #define CSR_MSCRATCH        0x340
166 #define CSR_MEPC            0x341
167 #define CSR_MCAUSE          0x342
168 #define CSR_MTVAL           0x343
169 #define CSR_MIP             0x344
170 
171 /* Supervisor Trap Setup */
172 #define CSR_SSTATUS         0x100
173 #define CSR_SEDELEG         0x102
174 #define CSR_SIDELEG         0x103
175 #define CSR_SIE             0x104
176 #define CSR_STVEC           0x105
177 #define CSR_SCOUNTEREN      0x106
178 
179 /* Supervisor Trap Handling */
180 #define CSR_SSCRATCH        0x140
181 #define CSR_SEPC            0x141
182 #define CSR_SCAUSE          0x142
183 #define CSR_STVAL           0x143
184 #define CSR_SIP             0x144
185 
186 /* Supervisor Protection and Translation */
187 #define CSR_SPTBR           0x180
188 #define CSR_SATP            0x180
189 
190 /* Hpervisor CSRs */
191 #define CSR_HSTATUS         0x600
192 #define CSR_HEDELEG         0x602
193 #define CSR_HIDELEG         0x603
194 #define CSR_HIE             0x604
195 #define CSR_HCOUNTEREN      0x606
196 #define CSR_HGEIE           0x607
197 #define CSR_HTVAL           0x643
198 #define CSR_HVIP            0x645
199 #define CSR_HIP             0x644
200 #define CSR_HTINST          0x64A
201 #define CSR_HGEIP           0xE12
202 #define CSR_HGATP           0x680
203 #define CSR_HTIMEDELTA      0x605
204 #define CSR_HTIMEDELTAH     0x615
205 
206 /* Virtual CSRs */
207 #define CSR_VSSTATUS        0x200
208 #define CSR_VSIE            0x204
209 #define CSR_VSTVEC          0x205
210 #define CSR_VSSCRATCH       0x240
211 #define CSR_VSEPC           0x241
212 #define CSR_VSCAUSE         0x242
213 #define CSR_VSTVAL          0x243
214 #define CSR_VSIP            0x244
215 #define CSR_VSATP           0x280
216 
217 #define CSR_MTINST          0x34a
218 #define CSR_MTVAL2          0x34b
219 
220 /* Enhanced Physical Memory Protection (ePMP) */
221 #define CSR_MSECCFG         0x747
222 #define CSR_MSECCFGH        0x757
223 /* Physical Memory Protection */
224 #define CSR_PMPCFG0         0x3a0
225 #define CSR_PMPCFG1         0x3a1
226 #define CSR_PMPCFG2         0x3a2
227 #define CSR_PMPCFG3         0x3a3
228 #define CSR_PMPADDR0        0x3b0
229 #define CSR_PMPADDR1        0x3b1
230 #define CSR_PMPADDR2        0x3b2
231 #define CSR_PMPADDR3        0x3b3
232 #define CSR_PMPADDR4        0x3b4
233 #define CSR_PMPADDR5        0x3b5
234 #define CSR_PMPADDR6        0x3b6
235 #define CSR_PMPADDR7        0x3b7
236 #define CSR_PMPADDR8        0x3b8
237 #define CSR_PMPADDR9        0x3b9
238 #define CSR_PMPADDR10       0x3ba
239 #define CSR_PMPADDR11       0x3bb
240 #define CSR_PMPADDR12       0x3bc
241 #define CSR_PMPADDR13       0x3bd
242 #define CSR_PMPADDR14       0x3be
243 #define CSR_PMPADDR15       0x3bf
244 
245 /* Debug/Trace Registers (shared with Debug Mode) */
246 #define CSR_TSELECT         0x7a0
247 #define CSR_TDATA1          0x7a1
248 #define CSR_TDATA2          0x7a2
249 #define CSR_TDATA3          0x7a3
250 
251 /* Debug Mode Registers */
252 #define CSR_DCSR            0x7b0
253 #define CSR_DPC             0x7b1
254 #define CSR_DSCRATCH        0x7b2
255 
256 /* Performance Counters */
257 #define CSR_MHPMCOUNTER3    0xb03
258 #define CSR_MHPMCOUNTER4    0xb04
259 #define CSR_MHPMCOUNTER5    0xb05
260 #define CSR_MHPMCOUNTER6    0xb06
261 #define CSR_MHPMCOUNTER7    0xb07
262 #define CSR_MHPMCOUNTER8    0xb08
263 #define CSR_MHPMCOUNTER9    0xb09
264 #define CSR_MHPMCOUNTER10   0xb0a
265 #define CSR_MHPMCOUNTER11   0xb0b
266 #define CSR_MHPMCOUNTER12   0xb0c
267 #define CSR_MHPMCOUNTER13   0xb0d
268 #define CSR_MHPMCOUNTER14   0xb0e
269 #define CSR_MHPMCOUNTER15   0xb0f
270 #define CSR_MHPMCOUNTER16   0xb10
271 #define CSR_MHPMCOUNTER17   0xb11
272 #define CSR_MHPMCOUNTER18   0xb12
273 #define CSR_MHPMCOUNTER19   0xb13
274 #define CSR_MHPMCOUNTER20   0xb14
275 #define CSR_MHPMCOUNTER21   0xb15
276 #define CSR_MHPMCOUNTER22   0xb16
277 #define CSR_MHPMCOUNTER23   0xb17
278 #define CSR_MHPMCOUNTER24   0xb18
279 #define CSR_MHPMCOUNTER25   0xb19
280 #define CSR_MHPMCOUNTER26   0xb1a
281 #define CSR_MHPMCOUNTER27   0xb1b
282 #define CSR_MHPMCOUNTER28   0xb1c
283 #define CSR_MHPMCOUNTER29   0xb1d
284 #define CSR_MHPMCOUNTER30   0xb1e
285 #define CSR_MHPMCOUNTER31   0xb1f
286 #define CSR_MHPMEVENT3      0x323
287 #define CSR_MHPMEVENT4      0x324
288 #define CSR_MHPMEVENT5      0x325
289 #define CSR_MHPMEVENT6      0x326
290 #define CSR_MHPMEVENT7      0x327
291 #define CSR_MHPMEVENT8      0x328
292 #define CSR_MHPMEVENT9      0x329
293 #define CSR_MHPMEVENT10     0x32a
294 #define CSR_MHPMEVENT11     0x32b
295 #define CSR_MHPMEVENT12     0x32c
296 #define CSR_MHPMEVENT13     0x32d
297 #define CSR_MHPMEVENT14     0x32e
298 #define CSR_MHPMEVENT15     0x32f
299 #define CSR_MHPMEVENT16     0x330
300 #define CSR_MHPMEVENT17     0x331
301 #define CSR_MHPMEVENT18     0x332
302 #define CSR_MHPMEVENT19     0x333
303 #define CSR_MHPMEVENT20     0x334
304 #define CSR_MHPMEVENT21     0x335
305 #define CSR_MHPMEVENT22     0x336
306 #define CSR_MHPMEVENT23     0x337
307 #define CSR_MHPMEVENT24     0x338
308 #define CSR_MHPMEVENT25     0x339
309 #define CSR_MHPMEVENT26     0x33a
310 #define CSR_MHPMEVENT27     0x33b
311 #define CSR_MHPMEVENT28     0x33c
312 #define CSR_MHPMEVENT29     0x33d
313 #define CSR_MHPMEVENT30     0x33e
314 #define CSR_MHPMEVENT31     0x33f
315 #define CSR_MHPMCOUNTER3H   0xb83
316 #define CSR_MHPMCOUNTER4H   0xb84
317 #define CSR_MHPMCOUNTER5H   0xb85
318 #define CSR_MHPMCOUNTER6H   0xb86
319 #define CSR_MHPMCOUNTER7H   0xb87
320 #define CSR_MHPMCOUNTER8H   0xb88
321 #define CSR_MHPMCOUNTER9H   0xb89
322 #define CSR_MHPMCOUNTER10H  0xb8a
323 #define CSR_MHPMCOUNTER11H  0xb8b
324 #define CSR_MHPMCOUNTER12H  0xb8c
325 #define CSR_MHPMCOUNTER13H  0xb8d
326 #define CSR_MHPMCOUNTER14H  0xb8e
327 #define CSR_MHPMCOUNTER15H  0xb8f
328 #define CSR_MHPMCOUNTER16H  0xb90
329 #define CSR_MHPMCOUNTER17H  0xb91
330 #define CSR_MHPMCOUNTER18H  0xb92
331 #define CSR_MHPMCOUNTER19H  0xb93
332 #define CSR_MHPMCOUNTER20H  0xb94
333 #define CSR_MHPMCOUNTER21H  0xb95
334 #define CSR_MHPMCOUNTER22H  0xb96
335 #define CSR_MHPMCOUNTER23H  0xb97
336 #define CSR_MHPMCOUNTER24H  0xb98
337 #define CSR_MHPMCOUNTER25H  0xb99
338 #define CSR_MHPMCOUNTER26H  0xb9a
339 #define CSR_MHPMCOUNTER27H  0xb9b
340 #define CSR_MHPMCOUNTER28H  0xb9c
341 #define CSR_MHPMCOUNTER29H  0xb9d
342 #define CSR_MHPMCOUNTER30H  0xb9e
343 #define CSR_MHPMCOUNTER31H  0xb9f
344 
345 /*
346  * User PointerMasking registers
347  * NB: actual CSR numbers might be changed in future
348  */
349 #define CSR_UMTE            0x4c0
350 #define CSR_UPMMASK         0x4c1
351 #define CSR_UPMBASE         0x4c2
352 
353 /*
354  * Machine PointerMasking registers
355  * NB: actual CSR numbers might be changed in future
356  */
357 #define CSR_MMTE            0x3c0
358 #define CSR_MPMMASK         0x3c1
359 #define CSR_MPMBASE         0x3c2
360 
361 /*
362  * Supervisor PointerMaster registers
363  * NB: actual CSR numbers might be changed in future
364  */
365 #define CSR_SMTE            0x1c0
366 #define CSR_SPMMASK         0x1c1
367 #define CSR_SPMBASE         0x1c2
368 
369 /*
370  * Hypervisor PointerMaster registers
371  * NB: actual CSR numbers might be changed in future
372  */
373 #define CSR_VSMTE           0x2c0
374 #define CSR_VSPMMASK        0x2c1
375 #define CSR_VSPMBASE        0x2c2
376 
377 /* mstatus CSR bits */
378 #define MSTATUS_UIE         0x00000001
379 #define MSTATUS_SIE         0x00000002
380 #define MSTATUS_MIE         0x00000008
381 #define MSTATUS_UPIE        0x00000010
382 #define MSTATUS_SPIE        0x00000020
383 #define MSTATUS_UBE         0x00000040
384 #define MSTATUS_MPIE        0x00000080
385 #define MSTATUS_SPP         0x00000100
386 #define MSTATUS_VS          0x00000600
387 #define MSTATUS_MPP         0x00001800
388 #define MSTATUS_FS          0x00006000
389 #define MSTATUS_XS          0x00018000
390 #define MSTATUS_MPRV        0x00020000
391 #define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
392 #define MSTATUS_MXR         0x00080000
393 #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
394 #define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
395 #define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
396 #define MSTATUS_GVA         0x4000000000ULL
397 #define MSTATUS_MPV         0x8000000000ULL
398 
399 #define MSTATUS64_UXL       0x0000000300000000ULL
400 #define MSTATUS64_SXL       0x0000000C00000000ULL
401 
402 #define MSTATUS32_SD        0x80000000
403 #define MSTATUS64_SD        0x8000000000000000ULL
404 #define MSTATUSH128_SD      0x8000000000000000ULL
405 
406 #define MISA32_MXL          0xC0000000
407 #define MISA64_MXL          0xC000000000000000ULL
408 
409 typedef enum {
410     MXL_RV32  = 1,
411     MXL_RV64  = 2,
412     MXL_RV128 = 3,
413 } RISCVMXL;
414 
415 /* sstatus CSR bits */
416 #define SSTATUS_UIE         0x00000001
417 #define SSTATUS_SIE         0x00000002
418 #define SSTATUS_UPIE        0x00000010
419 #define SSTATUS_SPIE        0x00000020
420 #define SSTATUS_SPP         0x00000100
421 #define SSTATUS_VS          0x00000600
422 #define SSTATUS_FS          0x00006000
423 #define SSTATUS_XS          0x00018000
424 #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
425 #define SSTATUS_MXR         0x00080000
426 
427 #define SSTATUS64_UXL       0x0000000300000000ULL
428 
429 #define SSTATUS32_SD        0x80000000
430 #define SSTATUS64_SD        0x8000000000000000ULL
431 
432 /* hstatus CSR bits */
433 #define HSTATUS_VSBE         0x00000020
434 #define HSTATUS_GVA          0x00000040
435 #define HSTATUS_SPV          0x00000080
436 #define HSTATUS_SPVP         0x00000100
437 #define HSTATUS_HU           0x00000200
438 #define HSTATUS_VGEIN        0x0003F000
439 #define HSTATUS_VTVM         0x00100000
440 #define HSTATUS_VTW          0x00200000
441 #define HSTATUS_VTSR         0x00400000
442 #define HSTATUS_VSXL         0x300000000
443 
444 #define HSTATUS32_WPRI       0xFF8FF87E
445 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
446 
447 #define COUNTEREN_CY         (1 << 0)
448 #define COUNTEREN_TM         (1 << 1)
449 #define COUNTEREN_IR         (1 << 2)
450 #define COUNTEREN_HPM3       (1 << 3)
451 
452 /* vsstatus CSR bits */
453 #define VSSTATUS64_UXL       0x0000000300000000ULL
454 
455 /* Privilege modes */
456 #define PRV_U 0
457 #define PRV_S 1
458 #define PRV_H 2 /* Reserved */
459 #define PRV_M 3
460 
461 /* Virtulisation Register Fields */
462 #define VIRT_ONOFF          1
463 
464 /* RV32 satp CSR field masks */
465 #define SATP32_MODE         0x80000000
466 #define SATP32_ASID         0x7fc00000
467 #define SATP32_PPN          0x003fffff
468 
469 /* RV64 satp CSR field masks */
470 #define SATP64_MODE         0xF000000000000000ULL
471 #define SATP64_ASID         0x0FFFF00000000000ULL
472 #define SATP64_PPN          0x00000FFFFFFFFFFFULL
473 
474 /* VM modes (satp.mode) privileged ISA 1.10 */
475 #define VM_1_10_MBARE       0
476 #define VM_1_10_SV32        1
477 #define VM_1_10_SV39        8
478 #define VM_1_10_SV48        9
479 #define VM_1_10_SV57        10
480 #define VM_1_10_SV64        11
481 
482 /* Page table entry (PTE) fields */
483 #define PTE_V               0x001 /* Valid */
484 #define PTE_R               0x002 /* Read */
485 #define PTE_W               0x004 /* Write */
486 #define PTE_X               0x008 /* Execute */
487 #define PTE_U               0x010 /* User */
488 #define PTE_G               0x020 /* Global */
489 #define PTE_A               0x040 /* Accessed */
490 #define PTE_D               0x080 /* Dirty */
491 #define PTE_SOFT            0x300 /* Reserved for Software */
492 
493 /* Page table PPN shift amount */
494 #define PTE_PPN_SHIFT       10
495 
496 /* Leaf page shift amount */
497 #define PGSHIFT             12
498 
499 /* Default Reset Vector adress */
500 #define DEFAULT_RSTVEC      0x1000
501 
502 /* Exception causes */
503 typedef enum RISCVException {
504     RISCV_EXCP_NONE = -1, /* sentinel value */
505     RISCV_EXCP_INST_ADDR_MIS = 0x0,
506     RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
507     RISCV_EXCP_ILLEGAL_INST = 0x2,
508     RISCV_EXCP_BREAKPOINT = 0x3,
509     RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
510     RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
511     RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
512     RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
513     RISCV_EXCP_U_ECALL = 0x8,
514     RISCV_EXCP_S_ECALL = 0x9,
515     RISCV_EXCP_VS_ECALL = 0xa,
516     RISCV_EXCP_M_ECALL = 0xb,
517     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
518     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
519     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
520     RISCV_EXCP_SEMIHOST = 0x10,
521     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
522     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
523     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
524     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
525 } RISCVException;
526 
527 #define RISCV_EXCP_INT_FLAG                0x80000000
528 #define RISCV_EXCP_INT_MASK                0x7fffffff
529 
530 /* Interrupt causes */
531 #define IRQ_U_SOFT                         0
532 #define IRQ_S_SOFT                         1
533 #define IRQ_VS_SOFT                        2
534 #define IRQ_M_SOFT                         3
535 #define IRQ_U_TIMER                        4
536 #define IRQ_S_TIMER                        5
537 #define IRQ_VS_TIMER                       6
538 #define IRQ_M_TIMER                        7
539 #define IRQ_U_EXT                          8
540 #define IRQ_S_EXT                          9
541 #define IRQ_VS_EXT                         10
542 #define IRQ_M_EXT                          11
543 
544 /* mip masks */
545 #define MIP_USIP                           (1 << IRQ_U_SOFT)
546 #define MIP_SSIP                           (1 << IRQ_S_SOFT)
547 #define MIP_VSSIP                          (1 << IRQ_VS_SOFT)
548 #define MIP_MSIP                           (1 << IRQ_M_SOFT)
549 #define MIP_UTIP                           (1 << IRQ_U_TIMER)
550 #define MIP_STIP                           (1 << IRQ_S_TIMER)
551 #define MIP_VSTIP                          (1 << IRQ_VS_TIMER)
552 #define MIP_MTIP                           (1 << IRQ_M_TIMER)
553 #define MIP_UEIP                           (1 << IRQ_U_EXT)
554 #define MIP_SEIP                           (1 << IRQ_S_EXT)
555 #define MIP_VSEIP                          (1 << IRQ_VS_EXT)
556 #define MIP_MEIP                           (1 << IRQ_M_EXT)
557 
558 /* sip masks */
559 #define SIP_SSIP                           MIP_SSIP
560 #define SIP_STIP                           MIP_STIP
561 #define SIP_SEIP                           MIP_SEIP
562 
563 /* MIE masks */
564 #define MIE_SEIE                           (1 << IRQ_S_EXT)
565 #define MIE_UEIE                           (1 << IRQ_U_EXT)
566 #define MIE_STIE                           (1 << IRQ_S_TIMER)
567 #define MIE_UTIE                           (1 << IRQ_U_TIMER)
568 #define MIE_SSIE                           (1 << IRQ_S_SOFT)
569 #define MIE_USIE                           (1 << IRQ_U_SOFT)
570 
571 /* General PointerMasking CSR bits*/
572 #define PM_ENABLE       0x00000001ULL
573 #define PM_CURRENT      0x00000002ULL
574 #define PM_INSN         0x00000004ULL
575 #define PM_XS_MASK      0x00000003ULL
576 
577 /* PointerMasking XS bits values */
578 #define PM_EXT_DISABLE  0x00000000ULL
579 #define PM_EXT_INITIAL  0x00000001ULL
580 #define PM_EXT_CLEAN    0x00000002ULL
581 #define PM_EXT_DIRTY    0x00000003ULL
582 
583 /* Offsets for every pair of control bits per each priv level */
584 #define XS_OFFSET    0ULL
585 #define U_OFFSET     2ULL
586 #define S_OFFSET     5ULL
587 #define M_OFFSET     8ULL
588 
589 #define PM_XS_BITS   (PM_XS_MASK << XS_OFFSET)
590 #define U_PM_ENABLE  (PM_ENABLE  << U_OFFSET)
591 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
592 #define U_PM_INSN    (PM_INSN    << U_OFFSET)
593 #define S_PM_ENABLE  (PM_ENABLE  << S_OFFSET)
594 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
595 #define S_PM_INSN    (PM_INSN    << S_OFFSET)
596 #define M_PM_ENABLE  (PM_ENABLE  << M_OFFSET)
597 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
598 #define M_PM_INSN    (PM_INSN    << M_OFFSET)
599 
600 /* mmte CSR bits */
601 #define MMTE_PM_XS_BITS     PM_XS_BITS
602 #define MMTE_U_PM_ENABLE    U_PM_ENABLE
603 #define MMTE_U_PM_CURRENT   U_PM_CURRENT
604 #define MMTE_U_PM_INSN      U_PM_INSN
605 #define MMTE_S_PM_ENABLE    S_PM_ENABLE
606 #define MMTE_S_PM_CURRENT   S_PM_CURRENT
607 #define MMTE_S_PM_INSN      S_PM_INSN
608 #define MMTE_M_PM_ENABLE    M_PM_ENABLE
609 #define MMTE_M_PM_CURRENT   M_PM_CURRENT
610 #define MMTE_M_PM_INSN      M_PM_INSN
611 #define MMTE_MASK    (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
612                       MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
613                       MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
614                       MMTE_PM_XS_BITS)
615 
616 /* (v)smte CSR bits */
617 #define SMTE_PM_XS_BITS     PM_XS_BITS
618 #define SMTE_U_PM_ENABLE    U_PM_ENABLE
619 #define SMTE_U_PM_CURRENT   U_PM_CURRENT
620 #define SMTE_U_PM_INSN      U_PM_INSN
621 #define SMTE_S_PM_ENABLE    S_PM_ENABLE
622 #define SMTE_S_PM_CURRENT   S_PM_CURRENT
623 #define SMTE_S_PM_INSN      S_PM_INSN
624 #define SMTE_MASK    (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
625                       SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
626                       SMTE_PM_XS_BITS)
627 
628 /* umte CSR bits */
629 #define UMTE_U_PM_ENABLE    U_PM_ENABLE
630 #define UMTE_U_PM_CURRENT   U_PM_CURRENT
631 #define UMTE_U_PM_INSN      U_PM_INSN
632 #define UMTE_MASK     (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
633 
634 #endif
635