xref: /openbmc/qemu/target/riscv/cpu_bits.h (revision 646b5378)
1 /* RISC-V ISA constants */
2 
3 #ifndef TARGET_RISCV_CPU_BITS_H
4 #define TARGET_RISCV_CPU_BITS_H
5 
6 #define get_field(reg, mask) (((reg) & \
7                  (uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
9                  (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
10                  (uint64_t)(mask)))
11 
12 /* Extension context status mask */
13 #define EXT_STATUS_MASK     0x3ULL
14 
15 /* Floating point round mode */
16 #define FSR_RD_SHIFT        5
17 #define FSR_RD              (0x7 << FSR_RD_SHIFT)
18 
19 /* Floating point accrued exception flags */
20 #define FPEXC_NX            0x01
21 #define FPEXC_UF            0x02
22 #define FPEXC_OF            0x04
23 #define FPEXC_DZ            0x08
24 #define FPEXC_NV            0x10
25 
26 /* Floating point status register bits */
27 #define FSR_AEXC_SHIFT      0
28 #define FSR_NVA             (FPEXC_NV << FSR_AEXC_SHIFT)
29 #define FSR_OFA             (FPEXC_OF << FSR_AEXC_SHIFT)
30 #define FSR_UFA             (FPEXC_UF << FSR_AEXC_SHIFT)
31 #define FSR_DZA             (FPEXC_DZ << FSR_AEXC_SHIFT)
32 #define FSR_NXA             (FPEXC_NX << FSR_AEXC_SHIFT)
33 #define FSR_AEXC            (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
34 
35 /* Control and Status Registers */
36 
37 /* zicfiss user ssp csr */
38 #define CSR_SSP             0x011
39 
40 /* User Trap Setup */
41 #define CSR_USTATUS         0x000
42 #define CSR_UIE             0x004
43 #define CSR_UTVEC           0x005
44 
45 /* User Trap Handling */
46 #define CSR_USCRATCH        0x040
47 #define CSR_UEPC            0x041
48 #define CSR_UCAUSE          0x042
49 #define CSR_UTVAL           0x043
50 #define CSR_UIP             0x044
51 
52 /* User Floating-Point CSRs */
53 #define CSR_FFLAGS          0x001
54 #define CSR_FRM             0x002
55 #define CSR_FCSR            0x003
56 
57 /* User Vector CSRs */
58 #define CSR_VSTART          0x008
59 #define CSR_VXSAT           0x009
60 #define CSR_VXRM            0x00a
61 #define CSR_VCSR            0x00f
62 #define CSR_VL              0xc20
63 #define CSR_VTYPE           0xc21
64 #define CSR_VLENB           0xc22
65 
66 /* VCSR fields */
67 #define VCSR_VXSAT_SHIFT    0
68 #define VCSR_VXSAT          (0x1 << VCSR_VXSAT_SHIFT)
69 #define VCSR_VXRM_SHIFT     1
70 #define VCSR_VXRM           (0x3 << VCSR_VXRM_SHIFT)
71 
72 /* User Timers and Counters */
73 #define CSR_CYCLE           0xc00
74 #define CSR_TIME            0xc01
75 #define CSR_INSTRET         0xc02
76 #define CSR_HPMCOUNTER3     0xc03
77 #define CSR_HPMCOUNTER4     0xc04
78 #define CSR_HPMCOUNTER5     0xc05
79 #define CSR_HPMCOUNTER6     0xc06
80 #define CSR_HPMCOUNTER7     0xc07
81 #define CSR_HPMCOUNTER8     0xc08
82 #define CSR_HPMCOUNTER9     0xc09
83 #define CSR_HPMCOUNTER10    0xc0a
84 #define CSR_HPMCOUNTER11    0xc0b
85 #define CSR_HPMCOUNTER12    0xc0c
86 #define CSR_HPMCOUNTER13    0xc0d
87 #define CSR_HPMCOUNTER14    0xc0e
88 #define CSR_HPMCOUNTER15    0xc0f
89 #define CSR_HPMCOUNTER16    0xc10
90 #define CSR_HPMCOUNTER17    0xc11
91 #define CSR_HPMCOUNTER18    0xc12
92 #define CSR_HPMCOUNTER19    0xc13
93 #define CSR_HPMCOUNTER20    0xc14
94 #define CSR_HPMCOUNTER21    0xc15
95 #define CSR_HPMCOUNTER22    0xc16
96 #define CSR_HPMCOUNTER23    0xc17
97 #define CSR_HPMCOUNTER24    0xc18
98 #define CSR_HPMCOUNTER25    0xc19
99 #define CSR_HPMCOUNTER26    0xc1a
100 #define CSR_HPMCOUNTER27    0xc1b
101 #define CSR_HPMCOUNTER28    0xc1c
102 #define CSR_HPMCOUNTER29    0xc1d
103 #define CSR_HPMCOUNTER30    0xc1e
104 #define CSR_HPMCOUNTER31    0xc1f
105 #define CSR_CYCLEH          0xc80
106 #define CSR_TIMEH           0xc81
107 #define CSR_INSTRETH        0xc82
108 #define CSR_HPMCOUNTER3H    0xc83
109 #define CSR_HPMCOUNTER4H    0xc84
110 #define CSR_HPMCOUNTER5H    0xc85
111 #define CSR_HPMCOUNTER6H    0xc86
112 #define CSR_HPMCOUNTER7H    0xc87
113 #define CSR_HPMCOUNTER8H    0xc88
114 #define CSR_HPMCOUNTER9H    0xc89
115 #define CSR_HPMCOUNTER10H   0xc8a
116 #define CSR_HPMCOUNTER11H   0xc8b
117 #define CSR_HPMCOUNTER12H   0xc8c
118 #define CSR_HPMCOUNTER13H   0xc8d
119 #define CSR_HPMCOUNTER14H   0xc8e
120 #define CSR_HPMCOUNTER15H   0xc8f
121 #define CSR_HPMCOUNTER16H   0xc90
122 #define CSR_HPMCOUNTER17H   0xc91
123 #define CSR_HPMCOUNTER18H   0xc92
124 #define CSR_HPMCOUNTER19H   0xc93
125 #define CSR_HPMCOUNTER20H   0xc94
126 #define CSR_HPMCOUNTER21H   0xc95
127 #define CSR_HPMCOUNTER22H   0xc96
128 #define CSR_HPMCOUNTER23H   0xc97
129 #define CSR_HPMCOUNTER24H   0xc98
130 #define CSR_HPMCOUNTER25H   0xc99
131 #define CSR_HPMCOUNTER26H   0xc9a
132 #define CSR_HPMCOUNTER27H   0xc9b
133 #define CSR_HPMCOUNTER28H   0xc9c
134 #define CSR_HPMCOUNTER29H   0xc9d
135 #define CSR_HPMCOUNTER30H   0xc9e
136 #define CSR_HPMCOUNTER31H   0xc9f
137 
138 /* Machine Timers and Counters */
139 #define CSR_MCYCLE          0xb00
140 #define CSR_MINSTRET        0xb02
141 #define CSR_MCYCLEH         0xb80
142 #define CSR_MINSTRETH       0xb82
143 
144 /* Machine Information Registers */
145 #define CSR_MVENDORID       0xf11
146 #define CSR_MARCHID         0xf12
147 #define CSR_MIMPID          0xf13
148 #define CSR_MHARTID         0xf14
149 #define CSR_MCONFIGPTR      0xf15
150 
151 /* Machine Trap Setup */
152 #define CSR_MSTATUS         0x300
153 #define CSR_MISA            0x301
154 #define CSR_MEDELEG         0x302
155 #define CSR_MIDELEG         0x303
156 #define CSR_MIE             0x304
157 #define CSR_MTVEC           0x305
158 #define CSR_MCOUNTEREN      0x306
159 
160 /* 32-bit only */
161 #define CSR_MSTATUSH        0x310
162 #define CSR_MEDELEGH        0x312
163 #define CSR_HEDELEGH        0x612
164 
165 /* Machine Trap Handling */
166 #define CSR_MSCRATCH        0x340
167 #define CSR_MEPC            0x341
168 #define CSR_MCAUSE          0x342
169 #define CSR_MTVAL           0x343
170 #define CSR_MIP             0x344
171 
172 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
173 #define CSR_MISELECT        0x350
174 #define CSR_MIREG           0x351
175 
176 /* Machine-Level Interrupts (AIA) */
177 #define CSR_MTOPEI          0x35c
178 #define CSR_MTOPI           0xfb0
179 
180 /* Virtual Interrupts for Supervisor Level (AIA) */
181 #define CSR_MVIEN           0x308
182 #define CSR_MVIP            0x309
183 
184 /* Machine-Level High-Half CSRs (AIA) */
185 #define CSR_MIDELEGH        0x313
186 #define CSR_MIEH            0x314
187 #define CSR_MVIENH          0x318
188 #define CSR_MVIPH           0x319
189 #define CSR_MIPH            0x354
190 
191 /* Supervisor Trap Setup */
192 #define CSR_SSTATUS         0x100
193 #define CSR_SIE             0x104
194 #define CSR_STVEC           0x105
195 #define CSR_SCOUNTEREN      0x106
196 
197 /* Supervisor Configuration CSRs */
198 #define CSR_SENVCFG         0x10A
199 
200 /* Supervisor state CSRs */
201 #define CSR_SSTATEEN0       0x10C
202 #define CSR_SSTATEEN1       0x10D
203 #define CSR_SSTATEEN2       0x10E
204 #define CSR_SSTATEEN3       0x10F
205 
206 /* Supervisor Trap Handling */
207 #define CSR_SSCRATCH        0x140
208 #define CSR_SEPC            0x141
209 #define CSR_SCAUSE          0x142
210 #define CSR_STVAL           0x143
211 #define CSR_SIP             0x144
212 
213 /* Sstc supervisor CSRs */
214 #define CSR_STIMECMP        0x14D
215 #define CSR_STIMECMPH       0x15D
216 
217 /* Supervisor Protection and Translation */
218 #define CSR_SPTBR           0x180
219 #define CSR_SATP            0x180
220 
221 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
222 #define CSR_SISELECT        0x150
223 #define CSR_SIREG           0x151
224 
225 /* Supervisor-Level Interrupts (AIA) */
226 #define CSR_STOPEI          0x15c
227 #define CSR_STOPI           0xdb0
228 
229 /* Supervisor-Level High-Half CSRs (AIA) */
230 #define CSR_SIEH            0x114
231 #define CSR_SIPH            0x154
232 
233 /* Hpervisor CSRs */
234 #define CSR_HSTATUS         0x600
235 #define CSR_HEDELEG         0x602
236 #define CSR_HIDELEG         0x603
237 #define CSR_HIE             0x604
238 #define CSR_HCOUNTEREN      0x606
239 #define CSR_HGEIE           0x607
240 #define CSR_HTVAL           0x643
241 #define CSR_HVIP            0x645
242 #define CSR_HIP             0x644
243 #define CSR_HTINST          0x64A
244 #define CSR_HGEIP           0xE12
245 #define CSR_HGATP           0x680
246 #define CSR_HTIMEDELTA      0x605
247 #define CSR_HTIMEDELTAH     0x615
248 
249 /* Hypervisor Configuration CSRs */
250 #define CSR_HENVCFG         0x60A
251 #define CSR_HENVCFGH        0x61A
252 
253 /* Hypervisor state CSRs */
254 #define CSR_HSTATEEN0       0x60C
255 #define CSR_HSTATEEN0H      0x61C
256 #define CSR_HSTATEEN1       0x60D
257 #define CSR_HSTATEEN1H      0x61D
258 #define CSR_HSTATEEN2       0x60E
259 #define CSR_HSTATEEN2H      0x61E
260 #define CSR_HSTATEEN3       0x60F
261 #define CSR_HSTATEEN3H      0x61F
262 
263 /* Virtual CSRs */
264 #define CSR_VSSTATUS        0x200
265 #define CSR_VSIE            0x204
266 #define CSR_VSTVEC          0x205
267 #define CSR_VSSCRATCH       0x240
268 #define CSR_VSEPC           0x241
269 #define CSR_VSCAUSE         0x242
270 #define CSR_VSTVAL          0x243
271 #define CSR_VSIP            0x244
272 #define CSR_VSATP           0x280
273 
274 /* Sstc virtual CSRs */
275 #define CSR_VSTIMECMP       0x24D
276 #define CSR_VSTIMECMPH      0x25D
277 
278 #define CSR_MTINST          0x34a
279 #define CSR_MTVAL2          0x34b
280 
281 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
282 #define CSR_HVIEN           0x608
283 #define CSR_HVICTL          0x609
284 #define CSR_HVIPRIO1        0x646
285 #define CSR_HVIPRIO2        0x647
286 
287 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
288 #define CSR_VSISELECT       0x250
289 #define CSR_VSIREG          0x251
290 
291 /* VS-Level Interrupts (H-extension with AIA) */
292 #define CSR_VSTOPEI         0x25c
293 #define CSR_VSTOPI          0xeb0
294 
295 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
296 #define CSR_HIDELEGH        0x613
297 #define CSR_HVIENH          0x618
298 #define CSR_HVIPH           0x655
299 #define CSR_HVIPRIO1H       0x656
300 #define CSR_HVIPRIO2H       0x657
301 #define CSR_VSIEH           0x214
302 #define CSR_VSIPH           0x254
303 
304 /* Machine Configuration CSRs */
305 #define CSR_MENVCFG         0x30A
306 #define CSR_MENVCFGH        0x31A
307 
308 /* Machine state CSRs */
309 #define CSR_MSTATEEN0       0x30C
310 #define CSR_MSTATEEN0H      0x31C
311 #define CSR_MSTATEEN1       0x30D
312 #define CSR_MSTATEEN1H      0x31D
313 #define CSR_MSTATEEN2       0x30E
314 #define CSR_MSTATEEN2H      0x31E
315 #define CSR_MSTATEEN3       0x30F
316 #define CSR_MSTATEEN3H      0x31F
317 
318 /* Common defines for all smstateen */
319 #define SMSTATEEN_MAX_COUNT 4
320 #define SMSTATEEN0_CS       (1ULL << 0)
321 #define SMSTATEEN0_FCSR     (1ULL << 1)
322 #define SMSTATEEN0_JVT      (1ULL << 2)
323 #define SMSTATEEN0_P1P13    (1ULL << 56)
324 #define SMSTATEEN0_HSCONTXT (1ULL << 57)
325 #define SMSTATEEN0_IMSIC    (1ULL << 58)
326 #define SMSTATEEN0_AIA      (1ULL << 59)
327 #define SMSTATEEN0_SVSLCT   (1ULL << 60)
328 #define SMSTATEEN0_HSENVCFG (1ULL << 62)
329 #define SMSTATEEN_STATEEN   (1ULL << 63)
330 
331 /* Enhanced Physical Memory Protection (ePMP) */
332 #define CSR_MSECCFG         0x747
333 #define CSR_MSECCFGH        0x757
334 /* Physical Memory Protection */
335 #define CSR_PMPCFG0         0x3a0
336 #define CSR_PMPCFG1         0x3a1
337 #define CSR_PMPCFG2         0x3a2
338 #define CSR_PMPCFG3         0x3a3
339 #define CSR_PMPADDR0        0x3b0
340 #define CSR_PMPADDR1        0x3b1
341 #define CSR_PMPADDR2        0x3b2
342 #define CSR_PMPADDR3        0x3b3
343 #define CSR_PMPADDR4        0x3b4
344 #define CSR_PMPADDR5        0x3b5
345 #define CSR_PMPADDR6        0x3b6
346 #define CSR_PMPADDR7        0x3b7
347 #define CSR_PMPADDR8        0x3b8
348 #define CSR_PMPADDR9        0x3b9
349 #define CSR_PMPADDR10       0x3ba
350 #define CSR_PMPADDR11       0x3bb
351 #define CSR_PMPADDR12       0x3bc
352 #define CSR_PMPADDR13       0x3bd
353 #define CSR_PMPADDR14       0x3be
354 #define CSR_PMPADDR15       0x3bf
355 
356 /* Debug/Trace Registers (shared with Debug Mode) */
357 #define CSR_TSELECT         0x7a0
358 #define CSR_TDATA1          0x7a1
359 #define CSR_TDATA2          0x7a2
360 #define CSR_TDATA3          0x7a3
361 #define CSR_TINFO           0x7a4
362 #define CSR_MCONTEXT        0x7a8
363 
364 /* Debug Mode Registers */
365 #define CSR_DCSR            0x7b0
366 #define CSR_DPC             0x7b1
367 #define CSR_DSCRATCH        0x7b2
368 
369 /* Performance Counters */
370 #define CSR_MHPMCOUNTER3    0xb03
371 #define CSR_MHPMCOUNTER4    0xb04
372 #define CSR_MHPMCOUNTER5    0xb05
373 #define CSR_MHPMCOUNTER6    0xb06
374 #define CSR_MHPMCOUNTER7    0xb07
375 #define CSR_MHPMCOUNTER8    0xb08
376 #define CSR_MHPMCOUNTER9    0xb09
377 #define CSR_MHPMCOUNTER10   0xb0a
378 #define CSR_MHPMCOUNTER11   0xb0b
379 #define CSR_MHPMCOUNTER12   0xb0c
380 #define CSR_MHPMCOUNTER13   0xb0d
381 #define CSR_MHPMCOUNTER14   0xb0e
382 #define CSR_MHPMCOUNTER15   0xb0f
383 #define CSR_MHPMCOUNTER16   0xb10
384 #define CSR_MHPMCOUNTER17   0xb11
385 #define CSR_MHPMCOUNTER18   0xb12
386 #define CSR_MHPMCOUNTER19   0xb13
387 #define CSR_MHPMCOUNTER20   0xb14
388 #define CSR_MHPMCOUNTER21   0xb15
389 #define CSR_MHPMCOUNTER22   0xb16
390 #define CSR_MHPMCOUNTER23   0xb17
391 #define CSR_MHPMCOUNTER24   0xb18
392 #define CSR_MHPMCOUNTER25   0xb19
393 #define CSR_MHPMCOUNTER26   0xb1a
394 #define CSR_MHPMCOUNTER27   0xb1b
395 #define CSR_MHPMCOUNTER28   0xb1c
396 #define CSR_MHPMCOUNTER29   0xb1d
397 #define CSR_MHPMCOUNTER30   0xb1e
398 #define CSR_MHPMCOUNTER31   0xb1f
399 
400 /* Machine counter-inhibit register */
401 #define CSR_MCOUNTINHIBIT   0x320
402 
403 /* Machine counter configuration registers */
404 #define CSR_MCYCLECFG       0x321
405 #define CSR_MINSTRETCFG     0x322
406 
407 #define CSR_MHPMEVENT3      0x323
408 #define CSR_MHPMEVENT4      0x324
409 #define CSR_MHPMEVENT5      0x325
410 #define CSR_MHPMEVENT6      0x326
411 #define CSR_MHPMEVENT7      0x327
412 #define CSR_MHPMEVENT8      0x328
413 #define CSR_MHPMEVENT9      0x329
414 #define CSR_MHPMEVENT10     0x32a
415 #define CSR_MHPMEVENT11     0x32b
416 #define CSR_MHPMEVENT12     0x32c
417 #define CSR_MHPMEVENT13     0x32d
418 #define CSR_MHPMEVENT14     0x32e
419 #define CSR_MHPMEVENT15     0x32f
420 #define CSR_MHPMEVENT16     0x330
421 #define CSR_MHPMEVENT17     0x331
422 #define CSR_MHPMEVENT18     0x332
423 #define CSR_MHPMEVENT19     0x333
424 #define CSR_MHPMEVENT20     0x334
425 #define CSR_MHPMEVENT21     0x335
426 #define CSR_MHPMEVENT22     0x336
427 #define CSR_MHPMEVENT23     0x337
428 #define CSR_MHPMEVENT24     0x338
429 #define CSR_MHPMEVENT25     0x339
430 #define CSR_MHPMEVENT26     0x33a
431 #define CSR_MHPMEVENT27     0x33b
432 #define CSR_MHPMEVENT28     0x33c
433 #define CSR_MHPMEVENT29     0x33d
434 #define CSR_MHPMEVENT30     0x33e
435 #define CSR_MHPMEVENT31     0x33f
436 
437 #define CSR_MCYCLECFGH      0x721
438 #define CSR_MINSTRETCFGH    0x722
439 
440 #define CSR_MHPMEVENT3H     0x723
441 #define CSR_MHPMEVENT4H     0x724
442 #define CSR_MHPMEVENT5H     0x725
443 #define CSR_MHPMEVENT6H     0x726
444 #define CSR_MHPMEVENT7H     0x727
445 #define CSR_MHPMEVENT8H     0x728
446 #define CSR_MHPMEVENT9H     0x729
447 #define CSR_MHPMEVENT10H    0x72a
448 #define CSR_MHPMEVENT11H    0x72b
449 #define CSR_MHPMEVENT12H    0x72c
450 #define CSR_MHPMEVENT13H    0x72d
451 #define CSR_MHPMEVENT14H    0x72e
452 #define CSR_MHPMEVENT15H    0x72f
453 #define CSR_MHPMEVENT16H    0x730
454 #define CSR_MHPMEVENT17H    0x731
455 #define CSR_MHPMEVENT18H    0x732
456 #define CSR_MHPMEVENT19H    0x733
457 #define CSR_MHPMEVENT20H    0x734
458 #define CSR_MHPMEVENT21H    0x735
459 #define CSR_MHPMEVENT22H    0x736
460 #define CSR_MHPMEVENT23H    0x737
461 #define CSR_MHPMEVENT24H    0x738
462 #define CSR_MHPMEVENT25H    0x739
463 #define CSR_MHPMEVENT26H    0x73a
464 #define CSR_MHPMEVENT27H    0x73b
465 #define CSR_MHPMEVENT28H    0x73c
466 #define CSR_MHPMEVENT29H    0x73d
467 #define CSR_MHPMEVENT30H    0x73e
468 #define CSR_MHPMEVENT31H    0x73f
469 
470 #define CSR_MHPMCOUNTER3H   0xb83
471 #define CSR_MHPMCOUNTER4H   0xb84
472 #define CSR_MHPMCOUNTER5H   0xb85
473 #define CSR_MHPMCOUNTER6H   0xb86
474 #define CSR_MHPMCOUNTER7H   0xb87
475 #define CSR_MHPMCOUNTER8H   0xb88
476 #define CSR_MHPMCOUNTER9H   0xb89
477 #define CSR_MHPMCOUNTER10H  0xb8a
478 #define CSR_MHPMCOUNTER11H  0xb8b
479 #define CSR_MHPMCOUNTER12H  0xb8c
480 #define CSR_MHPMCOUNTER13H  0xb8d
481 #define CSR_MHPMCOUNTER14H  0xb8e
482 #define CSR_MHPMCOUNTER15H  0xb8f
483 #define CSR_MHPMCOUNTER16H  0xb90
484 #define CSR_MHPMCOUNTER17H  0xb91
485 #define CSR_MHPMCOUNTER18H  0xb92
486 #define CSR_MHPMCOUNTER19H  0xb93
487 #define CSR_MHPMCOUNTER20H  0xb94
488 #define CSR_MHPMCOUNTER21H  0xb95
489 #define CSR_MHPMCOUNTER22H  0xb96
490 #define CSR_MHPMCOUNTER23H  0xb97
491 #define CSR_MHPMCOUNTER24H  0xb98
492 #define CSR_MHPMCOUNTER25H  0xb99
493 #define CSR_MHPMCOUNTER26H  0xb9a
494 #define CSR_MHPMCOUNTER27H  0xb9b
495 #define CSR_MHPMCOUNTER28H  0xb9c
496 #define CSR_MHPMCOUNTER29H  0xb9d
497 #define CSR_MHPMCOUNTER30H  0xb9e
498 #define CSR_MHPMCOUNTER31H  0xb9f
499 
500 /*
501  * User PointerMasking registers
502  * NB: actual CSR numbers might be changed in future
503  */
504 #define CSR_UMTE            0x4c0
505 #define CSR_UPMMASK         0x4c1
506 #define CSR_UPMBASE         0x4c2
507 
508 /*
509  * Machine PointerMasking registers
510  * NB: actual CSR numbers might be changed in future
511  */
512 #define CSR_MMTE            0x3c0
513 #define CSR_MPMMASK         0x3c1
514 #define CSR_MPMBASE         0x3c2
515 
516 /*
517  * Supervisor PointerMaster registers
518  * NB: actual CSR numbers might be changed in future
519  */
520 #define CSR_SMTE            0x1c0
521 #define CSR_SPMMASK         0x1c1
522 #define CSR_SPMBASE         0x1c2
523 
524 /*
525  * Hypervisor PointerMaster registers
526  * NB: actual CSR numbers might be changed in future
527  */
528 #define CSR_VSMTE           0x2c0
529 #define CSR_VSPMMASK        0x2c1
530 #define CSR_VSPMBASE        0x2c2
531 #define CSR_SCOUNTOVF       0xda0
532 
533 /* Crypto Extension */
534 #define CSR_SEED            0x015
535 
536 /* Zcmt Extension */
537 #define CSR_JVT             0x017
538 
539 /* mstatus CSR bits */
540 #define MSTATUS_UIE         0x00000001
541 #define MSTATUS_SIE         0x00000002
542 #define MSTATUS_MIE         0x00000008
543 #define MSTATUS_UPIE        0x00000010
544 #define MSTATUS_SPIE        0x00000020
545 #define MSTATUS_UBE         0x00000040
546 #define MSTATUS_MPIE        0x00000080
547 #define MSTATUS_SPP         0x00000100
548 #define MSTATUS_VS          0x00000600
549 #define MSTATUS_MPP         0x00001800
550 #define MSTATUS_FS          0x00006000
551 #define MSTATUS_XS          0x00018000
552 #define MSTATUS_MPRV        0x00020000
553 #define MSTATUS_SUM         0x00040000 /* since: priv-1.10 */
554 #define MSTATUS_MXR         0x00080000
555 #define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */
556 #define MSTATUS_TW          0x00200000 /* since: priv-1.10 */
557 #define MSTATUS_TSR         0x00400000 /* since: priv-1.10 */
558 #define MSTATUS_SPELP       0x00800000 /* zicfilp */
559 #define MSTATUS_MPELP       0x020000000000 /* zicfilp */
560 #define MSTATUS_GVA         0x4000000000ULL
561 #define MSTATUS_MPV         0x8000000000ULL
562 
563 #define MSTATUS64_UXL       0x0000000300000000ULL
564 #define MSTATUS64_SXL       0x0000000C00000000ULL
565 
566 #define MSTATUS32_SD        0x80000000
567 #define MSTATUS64_SD        0x8000000000000000ULL
568 #define MSTATUSH128_SD      0x8000000000000000ULL
569 
570 #define MISA32_MXL          0xC0000000
571 #define MISA64_MXL          0xC000000000000000ULL
572 
573 typedef enum {
574     MXL_RV32  = 1,
575     MXL_RV64  = 2,
576     MXL_RV128 = 3,
577 } RISCVMXL;
578 
579 /* sstatus CSR bits */
580 #define SSTATUS_UIE         0x00000001
581 #define SSTATUS_SIE         0x00000002
582 #define SSTATUS_UPIE        0x00000010
583 #define SSTATUS_SPIE        0x00000020
584 #define SSTATUS_SPP         0x00000100
585 #define SSTATUS_VS          0x00000600
586 #define SSTATUS_FS          0x00006000
587 #define SSTATUS_XS          0x00018000
588 #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
589 #define SSTATUS_MXR         0x00080000
590 #define SSTATUS_SPELP       MSTATUS_SPELP   /* zicfilp */
591 
592 #define SSTATUS64_UXL       0x0000000300000000ULL
593 
594 #define SSTATUS32_SD        0x80000000
595 #define SSTATUS64_SD        0x8000000000000000ULL
596 
597 /* hstatus CSR bits */
598 #define HSTATUS_VSBE         0x00000020
599 #define HSTATUS_GVA          0x00000040
600 #define HSTATUS_SPV          0x00000080
601 #define HSTATUS_SPVP         0x00000100
602 #define HSTATUS_HU           0x00000200
603 #define HSTATUS_VGEIN        0x0003F000
604 #define HSTATUS_VTVM         0x00100000
605 #define HSTATUS_VTW          0x00200000
606 #define HSTATUS_VTSR         0x00400000
607 #define HSTATUS_VSXL         0x300000000
608 
609 #define HSTATUS32_WPRI       0xFF8FF87E
610 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
611 
612 #define COUNTEREN_CY         (1 << 0)
613 #define COUNTEREN_TM         (1 << 1)
614 #define COUNTEREN_IR         (1 << 2)
615 #define COUNTEREN_HPM3       (1 << 3)
616 
617 /* vsstatus CSR bits */
618 #define VSSTATUS64_UXL       0x0000000300000000ULL
619 
620 /* Privilege modes */
621 #define PRV_U 0
622 #define PRV_S 1
623 #define PRV_RESERVED 2
624 #define PRV_M 3
625 
626 /* RV32 satp CSR field masks */
627 #define SATP32_MODE         0x80000000
628 #define SATP32_ASID         0x7fc00000
629 #define SATP32_PPN          0x003fffff
630 
631 /* RV64 satp CSR field masks */
632 #define SATP64_MODE         0xF000000000000000ULL
633 #define SATP64_ASID         0x0FFFF00000000000ULL
634 #define SATP64_PPN          0x00000FFFFFFFFFFFULL
635 
636 /* VM modes (satp.mode) privileged ISA 1.10 */
637 #define VM_1_10_MBARE       0
638 #define VM_1_10_SV32        1
639 #define VM_1_10_SV39        8
640 #define VM_1_10_SV48        9
641 #define VM_1_10_SV57        10
642 #define VM_1_10_SV64        11
643 
644 /* Page table entry (PTE) fields */
645 #define PTE_V               0x001 /* Valid */
646 #define PTE_R               0x002 /* Read */
647 #define PTE_W               0x004 /* Write */
648 #define PTE_X               0x008 /* Execute */
649 #define PTE_U               0x010 /* User */
650 #define PTE_G               0x020 /* Global */
651 #define PTE_A               0x040 /* Accessed */
652 #define PTE_D               0x080 /* Dirty */
653 #define PTE_SOFT            0x300 /* Reserved for Software */
654 #define PTE_PBMT            0x6000000000000000ULL /* Page-based memory types */
655 #define PTE_N               0x8000000000000000ULL /* NAPOT translation */
656 #define PTE_RESERVED        0x1FC0000000000000ULL /* Reserved bits */
657 #define PTE_ATTR            (PTE_N | PTE_PBMT) /* All attributes bits */
658 
659 /* Page table PPN shift amount */
660 #define PTE_PPN_SHIFT       10
661 
662 /* Page table PPN mask */
663 #define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
664 
665 /* Leaf page shift amount */
666 #define PGSHIFT             12
667 
668 /* Default Reset Vector address */
669 #define DEFAULT_RSTVEC      0x1000
670 
671 /* Exception causes */
672 typedef enum RISCVException {
673     RISCV_EXCP_NONE = -1, /* sentinel value */
674     RISCV_EXCP_INST_ADDR_MIS = 0x0,
675     RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
676     RISCV_EXCP_ILLEGAL_INST = 0x2,
677     RISCV_EXCP_BREAKPOINT = 0x3,
678     RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
679     RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
680     RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
681     RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
682     RISCV_EXCP_U_ECALL = 0x8,
683     RISCV_EXCP_S_ECALL = 0x9,
684     RISCV_EXCP_VS_ECALL = 0xa,
685     RISCV_EXCP_M_ECALL = 0xb,
686     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
687     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
688     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
689     RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
690     RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
691     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
692     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
693     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
694     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
695     RISCV_EXCP_SEMIHOST = 0x3f,
696 } RISCVException;
697 
698 /* zicfilp defines lp violation results in sw check with tval = 2*/
699 #define RISCV_EXCP_SW_CHECK_FCFI_TVAL      2
700 /* zicfiss defines ss violation results in sw check with tval = 3*/
701 #define RISCV_EXCP_SW_CHECK_BCFI_TVAL      3
702 
703 #define RISCV_EXCP_INT_FLAG                0x80000000
704 #define RISCV_EXCP_INT_MASK                0x7fffffff
705 
706 /* Interrupt causes */
707 #define IRQ_U_SOFT                         0
708 #define IRQ_S_SOFT                         1
709 #define IRQ_VS_SOFT                        2
710 #define IRQ_M_SOFT                         3
711 #define IRQ_U_TIMER                        4
712 #define IRQ_S_TIMER                        5
713 #define IRQ_VS_TIMER                       6
714 #define IRQ_M_TIMER                        7
715 #define IRQ_U_EXT                          8
716 #define IRQ_S_EXT                          9
717 #define IRQ_VS_EXT                         10
718 #define IRQ_M_EXT                          11
719 #define IRQ_S_GEXT                         12
720 #define IRQ_PMU_OVF                        13
721 #define IRQ_LOCAL_MAX                      64
722 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
723 #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
724 
725 /* mip masks */
726 #define MIP_USIP                           (1 << IRQ_U_SOFT)
727 #define MIP_SSIP                           (1 << IRQ_S_SOFT)
728 #define MIP_VSSIP                          (1 << IRQ_VS_SOFT)
729 #define MIP_MSIP                           (1 << IRQ_M_SOFT)
730 #define MIP_UTIP                           (1 << IRQ_U_TIMER)
731 #define MIP_STIP                           (1 << IRQ_S_TIMER)
732 #define MIP_VSTIP                          (1 << IRQ_VS_TIMER)
733 #define MIP_MTIP                           (1 << IRQ_M_TIMER)
734 #define MIP_UEIP                           (1 << IRQ_U_EXT)
735 #define MIP_SEIP                           (1 << IRQ_S_EXT)
736 #define MIP_VSEIP                          (1 << IRQ_VS_EXT)
737 #define MIP_MEIP                           (1 << IRQ_M_EXT)
738 #define MIP_SGEIP                          (1 << IRQ_S_GEXT)
739 #define MIP_LCOFIP                         (1 << IRQ_PMU_OVF)
740 
741 /* sip masks */
742 #define SIP_SSIP                           MIP_SSIP
743 #define SIP_STIP                           MIP_STIP
744 #define SIP_SEIP                           MIP_SEIP
745 #define SIP_LCOFIP                         MIP_LCOFIP
746 
747 /* MIE masks */
748 #define MIE_SEIE                           (1 << IRQ_S_EXT)
749 #define MIE_UEIE                           (1 << IRQ_U_EXT)
750 #define MIE_STIE                           (1 << IRQ_S_TIMER)
751 #define MIE_UTIE                           (1 << IRQ_U_TIMER)
752 #define MIE_SSIE                           (1 << IRQ_S_SOFT)
753 #define MIE_USIE                           (1 << IRQ_U_SOFT)
754 
755 /* Machine constants */
756 #define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
757 #define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
758 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
759 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
760 
761 /* General PointerMasking CSR bits */
762 #define PM_ENABLE       0x00000001ULL
763 #define PM_CURRENT      0x00000002ULL
764 #define PM_INSN         0x00000004ULL
765 
766 /* Execution environment configuration bits */
767 #define MENVCFG_FIOM                       BIT(0)
768 #define MENVCFG_LPE                        BIT(2) /* zicfilp */
769 #define MENVCFG_SSE                        BIT(3) /* zicfiss */
770 #define MENVCFG_CBIE                       (3UL << 4)
771 #define MENVCFG_CBCFE                      BIT(6)
772 #define MENVCFG_CBZE                       BIT(7)
773 #define MENVCFG_ADUE                       (1ULL << 61)
774 #define MENVCFG_PBMTE                      (1ULL << 62)
775 #define MENVCFG_STCE                       (1ULL << 63)
776 
777 /* For RV32 */
778 #define MENVCFGH_ADUE                      BIT(29)
779 #define MENVCFGH_PBMTE                     BIT(30)
780 #define MENVCFGH_STCE                      BIT(31)
781 
782 #define SENVCFG_FIOM                       MENVCFG_FIOM
783 #define SENVCFG_LPE                        MENVCFG_LPE
784 #define SENVCFG_SSE                        MENVCFG_SSE
785 #define SENVCFG_CBIE                       MENVCFG_CBIE
786 #define SENVCFG_CBCFE                      MENVCFG_CBCFE
787 #define SENVCFG_CBZE                       MENVCFG_CBZE
788 
789 #define HENVCFG_FIOM                       MENVCFG_FIOM
790 #define HENVCFG_LPE                        MENVCFG_LPE
791 #define HENVCFG_SSE                        MENVCFG_SSE
792 #define HENVCFG_CBIE                       MENVCFG_CBIE
793 #define HENVCFG_CBCFE                      MENVCFG_CBCFE
794 #define HENVCFG_CBZE                       MENVCFG_CBZE
795 #define HENVCFG_ADUE                       MENVCFG_ADUE
796 #define HENVCFG_PBMTE                      MENVCFG_PBMTE
797 #define HENVCFG_STCE                       MENVCFG_STCE
798 
799 /* For RV32 */
800 #define HENVCFGH_ADUE                       MENVCFGH_ADUE
801 #define HENVCFGH_PBMTE                      MENVCFGH_PBMTE
802 #define HENVCFGH_STCE                       MENVCFGH_STCE
803 
804 /* Offsets for every pair of control bits per each priv level */
805 #define XS_OFFSET    0ULL
806 #define U_OFFSET     2ULL
807 #define S_OFFSET     5ULL
808 #define M_OFFSET     8ULL
809 
810 #define PM_XS_BITS   (EXT_STATUS_MASK << XS_OFFSET)
811 #define U_PM_ENABLE  (PM_ENABLE  << U_OFFSET)
812 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
813 #define U_PM_INSN    (PM_INSN    << U_OFFSET)
814 #define S_PM_ENABLE  (PM_ENABLE  << S_OFFSET)
815 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
816 #define S_PM_INSN    (PM_INSN    << S_OFFSET)
817 #define M_PM_ENABLE  (PM_ENABLE  << M_OFFSET)
818 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
819 #define M_PM_INSN    (PM_INSN    << M_OFFSET)
820 
821 /* mmte CSR bits */
822 #define MMTE_PM_XS_BITS     PM_XS_BITS
823 #define MMTE_U_PM_ENABLE    U_PM_ENABLE
824 #define MMTE_U_PM_CURRENT   U_PM_CURRENT
825 #define MMTE_U_PM_INSN      U_PM_INSN
826 #define MMTE_S_PM_ENABLE    S_PM_ENABLE
827 #define MMTE_S_PM_CURRENT   S_PM_CURRENT
828 #define MMTE_S_PM_INSN      S_PM_INSN
829 #define MMTE_M_PM_ENABLE    M_PM_ENABLE
830 #define MMTE_M_PM_CURRENT   M_PM_CURRENT
831 #define MMTE_M_PM_INSN      M_PM_INSN
832 #define MMTE_MASK    (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
833                       MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
834                       MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
835                       MMTE_PM_XS_BITS)
836 
837 /* (v)smte CSR bits */
838 #define SMTE_PM_XS_BITS     PM_XS_BITS
839 #define SMTE_U_PM_ENABLE    U_PM_ENABLE
840 #define SMTE_U_PM_CURRENT   U_PM_CURRENT
841 #define SMTE_U_PM_INSN      U_PM_INSN
842 #define SMTE_S_PM_ENABLE    S_PM_ENABLE
843 #define SMTE_S_PM_CURRENT   S_PM_CURRENT
844 #define SMTE_S_PM_INSN      S_PM_INSN
845 #define SMTE_MASK    (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
846                       SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
847                       SMTE_PM_XS_BITS)
848 
849 /* umte CSR bits */
850 #define UMTE_U_PM_ENABLE    U_PM_ENABLE
851 #define UMTE_U_PM_CURRENT   U_PM_CURRENT
852 #define UMTE_U_PM_INSN      U_PM_INSN
853 #define UMTE_MASK     (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
854 
855 /* MISELECT, SISELECT, and VSISELECT bits (AIA) */
856 #define ISELECT_IPRIO0                     0x30
857 #define ISELECT_IPRIO15                    0x3f
858 #define ISELECT_IMSIC_EIDELIVERY           0x70
859 #define ISELECT_IMSIC_EITHRESHOLD          0x72
860 #define ISELECT_IMSIC_EIP0                 0x80
861 #define ISELECT_IMSIC_EIP63                0xbf
862 #define ISELECT_IMSIC_EIE0                 0xc0
863 #define ISELECT_IMSIC_EIE63                0xff
864 #define ISELECT_IMSIC_FIRST                ISELECT_IMSIC_EIDELIVERY
865 #define ISELECT_IMSIC_LAST                 ISELECT_IMSIC_EIE63
866 #define ISELECT_MASK                       0x1ff
867 
868 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */
869 #define ISELECT_IMSIC_TOPEI                (ISELECT_MASK + 1)
870 
871 /* IMSIC bits (AIA) */
872 #define IMSIC_TOPEI_IID_SHIFT              16
873 #define IMSIC_TOPEI_IID_MASK               0x7ff
874 #define IMSIC_TOPEI_IPRIO_MASK             0x7ff
875 #define IMSIC_EIPx_BITS                    32
876 #define IMSIC_EIEx_BITS                    32
877 
878 /* MTOPI and STOPI bits (AIA) */
879 #define TOPI_IID_SHIFT                     16
880 #define TOPI_IID_MASK                      0xfff
881 #define TOPI_IPRIO_MASK                    0xff
882 
883 /* Interrupt priority bits (AIA) */
884 #define IPRIO_IRQ_BITS                     8
885 #define IPRIO_MMAXIPRIO                    255
886 #define IPRIO_DEFAULT_UPPER                4
887 #define IPRIO_DEFAULT_MIDDLE               (IPRIO_DEFAULT_UPPER + 12)
888 #define IPRIO_DEFAULT_M                    IPRIO_DEFAULT_MIDDLE
889 #define IPRIO_DEFAULT_S                    (IPRIO_DEFAULT_M + 3)
890 #define IPRIO_DEFAULT_SGEXT                (IPRIO_DEFAULT_S + 3)
891 #define IPRIO_DEFAULT_VS                   (IPRIO_DEFAULT_SGEXT + 1)
892 #define IPRIO_DEFAULT_LOWER                (IPRIO_DEFAULT_VS + 3)
893 
894 /* HVICTL bits (AIA) */
895 #define HVICTL_VTI                         0x40000000
896 #define HVICTL_IID                         0x0fff0000
897 #define HVICTL_IPRIOM                      0x00000100
898 #define HVICTL_IPRIO                       0x000000ff
899 #define HVICTL_VALID_MASK                  \
900     (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
901 
902 /* seed CSR bits */
903 #define SEED_OPST                        (0b11 << 30)
904 #define SEED_OPST_BIST                   (0b00 << 30)
905 #define SEED_OPST_WAIT                   (0b01 << 30)
906 #define SEED_OPST_ES16                   (0b10 << 30)
907 #define SEED_OPST_DEAD                   (0b11 << 30)
908 /* PMU related bits */
909 #define MIE_LCOFIE                         (1 << IRQ_PMU_OVF)
910 
911 #define MCYCLECFG_BIT_MINH                 BIT_ULL(62)
912 #define MCYCLECFGH_BIT_MINH                BIT(30)
913 #define MCYCLECFG_BIT_SINH                 BIT_ULL(61)
914 #define MCYCLECFGH_BIT_SINH                BIT(29)
915 #define MCYCLECFG_BIT_UINH                 BIT_ULL(60)
916 #define MCYCLECFGH_BIT_UINH                BIT(28)
917 #define MCYCLECFG_BIT_VSINH                BIT_ULL(59)
918 #define MCYCLECFGH_BIT_VSINH               BIT(27)
919 #define MCYCLECFG_BIT_VUINH                BIT_ULL(58)
920 #define MCYCLECFGH_BIT_VUINH               BIT(26)
921 
922 #define MINSTRETCFG_BIT_MINH               BIT_ULL(62)
923 #define MINSTRETCFGH_BIT_MINH              BIT(30)
924 #define MINSTRETCFG_BIT_SINH               BIT_ULL(61)
925 #define MINSTRETCFGH_BIT_SINH              BIT(29)
926 #define MINSTRETCFG_BIT_UINH               BIT_ULL(60)
927 #define MINSTRETCFGH_BIT_UINH              BIT(28)
928 #define MINSTRETCFG_BIT_VSINH              BIT_ULL(59)
929 #define MINSTRETCFGH_BIT_VSINH             BIT(27)
930 #define MINSTRETCFG_BIT_VUINH              BIT_ULL(58)
931 #define MINSTRETCFGH_BIT_VUINH             BIT(26)
932 
933 #define MHPMEVENT_BIT_OF                   BIT_ULL(63)
934 #define MHPMEVENTH_BIT_OF                  BIT(31)
935 #define MHPMEVENT_BIT_MINH                 BIT_ULL(62)
936 #define MHPMEVENTH_BIT_MINH                BIT(30)
937 #define MHPMEVENT_BIT_SINH                 BIT_ULL(61)
938 #define MHPMEVENTH_BIT_SINH                BIT(29)
939 #define MHPMEVENT_BIT_UINH                 BIT_ULL(60)
940 #define MHPMEVENTH_BIT_UINH                BIT(28)
941 #define MHPMEVENT_BIT_VSINH                BIT_ULL(59)
942 #define MHPMEVENTH_BIT_VSINH               BIT(27)
943 #define MHPMEVENT_BIT_VUINH                BIT_ULL(58)
944 #define MHPMEVENTH_BIT_VUINH               BIT(26)
945 
946 #define MHPMEVENT_FILTER_MASK              (MHPMEVENT_BIT_MINH  | \
947                                             MHPMEVENT_BIT_SINH  | \
948                                             MHPMEVENT_BIT_UINH  | \
949                                             MHPMEVENT_BIT_VSINH | \
950                                             MHPMEVENT_BIT_VUINH)
951 
952 #define MHPMEVENTH_FILTER_MASK              (MHPMEVENTH_BIT_MINH  | \
953                                             MHPMEVENTH_BIT_SINH  | \
954                                             MHPMEVENTH_BIT_UINH  | \
955                                             MHPMEVENTH_BIT_VSINH | \
956                                             MHPMEVENTH_BIT_VUINH)
957 
958 #define MHPMEVENT_SSCOF_MASK               _ULL(0xFFFF000000000000)
959 #define MHPMEVENT_IDX_MASK                 0xFFFFF
960 #define MHPMEVENT_SSCOF_RESVD              16
961 
962 /* JVT CSR bits */
963 #define JVT_MODE                           0x3F
964 #define JVT_BASE                           (~0x3F)
965 
966 /* Debug Sdtrig CSR masks */
967 #define TEXTRA32_MHVALUE                   0xFC000000
968 #define TEXTRA32_MHSELECT                  0x03800000
969 #define TEXTRA32_SBYTEMASK                 0x000C0000
970 #define TEXTRA32_SVALUE                    0x0003FFFC
971 #define TEXTRA32_SSELECT                   0x00000003
972 #define TEXTRA64_MHVALUE                   0xFFF8000000000000ULL
973 #define TEXTRA64_MHSELECT                  0x0007000000000000ULL
974 #define TEXTRA64_SBYTEMASK                 0x000000F000000000ULL
975 #define TEXTRA64_SVALUE                    0x00000003FFFFFFFCULL
976 #define TEXTRA64_SSELECT                   0x0000000000000003ULL
977 #define MCONTEXT32                         0x0000003F
978 #define MCONTEXT64                         0x0000000000001FFFULL
979 #define MCONTEXT32_HCONTEXT                0x0000007F
980 #define MCONTEXT64_HCONTEXT                0x0000000000003FFFULL
981 #endif
982