1 /* RISC-V ISA constants */ 2 3 #ifndef TARGET_RISCV_CPU_BITS_H 4 #define TARGET_RISCV_CPU_BITS_H 5 6 #define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ 9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ 10 (uint64_t)(mask))) 11 12 /* Extension context status mask */ 13 #define EXT_STATUS_MASK 0x3ULL 14 15 /* Floating point round mode */ 16 #define FSR_RD_SHIFT 5 17 #define FSR_RD (0x7 << FSR_RD_SHIFT) 18 19 /* Floating point accrued exception flags */ 20 #define FPEXC_NX 0x01 21 #define FPEXC_UF 0x02 22 #define FPEXC_OF 0x04 23 #define FPEXC_DZ 0x08 24 #define FPEXC_NV 0x10 25 26 /* Floating point status register bits */ 27 #define FSR_AEXC_SHIFT 0 28 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 29 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 30 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 31 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 32 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 33 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 34 35 /* Vector Fixed-Point round model */ 36 #define FSR_VXRM_SHIFT 9 37 #define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) 38 39 /* Vector Fixed-Point saturation flag */ 40 #define FSR_VXSAT_SHIFT 8 41 #define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) 42 43 /* Control and Status Registers */ 44 45 /* User Trap Setup */ 46 #define CSR_USTATUS 0x000 47 #define CSR_UIE 0x004 48 #define CSR_UTVEC 0x005 49 50 /* User Trap Handling */ 51 #define CSR_USCRATCH 0x040 52 #define CSR_UEPC 0x041 53 #define CSR_UCAUSE 0x042 54 #define CSR_UTVAL 0x043 55 #define CSR_UIP 0x044 56 57 /* User Floating-Point CSRs */ 58 #define CSR_FFLAGS 0x001 59 #define CSR_FRM 0x002 60 #define CSR_FCSR 0x003 61 62 /* User Vector CSRs */ 63 #define CSR_VSTART 0x008 64 #define CSR_VXSAT 0x009 65 #define CSR_VXRM 0x00a 66 #define CSR_VCSR 0x00f 67 #define CSR_VL 0xc20 68 #define CSR_VTYPE 0xc21 69 #define CSR_VLENB 0xc22 70 71 /* VCSR fields */ 72 #define VCSR_VXSAT_SHIFT 0 73 #define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) 74 #define VCSR_VXRM_SHIFT 1 75 #define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) 76 77 /* User Timers and Counters */ 78 #define CSR_CYCLE 0xc00 79 #define CSR_TIME 0xc01 80 #define CSR_INSTRET 0xc02 81 #define CSR_HPMCOUNTER3 0xc03 82 #define CSR_HPMCOUNTER4 0xc04 83 #define CSR_HPMCOUNTER5 0xc05 84 #define CSR_HPMCOUNTER6 0xc06 85 #define CSR_HPMCOUNTER7 0xc07 86 #define CSR_HPMCOUNTER8 0xc08 87 #define CSR_HPMCOUNTER9 0xc09 88 #define CSR_HPMCOUNTER10 0xc0a 89 #define CSR_HPMCOUNTER11 0xc0b 90 #define CSR_HPMCOUNTER12 0xc0c 91 #define CSR_HPMCOUNTER13 0xc0d 92 #define CSR_HPMCOUNTER14 0xc0e 93 #define CSR_HPMCOUNTER15 0xc0f 94 #define CSR_HPMCOUNTER16 0xc10 95 #define CSR_HPMCOUNTER17 0xc11 96 #define CSR_HPMCOUNTER18 0xc12 97 #define CSR_HPMCOUNTER19 0xc13 98 #define CSR_HPMCOUNTER20 0xc14 99 #define CSR_HPMCOUNTER21 0xc15 100 #define CSR_HPMCOUNTER22 0xc16 101 #define CSR_HPMCOUNTER23 0xc17 102 #define CSR_HPMCOUNTER24 0xc18 103 #define CSR_HPMCOUNTER25 0xc19 104 #define CSR_HPMCOUNTER26 0xc1a 105 #define CSR_HPMCOUNTER27 0xc1b 106 #define CSR_HPMCOUNTER28 0xc1c 107 #define CSR_HPMCOUNTER29 0xc1d 108 #define CSR_HPMCOUNTER30 0xc1e 109 #define CSR_HPMCOUNTER31 0xc1f 110 #define CSR_CYCLEH 0xc80 111 #define CSR_TIMEH 0xc81 112 #define CSR_INSTRETH 0xc82 113 #define CSR_HPMCOUNTER3H 0xc83 114 #define CSR_HPMCOUNTER4H 0xc84 115 #define CSR_HPMCOUNTER5H 0xc85 116 #define CSR_HPMCOUNTER6H 0xc86 117 #define CSR_HPMCOUNTER7H 0xc87 118 #define CSR_HPMCOUNTER8H 0xc88 119 #define CSR_HPMCOUNTER9H 0xc89 120 #define CSR_HPMCOUNTER10H 0xc8a 121 #define CSR_HPMCOUNTER11H 0xc8b 122 #define CSR_HPMCOUNTER12H 0xc8c 123 #define CSR_HPMCOUNTER13H 0xc8d 124 #define CSR_HPMCOUNTER14H 0xc8e 125 #define CSR_HPMCOUNTER15H 0xc8f 126 #define CSR_HPMCOUNTER16H 0xc90 127 #define CSR_HPMCOUNTER17H 0xc91 128 #define CSR_HPMCOUNTER18H 0xc92 129 #define CSR_HPMCOUNTER19H 0xc93 130 #define CSR_HPMCOUNTER20H 0xc94 131 #define CSR_HPMCOUNTER21H 0xc95 132 #define CSR_HPMCOUNTER22H 0xc96 133 #define CSR_HPMCOUNTER23H 0xc97 134 #define CSR_HPMCOUNTER24H 0xc98 135 #define CSR_HPMCOUNTER25H 0xc99 136 #define CSR_HPMCOUNTER26H 0xc9a 137 #define CSR_HPMCOUNTER27H 0xc9b 138 #define CSR_HPMCOUNTER28H 0xc9c 139 #define CSR_HPMCOUNTER29H 0xc9d 140 #define CSR_HPMCOUNTER30H 0xc9e 141 #define CSR_HPMCOUNTER31H 0xc9f 142 143 /* Machine Timers and Counters */ 144 #define CSR_MCYCLE 0xb00 145 #define CSR_MINSTRET 0xb02 146 #define CSR_MCYCLEH 0xb80 147 #define CSR_MINSTRETH 0xb82 148 149 /* Machine Information Registers */ 150 #define CSR_MVENDORID 0xf11 151 #define CSR_MARCHID 0xf12 152 #define CSR_MIMPID 0xf13 153 #define CSR_MHARTID 0xf14 154 #define CSR_MCONFIGPTR 0xf15 155 156 /* Machine Trap Setup */ 157 #define CSR_MSTATUS 0x300 158 #define CSR_MISA 0x301 159 #define CSR_MEDELEG 0x302 160 #define CSR_MIDELEG 0x303 161 #define CSR_MIE 0x304 162 #define CSR_MTVEC 0x305 163 #define CSR_MCOUNTEREN 0x306 164 165 /* 32-bit only */ 166 #define CSR_MSTATUSH 0x310 167 168 /* Machine Trap Handling */ 169 #define CSR_MSCRATCH 0x340 170 #define CSR_MEPC 0x341 171 #define CSR_MCAUSE 0x342 172 #define CSR_MTVAL 0x343 173 #define CSR_MIP 0x344 174 175 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 176 #define CSR_MISELECT 0x350 177 #define CSR_MIREG 0x351 178 179 /* Machine-Level Interrupts (AIA) */ 180 #define CSR_MTOPEI 0x35c 181 #define CSR_MTOPI 0xfb0 182 183 /* Virtual Interrupts for Supervisor Level (AIA) */ 184 #define CSR_MVIEN 0x308 185 #define CSR_MVIP 0x309 186 187 /* Machine-Level High-Half CSRs (AIA) */ 188 #define CSR_MIDELEGH 0x313 189 #define CSR_MIEH 0x314 190 #define CSR_MVIENH 0x318 191 #define CSR_MVIPH 0x319 192 #define CSR_MIPH 0x354 193 194 /* Supervisor Trap Setup */ 195 #define CSR_SSTATUS 0x100 196 #define CSR_SIE 0x104 197 #define CSR_STVEC 0x105 198 #define CSR_SCOUNTEREN 0x106 199 200 /* Supervisor Configuration CSRs */ 201 #define CSR_SENVCFG 0x10A 202 203 /* Supervisor state CSRs */ 204 #define CSR_SSTATEEN0 0x10C 205 #define CSR_SSTATEEN1 0x10D 206 #define CSR_SSTATEEN2 0x10E 207 #define CSR_SSTATEEN3 0x10F 208 209 /* Supervisor Trap Handling */ 210 #define CSR_SSCRATCH 0x140 211 #define CSR_SEPC 0x141 212 #define CSR_SCAUSE 0x142 213 #define CSR_STVAL 0x143 214 #define CSR_SIP 0x144 215 216 /* Sstc supervisor CSRs */ 217 #define CSR_STIMECMP 0x14D 218 #define CSR_STIMECMPH 0x15D 219 220 /* Supervisor Protection and Translation */ 221 #define CSR_SPTBR 0x180 222 #define CSR_SATP 0x180 223 224 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 225 #define CSR_SISELECT 0x150 226 #define CSR_SIREG 0x151 227 228 /* Supervisor-Level Interrupts (AIA) */ 229 #define CSR_STOPEI 0x15c 230 #define CSR_STOPI 0xdb0 231 232 /* Supervisor-Level High-Half CSRs (AIA) */ 233 #define CSR_SIEH 0x114 234 #define CSR_SIPH 0x154 235 236 /* Hpervisor CSRs */ 237 #define CSR_HSTATUS 0x600 238 #define CSR_HEDELEG 0x602 239 #define CSR_HIDELEG 0x603 240 #define CSR_HIE 0x604 241 #define CSR_HCOUNTEREN 0x606 242 #define CSR_HGEIE 0x607 243 #define CSR_HTVAL 0x643 244 #define CSR_HVIP 0x645 245 #define CSR_HIP 0x644 246 #define CSR_HTINST 0x64A 247 #define CSR_HGEIP 0xE12 248 #define CSR_HGATP 0x680 249 #define CSR_HTIMEDELTA 0x605 250 #define CSR_HTIMEDELTAH 0x615 251 252 /* Hypervisor Configuration CSRs */ 253 #define CSR_HENVCFG 0x60A 254 #define CSR_HENVCFGH 0x61A 255 256 /* Hypervisor state CSRs */ 257 #define CSR_HSTATEEN0 0x60C 258 #define CSR_HSTATEEN0H 0x61C 259 #define CSR_HSTATEEN1 0x60D 260 #define CSR_HSTATEEN1H 0x61D 261 #define CSR_HSTATEEN2 0x60E 262 #define CSR_HSTATEEN2H 0x61E 263 #define CSR_HSTATEEN3 0x60F 264 #define CSR_HSTATEEN3H 0x61F 265 266 /* Virtual CSRs */ 267 #define CSR_VSSTATUS 0x200 268 #define CSR_VSIE 0x204 269 #define CSR_VSTVEC 0x205 270 #define CSR_VSSCRATCH 0x240 271 #define CSR_VSEPC 0x241 272 #define CSR_VSCAUSE 0x242 273 #define CSR_VSTVAL 0x243 274 #define CSR_VSIP 0x244 275 #define CSR_VSATP 0x280 276 277 /* Sstc virtual CSRs */ 278 #define CSR_VSTIMECMP 0x24D 279 #define CSR_VSTIMECMPH 0x25D 280 281 #define CSR_MTINST 0x34a 282 #define CSR_MTVAL2 0x34b 283 284 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 285 #define CSR_HVIEN 0x608 286 #define CSR_HVICTL 0x609 287 #define CSR_HVIPRIO1 0x646 288 #define CSR_HVIPRIO2 0x647 289 290 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 291 #define CSR_VSISELECT 0x250 292 #define CSR_VSIREG 0x251 293 294 /* VS-Level Interrupts (H-extension with AIA) */ 295 #define CSR_VSTOPEI 0x25c 296 #define CSR_VSTOPI 0xeb0 297 298 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 299 #define CSR_HIDELEGH 0x613 300 #define CSR_HVIENH 0x618 301 #define CSR_HVIPH 0x655 302 #define CSR_HVIPRIO1H 0x656 303 #define CSR_HVIPRIO2H 0x657 304 #define CSR_VSIEH 0x214 305 #define CSR_VSIPH 0x254 306 307 /* Machine Configuration CSRs */ 308 #define CSR_MENVCFG 0x30A 309 #define CSR_MENVCFGH 0x31A 310 311 /* Machine state CSRs */ 312 #define CSR_MSTATEEN0 0x30C 313 #define CSR_MSTATEEN0H 0x31C 314 #define CSR_MSTATEEN1 0x30D 315 #define CSR_MSTATEEN1H 0x31D 316 #define CSR_MSTATEEN2 0x30E 317 #define CSR_MSTATEEN2H 0x31E 318 #define CSR_MSTATEEN3 0x30F 319 #define CSR_MSTATEEN3H 0x31F 320 321 /* Common defines for all smstateen */ 322 #define SMSTATEEN_MAX_COUNT 4 323 #define SMSTATEEN0_CS (1ULL << 0) 324 #define SMSTATEEN0_FCSR (1ULL << 1) 325 #define SMSTATEEN0_JVT (1ULL << 2) 326 #define SMSTATEEN0_HSCONTXT (1ULL << 57) 327 #define SMSTATEEN0_IMSIC (1ULL << 58) 328 #define SMSTATEEN0_AIA (1ULL << 59) 329 #define SMSTATEEN0_SVSLCT (1ULL << 60) 330 #define SMSTATEEN0_HSENVCFG (1ULL << 62) 331 #define SMSTATEEN_STATEEN (1ULL << 63) 332 333 /* Enhanced Physical Memory Protection (ePMP) */ 334 #define CSR_MSECCFG 0x747 335 #define CSR_MSECCFGH 0x757 336 /* Physical Memory Protection */ 337 #define CSR_PMPCFG0 0x3a0 338 #define CSR_PMPCFG1 0x3a1 339 #define CSR_PMPCFG2 0x3a2 340 #define CSR_PMPCFG3 0x3a3 341 #define CSR_PMPADDR0 0x3b0 342 #define CSR_PMPADDR1 0x3b1 343 #define CSR_PMPADDR2 0x3b2 344 #define CSR_PMPADDR3 0x3b3 345 #define CSR_PMPADDR4 0x3b4 346 #define CSR_PMPADDR5 0x3b5 347 #define CSR_PMPADDR6 0x3b6 348 #define CSR_PMPADDR7 0x3b7 349 #define CSR_PMPADDR8 0x3b8 350 #define CSR_PMPADDR9 0x3b9 351 #define CSR_PMPADDR10 0x3ba 352 #define CSR_PMPADDR11 0x3bb 353 #define CSR_PMPADDR12 0x3bc 354 #define CSR_PMPADDR13 0x3bd 355 #define CSR_PMPADDR14 0x3be 356 #define CSR_PMPADDR15 0x3bf 357 358 /* Debug/Trace Registers (shared with Debug Mode) */ 359 #define CSR_TSELECT 0x7a0 360 #define CSR_TDATA1 0x7a1 361 #define CSR_TDATA2 0x7a2 362 #define CSR_TDATA3 0x7a3 363 #define CSR_TINFO 0x7a4 364 365 /* Debug Mode Registers */ 366 #define CSR_DCSR 0x7b0 367 #define CSR_DPC 0x7b1 368 #define CSR_DSCRATCH 0x7b2 369 370 /* Performance Counters */ 371 #define CSR_MHPMCOUNTER3 0xb03 372 #define CSR_MHPMCOUNTER4 0xb04 373 #define CSR_MHPMCOUNTER5 0xb05 374 #define CSR_MHPMCOUNTER6 0xb06 375 #define CSR_MHPMCOUNTER7 0xb07 376 #define CSR_MHPMCOUNTER8 0xb08 377 #define CSR_MHPMCOUNTER9 0xb09 378 #define CSR_MHPMCOUNTER10 0xb0a 379 #define CSR_MHPMCOUNTER11 0xb0b 380 #define CSR_MHPMCOUNTER12 0xb0c 381 #define CSR_MHPMCOUNTER13 0xb0d 382 #define CSR_MHPMCOUNTER14 0xb0e 383 #define CSR_MHPMCOUNTER15 0xb0f 384 #define CSR_MHPMCOUNTER16 0xb10 385 #define CSR_MHPMCOUNTER17 0xb11 386 #define CSR_MHPMCOUNTER18 0xb12 387 #define CSR_MHPMCOUNTER19 0xb13 388 #define CSR_MHPMCOUNTER20 0xb14 389 #define CSR_MHPMCOUNTER21 0xb15 390 #define CSR_MHPMCOUNTER22 0xb16 391 #define CSR_MHPMCOUNTER23 0xb17 392 #define CSR_MHPMCOUNTER24 0xb18 393 #define CSR_MHPMCOUNTER25 0xb19 394 #define CSR_MHPMCOUNTER26 0xb1a 395 #define CSR_MHPMCOUNTER27 0xb1b 396 #define CSR_MHPMCOUNTER28 0xb1c 397 #define CSR_MHPMCOUNTER29 0xb1d 398 #define CSR_MHPMCOUNTER30 0xb1e 399 #define CSR_MHPMCOUNTER31 0xb1f 400 401 /* Machine counter-inhibit register */ 402 #define CSR_MCOUNTINHIBIT 0x320 403 404 #define CSR_MHPMEVENT3 0x323 405 #define CSR_MHPMEVENT4 0x324 406 #define CSR_MHPMEVENT5 0x325 407 #define CSR_MHPMEVENT6 0x326 408 #define CSR_MHPMEVENT7 0x327 409 #define CSR_MHPMEVENT8 0x328 410 #define CSR_MHPMEVENT9 0x329 411 #define CSR_MHPMEVENT10 0x32a 412 #define CSR_MHPMEVENT11 0x32b 413 #define CSR_MHPMEVENT12 0x32c 414 #define CSR_MHPMEVENT13 0x32d 415 #define CSR_MHPMEVENT14 0x32e 416 #define CSR_MHPMEVENT15 0x32f 417 #define CSR_MHPMEVENT16 0x330 418 #define CSR_MHPMEVENT17 0x331 419 #define CSR_MHPMEVENT18 0x332 420 #define CSR_MHPMEVENT19 0x333 421 #define CSR_MHPMEVENT20 0x334 422 #define CSR_MHPMEVENT21 0x335 423 #define CSR_MHPMEVENT22 0x336 424 #define CSR_MHPMEVENT23 0x337 425 #define CSR_MHPMEVENT24 0x338 426 #define CSR_MHPMEVENT25 0x339 427 #define CSR_MHPMEVENT26 0x33a 428 #define CSR_MHPMEVENT27 0x33b 429 #define CSR_MHPMEVENT28 0x33c 430 #define CSR_MHPMEVENT29 0x33d 431 #define CSR_MHPMEVENT30 0x33e 432 #define CSR_MHPMEVENT31 0x33f 433 434 #define CSR_MHPMEVENT3H 0x723 435 #define CSR_MHPMEVENT4H 0x724 436 #define CSR_MHPMEVENT5H 0x725 437 #define CSR_MHPMEVENT6H 0x726 438 #define CSR_MHPMEVENT7H 0x727 439 #define CSR_MHPMEVENT8H 0x728 440 #define CSR_MHPMEVENT9H 0x729 441 #define CSR_MHPMEVENT10H 0x72a 442 #define CSR_MHPMEVENT11H 0x72b 443 #define CSR_MHPMEVENT12H 0x72c 444 #define CSR_MHPMEVENT13H 0x72d 445 #define CSR_MHPMEVENT14H 0x72e 446 #define CSR_MHPMEVENT15H 0x72f 447 #define CSR_MHPMEVENT16H 0x730 448 #define CSR_MHPMEVENT17H 0x731 449 #define CSR_MHPMEVENT18H 0x732 450 #define CSR_MHPMEVENT19H 0x733 451 #define CSR_MHPMEVENT20H 0x734 452 #define CSR_MHPMEVENT21H 0x735 453 #define CSR_MHPMEVENT22H 0x736 454 #define CSR_MHPMEVENT23H 0x737 455 #define CSR_MHPMEVENT24H 0x738 456 #define CSR_MHPMEVENT25H 0x739 457 #define CSR_MHPMEVENT26H 0x73a 458 #define CSR_MHPMEVENT27H 0x73b 459 #define CSR_MHPMEVENT28H 0x73c 460 #define CSR_MHPMEVENT29H 0x73d 461 #define CSR_MHPMEVENT30H 0x73e 462 #define CSR_MHPMEVENT31H 0x73f 463 464 #define CSR_MHPMCOUNTER3H 0xb83 465 #define CSR_MHPMCOUNTER4H 0xb84 466 #define CSR_MHPMCOUNTER5H 0xb85 467 #define CSR_MHPMCOUNTER6H 0xb86 468 #define CSR_MHPMCOUNTER7H 0xb87 469 #define CSR_MHPMCOUNTER8H 0xb88 470 #define CSR_MHPMCOUNTER9H 0xb89 471 #define CSR_MHPMCOUNTER10H 0xb8a 472 #define CSR_MHPMCOUNTER11H 0xb8b 473 #define CSR_MHPMCOUNTER12H 0xb8c 474 #define CSR_MHPMCOUNTER13H 0xb8d 475 #define CSR_MHPMCOUNTER14H 0xb8e 476 #define CSR_MHPMCOUNTER15H 0xb8f 477 #define CSR_MHPMCOUNTER16H 0xb90 478 #define CSR_MHPMCOUNTER17H 0xb91 479 #define CSR_MHPMCOUNTER18H 0xb92 480 #define CSR_MHPMCOUNTER19H 0xb93 481 #define CSR_MHPMCOUNTER20H 0xb94 482 #define CSR_MHPMCOUNTER21H 0xb95 483 #define CSR_MHPMCOUNTER22H 0xb96 484 #define CSR_MHPMCOUNTER23H 0xb97 485 #define CSR_MHPMCOUNTER24H 0xb98 486 #define CSR_MHPMCOUNTER25H 0xb99 487 #define CSR_MHPMCOUNTER26H 0xb9a 488 #define CSR_MHPMCOUNTER27H 0xb9b 489 #define CSR_MHPMCOUNTER28H 0xb9c 490 #define CSR_MHPMCOUNTER29H 0xb9d 491 #define CSR_MHPMCOUNTER30H 0xb9e 492 #define CSR_MHPMCOUNTER31H 0xb9f 493 494 /* 495 * User PointerMasking registers 496 * NB: actual CSR numbers might be changed in future 497 */ 498 #define CSR_UMTE 0x4c0 499 #define CSR_UPMMASK 0x4c1 500 #define CSR_UPMBASE 0x4c2 501 502 /* 503 * Machine PointerMasking registers 504 * NB: actual CSR numbers might be changed in future 505 */ 506 #define CSR_MMTE 0x3c0 507 #define CSR_MPMMASK 0x3c1 508 #define CSR_MPMBASE 0x3c2 509 510 /* 511 * Supervisor PointerMaster registers 512 * NB: actual CSR numbers might be changed in future 513 */ 514 #define CSR_SMTE 0x1c0 515 #define CSR_SPMMASK 0x1c1 516 #define CSR_SPMBASE 0x1c2 517 518 /* 519 * Hypervisor PointerMaster registers 520 * NB: actual CSR numbers might be changed in future 521 */ 522 #define CSR_VSMTE 0x2c0 523 #define CSR_VSPMMASK 0x2c1 524 #define CSR_VSPMBASE 0x2c2 525 #define CSR_SCOUNTOVF 0xda0 526 527 /* Crypto Extension */ 528 #define CSR_SEED 0x015 529 530 /* Zcmt Extension */ 531 #define CSR_JVT 0x017 532 533 /* mstatus CSR bits */ 534 #define MSTATUS_UIE 0x00000001 535 #define MSTATUS_SIE 0x00000002 536 #define MSTATUS_MIE 0x00000008 537 #define MSTATUS_UPIE 0x00000010 538 #define MSTATUS_SPIE 0x00000020 539 #define MSTATUS_UBE 0x00000040 540 #define MSTATUS_MPIE 0x00000080 541 #define MSTATUS_SPP 0x00000100 542 #define MSTATUS_VS 0x00000600 543 #define MSTATUS_MPP 0x00001800 544 #define MSTATUS_FS 0x00006000 545 #define MSTATUS_XS 0x00018000 546 #define MSTATUS_MPRV 0x00020000 547 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 548 #define MSTATUS_MXR 0x00080000 549 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 550 #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ 551 #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ 552 #define MSTATUS_GVA 0x4000000000ULL 553 #define MSTATUS_MPV 0x8000000000ULL 554 555 #define MSTATUS64_UXL 0x0000000300000000ULL 556 #define MSTATUS64_SXL 0x0000000C00000000ULL 557 558 #define MSTATUS32_SD 0x80000000 559 #define MSTATUS64_SD 0x8000000000000000ULL 560 #define MSTATUSH128_SD 0x8000000000000000ULL 561 562 #define MISA32_MXL 0xC0000000 563 #define MISA64_MXL 0xC000000000000000ULL 564 565 typedef enum { 566 MXL_RV32 = 1, 567 MXL_RV64 = 2, 568 MXL_RV128 = 3, 569 } RISCVMXL; 570 571 /* sstatus CSR bits */ 572 #define SSTATUS_UIE 0x00000001 573 #define SSTATUS_SIE 0x00000002 574 #define SSTATUS_UPIE 0x00000010 575 #define SSTATUS_SPIE 0x00000020 576 #define SSTATUS_SPP 0x00000100 577 #define SSTATUS_VS 0x00000600 578 #define SSTATUS_FS 0x00006000 579 #define SSTATUS_XS 0x00018000 580 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 581 #define SSTATUS_MXR 0x00080000 582 583 #define SSTATUS64_UXL 0x0000000300000000ULL 584 585 #define SSTATUS32_SD 0x80000000 586 #define SSTATUS64_SD 0x8000000000000000ULL 587 588 /* hstatus CSR bits */ 589 #define HSTATUS_VSBE 0x00000020 590 #define HSTATUS_GVA 0x00000040 591 #define HSTATUS_SPV 0x00000080 592 #define HSTATUS_SPVP 0x00000100 593 #define HSTATUS_HU 0x00000200 594 #define HSTATUS_VGEIN 0x0003F000 595 #define HSTATUS_VTVM 0x00100000 596 #define HSTATUS_VTW 0x00200000 597 #define HSTATUS_VTSR 0x00400000 598 #define HSTATUS_VSXL 0x300000000 599 600 #define HSTATUS32_WPRI 0xFF8FF87E 601 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL 602 603 #define COUNTEREN_CY (1 << 0) 604 #define COUNTEREN_TM (1 << 1) 605 #define COUNTEREN_IR (1 << 2) 606 #define COUNTEREN_HPM3 (1 << 3) 607 608 /* vsstatus CSR bits */ 609 #define VSSTATUS64_UXL 0x0000000300000000ULL 610 611 /* Privilege modes */ 612 #define PRV_U 0 613 #define PRV_S 1 614 #define PRV_RESERVED 2 615 #define PRV_M 3 616 617 /* RV32 satp CSR field masks */ 618 #define SATP32_MODE 0x80000000 619 #define SATP32_ASID 0x7fc00000 620 #define SATP32_PPN 0x003fffff 621 622 /* RV64 satp CSR field masks */ 623 #define SATP64_MODE 0xF000000000000000ULL 624 #define SATP64_ASID 0x0FFFF00000000000ULL 625 #define SATP64_PPN 0x00000FFFFFFFFFFFULL 626 627 /* VM modes (satp.mode) privileged ISA 1.10 */ 628 #define VM_1_10_MBARE 0 629 #define VM_1_10_SV32 1 630 #define VM_1_10_SV39 8 631 #define VM_1_10_SV48 9 632 #define VM_1_10_SV57 10 633 #define VM_1_10_SV64 11 634 635 /* Page table entry (PTE) fields */ 636 #define PTE_V 0x001 /* Valid */ 637 #define PTE_R 0x002 /* Read */ 638 #define PTE_W 0x004 /* Write */ 639 #define PTE_X 0x008 /* Execute */ 640 #define PTE_U 0x010 /* User */ 641 #define PTE_G 0x020 /* Global */ 642 #define PTE_A 0x040 /* Accessed */ 643 #define PTE_D 0x080 /* Dirty */ 644 #define PTE_SOFT 0x300 /* Reserved for Software */ 645 #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */ 646 #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ 647 #define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */ 648 #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ 649 650 /* Page table PPN shift amount */ 651 #define PTE_PPN_SHIFT 10 652 653 /* Page table PPN mask */ 654 #define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL 655 656 /* Leaf page shift amount */ 657 #define PGSHIFT 12 658 659 /* Default Reset Vector address */ 660 #define DEFAULT_RSTVEC 0x1000 661 662 /* Exception causes */ 663 typedef enum RISCVException { 664 RISCV_EXCP_NONE = -1, /* sentinel value */ 665 RISCV_EXCP_INST_ADDR_MIS = 0x0, 666 RISCV_EXCP_INST_ACCESS_FAULT = 0x1, 667 RISCV_EXCP_ILLEGAL_INST = 0x2, 668 RISCV_EXCP_BREAKPOINT = 0x3, 669 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, 670 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, 671 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, 672 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, 673 RISCV_EXCP_U_ECALL = 0x8, 674 RISCV_EXCP_S_ECALL = 0x9, 675 RISCV_EXCP_VS_ECALL = 0xa, 676 RISCV_EXCP_M_ECALL = 0xb, 677 RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ 678 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ 679 RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ 680 RISCV_EXCP_SEMIHOST = 0x10, 681 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, 682 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, 683 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, 684 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, 685 } RISCVException; 686 687 #define RISCV_EXCP_INT_FLAG 0x80000000 688 #define RISCV_EXCP_INT_MASK 0x7fffffff 689 690 /* Interrupt causes */ 691 #define IRQ_U_SOFT 0 692 #define IRQ_S_SOFT 1 693 #define IRQ_VS_SOFT 2 694 #define IRQ_M_SOFT 3 695 #define IRQ_U_TIMER 4 696 #define IRQ_S_TIMER 5 697 #define IRQ_VS_TIMER 6 698 #define IRQ_M_TIMER 7 699 #define IRQ_U_EXT 8 700 #define IRQ_S_EXT 9 701 #define IRQ_VS_EXT 10 702 #define IRQ_M_EXT 11 703 #define IRQ_S_GEXT 12 704 #define IRQ_PMU_OVF 13 705 #define IRQ_LOCAL_MAX 16 706 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) 707 708 /* mip masks */ 709 #define MIP_USIP (1 << IRQ_U_SOFT) 710 #define MIP_SSIP (1 << IRQ_S_SOFT) 711 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 712 #define MIP_MSIP (1 << IRQ_M_SOFT) 713 #define MIP_UTIP (1 << IRQ_U_TIMER) 714 #define MIP_STIP (1 << IRQ_S_TIMER) 715 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 716 #define MIP_MTIP (1 << IRQ_M_TIMER) 717 #define MIP_UEIP (1 << IRQ_U_EXT) 718 #define MIP_SEIP (1 << IRQ_S_EXT) 719 #define MIP_VSEIP (1 << IRQ_VS_EXT) 720 #define MIP_MEIP (1 << IRQ_M_EXT) 721 #define MIP_SGEIP (1 << IRQ_S_GEXT) 722 #define MIP_LCOFIP (1 << IRQ_PMU_OVF) 723 724 /* sip masks */ 725 #define SIP_SSIP MIP_SSIP 726 #define SIP_STIP MIP_STIP 727 #define SIP_SEIP MIP_SEIP 728 #define SIP_LCOFIP MIP_LCOFIP 729 730 /* MIE masks */ 731 #define MIE_SEIE (1 << IRQ_S_EXT) 732 #define MIE_UEIE (1 << IRQ_U_EXT) 733 #define MIE_STIE (1 << IRQ_S_TIMER) 734 #define MIE_UTIE (1 << IRQ_U_TIMER) 735 #define MIE_SSIE (1 << IRQ_S_SOFT) 736 #define MIE_USIE (1 << IRQ_U_SOFT) 737 738 /* General PointerMasking CSR bits */ 739 #define PM_ENABLE 0x00000001ULL 740 #define PM_CURRENT 0x00000002ULL 741 #define PM_INSN 0x00000004ULL 742 743 /* Execution environment configuration bits */ 744 #define MENVCFG_FIOM BIT(0) 745 #define MENVCFG_CBIE (3UL << 4) 746 #define MENVCFG_CBCFE BIT(6) 747 #define MENVCFG_CBZE BIT(7) 748 #define MENVCFG_ADUE (1ULL << 61) 749 #define MENVCFG_PBMTE (1ULL << 62) 750 #define MENVCFG_STCE (1ULL << 63) 751 752 /* For RV32 */ 753 #define MENVCFGH_ADUE BIT(29) 754 #define MENVCFGH_PBMTE BIT(30) 755 #define MENVCFGH_STCE BIT(31) 756 757 #define SENVCFG_FIOM MENVCFG_FIOM 758 #define SENVCFG_CBIE MENVCFG_CBIE 759 #define SENVCFG_CBCFE MENVCFG_CBCFE 760 #define SENVCFG_CBZE MENVCFG_CBZE 761 762 #define HENVCFG_FIOM MENVCFG_FIOM 763 #define HENVCFG_CBIE MENVCFG_CBIE 764 #define HENVCFG_CBCFE MENVCFG_CBCFE 765 #define HENVCFG_CBZE MENVCFG_CBZE 766 #define HENVCFG_ADUE MENVCFG_ADUE 767 #define HENVCFG_PBMTE MENVCFG_PBMTE 768 #define HENVCFG_STCE MENVCFG_STCE 769 770 /* For RV32 */ 771 #define HENVCFGH_ADUE MENVCFGH_ADUE 772 #define HENVCFGH_PBMTE MENVCFGH_PBMTE 773 #define HENVCFGH_STCE MENVCFGH_STCE 774 775 /* Offsets for every pair of control bits per each priv level */ 776 #define XS_OFFSET 0ULL 777 #define U_OFFSET 2ULL 778 #define S_OFFSET 5ULL 779 #define M_OFFSET 8ULL 780 781 #define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) 782 #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) 783 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) 784 #define U_PM_INSN (PM_INSN << U_OFFSET) 785 #define S_PM_ENABLE (PM_ENABLE << S_OFFSET) 786 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET) 787 #define S_PM_INSN (PM_INSN << S_OFFSET) 788 #define M_PM_ENABLE (PM_ENABLE << M_OFFSET) 789 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET) 790 #define M_PM_INSN (PM_INSN << M_OFFSET) 791 792 /* mmte CSR bits */ 793 #define MMTE_PM_XS_BITS PM_XS_BITS 794 #define MMTE_U_PM_ENABLE U_PM_ENABLE 795 #define MMTE_U_PM_CURRENT U_PM_CURRENT 796 #define MMTE_U_PM_INSN U_PM_INSN 797 #define MMTE_S_PM_ENABLE S_PM_ENABLE 798 #define MMTE_S_PM_CURRENT S_PM_CURRENT 799 #define MMTE_S_PM_INSN S_PM_INSN 800 #define MMTE_M_PM_ENABLE M_PM_ENABLE 801 #define MMTE_M_PM_CURRENT M_PM_CURRENT 802 #define MMTE_M_PM_INSN M_PM_INSN 803 #define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ 804 MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ 805 MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ 806 MMTE_PM_XS_BITS) 807 808 /* (v)smte CSR bits */ 809 #define SMTE_PM_XS_BITS PM_XS_BITS 810 #define SMTE_U_PM_ENABLE U_PM_ENABLE 811 #define SMTE_U_PM_CURRENT U_PM_CURRENT 812 #define SMTE_U_PM_INSN U_PM_INSN 813 #define SMTE_S_PM_ENABLE S_PM_ENABLE 814 #define SMTE_S_PM_CURRENT S_PM_CURRENT 815 #define SMTE_S_PM_INSN S_PM_INSN 816 #define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ 817 SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ 818 SMTE_PM_XS_BITS) 819 820 /* umte CSR bits */ 821 #define UMTE_U_PM_ENABLE U_PM_ENABLE 822 #define UMTE_U_PM_CURRENT U_PM_CURRENT 823 #define UMTE_U_PM_INSN U_PM_INSN 824 #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) 825 826 /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ 827 #define ISELECT_IPRIO0 0x30 828 #define ISELECT_IPRIO15 0x3f 829 #define ISELECT_IMSIC_EIDELIVERY 0x70 830 #define ISELECT_IMSIC_EITHRESHOLD 0x72 831 #define ISELECT_IMSIC_EIP0 0x80 832 #define ISELECT_IMSIC_EIP63 0xbf 833 #define ISELECT_IMSIC_EIE0 0xc0 834 #define ISELECT_IMSIC_EIE63 0xff 835 #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY 836 #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 837 #define ISELECT_MASK 0x1ff 838 839 /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ 840 #define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) 841 842 /* IMSIC bits (AIA) */ 843 #define IMSIC_TOPEI_IID_SHIFT 16 844 #define IMSIC_TOPEI_IID_MASK 0x7ff 845 #define IMSIC_TOPEI_IPRIO_MASK 0x7ff 846 #define IMSIC_EIPx_BITS 32 847 #define IMSIC_EIEx_BITS 32 848 849 /* MTOPI and STOPI bits (AIA) */ 850 #define TOPI_IID_SHIFT 16 851 #define TOPI_IID_MASK 0xfff 852 #define TOPI_IPRIO_MASK 0xff 853 854 /* Interrupt priority bits (AIA) */ 855 #define IPRIO_IRQ_BITS 8 856 #define IPRIO_MMAXIPRIO 255 857 #define IPRIO_DEFAULT_UPPER 4 858 #define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) 859 #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE 860 #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) 861 #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) 862 #define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1) 863 #define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3) 864 865 /* HVICTL bits (AIA) */ 866 #define HVICTL_VTI 0x40000000 867 #define HVICTL_IID 0x0fff0000 868 #define HVICTL_IPRIOM 0x00000100 869 #define HVICTL_IPRIO 0x000000ff 870 #define HVICTL_VALID_MASK \ 871 (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) 872 873 /* seed CSR bits */ 874 #define SEED_OPST (0b11 << 30) 875 #define SEED_OPST_BIST (0b00 << 30) 876 #define SEED_OPST_WAIT (0b01 << 30) 877 #define SEED_OPST_ES16 (0b10 << 30) 878 #define SEED_OPST_DEAD (0b11 << 30) 879 /* PMU related bits */ 880 #define MIE_LCOFIE (1 << IRQ_PMU_OVF) 881 882 #define MHPMEVENT_BIT_OF BIT_ULL(63) 883 #define MHPMEVENTH_BIT_OF BIT(31) 884 #define MHPMEVENT_BIT_MINH BIT_ULL(62) 885 #define MHPMEVENTH_BIT_MINH BIT(30) 886 #define MHPMEVENT_BIT_SINH BIT_ULL(61) 887 #define MHPMEVENTH_BIT_SINH BIT(29) 888 #define MHPMEVENT_BIT_UINH BIT_ULL(60) 889 #define MHPMEVENTH_BIT_UINH BIT(28) 890 #define MHPMEVENT_BIT_VSINH BIT_ULL(59) 891 #define MHPMEVENTH_BIT_VSINH BIT(27) 892 #define MHPMEVENT_BIT_VUINH BIT_ULL(58) 893 #define MHPMEVENTH_BIT_VUINH BIT(26) 894 895 #define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) 896 #define MHPMEVENT_IDX_MASK 0xFFFFF 897 #define MHPMEVENT_SSCOF_RESVD 16 898 899 /* JVT CSR bits */ 900 #define JVT_MODE 0x3F 901 #define JVT_BASE (~0x3F) 902 #endif 903