1 /* RISC-V ISA constants */ 2 3 #ifndef TARGET_RISCV_CPU_BITS_H 4 #define TARGET_RISCV_CPU_BITS_H 5 6 #define get_field(reg, mask) (((reg) & \ 7 (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) 8 #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ 9 (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ 10 (uint64_t)(mask))) 11 12 /* Floating point round mode */ 13 #define FSR_RD_SHIFT 5 14 #define FSR_RD (0x7 << FSR_RD_SHIFT) 15 16 /* Floating point accrued exception flags */ 17 #define FPEXC_NX 0x01 18 #define FPEXC_UF 0x02 19 #define FPEXC_OF 0x04 20 #define FPEXC_DZ 0x08 21 #define FPEXC_NV 0x10 22 23 /* Floating point status register bits */ 24 #define FSR_AEXC_SHIFT 0 25 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 26 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 27 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 29 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 31 32 /* Vector Fixed-Point round model */ 33 #define FSR_VXRM_SHIFT 9 34 #define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) 35 36 /* Vector Fixed-Point saturation flag */ 37 #define FSR_VXSAT_SHIFT 8 38 #define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) 39 40 /* Control and Status Registers */ 41 42 /* User Trap Setup */ 43 #define CSR_USTATUS 0x000 44 #define CSR_UIE 0x004 45 #define CSR_UTVEC 0x005 46 47 /* User Trap Handling */ 48 #define CSR_USCRATCH 0x040 49 #define CSR_UEPC 0x041 50 #define CSR_UCAUSE 0x042 51 #define CSR_UTVAL 0x043 52 #define CSR_UIP 0x044 53 54 /* User Floating-Point CSRs */ 55 #define CSR_FFLAGS 0x001 56 #define CSR_FRM 0x002 57 #define CSR_FCSR 0x003 58 59 /* User Vector CSRs */ 60 #define CSR_VSTART 0x008 61 #define CSR_VXSAT 0x009 62 #define CSR_VXRM 0x00a 63 #define CSR_VCSR 0x00f 64 #define CSR_VL 0xc20 65 #define CSR_VTYPE 0xc21 66 67 /* VCSR fields */ 68 #define VCSR_VXSAT_SHIFT 0 69 #define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) 70 #define VCSR_VXRM_SHIFT 1 71 #define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) 72 73 /* User Timers and Counters */ 74 #define CSR_CYCLE 0xc00 75 #define CSR_TIME 0xc01 76 #define CSR_INSTRET 0xc02 77 #define CSR_HPMCOUNTER3 0xc03 78 #define CSR_HPMCOUNTER4 0xc04 79 #define CSR_HPMCOUNTER5 0xc05 80 #define CSR_HPMCOUNTER6 0xc06 81 #define CSR_HPMCOUNTER7 0xc07 82 #define CSR_HPMCOUNTER8 0xc08 83 #define CSR_HPMCOUNTER9 0xc09 84 #define CSR_HPMCOUNTER10 0xc0a 85 #define CSR_HPMCOUNTER11 0xc0b 86 #define CSR_HPMCOUNTER12 0xc0c 87 #define CSR_HPMCOUNTER13 0xc0d 88 #define CSR_HPMCOUNTER14 0xc0e 89 #define CSR_HPMCOUNTER15 0xc0f 90 #define CSR_HPMCOUNTER16 0xc10 91 #define CSR_HPMCOUNTER17 0xc11 92 #define CSR_HPMCOUNTER18 0xc12 93 #define CSR_HPMCOUNTER19 0xc13 94 #define CSR_HPMCOUNTER20 0xc14 95 #define CSR_HPMCOUNTER21 0xc15 96 #define CSR_HPMCOUNTER22 0xc16 97 #define CSR_HPMCOUNTER23 0xc17 98 #define CSR_HPMCOUNTER24 0xc18 99 #define CSR_HPMCOUNTER25 0xc19 100 #define CSR_HPMCOUNTER26 0xc1a 101 #define CSR_HPMCOUNTER27 0xc1b 102 #define CSR_HPMCOUNTER28 0xc1c 103 #define CSR_HPMCOUNTER29 0xc1d 104 #define CSR_HPMCOUNTER30 0xc1e 105 #define CSR_HPMCOUNTER31 0xc1f 106 #define CSR_CYCLEH 0xc80 107 #define CSR_TIMEH 0xc81 108 #define CSR_INSTRETH 0xc82 109 #define CSR_HPMCOUNTER3H 0xc83 110 #define CSR_HPMCOUNTER4H 0xc84 111 #define CSR_HPMCOUNTER5H 0xc85 112 #define CSR_HPMCOUNTER6H 0xc86 113 #define CSR_HPMCOUNTER7H 0xc87 114 #define CSR_HPMCOUNTER8H 0xc88 115 #define CSR_HPMCOUNTER9H 0xc89 116 #define CSR_HPMCOUNTER10H 0xc8a 117 #define CSR_HPMCOUNTER11H 0xc8b 118 #define CSR_HPMCOUNTER12H 0xc8c 119 #define CSR_HPMCOUNTER13H 0xc8d 120 #define CSR_HPMCOUNTER14H 0xc8e 121 #define CSR_HPMCOUNTER15H 0xc8f 122 #define CSR_HPMCOUNTER16H 0xc90 123 #define CSR_HPMCOUNTER17H 0xc91 124 #define CSR_HPMCOUNTER18H 0xc92 125 #define CSR_HPMCOUNTER19H 0xc93 126 #define CSR_HPMCOUNTER20H 0xc94 127 #define CSR_HPMCOUNTER21H 0xc95 128 #define CSR_HPMCOUNTER22H 0xc96 129 #define CSR_HPMCOUNTER23H 0xc97 130 #define CSR_HPMCOUNTER24H 0xc98 131 #define CSR_HPMCOUNTER25H 0xc99 132 #define CSR_HPMCOUNTER26H 0xc9a 133 #define CSR_HPMCOUNTER27H 0xc9b 134 #define CSR_HPMCOUNTER28H 0xc9c 135 #define CSR_HPMCOUNTER29H 0xc9d 136 #define CSR_HPMCOUNTER30H 0xc9e 137 #define CSR_HPMCOUNTER31H 0xc9f 138 139 /* Machine Timers and Counters */ 140 #define CSR_MCYCLE 0xb00 141 #define CSR_MINSTRET 0xb02 142 #define CSR_MCYCLEH 0xb80 143 #define CSR_MINSTRETH 0xb82 144 145 /* Machine Information Registers */ 146 #define CSR_MVENDORID 0xf11 147 #define CSR_MARCHID 0xf12 148 #define CSR_MIMPID 0xf13 149 #define CSR_MHARTID 0xf14 150 151 /* Machine Trap Setup */ 152 #define CSR_MSTATUS 0x300 153 #define CSR_MISA 0x301 154 #define CSR_MEDELEG 0x302 155 #define CSR_MIDELEG 0x303 156 #define CSR_MIE 0x304 157 #define CSR_MTVEC 0x305 158 #define CSR_MCOUNTEREN 0x306 159 160 /* 32-bit only */ 161 #define CSR_MSTATUSH 0x310 162 163 /* Machine Trap Handling */ 164 #define CSR_MSCRATCH 0x340 165 #define CSR_MEPC 0x341 166 #define CSR_MCAUSE 0x342 167 #define CSR_MTVAL 0x343 168 #define CSR_MIP 0x344 169 170 /* Supervisor Trap Setup */ 171 #define CSR_SSTATUS 0x100 172 #define CSR_SEDELEG 0x102 173 #define CSR_SIDELEG 0x103 174 #define CSR_SIE 0x104 175 #define CSR_STVEC 0x105 176 #define CSR_SCOUNTEREN 0x106 177 178 /* Supervisor Trap Handling */ 179 #define CSR_SSCRATCH 0x140 180 #define CSR_SEPC 0x141 181 #define CSR_SCAUSE 0x142 182 #define CSR_STVAL 0x143 183 #define CSR_SIP 0x144 184 185 /* Supervisor Protection and Translation */ 186 #define CSR_SPTBR 0x180 187 #define CSR_SATP 0x180 188 189 /* Hpervisor CSRs */ 190 #define CSR_HSTATUS 0x600 191 #define CSR_HEDELEG 0x602 192 #define CSR_HIDELEG 0x603 193 #define CSR_HIE 0x604 194 #define CSR_HCOUNTEREN 0x606 195 #define CSR_HGEIE 0x607 196 #define CSR_HTVAL 0x643 197 #define CSR_HVIP 0x645 198 #define CSR_HIP 0x644 199 #define CSR_HTINST 0x64A 200 #define CSR_HGEIP 0xE12 201 #define CSR_HGATP 0x680 202 #define CSR_HTIMEDELTA 0x605 203 #define CSR_HTIMEDELTAH 0x615 204 205 /* Virtual CSRs */ 206 #define CSR_VSSTATUS 0x200 207 #define CSR_VSIE 0x204 208 #define CSR_VSTVEC 0x205 209 #define CSR_VSSCRATCH 0x240 210 #define CSR_VSEPC 0x241 211 #define CSR_VSCAUSE 0x242 212 #define CSR_VSTVAL 0x243 213 #define CSR_VSIP 0x244 214 #define CSR_VSATP 0x280 215 216 #define CSR_MTINST 0x34a 217 #define CSR_MTVAL2 0x34b 218 219 /* Enhanced Physical Memory Protection (ePMP) */ 220 #define CSR_MSECCFG 0x747 221 #define CSR_MSECCFGH 0x757 222 /* Physical Memory Protection */ 223 #define CSR_PMPCFG0 0x3a0 224 #define CSR_PMPCFG1 0x3a1 225 #define CSR_PMPCFG2 0x3a2 226 #define CSR_PMPCFG3 0x3a3 227 #define CSR_PMPADDR0 0x3b0 228 #define CSR_PMPADDR1 0x3b1 229 #define CSR_PMPADDR2 0x3b2 230 #define CSR_PMPADDR3 0x3b3 231 #define CSR_PMPADDR4 0x3b4 232 #define CSR_PMPADDR5 0x3b5 233 #define CSR_PMPADDR6 0x3b6 234 #define CSR_PMPADDR7 0x3b7 235 #define CSR_PMPADDR8 0x3b8 236 #define CSR_PMPADDR9 0x3b9 237 #define CSR_PMPADDR10 0x3ba 238 #define CSR_PMPADDR11 0x3bb 239 #define CSR_PMPADDR12 0x3bc 240 #define CSR_PMPADDR13 0x3bd 241 #define CSR_PMPADDR14 0x3be 242 #define CSR_PMPADDR15 0x3bf 243 244 /* Debug/Trace Registers (shared with Debug Mode) */ 245 #define CSR_TSELECT 0x7a0 246 #define CSR_TDATA1 0x7a1 247 #define CSR_TDATA2 0x7a2 248 #define CSR_TDATA3 0x7a3 249 250 /* Debug Mode Registers */ 251 #define CSR_DCSR 0x7b0 252 #define CSR_DPC 0x7b1 253 #define CSR_DSCRATCH 0x7b2 254 255 /* Performance Counters */ 256 #define CSR_MHPMCOUNTER3 0xb03 257 #define CSR_MHPMCOUNTER4 0xb04 258 #define CSR_MHPMCOUNTER5 0xb05 259 #define CSR_MHPMCOUNTER6 0xb06 260 #define CSR_MHPMCOUNTER7 0xb07 261 #define CSR_MHPMCOUNTER8 0xb08 262 #define CSR_MHPMCOUNTER9 0xb09 263 #define CSR_MHPMCOUNTER10 0xb0a 264 #define CSR_MHPMCOUNTER11 0xb0b 265 #define CSR_MHPMCOUNTER12 0xb0c 266 #define CSR_MHPMCOUNTER13 0xb0d 267 #define CSR_MHPMCOUNTER14 0xb0e 268 #define CSR_MHPMCOUNTER15 0xb0f 269 #define CSR_MHPMCOUNTER16 0xb10 270 #define CSR_MHPMCOUNTER17 0xb11 271 #define CSR_MHPMCOUNTER18 0xb12 272 #define CSR_MHPMCOUNTER19 0xb13 273 #define CSR_MHPMCOUNTER20 0xb14 274 #define CSR_MHPMCOUNTER21 0xb15 275 #define CSR_MHPMCOUNTER22 0xb16 276 #define CSR_MHPMCOUNTER23 0xb17 277 #define CSR_MHPMCOUNTER24 0xb18 278 #define CSR_MHPMCOUNTER25 0xb19 279 #define CSR_MHPMCOUNTER26 0xb1a 280 #define CSR_MHPMCOUNTER27 0xb1b 281 #define CSR_MHPMCOUNTER28 0xb1c 282 #define CSR_MHPMCOUNTER29 0xb1d 283 #define CSR_MHPMCOUNTER30 0xb1e 284 #define CSR_MHPMCOUNTER31 0xb1f 285 #define CSR_MHPMEVENT3 0x323 286 #define CSR_MHPMEVENT4 0x324 287 #define CSR_MHPMEVENT5 0x325 288 #define CSR_MHPMEVENT6 0x326 289 #define CSR_MHPMEVENT7 0x327 290 #define CSR_MHPMEVENT8 0x328 291 #define CSR_MHPMEVENT9 0x329 292 #define CSR_MHPMEVENT10 0x32a 293 #define CSR_MHPMEVENT11 0x32b 294 #define CSR_MHPMEVENT12 0x32c 295 #define CSR_MHPMEVENT13 0x32d 296 #define CSR_MHPMEVENT14 0x32e 297 #define CSR_MHPMEVENT15 0x32f 298 #define CSR_MHPMEVENT16 0x330 299 #define CSR_MHPMEVENT17 0x331 300 #define CSR_MHPMEVENT18 0x332 301 #define CSR_MHPMEVENT19 0x333 302 #define CSR_MHPMEVENT20 0x334 303 #define CSR_MHPMEVENT21 0x335 304 #define CSR_MHPMEVENT22 0x336 305 #define CSR_MHPMEVENT23 0x337 306 #define CSR_MHPMEVENT24 0x338 307 #define CSR_MHPMEVENT25 0x339 308 #define CSR_MHPMEVENT26 0x33a 309 #define CSR_MHPMEVENT27 0x33b 310 #define CSR_MHPMEVENT28 0x33c 311 #define CSR_MHPMEVENT29 0x33d 312 #define CSR_MHPMEVENT30 0x33e 313 #define CSR_MHPMEVENT31 0x33f 314 #define CSR_MHPMCOUNTER3H 0xb83 315 #define CSR_MHPMCOUNTER4H 0xb84 316 #define CSR_MHPMCOUNTER5H 0xb85 317 #define CSR_MHPMCOUNTER6H 0xb86 318 #define CSR_MHPMCOUNTER7H 0xb87 319 #define CSR_MHPMCOUNTER8H 0xb88 320 #define CSR_MHPMCOUNTER9H 0xb89 321 #define CSR_MHPMCOUNTER10H 0xb8a 322 #define CSR_MHPMCOUNTER11H 0xb8b 323 #define CSR_MHPMCOUNTER12H 0xb8c 324 #define CSR_MHPMCOUNTER13H 0xb8d 325 #define CSR_MHPMCOUNTER14H 0xb8e 326 #define CSR_MHPMCOUNTER15H 0xb8f 327 #define CSR_MHPMCOUNTER16H 0xb90 328 #define CSR_MHPMCOUNTER17H 0xb91 329 #define CSR_MHPMCOUNTER18H 0xb92 330 #define CSR_MHPMCOUNTER19H 0xb93 331 #define CSR_MHPMCOUNTER20H 0xb94 332 #define CSR_MHPMCOUNTER21H 0xb95 333 #define CSR_MHPMCOUNTER22H 0xb96 334 #define CSR_MHPMCOUNTER23H 0xb97 335 #define CSR_MHPMCOUNTER24H 0xb98 336 #define CSR_MHPMCOUNTER25H 0xb99 337 #define CSR_MHPMCOUNTER26H 0xb9a 338 #define CSR_MHPMCOUNTER27H 0xb9b 339 #define CSR_MHPMCOUNTER28H 0xb9c 340 #define CSR_MHPMCOUNTER29H 0xb9d 341 #define CSR_MHPMCOUNTER30H 0xb9e 342 #define CSR_MHPMCOUNTER31H 0xb9f 343 344 /* 345 * User PointerMasking registers 346 * NB: actual CSR numbers might be changed in future 347 */ 348 #define CSR_UMTE 0x4c0 349 #define CSR_UPMMASK 0x4c1 350 #define CSR_UPMBASE 0x4c2 351 352 /* 353 * Machine PointerMasking registers 354 * NB: actual CSR numbers might be changed in future 355 */ 356 #define CSR_MMTE 0x3c0 357 #define CSR_MPMMASK 0x3c1 358 #define CSR_MPMBASE 0x3c2 359 360 /* 361 * Supervisor PointerMaster registers 362 * NB: actual CSR numbers might be changed in future 363 */ 364 #define CSR_SMTE 0x1c0 365 #define CSR_SPMMASK 0x1c1 366 #define CSR_SPMBASE 0x1c2 367 368 /* 369 * Hypervisor PointerMaster registers 370 * NB: actual CSR numbers might be changed in future 371 */ 372 #define CSR_VSMTE 0x2c0 373 #define CSR_VSPMMASK 0x2c1 374 #define CSR_VSPMBASE 0x2c2 375 376 /* mstatus CSR bits */ 377 #define MSTATUS_UIE 0x00000001 378 #define MSTATUS_SIE 0x00000002 379 #define MSTATUS_MIE 0x00000008 380 #define MSTATUS_UPIE 0x00000010 381 #define MSTATUS_SPIE 0x00000020 382 #define MSTATUS_UBE 0x00000040 383 #define MSTATUS_MPIE 0x00000080 384 #define MSTATUS_SPP 0x00000100 385 #define MSTATUS_VS 0x00000600 386 #define MSTATUS_MPP 0x00001800 387 #define MSTATUS_FS 0x00006000 388 #define MSTATUS_XS 0x00018000 389 #define MSTATUS_MPRV 0x00020000 390 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 391 #define MSTATUS_MXR 0x00080000 392 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 393 #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ 394 #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ 395 #define MSTATUS_GVA 0x4000000000ULL 396 #define MSTATUS_MPV 0x8000000000ULL 397 398 #define MSTATUS64_UXL 0x0000000300000000ULL 399 #define MSTATUS64_SXL 0x0000000C00000000ULL 400 401 #define MSTATUS32_SD 0x80000000 402 #define MSTATUS64_SD 0x8000000000000000ULL 403 404 #define MISA32_MXL 0xC0000000 405 #define MISA64_MXL 0xC000000000000000ULL 406 407 typedef enum { 408 MXL_RV32 = 1, 409 MXL_RV64 = 2, 410 MXL_RV128 = 3, 411 } RISCVMXL; 412 413 /* sstatus CSR bits */ 414 #define SSTATUS_UIE 0x00000001 415 #define SSTATUS_SIE 0x00000002 416 #define SSTATUS_UPIE 0x00000010 417 #define SSTATUS_SPIE 0x00000020 418 #define SSTATUS_SPP 0x00000100 419 #define SSTATUS_VS 0x00000600 420 #define SSTATUS_FS 0x00006000 421 #define SSTATUS_XS 0x00018000 422 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 423 #define SSTATUS_MXR 0x00080000 424 425 #define SSTATUS32_SD 0x80000000 426 #define SSTATUS64_SD 0x8000000000000000ULL 427 428 /* hstatus CSR bits */ 429 #define HSTATUS_VSBE 0x00000020 430 #define HSTATUS_GVA 0x00000040 431 #define HSTATUS_SPV 0x00000080 432 #define HSTATUS_SPVP 0x00000100 433 #define HSTATUS_HU 0x00000200 434 #define HSTATUS_VGEIN 0x0003F000 435 #define HSTATUS_VTVM 0x00100000 436 #define HSTATUS_VTW 0x00200000 437 #define HSTATUS_VTSR 0x00400000 438 #define HSTATUS_VSXL 0x300000000 439 440 #define HSTATUS32_WPRI 0xFF8FF87E 441 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL 442 443 #define COUNTEREN_CY (1 << 0) 444 #define COUNTEREN_TM (1 << 1) 445 #define COUNTEREN_IR (1 << 2) 446 #define COUNTEREN_HPM3 (1 << 3) 447 448 /* Privilege modes */ 449 #define PRV_U 0 450 #define PRV_S 1 451 #define PRV_H 2 /* Reserved */ 452 #define PRV_M 3 453 454 /* Virtulisation Register Fields */ 455 #define VIRT_ONOFF 1 456 457 /* RV32 satp CSR field masks */ 458 #define SATP32_MODE 0x80000000 459 #define SATP32_ASID 0x7fc00000 460 #define SATP32_PPN 0x003fffff 461 462 /* RV64 satp CSR field masks */ 463 #define SATP64_MODE 0xF000000000000000ULL 464 #define SATP64_ASID 0x0FFFF00000000000ULL 465 #define SATP64_PPN 0x00000FFFFFFFFFFFULL 466 467 /* VM modes (satp.mode) privileged ISA 1.10 */ 468 #define VM_1_10_MBARE 0 469 #define VM_1_10_SV32 1 470 #define VM_1_10_SV39 8 471 #define VM_1_10_SV48 9 472 #define VM_1_10_SV57 10 473 #define VM_1_10_SV64 11 474 475 /* Page table entry (PTE) fields */ 476 #define PTE_V 0x001 /* Valid */ 477 #define PTE_R 0x002 /* Read */ 478 #define PTE_W 0x004 /* Write */ 479 #define PTE_X 0x008 /* Execute */ 480 #define PTE_U 0x010 /* User */ 481 #define PTE_G 0x020 /* Global */ 482 #define PTE_A 0x040 /* Accessed */ 483 #define PTE_D 0x080 /* Dirty */ 484 #define PTE_SOFT 0x300 /* Reserved for Software */ 485 486 /* Page table PPN shift amount */ 487 #define PTE_PPN_SHIFT 10 488 489 /* Leaf page shift amount */ 490 #define PGSHIFT 12 491 492 /* Default Reset Vector adress */ 493 #define DEFAULT_RSTVEC 0x1000 494 495 /* Exception causes */ 496 typedef enum RISCVException { 497 RISCV_EXCP_NONE = -1, /* sentinel value */ 498 RISCV_EXCP_INST_ADDR_MIS = 0x0, 499 RISCV_EXCP_INST_ACCESS_FAULT = 0x1, 500 RISCV_EXCP_ILLEGAL_INST = 0x2, 501 RISCV_EXCP_BREAKPOINT = 0x3, 502 RISCV_EXCP_LOAD_ADDR_MIS = 0x4, 503 RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, 504 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, 505 RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, 506 RISCV_EXCP_U_ECALL = 0x8, 507 RISCV_EXCP_S_ECALL = 0x9, 508 RISCV_EXCP_VS_ECALL = 0xa, 509 RISCV_EXCP_M_ECALL = 0xb, 510 RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ 511 RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ 512 RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ 513 RISCV_EXCP_SEMIHOST = 0x10, 514 RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, 515 RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, 516 RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, 517 RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, 518 } RISCVException; 519 520 #define RISCV_EXCP_INT_FLAG 0x80000000 521 #define RISCV_EXCP_INT_MASK 0x7fffffff 522 523 /* Interrupt causes */ 524 #define IRQ_U_SOFT 0 525 #define IRQ_S_SOFT 1 526 #define IRQ_VS_SOFT 2 527 #define IRQ_M_SOFT 3 528 #define IRQ_U_TIMER 4 529 #define IRQ_S_TIMER 5 530 #define IRQ_VS_TIMER 6 531 #define IRQ_M_TIMER 7 532 #define IRQ_U_EXT 8 533 #define IRQ_S_EXT 9 534 #define IRQ_VS_EXT 10 535 #define IRQ_M_EXT 11 536 537 /* mip masks */ 538 #define MIP_USIP (1 << IRQ_U_SOFT) 539 #define MIP_SSIP (1 << IRQ_S_SOFT) 540 #define MIP_VSSIP (1 << IRQ_VS_SOFT) 541 #define MIP_MSIP (1 << IRQ_M_SOFT) 542 #define MIP_UTIP (1 << IRQ_U_TIMER) 543 #define MIP_STIP (1 << IRQ_S_TIMER) 544 #define MIP_VSTIP (1 << IRQ_VS_TIMER) 545 #define MIP_MTIP (1 << IRQ_M_TIMER) 546 #define MIP_UEIP (1 << IRQ_U_EXT) 547 #define MIP_SEIP (1 << IRQ_S_EXT) 548 #define MIP_VSEIP (1 << IRQ_VS_EXT) 549 #define MIP_MEIP (1 << IRQ_M_EXT) 550 551 /* sip masks */ 552 #define SIP_SSIP MIP_SSIP 553 #define SIP_STIP MIP_STIP 554 #define SIP_SEIP MIP_SEIP 555 556 /* MIE masks */ 557 #define MIE_SEIE (1 << IRQ_S_EXT) 558 #define MIE_UEIE (1 << IRQ_U_EXT) 559 #define MIE_STIE (1 << IRQ_S_TIMER) 560 #define MIE_UTIE (1 << IRQ_U_TIMER) 561 #define MIE_SSIE (1 << IRQ_S_SOFT) 562 #define MIE_USIE (1 << IRQ_U_SOFT) 563 564 /* General PointerMasking CSR bits*/ 565 #define PM_ENABLE 0x00000001ULL 566 #define PM_CURRENT 0x00000002ULL 567 #define PM_INSN 0x00000004ULL 568 #define PM_XS_MASK 0x00000003ULL 569 570 /* PointerMasking XS bits values */ 571 #define PM_EXT_DISABLE 0x00000000ULL 572 #define PM_EXT_INITIAL 0x00000001ULL 573 #define PM_EXT_CLEAN 0x00000002ULL 574 #define PM_EXT_DIRTY 0x00000003ULL 575 576 /* Offsets for every pair of control bits per each priv level */ 577 #define XS_OFFSET 0ULL 578 #define U_OFFSET 2ULL 579 #define S_OFFSET 5ULL 580 #define M_OFFSET 8ULL 581 582 #define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) 583 #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) 584 #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) 585 #define U_PM_INSN (PM_INSN << U_OFFSET) 586 #define S_PM_ENABLE (PM_ENABLE << S_OFFSET) 587 #define S_PM_CURRENT (PM_CURRENT << S_OFFSET) 588 #define S_PM_INSN (PM_INSN << S_OFFSET) 589 #define M_PM_ENABLE (PM_ENABLE << M_OFFSET) 590 #define M_PM_CURRENT (PM_CURRENT << M_OFFSET) 591 #define M_PM_INSN (PM_INSN << M_OFFSET) 592 593 /* mmte CSR bits */ 594 #define MMTE_PM_XS_BITS PM_XS_BITS 595 #define MMTE_U_PM_ENABLE U_PM_ENABLE 596 #define MMTE_U_PM_CURRENT U_PM_CURRENT 597 #define MMTE_U_PM_INSN U_PM_INSN 598 #define MMTE_S_PM_ENABLE S_PM_ENABLE 599 #define MMTE_S_PM_CURRENT S_PM_CURRENT 600 #define MMTE_S_PM_INSN S_PM_INSN 601 #define MMTE_M_PM_ENABLE M_PM_ENABLE 602 #define MMTE_M_PM_CURRENT M_PM_CURRENT 603 #define MMTE_M_PM_INSN M_PM_INSN 604 #define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ 605 MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ 606 MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ 607 MMTE_PM_XS_BITS) 608 609 /* (v)smte CSR bits */ 610 #define SMTE_PM_XS_BITS PM_XS_BITS 611 #define SMTE_U_PM_ENABLE U_PM_ENABLE 612 #define SMTE_U_PM_CURRENT U_PM_CURRENT 613 #define SMTE_U_PM_INSN U_PM_INSN 614 #define SMTE_S_PM_ENABLE S_PM_ENABLE 615 #define SMTE_S_PM_CURRENT S_PM_CURRENT 616 #define SMTE_S_PM_INSN S_PM_INSN 617 #define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ 618 SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ 619 SMTE_PM_XS_BITS) 620 621 /* umte CSR bits */ 622 #define UMTE_U_PM_ENABLE U_PM_ENABLE 623 #define UMTE_U_PM_CURRENT U_PM_CURRENT 624 #define UMTE_U_PM_INSN U_PM_INSN 625 #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) 626 627 #endif 628